Array substrate, chip on film, display panel and apparatus, and resistance test method

Abstract

Disclosed in the present disclosure are an array substrate, a chip on film, a display panel and apparatus, and a resistance test method. The array substrate comprises: a base substrate, which comprises a display area and a bonding area located on one side of the display area; a plurality of first pins, which are located in the bonding area; and at least two first signal lines, which are electrically connected to the plurality of first pins, wherein a spacing between the first pins corresponding to adjacent first signal lines is S, a spacing between the first pins corresponding to the same first signal line is S1, a line width of each first pin is W, and W>S>S1.

Description

Array substrate, flip-chip film, display panel and device, resistance testing method Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a flip-chip film, a display panel and device, and a resistance testing method. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Summary of the Invention

[0003] The array substrate, flip-chip film, display panel and device, and resistance testing method disclosed herein are specifically implemented as follows:

[0004] On the one hand, the array substrate provided in this disclosure includes:

[0005] A substrate, the substrate including a display area and a bonding area located on one side of the display area;

[0006] Multiple first pins are located in the bonding area;

[0007] There are at least two first signal lines, each first signal line is electrically connected to a plurality of first pins, the spacing between adjacent first signal lines and corresponding first pins is S, the spacing between the same first signal line and corresponding first pins is S1, and the line width of the first pin is W, where W > S > S1.

[0008] In some embodiments, the array substrate provided in this disclosure further includes multiple first connection lines, and adjacent first pins are electrically connected through at least one first connection line among multiple first pins corresponding to the same first signal line.

[0009] In some embodiments, the array substrate provided in this disclosure further includes a plurality of first adapter electrodes located on the side of the plurality of first pins away from the substrate. The first adapter electrodes are electrically connected to the first pins, and the orthographic projection of the first adapter electrodes on the substrate overlaps with the orthographic projection of the electrically connected first pins on the substrate.

[0010] In some embodiments, in the array substrate provided in the present disclosure, one first adapter electrode is electrically connected to a plurality of first pins corresponding to the same first signal line.

[0011] In some embodiments, in the array substrate provided in the present disclosure, the orthographic projection of the first adapter electrode on the substrate and the gap between the first pin electrically connected to it and the orthographic projection of the first adapter electrode on the substrate overlap each other.

[0012] In some embodiments, the array substrate provided in this disclosure further includes multiple first connection lines, and the first adapter electrode is electrically connected to the first connection lines.

[0013] In some embodiments, in the array substrate provided in the present disclosure, the first adapter electrode is electrically connected to the first pin in a one-to-one correspondence.

[0014] In some embodiments, in the array substrate provided in the present disclosure, the orthographic projection of the first adapter electrode on the substrate and the orthographic projection of the gap of the first pin on the substrate do not overlap.

[0015] In some embodiments, the array substrate provided in the present disclosure further includes two first dummy pins, the ends of the two first dummy pins near the display area are connected, the line width W1 of the first dummy pins is approximately the same as the line width W of the first pin, and the spacing S2 of the first dummy pins is approximately the same as the spacing S1 of the first pin corresponding to the same first signal line.

[0016] In some embodiments, the array substrate provided in the present disclosure further includes a second transfer electrode electrically connected to the first dummy pin. The orthographic projection of the second transfer electrode on the substrate overlaps with the orthographic projection of the first dummy pin on the substrate, and the structure of the second transfer electrode is the same as that of the first transfer electrode.

[0017] In some embodiments, the array substrate provided in this disclosure further includes a plurality of second connection lines, adjacent second pins are electrically connected through at least one second connection line, the orthographic projection of the second adapter electrode on the substrate overlaps with the orthographic projection of the second connection line on the substrate, and the second adapter electrode is electrically connected to the second connection line.

[0018] In some embodiments, the array substrate provided in this disclosure further includes a plurality of second pins located in the bonding area, and a plurality of second signal lines electrically connected to the plurality of second pins in a one-to-one correspondence. The line width w of the second pins, the spacing s between adjacent second pins, and the spacing S between adjacent first signal lines corresponding to the first pins are approximately the same.

[0019] In some embodiments, the array substrate provided in this disclosure further includes a plurality of third adapter electrodes located on the side of the plurality of second pins away from the substrate. The third adapter electrodes are electrically connected to the second pins one-to-one, and the orthographic projection of the third adapter electrode on the substrate overlaps with the orthographic projection of the electrically connected second pin on the substrate.

[0020] On the other hand, this disclosure provides a flip-chip film for bonding and connecting with the array substrate provided in this disclosure, wherein the flip-chip film includes:

[0021] Multiple third pins are connected to multiple first pins. The spacing between the third pins connected to the first pins corresponding to the adjacent first signal lines is S', and the spacing between the third pins connected to the first pins corresponding to the same first signal lines is S1'. The line width of the third pins is W', where W' > S' > S1'.

[0022] In some embodiments, the flip-chip film provided in this disclosure further includes multiple third connection lines. Among the multiple third pins that are bound to the multiple first pins corresponding to the same first signal line, adjacent third pins are electrically connected through at least one of the third connection lines.

[0023] In some embodiments, the flip-chip film provided in this disclosure further includes two second dummy pins bonded to the two first dummy pins. The linewidth W1' of the second dummy pins is approximately the same as the linewidth W' of the third pin, and the spacing S2' of the second dummy pins is approximately the same as the spacing S1' of the third pin bonded to the first pin corresponding to the same first signal line.

[0024] In some embodiments, the flip-chip film provided in this disclosure further includes a fourth connecting line, through which the two second dummy pins are connected.

[0025] In some embodiments, the flip-chip film provided in this disclosure further includes a plurality of fourth pins, which are bonded to the plurality of second pins. The line width w' of the fourth pin, the spacing s' between adjacent fourth pins, and the spacing S' of the third pins bonded to the first pins of adjacent first signal lines are approximately the same.

[0026] On the other hand, this disclosure provides a display panel including the array substrate provided in this disclosure and a counter substrate disposed opposite to the array substrate.

[0027] On the other hand, this disclosure provides a display device, including the display panel provided in this disclosure and a flip-chip film bonded to the array substrate.

[0028] In some embodiments, in the display device provided in the present disclosure, the flip-chip film is the flip-chip film provided in the present disclosure.

[0029] On the other hand, embodiments of this disclosure provide a resistance testing method, including:

[0030] Two second dummy pins are routed to test points on the printed circuit board;

[0031] The test point is contacted by an external device probe to collect the voltage and / or current values ​​of the loop formed by the two second dummy pins and the two first dummy pins;

[0032] Based on the voltage value and / or the current value, obtain the contact resistance between the two second dummy pins and the two first dummy pins. Attached Figure Description

[0033] Figure 1 is a schematic diagram of the structure of the array substrate provided in an embodiment of this disclosure;

[0034] Figure 2 is a schematic diagram of the pins of the array substrate and a flip-chip film provided in an embodiment of this disclosure;

[0035] Figure 3 is a schematic diagram of a structure at the first pin of an array substrate provided in an embodiment of this disclosure;

[0036] Figure 4 is a cross-sectional view along line I-I' in Figure 3;

[0037] Figure 5a is a schematic diagram of another structure at the first pin provided in an embodiment of this disclosure;

[0038] Figure 5b is a schematic diagram of another structure at the first pin provided in an embodiment of this disclosure;

[0039] Figure 6 is a cross-sectional view along line II-II' in Figure 5a or Figure 5b;

[0040] Figure 7 is a schematic diagram of another structure at the first pin provided in an embodiment of this disclosure;

[0041] Figure 8 is a cross-sectional view along line III-III' in Figure 7;

[0042] Figure 9 is a schematic diagram of another structure at the first pin provided in an embodiment of this disclosure;

[0043] Figure 10 is a cross-sectional view along line IV-IV' in Figure 9;

[0044] Figure 11a is a superimposed schematic diagram of the embodiments shown in Figures 5a and 8;

[0045] Figure 11b is a superimposed schematic diagram of the embodiments shown in Figures 5b and 8;

[0046] Figure 12 is a cross-sectional view along line V-V' in Figure 11a or Figure 11b;

[0047] Figure 13 is a schematic diagram of a structure at the first pin and the first dummy pin provided in an embodiment of this disclosure;

[0048] Figure 14a is a schematic diagram of another structure at the first pin and the first dummy pin provided in an embodiment of this disclosure;

[0049] Figure 14b is a schematic diagram of another structure at the first pin and the first dummy pin provided in an embodiment of this disclosure;

[0050] Figure 15 is a schematic diagram of the structure at the second pin provided in an embodiment of this disclosure;

[0051] Figure 16 is a cross-sectional view along line VI-VI' in Figure 15;

[0052] Figure 17 is a schematic diagram of the pin structure of the flip-chip thin film provided in the embodiments of this disclosure;

[0053] Figure 18 is a schematic diagram of a third pin provided in an embodiment of this disclosure;

[0054] Figure 19a is a schematic diagram of another structure of the third pin provided in an embodiment of this disclosure;

[0055] Figure 19b is a schematic diagram of another structure of the third pin provided in an embodiment of this disclosure;

[0056] Figure 20 is a schematic diagram of a structure of the third pin and the second dummy pin provided in an embodiment of this disclosure;

[0057] Figure 21a is a schematic diagram of another structure of the third pin and the second dummy pin provided in the embodiments of this disclosure;

[0058] Figure 21b is a schematic diagram of another structure of the third pin and the second dummy pin provided in the embodiments of this disclosure;

[0059] Figure 22 is a schematic diagram of the structure of the fourth pin provided in an embodiment of this disclosure;

[0060] Figure 23 is a schematic diagram of the relevant test methods for bonding resistors;

[0061] Figure 24 is a flowchart of the resistance testing method provided in an embodiment of this disclosure;

[0062] Figure 25 is a schematic diagram of the resistance test principle provided in an embodiment of this disclosure;

[0063] Figure 26 is a schematic diagram of the structure of the display panel provided in an embodiment of this disclosure;

[0064] Figure 27 is a schematic diagram of a display device provided in an embodiment of the present disclosure;

[0065] Figure 28 is a schematic diagram of another structure of the display device provided in an embodiment of the present disclosure;

[0066] Figure 29 is a schematic diagram of another structure of the display device provided in the embodiments of this disclosure. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0068] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0069] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0070] In products integrating chip-on-film (COF) technology, the COF enables electrical conductivity between the printed circuit board (PCBA) and the display panel (PNL). Signals generated on the PCBA are transmitted to the PNL via the COF to drive the PNL to display different images. In some embodiments, the COF can be bonded to the step edge formed where the array substrate of the PNL extends beyond the opposing substrate. The number of COFs is related to the product's resolution and the COF specifications (e.g., 720CH, 960CH, 1440CH). For example, a single-gate full HD (FHD) product includes six 960CH COFs; a single-gate ultra-high-definition (UHD) product includes twelve 960CH COFs. To meet requirements for bonding processes and cell testing, there are distance limitations between different COFs. In some embodiments, the spacing between different flip-chip films (COFs) electrically connected to the same printed circuit board (PCBA) must be ≥4mm.

[0071] As product specifications improve, narrow-bandwidth flip-chip COFs are required to accommodate multiple flip-chip COFs in the bonding area of ​​high-resolution PPI products. This necessitates reducing the bonding lead pitch (the sum of lead width and lead spacing) of the flip-chip COF. This inevitably leads to a smaller contact area between the lead and the anisotropic conductive adhesive (ACF) particles, resulting in increased impedance. In particular, the increased resistance at the gate drive circuit (GOA) signal lines (e.g., CLK) causes poor contact and defects such as horizontal lines when the indentation of the anisotropic conductive adhesive (ACF) particles fluctuates. Especially for gaming monitors, the high voltage difference / high frequency of the clock signal increases the surface current density and resistance between the lead and the anisotropic conductive adhesive (ACF) particles, exacerbating defects.

[0072] To address the aforementioned technical problems, this disclosure provides an array substrate. Figure 1 is a schematic diagram of the array substrate provided in this disclosure, Figure 2 is a schematic diagram of the pins of the array substrate and a COF (Chip-on-Foil) film bonded together, Figure 3 is a schematic diagram of a structure at the first pin of the array substrate provided in this disclosure, and Figure 4 is a cross-sectional view along line I-I' in Figure 3. As can be seen from Figures 1 to 4, the array substrate provided in this disclosure includes:

[0073] The substrate 101 includes a display area AA, a first non-display area DP and a second non-display area DPO disposed opposite each other on both sides of the display area AA, and two third non-display areas GL & GR connecting the first non-display area DP and the second non-display area DPO; wherein, the first non-display area DP includes a bonding area BA for bonding a circuit board (e.g., a flexible circuit board FPC, or a driving circuit for bonding a data chip Source IC, etc.), and the third non-display areas GL & GR include multiple shift registers GOA. Optionally, all shift registers GOA may be located in the third non-display area GL on the left or the third non-display area GR on the right, or half of the shift registers GOA may be located in the third non-display area GL on the left and the other half of the shift registers GOA may be located in the third non-display area GR on the right.

[0074] Multiple first pins 102 are located in the bonding region BA. Optionally, the multiple first pins 102 are located in the gate metal layer. The material of the gate metal layer can include metals with good conductivity such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), chromium (Cr), and nickel (Ni). The gate metal layer can be a single-layer structure or a stacked structure. For example, the gate metal layer is a single-layer structure composed of a copper metal layer or an aluminum metal layer.

[0075] At least two first signal lines 103 (e.g., CLK, VDD, STV, or other GOA signal lines, or a common electrode signal line Vcom) are provided. Each first signal line 103 can be electrically connected to at least two first pins 102 to enhance the signal conduction capability of the first signal line 103. When the first signal line 103 is a CLK line, increasing the conduction capability of the CLK signal can effectively drive the entire panel's grid lines to open and scan line by line. In some embodiments, the first signal line 103 can branch within the bonding area BA to form at least two first pins 102; that is, the first signal line 103 and each first pin 102 electrically connected to it can be a single integrated structure. Optionally, the spacing between adjacent first signal lines 103 and corresponding first pins 102 is S, the spacing between the same first signal line 103 and corresponding first pins 102 is S1, and the line width of the first pin 102 is W, where W > S > S1. In some embodiments, during bonding, the anisotropic conductive adhesive ACF overflows into the gap S1. To increase the probability that the particles of the anisotropic conductive adhesive ACF can be compressed and effectively conduct the first pin 102 and the flip-chip film COF, the gap S1 can be set to be greater than or equal to 7 μm.

[0076] In some embodiments, the pin width and pin spacing are equal, which maximizes the reduction of mismargin in the bonding process. This disclosure increases the width W of the first pin 102 and reduces the spacing between the first pins 102 corresponding to the same first signal line 103 to S1, thereby increasing the area of ​​a single first pin 102 by ΔW*L (ΔW is the increase in the line width of the first pin 102, and L is the length of the first pin 102), thus reducing the contact resistance between the first pin 102 and the flip-chip COF. Furthermore, by maintaining the spacing S between the first pins 102 corresponding to adjacent first signal lines 103, misalignment between any first signal line 103 and the pins on the flip-chip COF corresponding to its adjacent first signal line 103 can be effectively avoided, for example, avoiding misalignment between the pins on the flip-chip COF corresponding to the CLK1 signal line and the CLK2 signal line.

[0077] In some embodiments, Figures 5a and 5b respectively show another structural schematic diagram of the first pin 102 provided in the embodiments of the present disclosure, and Figure 6 is a cross-sectional view along line II-II' in Figure 5a or Figure 5b. As shown in Figures 5a, 5b and 6, the array substrate provided in the embodiments of the present disclosure may also include multiple first connection lines 104. In the multiple first pins 102 corresponding to the same first signal line 103, adjacent first pins 102 are electrically connected through at least one first connection line 104. Optionally, the first connection line 104 and the first pin 102 electrically connected to it are integrally disposed.

[0078] For two adjacent first pins 102 corresponding to the same first signal line 103, they can be locally connected by a first connecting line 104, such as connecting them in the middle to form an "I" structure; alternatively, multiple first connecting lines 104 can be used to bridge the two adjacent first pins 102 corresponding to the same first signal line 103. A certain gap is always maintained between the two adjacent first pins 102 corresponding to the same first signal line 103 to allow for ACF adhesive overflow. This not only increases the number of parallel connection points for the two adjacent first pins 102 corresponding to the same first signal line 103, reducing the overall resistance of the first pins 102 corresponding to the same first signal line 103, but also increases the contact area of ​​the ACF adhesive particles at the first connecting line 104, reducing the contact resistance between the first pin 102 and the COF flip-chip film.

[0079] It should be understood that, when the contact resistance between the first pin 102 and the flip-chip COF is effectively reduced by using the first connecting line 104, the present disclosure can, as shown in FIG3, set the line width W of the first pin 102 to be greater than the spacing S of the first pin 102 corresponding to different first signal lines 103, and the spacing S of the first pin 102 corresponding to different first signal lines 103 to be greater than the spacing S1 of the first pin 102 corresponding to the same first signal line 103; alternatively, as shown in FIG5a and FIG5b, the line width W of the first pin 102, the spacing S of the first pin 102 corresponding to different first signal lines 103, and the spacing S1 of the first pin 102 corresponding to the same first signal line 103 can be set to be approximately the same (for example, the difference between any two of the three is within the error range caused by factors such as manufacturing and measurement). In the embodiment where the first connecting line 104 is combined with increasing the line width W of the first pin 102, the contact resistance between the first pin 102 and the flip-chip COF can be further reduced.

[0080] In some embodiments, the array substrate provided in this disclosure, as shown in FIG3, 4, 5a, 5b and 6, may further include a plurality of first transition electrodes 105 located on the side of the plurality of first pins 102 away from the substrate 101. Optionally, the first transition electrodes 105 are disposed in the same layer as the transparent electrodes, and the material of the transparent electrode layer includes, but is not limited to, indium tin oxide (ITO), indium zinc oxide (IZO), zinc aluminum oxide (AZO), zinc gallium oxide (GZO), etc. For example, when the array substrate has pixel electrodes but no common electrodes, the first transition electrodes 105 are in the same layer and made of the same material as the pixel electrodes; or, when the array substrate has pixel electrodes and common electrodes that are insulated from each other in different layers, the first transition electrodes 105 are in the same layer and made of the same material as the top transparent electrode (e.g., common electrode or pixel electrode) that is farther away from the substrate 101; or, when the array substrate has pixel electrodes and common electrodes that are insulated from each other in the same layer, the first transition electrodes 105 are in the same layer and made of the same material as the common electrode and pixel electrode. In some embodiments, the orthographic projection of the first adapter electrode 105 on the substrate 101 overlaps with the orthographic projection of its electrically connected first pin 102 on the substrate 101. Optionally, the first adapter electrode 105 is electrically connected to the first pin 102 through a first via V1 penetrating the insulating layer 106 (including but not limited to the first insulating layer 1061 and the second insulating layer 1062), thereby achieving bonding between the first pin 102 and the flip-chip COF. Because the transparent electrode layer where the first adapter electrode 105 is located has good water and oxygen barrier properties, compared to directly bonding the water- and oxygen-sensitive first pin 102 to the flip-chip COF, this disclosure uses the first adapter electrode 105 to connect the first pin 102 to the flip-chip COF, which can effectively prevent the first pin 102 from being damaged by water and oxygen erosion, thereby improving the bonding effect.

[0081] It should be noted that when the first adapter electrode 105 is used to connect the first pin 102 and the flip-chip COF, if the linewidth of the first pin 102 is increased by ΔW, the linewidth of the first adapter electrode 105 can also be increased by ΔW accordingly. Then the area of ​​the first adapter electrode 105 is increased by ΔW*L' (L' is the length of the first adapter electrode 105, and L' can be greater than the length L of the first pin 102), thereby effectively reducing the contact resistance between the first adapter electrode 105 and the flip-chip COF.

[0082] In some embodiments, FIG7 is a schematic diagram of another structure at the first pin 102 provided in the embodiments of the present disclosure, FIG8 is a cross-sectional view along line III-III' in FIG7, FIG9 is a schematic diagram of another structure at the first pin 102 provided in the embodiments of the present disclosure, and FIG10 is a cross-sectional view along line IV-IV' in FIG9. As shown in FIG7 to FIG10, in the array substrate provided in the embodiments of the present disclosure, one first adapter electrode 105 can be electrically connected to all first pins 102 corresponding to the same first signal line 103. In other embodiments, as shown in FIG3, FIG4, FIG5a, FIG5b and FIG6, one first adapter electrode 105 can also be electrically connected to one corresponding first pin 102.

[0083] Referring again to Figures 7 and 8, the orthographic projection of the first adapter electrode 105 on the substrate 101 overlaps with the orthographic projection of the gap between its electrically connected first pin 102 on the substrate 101. In some embodiments, the first adapter electrode 105 can cover both the electrically connected first pin 102 and the gap between its electrically connected first pin 102. Since the first pins 102 covered by the first adapter electrode 105 are separate, there is still space for ACF adhesive overflow at the gap between the first pins 102. The ACF adhesive particles are in direct contact with the first adapter electrode 105. Therefore, compared to embodiments where the pin width and pin spacing are the same and the first adapter electrode 105 only covers the first pins 102, the contact area increases by S1*L', thereby reducing the contact resistance.

[0084] Of course, in some embodiments, if the contact resistance is reduced by other means (e.g., increasing the linewidth of the first pin 102 and / or using the first connecting line 104 to connect adjacent first pins 102 corresponding to the same first signal line 103), the orthographic projection of the first adapter electrode 105 on the substrate 101 and the orthographic projection of the gap of the first pin 102 on the substrate 101 can be configured not to overlap, as shown in Figures 3, 4, 5a, 5b, 6, 9, and 10. It should be noted that due to limitations in process conditions or the influence of other factors such as measurement, the orthographic projection of the first adapter electrode 105 on the substrate 101 and the orthographic projection of the gap of the first pin 102 on the substrate 101 may exactly not overlap or may slightly overlap.

[0085] In some embodiments, to achieve optimal resistance optimization, the present disclosure can also be superimposed according to product design requirements. For example, FIG11a is a superimposed schematic diagram of the embodiments shown in FIG5a and FIG7, FIG11b is a superimposed schematic diagram of the embodiments shown in FIG5b and FIG7, and FIG12 is a cross-sectional view along the V-V' line in FIG11a or FIG11b. In FIG11a, FIG11b and FIG12, the first adapter electrode 105 can also be electrically connected to the first connecting line 104 through the second via V2 penetrating the insulating layer 106. Considering that the ACF adhesive particles are in direct contact with the first adapter electrode 105, and the first adapter electrode 105 is connected to the first pin 102 and the first connecting line 104 through the first via V1 and the second via V2 respectively, the conduction path between the first adapter electrode 105 and the first signal line 103 is increased, the overall via resistance is reduced, and the electrical signal transmitted by the ACF adhesive particles can be transmitted to the inside of the panel more losslessly.

[0086] In some embodiments, FIG13 shows a schematic diagram of the structure at the first pin 102 and the first dummy pin 107. As can be seen from FIG13, in the array substrate provided in the embodiments of this disclosure, two first dummy pins 107 of the same layer and material as the first pin 102 may also be provided. The ends of the two first dummy pins 107 near the display area AA are connected. The line width W1 of the first dummy pin 107 is approximately the same as the line width W of the first pin 102 (for example, the difference between the two is within the error range caused by factors such as manufacturing and measurement). The spacing S2 of the first dummy pins 107 is approximately the same as the spacing S1 of the first pin 102 corresponding to the same first signal line 103 (for example, the difference between the two is within the error range caused by factors such as manufacturing and measurement). The contact resistance at the first pin 102 can be characterized by the first dummy pins 107 with the same structure as the first pin 102.

[0087] Referring again to Figure 13, the array substrate provided in this embodiment may further include a second transfer electrode 108 electrically connected to the first dummy pin 107. The orthographic projection of the second transfer electrode 108 on the substrate 101 overlaps with the orthographic projection of the first dummy pin 107 on the substrate 101. Optionally, the second transfer electrode 108 and the first transfer electrode 105 are in the same layer and made of the same material, and the second transfer electrode 108 can be electrically connected to the first dummy pin 107 through a third via V3 penetrating the insulating layer 106. In some embodiments, the structure of the second transfer electrode 108 is the same as that of the first transfer electrode 105. This not only avoids poor bonding caused by water and oxygen corrosion by leading out the first dummy pin 107 through the second transfer electrode 108, but also allows the second transfer electrode 108, which has the same structure as the first transfer electrode 105, to characterize the contact resistance at the first pin 102.

[0088] In some embodiments, Figures 14a and 14b show schematic diagrams of a structure at the first pin 102 and the first dummy pin 107, respectively. As can be seen from Figures 14a and 14b, in the array substrate provided in the embodiments of this disclosure, a second connecting line 109 may also be provided. The two first dummy pins 107 are electrically connected through the second connecting line 109. Optionally, the line width of the second connecting line 109 is approximately the same as the line width of the first connecting line 104 (for example, the difference between the two is within the error range caused by factors such as manufacturing and measurement). The number of second connecting lines 109 is the same as the number of first connecting lines 104 connecting the two first pins 102. The spacing between adjacent second connecting lines 109 is approximately the same as the spacing between adjacent first connecting lines 104 (for example, the difference between the two is within the error range caused by factors such as manufacturing and measurement). Optionally, the orthographic projection of the second transition electrode 108 on the substrate 101 overlaps with the orthographic projection of the second connecting line 109 on the substrate 101, and the second transition electrode 108 is electrically connected to the second connecting line 109 through a fourth via V4 penetrating the insulating layer 106. Referring to Figures 13, 14a, and 14b, the patterns of the areas where the two first virtual pins 107 are located are the same as the patterns of the areas where the two adjacent first pins 102 corresponding to the same first signal line 103 are located. Therefore, the contact resistance between the area where the first virtual pin 107 is located and the flip-chip COF can be accurately characterized by the contact resistance between the area where the first virtual pin 107 is located and the flip-chip COF.

[0089] In some embodiments, FIG15 shows a structural schematic diagram at the second pin, and FIG16 is a cross-sectional view along line VI-VI' in FIG15. As can be seen from FIG2, FIG3, FIG15 and FIG16, the array substrate provided in the embodiments of this disclosure may further include a plurality of second pins 110 located in the bonding region BA, and a plurality of second signal lines 111 (e.g., data lines D1 to Dn) electrically connected to the plurality of second pins 110 in a one-to-one correspondence. The line width w of the second pin 110, the spacing s of adjacent second pins 110, and the spacing S of adjacent first signal lines 103 corresponding to first pins 102 are approximately the same (e.g., the difference between any two of the three is within the error range caused by factors such as manufacturing and measurement), which can effectively avoid misalignment of any second signal line 111 with the pins on the flip-chip COF corresponding to its adjacent second signal line 111. Optionally, the second pin 110 is located in the gate metal layer, and the second signal line 111 extends from the display area AA to the bonding area BA. The portion of the second signal line 111 in the bonding area BA is located in the gate metal layer and is integrally formed with the second pin 110. The portion of the second signal line 111 in the display area AA is located in the source / drain metal layer. Referring to Figure 2, the first pin 102 can be located on one side or both sides of the second pin 110. Figure 2 shows an example where the first pin 102 is located on both sides of the second pin 110.

[0090] Referring again to Figures 15 and 16, the array substrate provided in this embodiment may further include a plurality of third transition electrodes 112 located on the side of the plurality of second pins 110 away from the substrate 101. The third transition electrodes 112 are electrically connected to the second pins 110 one-to-one through a fifth via V5 penetrating the insulating layer 106, and the orthographic projection of the third transition electrode 112 on the substrate 101 overlaps with the orthographic projection of the electrically connected second pins 110 on the substrate 101. Optionally, the third transition electrode 112 is in the same layer and made of the same material as the first transition electrode 105, and the second pins 110 are bonded to the COF (Chip-on-Foil) film through the third transition electrode 112.

[0091] In some embodiments, the array substrate provided in the present disclosure, as shown in FIG2, may further include a first alignment mark 113. Other essential components of the array substrate are those that should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limitations on the present disclosure.

[0092] On the other hand, this disclosure provides a flip-chip film for bonding and connecting with the array substrate provided in this disclosure. Figure 17 is a schematic diagram of the pin structure of the flip-chip film provided in this disclosure, and Figure 18 is a schematic diagram of a third pin structure in the flip-chip film. As shown in Figures 17 and 18, the flip-chip film includes: a plurality of third pins 201, which are bonded and connected to a plurality of first pins 102. The spacing between the third pins 201 bonded to the first pin 102 corresponding to an adjacent first signal line 103 is S', the spacing between the third pins 201 bonded to the first pin 102 corresponding to the same first signal line 103 is S1', and the linewidth of the third pins 201 is W', where W' > S' > S1'. By reducing the spacing S1' of the third pins 201 bonded to the first pin 102 corresponding to the same first signal line and increasing the linewidth W' of the third pins 201, the bonding area between the third pins 201 and the first pins 102 can be increased, thereby reducing the contact resistance. Furthermore, by maintaining the spacing S' of the third pin 201 bound to the first pin 102 of the adjacent first signal line 103 unchanged, it can be ensured that the third pin 201 on the flip-chip COF is accurately aligned and connected with the first pin 102 on the array substrate.

[0093] In some embodiments, the line width of the third pin 201 is W', which is approximately the same as the line width W of the first pin 102 (for example, the difference between the two is within the error range caused by factors such as manufacturing and measurement). The spacing of the third pin 201 bound to the first pin 102 of the adjacent first signal line 103 is S', which is approximately the same as the spacing S of the first pin 102 of the adjacent first signal line 103 (for example, the difference between the two is within the error range caused by factors such as manufacturing and measurement). The spacing of the third pin 201 bound to the first pin 102 of the same first signal line 103 is S1', which is approximately the same as the spacing S1 of the first pin 102 of the same first signal line 103 (for example, the difference between the two is within the error range caused by factors such as manufacturing and measurement).

[0094] In some embodiments, Figures 19a and 19b respectively show another structural schematic diagram of the third pin in the flip-chip film. As shown in Figures 19a and 19b, the flip-chip film provided in the embodiments of this disclosure further includes multiple third connecting lines 202. Among the multiple third pins 201 bound to the multiple first pins 102 corresponding to the same first signal line 103, adjacent third pins 201 are electrically connected by at least one third connecting line 202. Optionally, the line width of the third connecting line 202 is approximately the same as the line width of the first connecting line 104 (for example, the difference between the two is within the error range caused by factors such as manufacturing and measurement), the number of third connecting lines 202 connecting two third pins 201 is the same as the number of first connecting lines 104 connecting two first pins 102, and the spacing between adjacent third connecting lines 202 is approximately the same as the spacing between adjacent first connecting lines 104 (for example, the difference between the two is within the error range caused by factors such as manufacturing and measurement). The third connecting line 202 adds two parallel points of the third pin 201, reducing the overall resistance of the third pin 201. It also increases the contact area of ​​the ACF adhesive particles at the third connecting line 202, thereby reducing the contact resistance.

[0095] In some embodiments, Figures 20, 21a, and 21b respectively show a schematic diagram of a second dummy pin in a flip-chip film. As shown in Figures 20, 21a, and 21b, the flip-chip film provided in the embodiments of this disclosure further includes two second dummy pins 203 bonded to two first dummy pins 107. The linewidth W1' of the second dummy pins 203 is approximately the same as the linewidth W' of the third pin 201 (for example, the difference between the two is within the error range caused by factors such as manufacturing and measurement). The spacing S2' of the second dummy pins 203 is approximately the same as the spacing S1' of the third pin 201 bonded to the first pin 102 corresponding to the same first signal line 103 (for example, the difference between the two is within the error range caused by factors such as manufacturing and measurement), so that the contact resistance at the second dummy pins 203 can be used to characterize the contact resistance at the third pin 201.

[0096] Referring again to Figures 21a and 21b, the array substrate provided in this embodiment may further include a fourth connection line 204. Two second dummy pins 203 are connected through the fourth connection line 204. Optionally, the two second dummy pins 203 are integrally formed with the fourth connection line 204. In some embodiments, the linewidth of the fourth connection line 204 may be approximately the same as the linewidth of the third connection line 202 (e.g., the difference between the two is within the error range caused by factors such as manufacturing and measurement). The number of fourth connection lines 204 connecting two third pins 201 may be the same as the number of third connection lines 202 connecting two first pins 102. The spacing between adjacent fourth connection lines 204 may be approximately the same as the spacing between adjacent third connection lines 202 (e.g., the difference between the two is within the error range caused by factors such as manufacturing and measurement). As can be seen from Figures 20, 21a and 21b, the patterns of the areas where the two second virtual pins 203 are located are the same as the patterns of the areas where the two third pins 201 are located. Therefore, the contact resistance between the area where the second virtual pins 203 are located and the array substrate can be accurately characterized by the contact resistance between the area where the second virtual pins 203 are located and the array substrate.

[0097] In some embodiments, FIG22 is a schematic diagram of the structure of the fourth pin in the flip-chip film. As shown in FIG22, the flip-chip film provided in the embodiments of this disclosure may further include a plurality of fourth pins 205. The plurality of fourth pins 205 are bonded to a plurality of second pins 110. The line width w' of the fourth pin 205, the spacing s' of adjacent fourth pins 205, and the spacing S' of the third pin 201 bonded to the first pin 102 of adjacent first signal lines 103 are approximately the same (for example, the difference between any two of the three is within the error range caused by factors such as manufacturing and measurement). This can ensure that the fourth pin 205 on the flip-chip film COF is accurately aligned and connected to the second pin 110 on the array substrate. Referring to FIG17, the third pin 201 may be disposed on one side or both sides of the fourth pin 205. FIG17 takes the case where the third pin 201 is disposed on both sides of the fourth pin 205 as an example.

[0098] In some embodiments, as shown in FIG17, the flip-chip film provided in this disclosure may further include a second alignment mark 206. This second alignment mark 206 can be used to align with the first alignment mark 113 during the alignment and bonding process between the flip-chip film COF and the display panel PNL, thereby improving alignment accuracy. Other essential components of the flip-chip film are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the scope of this disclosure.

[0099] Figure 23 illustrates a conventional method for monitoring bonding resistance. As shown in Figure 23, during the COF bonding process, ACF adhesive particles are crushed and electrically connected to pin 1 on the COF film and pin 2 on the display panel. This process creates microscopically visible indentations on pin 2 on the display panel. Typically, the number of these indentations (referred to as particle count) is observed under a microscope on the back of the array substrate, and the bonding quality can be determined by the particle count. In some embodiments, monitoring is performed by sampling; a minimum of 15 particles per pin 2 is required to determine if the bonding quality is acceptable; otherwise, it is considered unacceptable. However, when the indentation depth varies, this method cannot quickly obtain the particle count, resulting in long monitoring times, reduced production capacity, and a high risk of misjudgment, leading to insufficient accuracy.

[0100] To address the aforementioned technical problems, this disclosure provides a resistance testing method, as shown in FIG24, which may include the following steps:

[0101] S2401. Lead the two second dummy pins out to the test points on the printed circuit board through wiring;

[0102] S2402. By contacting the test point with an external device probe, the voltage and / or current values ​​of the loop formed by the binding of two second dummy pins and two first dummy pins are collected.

[0103] S2403. Based on voltage and / or current values, obtain the contact resistance between the two second dummy pins and the two first dummy pins.

[0104] Specifically, as shown in Figure 25, after the display panel PNL is bonded to the chip-on-film (COF) film, the ACF adhesive particles are pressed together. The second dummy pin 203 on the COF film and the first dummy pin 107 on the array substrate contained in the display panel PNL form a circuit through the ACF adhesive particles. The second dummy pin 203 of the COF film is led out to the test point of the printed circuit board (PCBA) through wiring. In this way, the voltage and / or current value of this circuit can be tested by external device probes, and the accurate bonding resistance value can be obtained. This method is more accurate than the conventional particle count monitoring method. Integrating the resistance testing equipment into the module production line can monitor the bonding quality of each display panel PNL, thereby avoiding defects caused by excessive resistance of the ACF adhesive particles.

[0105] Based on the same inventive concept, this disclosure provides a display panel. FIG26 is a schematic diagram of the structure of the display panel provided in this disclosure. As shown in FIG26, the display panel of this disclosure includes the array substrate 001 provided in this disclosure embodiment and a counter substrate 002 disposed opposite to the array substrate 001. Optionally, the counter substrate 002 includes a black matrix and a color resist. In some embodiments, the color resist may also be disposed on the array substrate. When the array substrate 001 only has pixel electrodes, the counter substrate 002 may further include a common electrode disposed on the entire surface of the display area AA. When the array substrate 001 has both pixel electrodes and a common electrode, the counter substrate 002 may not have any common electrode. Other essential components of the array substrate 001 and the counter substrate 002 are all understood by those skilled in the art and will not be described in detail here, nor should they be construed as limitations on this disclosure.

[0106] Referring again to Figure 26, the display panel provided in this embodiment may further include a liquid crystal layer 003 between the array substrate 001 and the opposing substrate 002. A first polarizer 004 may be disposed on the side of the array substrate 001 away from the opposing substrate 002, and a second polarizer 005 may be disposed on the side of the opposing substrate 002 away from the array substrate 001. The polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0107] Based on the same inventive concept, this disclosure provides a display device, and Figure 27 is a structural schematic diagram of the display device provided in this disclosure. As shown in Figure 27, the display device provided in this disclosure may include the display panel PNL provided in this disclosure, and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU may be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source may be light-emitting devices (LEDs), such as quantum dot light-emitting devices.

[0108] In some embodiments, the LEDs can also be micro-light-emitting devices (such as Mini LEDs and Micro LEDs). Sub-millimeter or even micrometer-scale micro-light-emitting devices, like organic light-emitting devices (OLEDs), are self-emissive devices. Like OLEDs, they offer advantages such as high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic light-emitting devices emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic light-emitting devices (based on organic materials) in terms of lower power consumption, greater resistance to high and low temperatures, and longer lifespan. Moreover, when micro-light-emitting devices are used as backlights, they can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while also solving the glare problem caused by traditional dynamic backlighting between bright and dark areas of the screen, thus optimizing the visual experience.

[0109] In some embodiments, Figures 28 and 29 respectively illustrate another structural schematic diagram of the display device provided in the embodiments of the present disclosure. As shown in Figures 28 and 29, the display device provided in the present disclosure may further include a flip-chip COF, which can be a conventional flip-chip COF with the same linewidth for different pins, or it can be the flip-chip COF provided in the embodiments of the present disclosure. Optionally, the display device provided in the present disclosure may further include a printed circuit board (PCBA), a timing control board (TCON), and a system board (SOC), etc. In some embodiments, the display panel (PNL) can be bonded to the printed circuit board (PCBA) via the flip-chip COF, and the timing control board (TCON) is electrically connected between the printed circuit board (PCBA) and the system board (SOC), or the timing control board (TCON) can also be integrated inside the system board (SOC).

[0110] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a television, monitor, projector, 3D printer, virtual reality device, mobile phone, tablet computer, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip includes a central processing unit, digital signal processor, etc. In some embodiments, the control chip may also include a memory, power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or arrange different components.

[0111] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0112] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, include: A substrate, the substrate including a display area and a bonding area located on one side of the display area; Multiple first pins are located in the bonding area; There are at least two first signal lines, each first signal line is electrically connected to a plurality of first pins, the spacing between adjacent first signal lines corresponding to the first pins is S, the spacing between the same first signal line corresponding to the first pins is S1, and the line width of the first pin is W, where W > S > S1.

2. The array substrate as claimed in claim 1, wherein, It also includes multiple first connection lines, in which adjacent first pins are electrically connected through at least one first connection line among multiple first pins corresponding to the same first signal line.

3. The array substrate as described in claim 1 or 2, wherein, It also includes a plurality of first adapter electrodes located on the side of the plurality of first pins away from the substrate, the first adapter electrodes being electrically connected to the first pins, and the orthographic projection of the first adapter electrodes on the substrate overlapping the orthographic projection of the electrically connected first pins on the substrate.

4. The array substrate as claimed in claim 3, wherein, One of the first adapter electrodes is electrically connected to a plurality of the first pins corresponding to the same first signal line.

5. The array substrate as claimed in claim 4, wherein, The orthographic projection of the first adapter electrode on the substrate overlaps with the orthographic projection of the gap between the first pin to which it is electrically connected on the substrate.

6. The array substrate as claimed in claim 5, wherein, It also includes multiple first connecting lines, and the first adapter electrode is electrically connected to the first connecting lines.

7. The array substrate as claimed in claim 3, wherein, The first adapter electrode is electrically connected to the first pin in a one-to-one correspondence.

8. The array substrate as claimed in claim 4 or 7, wherein, The orthographic projection of the first adapter electrode on the substrate and the orthographic projection of the gap of the first pin on the substrate do not overlap.

9. The array substrate according to any one of claims 3 to 8, wherein, It also includes two first dummy pins, which are connected at the ends near the display area. The line width W1 of the first dummy pins is approximately the same as the line width W of the first pin, and the spacing S2 of the first dummy pins is approximately the same as the spacing S1 of the first pin corresponding to the same first signal line.

10. The array substrate as claimed in claim 9, wherein, It also includes a second adapter electrode electrically connected to the first dummy pin, wherein the orthographic projection of the second adapter electrode on the substrate overlaps with the orthographic projection of the first dummy pin on the substrate, and the structure of the second adapter electrode is the same as that of the first adapter electrode.

11. The array substrate according to any one of claims 1 to 10, wherein, It also includes a plurality of second pins located in the bonding area, and a plurality of second signal lines electrically connected to the plurality of second pins in a one-to-one correspondence, wherein the line width w of the second pin, the spacing s between adjacent second pins, and the spacing S between adjacent first signal lines corresponding to the first pins are approximately the same.

12. The array substrate as claimed in claim 11, wherein, It also includes a plurality of third adapter electrodes located on the side of the plurality of second pins away from the substrate, wherein the second adapter electrodes are electrically connected to the first pins one by one, and the orthographic projection of the third adapter electrode on the substrate overlaps with the orthographic projection of the electrically connected second pin on the substrate.

13. A flip-chip thin film for bonding to an array substrate as described in any one of claims 1 to 12, wherein, The flip-chip film includes: Multiple third pins are connected to multiple first pins. The spacing between the third pins connected to the first pins corresponding to the adjacent first signal lines is S', and the spacing between the third pins connected to the first pins corresponding to the same first signal lines is S1'. The line width of the third pins is W', where W' > S' > S1'.

14. The flip-chip film as claimed in claim 13, wherein, It also includes multiple second connection lines, in which adjacent third pins are electrically connected through at least one second connection line among multiple third pins that are bound to multiple first pins corresponding to the same first signal line.

15. The flip-chip thin film as described in claim 13 or 14, wherein, It also includes two second dummy pins that are bonded to the two first dummy pins. The line width W1' of the second dummy pins is approximately the same as the line width W' of the third pin, and the spacing S2' of the second dummy pins is approximately the same as the spacing S1' of the third pins bonded to the first pins corresponding to the first signal lines.

16. The flip-chip thin film according to any one of claims 13 to 15, wherein, It also includes a plurality of fourth pins, which are bonded to the plurality of second pins. The line width w' of the fourth pin, the spacing s' between adjacent fourth pins, and the spacing S' of the third pins bonded to the first pins of adjacent first signal lines are approximately the same.

17. A display panel, wherein, It includes the array substrate as described in any one of claims 1 to 12, and a counter substrate disposed opposite to the array substrate.

18. A display device, wherein, It includes the display panel as described in claim 17, and the flip-chip film bonded to the array substrate.

19. The display device as claimed in claim 18, wherein, The flip-chip film is the flip-chip film as described in any one of claims 13 to 16.

20. A resistance testing method, wherein, include: Two second dummy pins are routed to test points on the printed circuit board; The test point is contacted by an external device probe to collect the voltage and / or current values ​​of the loop formed by the two second dummy pins and the two first dummy pins; Based on the voltage value and / or the current value, obtain the contact resistance between the two second dummy pins and the two first dummy pins.

Images