Semiconductor memory device

Abstract

The semiconductor storage device of the present application includes: first to third conductive layers arranged in a first direction; fourth to sixth conductive layers arranged in the first direction; a first semiconductor layer provided between the first to third conductive layers and the fourth to sixth conductive layers and extending in the first direction; and a charge accumulation layer including a first portion provided between the first to third conductive layers and the first semiconductor layer and a second portion provided between the fourth to sixth conductive layers and the first semiconductor layer. The first conductive layer is provided between the second conductive layer and the third conductive layer. The fourth conductive layer is provided between the fifth conductive layer and the sixth conductive layer. In a first verification operation, a verification voltage is supplied to the first conductive layer, a first voltage smaller than the verification voltage is supplied to the fourth conductive layer, a read path voltage is supplied to the second and fifth conductive layers, and a second voltage smaller than the read path voltage is supplied to the third conductive layer or the sixth conductive layer.

Description

[0001] [Cross-references to related applications]

[0002] This application claims priority based on and asserts priority interest in Japanese Patent Application No. 2022-47651, filed on March 23, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described below relate to a semiconductor memory device. Background Technology

[0004] A known semiconductor memory device includes a substrate, a plurality of gate electrodes deposited in a direction intersecting the surface of the substrate, a semiconductor layer facing the plurality of gate electrodes, and a gate insulating layer disposed between the gate electrodes and the semiconductor layer. The gate insulating layer is, for example, a charge storage layer having insulating properties such as silicon nitride (Si3N4) or conductive properties such as a floating gate, which is a memory section capable of storing data. Summary of the Invention

[0005] One embodiment provides a semiconductor memory device that operates suitably.

[0006] A semiconductor memory device according to one embodiment includes: first conductive layers to third conductive layers arranged in a first direction; fourth conductive layers to sixth conductive layers arranged in the first direction and disposed at a distance from the first conductive layers to third conductive layers in a second direction intersecting the first direction; a first semiconductor layer disposed between the first conductive layers to third conductive layers and the fourth conductive layers to sixth conductive layers, extending along the first direction and facing the first conductive layers to sixth conductive layers; and a charge storage layer having a first portion disposed between the first conductive layers to third conductive layers and the first semiconductor layer, and a second portion disposed between the fourth conductive layers to sixth conductive layers and the first semiconductor layer. The first conductive layer is disposed between the second conductive layer and the third conductive layer. The fourth conductive layer is disposed between the fifth conductive layer and the sixth conductive layer. The first conductive layer is parallel to the fourth conductive layer in the second direction. The second conductive layer is parallel to the fifth conductive layer in the second direction. The third conductive layer is parallel to the sixth conductive layer in the second direction. Furthermore, the semiconductor memory device of this embodiment is configured to perform a first write operation corresponding to the first conductive layer. The first write operation includes a first verification operation. In the first verification operation, a verification voltage is supplied to the first conductive layer. Additionally, a first voltage lower than the verification voltage is supplied to the fourth conductive layer. Furthermore, a readout path voltage higher than the verification voltage is supplied to the second and fifth conductive layers. Additionally, a second voltage lower than the readout path voltage is supplied to the third or sixth conductive layer.

[0007] Based on the aforementioned configuration, a suitable semiconductor memory device can be provided. Attached Figure Description

[0008] Figure 1 This is a schematic block diagram showing a portion of the semiconductor memory device according to the first embodiment.

[0009] Figure 2 This is a schematic equivalent circuit diagram representing a portion of the semiconductor memory device.

[0010] Figure 3 This is a schematic equivalent circuit diagram representing a portion of the semiconductor memory device.

[0011] Figure 4 This is a schematic three-dimensional diagram showing a portion of the structure of the semiconductor memory device.

[0012] Figure 5 This is a schematic top view showing a portion of the structure of the semiconductor memory device.

[0013] Figure 6 It is a schematic histogram used to illustrate the threshold voltage of a storage cell MC that records multi-bit data.

[0014] Figure 7 This is a schematic cross-sectional view used to explain the readout operation of the first embodiment.

[0015] Figure 8 This is a schematic flowchart used to explain the writing operation of the first embodiment.

[0016] Figure 9 This is a schematic cross-sectional view used to explain the programming operations of the first embodiment.

[0017] Figure 10 This is a schematic cross-sectional view used to explain the verification operation of the first embodiment.

[0018] Figure 11 It is a schematic cross-sectional view used to illustrate the verification process of the comparative example.

[0019] Figure 12 This is a schematic cross-sectional view used to explain the verification operation of the second embodiment.

[0020] Figure 13 This is a schematic cross-sectional view used to explain the verification operation of the third embodiment.

[0021] Figure 14 This is a schematic cross-sectional view used to explain the verification operation of the third embodiment.

[0022] Figure 15This is a schematic cross-sectional view used to explain the verification operation of the fourth embodiment.

[0023] Figure 16 This is a schematic cross-sectional view used to explain the verification operation of the fifth embodiment.

[0024] Figure 17 This is a schematic cross-sectional view used to explain the verification operation of the sixth embodiment. Detailed Implementation

[0025] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the present invention. Additionally, the following drawings are schematic diagrams, and for ease of explanation, some components may be omitted. Furthermore, common parts in multiple embodiments are labeled with the same symbols, and descriptions may sometimes be omitted.

[0026] Furthermore, in this specification, the term "semiconductor memory device" sometimes refers to a memory die, and sometimes to a memory system that includes a control die, such as a memory chip, memory card, or SSD (Solid State Drive). Additionally, it sometimes refers to a device including a host, such as a smartphone, tablet, or personal computer.

[0027] Furthermore, when this specification mentions that the first component is "electrically connected to" the second component, it can mean that the first component is directly connected to the second component, or that the first component is connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in an off state, the first transistor is "electrically connected to" the third transistor.

[0028] Additionally, in this specification, when it is mentioned that the first component is "connected" between the second and third components, it sometimes means that the first, second, and third components are connected in series, and the second component is connected to the third component via the first component.

[0029] Furthermore, when this specification mentions that a circuit or the like "connects" two wirings, for example, it sometimes means that the circuit or the like includes a transistor or the like, which is disposed in the current path between the two wirings and is in a switched-on state.

[0030] In addition, in this specification, a specific direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0031] In addition, in this specification, the direction along a specific surface is sometimes referred to as the first direction, the direction along the specific surface that intersects the first direction is referred to as the second direction, and the direction that intersects the specific surface is referred to as the third direction. These first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond to each other.

[0032] Furthermore, in this specification, terms such as "upper" or "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Additionally, when referring to a certain configuration as a lower surface or lower end, it refers to the surface or end of that configuration on the substrate side; when referring to an upper surface or upper end, it refers to the surface or end of that configuration on the side opposite to the substrate. Furthermore, a surface intersecting the X or Y direction is called a side surface, etc.

[0033] [First Embodiment] [Structure] Figure 1 This is a schematic block diagram showing a portion of the semiconductor memory device according to the first embodiment. Figure 2 and Figure 3 This is a schematic equivalent circuit diagram representing a portion of the semiconductor memory device.

[0034] like Figure 1 As shown, the semiconductor memory device of this embodiment includes a memory cell array (MCA) and a peripheral circuit (PC) for controlling the memory cell array (MCA).

[0035] The memory cell array (MCA) has multiple memory blocks (BLK). Each memory block (BLK) has multiple string components (SU). For example, such as... Figure 2 As shown, the string component SU has multiple memory components MU. Each of these memory components MU has two electrically independent memory strings MSa and MSb. One end of each memory string MSa and MSb is connected to a drain-side select transistor STD, and is connected to a common bit line BL via these drain-side select transistors. The other end of each memory string MSa and MSb is connected to a common source-side select transistor STS, and is connected to a common source line SL via this source-side select transistor.

[0036] Memory strings MSa and MSb each have multiple memory cells MC connected in series. Each memory cell MC is a field-effect transistor (FET) having a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating layer has a charge accumulation layer capable of storing data. The threshold voltage of each memory cell MC varies depending on the amount of charge in the charge accumulation layer. The gate electrodes of the multiple memory cells MC corresponding to memory string MSa are connected to word line WLa. Similarly, the gate electrodes of the multiple memory cells MC corresponding to memory string MSb are connected to word line WLb. Word lines WLa and WLb are connected to all memory components MU in memory block BLK.

[0037] Select transistors (STD, STS) are field-effect transistors with a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer functions as a channel region. The gate electrode of the drain-side select transistor STD corresponding to memory string MSa is connected to the drain-side select gate line SGDa. The gate electrode of the drain-side select transistor STD corresponding to memory string MSb is connected to the drain-side select gate line SGDb. The drain-side select gate lines SGDa and SGDb are connected to all memory modules MU in the string assembly SU. The gate electrode of the source-side select transistor STS is connected to the source-side select gate line SGS. The source-side select gate line SGS is connected to all memory modules MU in the memory block BLK.

[0038] For example, such as Figure 1 As shown, the peripheral circuit PC includes: row decoders RDa and RDb, connected to the memory cell array MCA; a sense amplifier module SAM, connected to the memory cell array MCA; and a voltage generation circuit VG, connected to the row decoders RDa and RDb and the sense amplifier module SAM. Additionally, the peripheral circuit PC includes a sequence generator (not shown), an address register, a status register, etc.

[0039] For example, such as Figure 3 As shown, the line decoder RDa includes a block decoder BLKDa, a word line decoder WLDa, and a driver circuit DRVa.

[0040] The block decoder BLKDa has multiple block decoding components blkda, each corresponding to a multiple memory block BLK in the memory cell array MCA. Each block decoding component blkda has multiple transistors T, each corresponding to a multiple word line WLa in the memory block BLK. BLK Transistor T BLK For example, a field-effect type NMOS (N-channel metal oxide semiconductor) transistor. Transistor T BLKThe drain electrode of transistor T is connected to word line WLa. BLK The source electrode is connected to wiring CG. Wiring CG is connected to all block decoding components (blkda) in the block decoder BLKDa. Transistor T BLK The gate electrode is connected to the signal supply line BLKSEL. Multiple signal supply lines BLKSEL are provided corresponding to all block decoding components blkda. Furthermore, the signal supply line BLKSEL is connected to all transistors T in the block decoding component blkda. BLK .

[0041] In read and write operations, for example, one signal supply line BLKSEL corresponding to a block address in an address register (not shown) becomes "H", while other signal supply lines BLKSEL become "L". For example, a specific positive drive voltage is supplied to one signal supply line BLKSEL, while a ground voltage V is supplied to the other signal supply lines BLKSEL. SS Therefore, all word lines WLa in a memory block BLK corresponding to this block address are connected to all wiring CG. Additionally, all word lines WLa in other memory blocks BLK become floating.

[0042] The word line decoder WLDa has multiple word line decoding components wlda, each corresponding to a multiple memory cell MC in the memory string MSa. In the illustrated example, the word line decoding component wlda has two transistors T. WL Transistor T WL For example, a field-effect NMOS transistor. Transistor T WL The drain electrode of transistor T is connected to wiring CG. WL The source electrode is connected to the wiring CG. S Or wired CG U Transistor T WL The gate electrode is connected to the signal supply line WLSEL. S Or signal supply line WLSEL U Signal supply line WLSEL S With a transistor T contained in all word line decoding components wlda WL Multiple signal supply lines (WLSEL) are correspondingly provided. U Another transistor T contained in all word line decoding components wlda WL Multiple corresponding settings are provided.

[0043] In read operations, write operations, etc., for example, the signal supply line WLSEL of the word line decoding component wlda corresponding to the page address in the address register (not shown). SWhen it becomes "H", the WLSEL corresponding to the word line decoding component wlda U It enters the "L" state. Additionally, the signal supply line WLSEL corresponds to the other word line decoding component wlda. S Becoming in the "L" state, corresponding to the WLSEL of the other word line decoding components wlda. U It will become "H" state. Additionally, the wiring CG... S Supply the voltage corresponding to the select word line WLa. Additionally, for wiring CG... U A voltage corresponding to the non-select word line WLa is supplied. Thus, the voltage corresponding to the select word line WLa is supplied to one word line WLa corresponding to the page address. Additionally, the voltage corresponding to the non-select word line WLa is supplied to the other word lines WLa. Furthermore, in cases where the page address in the address register (not shown) corresponds to word line WLb instead of WLa, sometimes the voltage corresponding to the non-select word line WLa is supplied to all word lines WLa.

[0044] The driver circuit DRVa, for example, has wiring CG S and wiring CG U Correspondingly, two driver components (drva) are configured. Each driver component (drva) has multiple transistors (T). DRV Transistor T DRV For example, a field-effect NMOS transistor. Transistor T DRV The drain electrode is connected to the wiring CG. S Or wired CG U Transistor T DRV The source electrode is connected to the voltage supply line L. VG Or voltage supply line L P Voltage supply line L VG One of the multiple output terminals connected to the voltage generation circuit VG. Voltage supply line L P Connected to the supplied ground voltage V SS The bonding pad electrode P. Transistor T. DRV The gate electrode is connected to the signal supply line VSEL.

[0045] In read operations, write operations, etc., for example, any one of the multiple signal supply lines VSEL corresponding to a driver component drva becomes the "H" state, and the other signal supply lines VSEL become the "L" state.

[0046] The line decoder RDb is constructed in a manner largely similar to that of the line decoder RDA. However, the transistor T in the line decoder RDb... BLK T WL T DRV Wiring CG, CGS CG U The word line WLb is not electrically connected to word line WLa.

[0047] For example, such as Figure 3 As shown, the voltage generation circuit VG includes multiple voltage generation components vg. During read operations, write operations, etc., the voltage generation components vg generate a specific voltage, which is then supplied via the voltage supply line L. VG The output voltage generating component, vg, can be either a boost circuit such as a charge pump circuit or a buck circuit such as a regulator.

[0048] Sensing Amplifier Module SAM ( Figure 1 It has the ability to work with multiple bit lines (BL). Figure 2 A plurality of sense amplifier components (not shown) are correspondingly arranged. Each sense amplifier component includes: a sense transistor having a gate electrode electrically connected to the bit line BL; a plurality of data latch circuits connected to the drain electrode of the sense transistor; and a voltage adjustment circuit for adjusting the voltage of the bit line BL according to one of the data from the plurality of data latch circuits.

[0049] Next, refer to Figure 4 and Figure 5 Here, an example of the configuration of the semiconductor memory device of this embodiment will be described. Figure 4 This is a schematic perspective view showing a portion of the configuration of the semiconductor memory device according to this embodiment. Figure 5 This is a schematic top view showing a portion of the configuration of the semiconductor memory device according to this embodiment.

[0050] like Figure 4 As shown, the semiconductor memory device of this embodiment includes a semiconductor substrate 100. The semiconductor substrate 100 is, for example, a single-crystal silicon (Si) semiconductor substrate containing p-type impurities. An n-type well containing n-type impurities and a p-type well containing p-type impurities are disposed on the upper surface of the semiconductor substrate. Furthermore, a peripheral circuit PC (PC) is disposed, for example, on the surface of the semiconductor substrate 100. Figure 1 At least a portion of the transistors and wiring, etc.

[0051] A string assembly SU is disposed above the semiconductor substrate 100.

[0052] For example, such as Figure 4As shown, the string assembly SU includes multiple stacked body structures LS arranged in the Y direction and trench structures AT disposed between these multiple stacked body structures LS. Each stacked body structure LS includes multiple conductive layers 110 stacked in the Z direction. The trench structure AT includes multiple memory string structures MSS arranged in the X direction. Each memory string structure MSS includes a generally bottom-cylindrical semiconductor layer 120 extending in the Z direction, a gate insulating layer 130 disposed between the stacked body structures LS and the semiconductor layer 120, and an insulating layer 140 such as silicon oxide (SiO2) disposed in the central portion of the semiconductor layer 120. Furthermore, insulating layers 150 such as silicon oxide (SiO2) are disposed between the multiple memory string structures MSS arranged in the X direction.

[0053] The conductive layer 110 is a generally plate-shaped conductive layer extending along the X direction, such as a multilayer film of titanium nitride (TiN) and tungsten (W), or a conductive layer of polycrystalline silicon (Si) implanted with impurities. A portion of the conductive layer 110 serves as word lines WLa or WLb, and memory cells MC. Figure 2 The gate electrode of the transistor functions as a gate electrode. Additionally, a portion of the conductive layer 110 located above the aforementioned portion serves as the drain-side select gate line SGDa or drain-side select gate line SGDb, and the drain-side select transistor STD. Figure 2 The gate electrode of the ) performs its function.

[0054] Below the plurality of conductive layers 110, for example, a conductive layer 111 comprising the same material as the conductive layers 110 is disposed. The conductive layer 111 serves as the source-side selected gate line (SGS) and the source-side selected transistor (STS). Figure 2 The gate electrode of the ) performs its function.

[0055] An insulating layer 101, such as silicon oxide (SiO2), is disposed between multiple conductive layers 110, between the bottommost conductive layer 110 and conductive layer 111, and between conductive layer 111 and semiconductor substrate 100.

[0056] In addition, Figure 5 In this example, the contact surface 113 between the conductive layer 110 and the gate insulating layer 130 is formed in a curved shape along the outer periphery of a generally circular region (e.g., a circular, elliptical, oblong, or other shaped region) centered on the central axis of the insulating layer 140. Additionally, the contact surface 114 between the conductive layer 110 and the insulating layer 150 is formed in a straight line extending in the X direction.

[0057] Hereinafter, the multiple conductive layers 110 contained in the even-numbered or odd-numbered stacked structure LS arranged in the Y direction will sometimes be referred to as conductive layers 110a. In addition, the multiple conductive layers 110 contained in other stacked structure LS will sometimes be referred to as conductive layers 110b.

[0058] The conductive layer 110a functions as the gate electrode and word line WLa of the memory cell MC contained in the memory string MSa, or as the gate electrode and drain-side select gate line SGDa of the drain-side select transistor STD contained in the memory string MSa.

[0059] The conductive layer 110b functions as the gate electrode and word line WLb of the memory cell MC contained in the memory string MSb, or the gate electrode and drain-side select gate line SGDb of the drain-side select transistor STD contained in the memory string MSb.

[0060] Semiconductor layer 120 is, for example, an undoped polycrystalline silicon (Si) semiconductor layer. As described above, semiconductor layer 120 has a generally cylindrical shape with a bottom. Furthermore, in the following description, the region in semiconductor layer 120 facing the plurality of conductive layers 110a is sometimes referred to as region 120a ( Figure 5 The region facing the multiple conductive layers 110b is called region 120b. Figure 5 Region 120a serves as the memory string MSa. Figure 2 The multiple memory cells MC and the channel region of the drain-side selection transistor STD contained in the memory string (MSb) function as the memory string. Figure 2 The multiple memory cells MC and the channel region of the drain-side selection transistor STD contained in the ) function.

[0061] Semiconductor layer 121 is connected to the lower end of semiconductor layer 120. Figure 4 Semiconductor layer 121 faces two adjacent conductive layers 111 in the Y direction. Semiconductor layer 121 is a single-crystal silicon (Si) or other semiconductor layer, serving as a source-side selection transistor (STS). Figure 2 The channel region functions as a semiconductor layer 121. An insulating layer 123, such as silicon oxide (SiO2), is disposed between the semiconductor layer 121 and the conductive layer 111.

[0062] In addition, Figure 4 In the example, semiconductor substrate 100 serves as source line SL ( Figure 2The semiconductor layer 120 functions as part of the semiconductor substrate 100 and is electrically connected to the peripheral circuit PC via the semiconductor layer 121 and the semiconductor substrate 100. However, this configuration is merely illustrative, and the specific configuration can be adjusted accordingly. For example, the semiconductor layer 121 can be omitted, and a source line SL can be provided below or above the memory block BLK. Figure 2 The wiring, etc., which are part of the function of the semiconductor layer 120, electrically connects the semiconductor layer 120 to the peripheral circuit PC.

[0063] The gate insulating layer 130 has a generally cylindrical shape and extends in the Z direction along the outer peripheral surface of the semiconductor layer 120. The gate insulating layer 130 includes a tunnel insulating layer 131 such as silicon oxide (SiO2), a charge storage layer 132 such as silicon nitride (SiN), and a barrier insulating layer 133 such as silicon oxide (SiO2) disposed from the semiconductor layer 120 side toward the conductive layer 110 side.

[0064] Furthermore, in the following description, the region in the charge storage layer 132 disposed between the conductive layer 110a and the region 120a of the semiconductor layer 120 is sometimes referred to as region 132a. Figure 5 The region between the conductive layer 110b and the semiconductor layer 120 is referred to as region 132b. Figure 5 Similarly, in the following description, the region in the tunnel insulation layer 131 located between region 120a and region 132a is sometimes referred to as region 131a. Figure 5 The region located between region 120b and region 132b is referred to as the second region 131b. Figure 5 ).

[0065] [Threshold voltage of memory cell MC] Next, refer to Figure 6 The threshold voltage of the memory cell MC is explained.

[0066] As described above, the memory cell array (MCA) has multiple memory cells (MCs). When a write operation is performed on these multiple memory cells (MCs), the threshold voltage of these memory cells (MCs) is controlled to various states.

[0067] Figure 6 This is a schematic histogram used to illustrate the threshold voltage of a memory cell (MC) that records multi-bit data. The horizontal axis represents the voltage of word lines WLa and WLb, and the vertical axis represents the number of memory cells (MC).

[0068] Figure 6 The middle figure shows the threshold voltage distribution of three memory cells MC. For example, the threshold voltage of the memory cell MC controlled in the Er state is greater than the readout interruption voltage V. OFF Less than the readout voltage V CGARAdditionally, the threshold voltage of the memory cell MC controlled in state A is greater than the read voltage V. CGAR Less than the readout voltage V CGBR Furthermore, the minimum threshold voltage included in the threshold distribution of state A is approximately equal to the verification voltage V. VFYA The size. Additionally, the threshold voltage of the memory cell MC controlled in state B is greater than the read voltage V. CGBR Furthermore, the minimum threshold voltage contained in the threshold distribution of state B is approximately equal to the verification voltage V. VFYB The size of the memory cell MC. Additionally, the threshold voltage of all memory cells MC is less than the read path voltage V. READ .

[0069] Each of these threshold distributions is assigned 1 bit or more bits of data.

[0070] For example, when 3 bits of data are allocated to the memory cell MC, the threshold voltage of the memory cell MC is in the range of 2. 3 =The threshold distribution method of any one of the 8 threshold distributions is controlled. In addition, any one of the following 8 threshold distributions is assigned: "0,0,0", "0,0,1", "0,1,0", "0,1,1", "1,0,0", "1,0,1", "1,1,0", and "1,1,1".

[0071] Additionally, for example, when allocating 1 bit of data to the memory cell MC, the threshold voltage of the memory cell MC is in the range of 2. 1 =The threshold distribution method of either of the two threshold distributions is controlled. In addition, either "0" or "1" data is assigned to these two threshold distributions.

[0072] [Read the action] Next, refer to Figure 7 The read operation of the semiconductor memory device in this embodiment will be explained. Figure 7 This is a schematic cross-sectional view used to explain the read operation. Furthermore, the read operation in this embodiment is performed together on all memory cells MC contained in a specified string component SU within a specified memory block BLK and connected to a specified word line WLa or word line WLb. Hereinafter, this configuration containing multiple memory cells MC will sometimes be referred to as a page section. Figure 7 The following example illustrates the process of reading the page corresponding to the memory string MSa.

[0073] Furthermore, in the following explanation, the non-select word line WLa located further from the bit line BL than the select word line WLa is sometimes referred to as the front drain-side word line WLa. Additionally, the non-select word line WLa located further from the source line SL than the select word line WLa is sometimes referred to as the front source-side word line WLa.

[0074] Additionally, in the following explanation, the word line WLb adjacent to the select word line WLa in the Y direction is sometimes referred to as the adjacent word line WLb. Furthermore, the non-select word line WLb located closer to the bit line BL than the adjacent word line WLb is sometimes referred to as the back drain-side word line WLb. Also, the non-select word line WLb located closer to the source line SL than the adjacent word line WLb is sometimes referred to as the back source-side word line WLb.

[0075] like Figure 7 As shown, during the read operation, a read voltage V is supplied to the select word line WLa. CGXR ( Figure 6 Readout voltage V CGAR V CGBR (or other readout voltages) supply the readout path voltage V to the non-select word line WLa. READ The gate line SGDa is selected on the drain side to supply voltage V. SG Additionally, a readout interruption voltage V is supplied to the adjacent word line WLb. OFF The read path voltage V is supplied to other non-selected word lines WLb. READ The gate line SGDb on the drain side is selected to supply ground voltage V. SS Additionally, a source-side gate selection voltage V is supplied to the gate line SGS. SG A source voltage V is supplied to the semiconductor substrate 100. SRC .

[0076] In addition, voltage V SG The voltage required to turn on both the drain-side select transistor STD and the source-side select transistor STS is greater than the ground voltage V. SS Source voltage V SRC It is the magnitude and the grounding voltage V SS For the same voltage level, it is greater than the ground voltage V. SS .

[0077] Therefore, in semiconductor layer 120, an electronic channel is formed that connects the bit line BL to the channel region of the selected memory cell MC, and an electronic channel that connects the source line SL to the channel region of the selected memory cell MC. Furthermore, depending on the amount of charge accumulated in the charge accumulation layer 132 of the selected memory cell MC, the selected memory cell MC is either in an on state or an off state. Peripheral circuit PC ( Figure 1 For example, the data recorded in the memory cell MC can be determined by detecting the voltage level of the bit line BL or the magnitude of the current flowing through the bit line BL.

[0078] [Write Action] Next, refer to Figures 8-10 The write operation of the semiconductor memory device in this embodiment will be described. Figure 8 It is a schematic flowchart used to illustrate the write operation. Figure 9 It is a schematic cross-sectional view used to illustrate programming actions. Figure 10 This is a schematic cross-sectional view used to illustrate the verification operation. Furthermore, in this embodiment, the write operation is performed simultaneously on the memory cells (MC) within a specified page section. Figure 9 and Figure 10 The following example illustrates the writing operation performed on the page portion corresponding to the memory string MSa.

[0079] In step S101 ( Figure 8 In ), the number of loops n W Set to 1. Number of loops n W Recorded in registers, etc.

[0080] In step S102, the programming action is performed.

[0081] During programming operations, for example, the bit line BL of the select memory cell MC connected to multiple select memory cells MC for threshold voltage adjustment. Figure 2 Supply source voltage V SRC A voltage V is supplied to the bit line BL of the select memory cell MC that is connected to multiple select memory cells MC without threshold voltage adjustment. DD .

[0082] In addition, such as Figure 9 As shown, a programming voltage V is supplied to the select word line WLa. PGM The write pass voltage V is supplied to the non-select word lines WLa and WLb. PASS The gate lines SGDa and SGDb on the drain side are selected to supply voltage V. SGD The source side selects to supply ground voltage V to the gate line SGS. SS .

[0083] Programming voltage V PGM The voltage required to accumulate electrons in the charge accumulation layer 132 of the selected storage cell MC is greater than the readout path voltage V. READ Write through voltage V PASS Regardless of the type of data recorded in the storage unit MC, the storage unit MC remains in an ON state at a voltage level consistent with the readout path voltage V. READ The same as or greater than the readout path voltage V READ And less than the programming voltage V PGM Voltage V SGD Supply source voltage V to alignment line BL SRCWhen the drain-side selector transistor STD is turned on, the voltage at which a specific drive voltage is supplied to the bit line BL turns the drain-side selector transistor STD off. Voltage V SGD Greater than the ground voltage V SS Less than the voltage V SG .

[0084] Thus, an electron channel is formed in the semiconductor layer 120 to connect the bit line BL with the channel region of the selected memory cell MC. In addition, electrons in the channel region of the selected memory cell MC are deposited in the charge accumulation layer 132 after tunneling through the insulating layer 131.

[0085] In step S103 ( Figure 8 In the process, the verification action is performed.

[0086] like Figure 10 As shown, the verification action is performed in essentially the same way as the read action.

[0087] However, during the verification process, the read voltage V is not supplied to the select word line WLa. CGXR Instead, it supplies the verification voltage V. VFYX ( Figure 6 Verification voltage V VFYA V VFYB (or other verification voltages).

[0088] Additionally, during the verification process, a readout interruption voltage V is supplied to the adjacent word line WLb and the back drain-side word line WLb. OFF The readout path voltage V is supplied to the word line WLb on the source side of the back side. READ .

[0089] In step S104 ( Figure 8 In step S105, the result of the verification action is determined. For example, if the ratio of memory cells MC detected as being in the ON state during the verification action is greater than a fixed number, the verification is determined to have failed, and the process proceeds to step S107. On the other hand, if the ratio of memory cells MC detected as being in the ON state during the verification action is less than a fixed number, the verification is determined to have passed, and the process proceeds to step S107.

[0090] In step S105, the number of loops n is determined. W Has a specific number N been reached? W When the specified number N is not reached. W Proceed to step S106. When a specific number N is reached... W Proceed to step S108.

[0091] In step S106, the number of loops n is increased. W Add 1, proceeding to step S102. Additionally, in step S106, for example, the programming voltage V...PGM Apply a specific voltage ΔV. For example, make the output programming voltage V... PGM voltage generating component vg( Figure 3 The output voltage increases the voltage ΔV.

[0092] In step S107, status data indicating that the write operation has been completed normally is stored in a status register (not shown), and the write operation ends.

[0093] In step S108, the status data indicating that the write operation did not end normally is stored in a status register (not shown), and the write operation is terminated.

[0094] [Page Section Targeted for Write Operation] In the semiconductor memory device of this embodiment, an erasure operation is performed on all memory cells MC within the memory block BLK simultaneously. Therefore, all memory cells MC contained in the memory block BLK after the erasure operation has just been performed are controlled as a reference. Figure 6 The Er state is described below. Hereinafter, this memory block BLK will sometimes be referred to as an erased block.

[0095] For erased blocks, write operations are performed sequentially, starting from the page section below. For example, in... Figure 10 In the example, after the erase operation is performed, the page section that is first written to after the erase operation is the page section corresponding to the first conductive layer 110a from the bottom. Next, the page section corresponding to the first conductive layer 110b from the bottom is written to. Thereafter, write operations are performed sequentially on the page sections corresponding to the conductive layers 110a and 110b located below. Hereinafter, the memory block BLK where a portion of the page sections has been written to is sometimes referred to as the input block. Alternatively, the memory block BLK where all page sections have been written to is sometimes referred to as the valid block.

[0096] [Comparative Example] Next, refer to Figure 11 The verification process for the comparative examples will be explained. Figure 11 It is a schematic cross-sectional view used to illustrate the verification process of the comparative example.

[0097] In the verification action of the comparative example, such as Figure 11 As shown, a readout interruption voltage V is supplied to the adjacent word line WLb. OFF The read path voltage V is supplied to other non-selected word lines WLb. READ .

[0098] Here, data has been written to the page portions corresponding to the front source-side word line WLa and the rear source-side word line WLb. Therefore, the memory cells MC contained in these page portions are controlled as references. Figure 6The described Er state, A state, B state, or other states.

[0099] On the other hand, no data was written to the page sections corresponding to the front drain-side word line WLa and the rear drain-side word line WLb. Therefore, all memory cells MC contained in these page sections were controlled as references. Figure 6 The Er state described.

[0100] Here, for example, when performing a read operation on a valid block, a write operation is performed on all page portions corresponding to the front drain-side word line WLa and the back drain-side word line WLb. Therefore, there exists a situation where the threshold voltage of the memory cells MC contained in these page portions is relatively high, and the current flowing in the bit line BL during the read operation is less than the current flowing in the bit line BL during the verification operation. Consequently, it may be impossible to properly determine the threshold voltage of the memory cells MC corresponding to the select word lines WLa and WLb, leading to false reads.

[0101] [Effect] See reference Figure 10 As explained, during the verification operation of the first embodiment, a readout interruption voltage V is supplied to the back drain-side word line WLb. OFF Therefore, the current flowing in the bit line BL during the verification operation can be made close to the current flowing in the bit line BL during the readout operation, thereby suppressing false readouts.

[0102] Additionally, as referenced Figure 3 As explained, during the write operation, the voltage generation circuit VG includes multiple voltage generation components vg, each generating and outputting a voltage of a specific magnitude. Here, in the verification operation of the first embodiment, the readout interruption voltage V supplied to the back drain-side word line WLb is... OFF The voltage supplied is equal to that supplied to the adjacent word line WLb. Therefore, the verification operation of the first embodiment can be performed without increasing the variety of voltages supplied at one time, and without increasing the circuit area of ​​the voltage generation circuit VG.

[0103] [Second Embodiment] Next, refer to Figure 12 The verification process for the second embodiment will be explained. Figure 12 This is a schematic cross-sectional view used to explain the verification operation of the second embodiment.

[0104] For reference Figure 10 As explained, during the verification operation of the first embodiment, a readout interruption voltage V is supplied to the back drain-side word line WLb. OFF However, this method is merely illustrative. The voltage supplied to the back drain-side word line WLb only needs to be less than the read path voltage V. READ The voltage is sufficient.

[0105] For example, such as Figure 12 As shown, during the verification operation of the second embodiment, the readout interruption voltage V was not supplied to the back drain-side word line WLb. OFF Instead, it supplies ground voltage V SS .

[0106] This method can also suppress the current flowing in the bit line BL during verification operations. Additionally, regarding the ground voltage V... SS Because it can be referenced Figure 3 The electrode P of the bonding pad described is supplied, so it can be used without increasing the circuit area of ​​the voltage generation circuit VG.

[0107] [Third Embodiment] Next, refer to Figure 13 and Figure 14 The verification process for the third embodiment will be explained. Figure 13 and Figure 14 This is a schematic cross-sectional view used to explain the verification operation of the third embodiment.

[0108] For reference Figure 10 and Figure 12 As explained, in the verification operations of the first and second embodiments, a voltage lower than the readout path voltage V is supplied to all back-side drain-side word lines WLb. READ The voltage (e.g., reading the interruption voltage V) OFF or ground voltage V SS However, this method is merely illustrative. For example, a read path voltage V could also be supplied to a portion of the back-side drain-side word line WLb. READ A portion of the back-side drain-side word lines WLb are supplied with a voltage lower than the readout path voltage V. READ The voltage.

[0109] For example, such as Figure 13 As shown, in the verification operation of the third embodiment, a readout path voltage V is supplied to the back drain-side word line WLb located above a certain height position among the multiple back drain-side word lines WLb. READ A lower voltage V than the readout path voltage is supplied to the back drain-side word line WLb, which is located at a position lower than a certain height. READ voltage (in) Figure 13 In the example, the interruption voltage V is read out. OFF ).

[0110] For example, in the verification operation of the first or second embodiment, when the current of the bit line BL becomes too small, it is also considered to adjust the current of the bit line BL by adjusting the magnitude of the voltage supplied to the back drain-side word line WLb. However, when this method is used, the number of types of voltages supplied at one time increases, and the circuit area of ​​the voltage generation circuit VG increases. On the other hand, according to the verification operation of the third embodiment, the current of the bit line BL can be adjusted using only the voltage supplied to other wirings. Therefore, this method can be implemented without increasing the circuit area of ​​the voltage generation circuit VG.

[0111] also, Figure 13 The method shown is merely an example; the specific method can be adjusted accordingly.

[0112] For example, such as Figure 14 As shown, in the verification operation of the third embodiment, a readout path voltage V can also be supplied to the back drain-side word line WLb located at a position lower than a certain height among the multiple back drain-side word lines WLb. READ A lower readout path voltage V is supplied to the back-side drain-side word line WLb, which is located higher than a certain height position. READ voltage (in) Figure 14 In the example, the interruption voltage V is read out. OFF ).

[0113] In addition, Figure 13 and Figure 14 In the example, the supplied readout interruption voltage V can also be used. OFF Multiple conductive layers 110b supply other voltages (e.g., ground voltage V). SS (), to replace reading the interruption voltage V OFF .

[0114] [Fourth Embodiment] Next, refer to Figure 15 The verification process for the fourth embodiment will be explained. Figure 15 This is a schematic cross-sectional view used to explain the verification operation of the fourth embodiment.

[0115] For reference Figure 13 and Figure 14 As explained, in the verification operation of the third embodiment, a readout path voltage V is supplied to one of the back drain-side word lines WLb located at a height higher than a certain position and the back drain-side word lines WLb located at a height lower than a certain position. READ The other is supplied with a voltage lower than the readout path voltage V. READ The voltage (e.g., reading the interruption voltage V) OFF or ground voltage V SS However, this method is merely an example.

[0116] For example, such as Figure 15 As shown, in the verification operation of the fourth embodiment, a readout path voltage V is supplied to one of the even-numbered back-drain-side word lines WLb from the bottom and the odd-numbered back-drain-side word lines WLb from the bottom. READ The other is supplied with a voltage lower than the readout path voltage V. READ The voltage (e.g., reading the interruption voltage V) OFF or ground voltage V SS ).

[0117] [Fifth Embodiment] Next, refer to Figure 16 The verification process for the fifth embodiment will be explained. Figure 16 This is a schematic cross-sectional view used to explain the verification operation of the fifth embodiment.

[0118] For reference Figure 10 and Figures 12-15 As explained, during the verification operation of the first to fourth embodiments, a readout path voltage V is supplied to the front drain-side word line WLa. READ However, this method is merely an example.

[0119] For example, such as Figure 16 As shown, in the verification operation of the fifth embodiment, a voltage V is supplied to the front drain-side word line WLa. DIM Voltage V DIM Greater than reference Figure 6 The grounding voltage V described SS Less than the readout path voltage V READ .

[0120] Consider using the verification operation of the fifth embodiment, for example, in a case where the current of the bit line BL cannot be sufficiently suppressed in the verification operation of the first or second embodiment.

[0121] also, Figure 16 The example shown illustrates supplying the same voltage to the back drain-side word line WLb as in the verification operation of the first embodiment. However, in the verification operation of the fifth embodiment, the same voltage as in the verification operation of any of the second to fourth embodiments may also be supplied to the back drain-side word line WLb.

[0122] in addition, Figure 16 The value in the figure represents the supply voltage V to all front-drain-side word lines WLa. DIM Examples. However, in the verification operation of the fifth embodiment, a voltage V can also be supplied to a portion of the front drain-side word lines WLa. DIMThe read path voltage V is supplied to the other front-side drain-side word lines WLa. READ .

[0123] [Sixth Embodiment] Next, refer to Figure 17 The verification process for the sixth embodiment will be explained. Figure 17 This is a schematic cross-sectional view used to explain the verification operation of the sixth embodiment.

[0124] For reference Figure 10 and Figures 12-16 As explained, in the verification operation of embodiments 1 to 5, the voltage supplied to at least a portion of the word line WLb on the back drain side is made less than the voltage supplied to the word line on the front drain side. However, this method is merely an example.

[0125] For example, such as Figure 17 As shown, in the verification operation of the sixth embodiment, the voltage supplied to at least a portion of the front drain-side word line WLa is made less than the voltage supplied to the back drain-side word line. Specifically, a voltage lower than the read path voltage V is supplied to the front drain-side word line. READ The voltage (e.g., reading the interruption voltage V) OFF or ground voltage V SS Additionally, a readout path voltage V is supplied to the word line on the drain side of the back side. READ .

[0126] Here, in the semiconductor memory devices of embodiments 1 to 5, a memory block BLK includes both word lines WLa and WLb. However, a memory block BLK may also include only one of word lines WLa and WLb. In other words, word lines WLa and WLb may be included in different memory blocks BLK.

[0127] In this case, for example, there may be a situation where the memory block BLK containing the conductive layer 110a is the input block, and the memory block BLK containing the conductive layer 110b is the valid block. In this case, even when a write operation is performed on the page portion corresponding to the conductive layer 110a, there may be a situation where current flows through the memory cell MC corresponding to the back drain-side word line WLb, causing the current of the bit line BL in the verification operation to be close to the current of the bit line BL in the read operation.

[0128] also, Figure 17The example shown illustrates supplying the same voltage to the front drain-side word line WLa as the voltage supplied to the back drain-side word line WLb during the verification operation in the first embodiment. However, during the verification operation in the sixth embodiment, the same voltage may also be supplied to the front drain-side word line WLa as the voltage supplied to the back drain-side word line WLb during the verification operation in any of the second to fifth embodiments.

[0129] in addition, Figure 17 The text indicates that the readout path voltage V is supplied to the back drain-side word line WLb. READ Examples. However, in the verification operation of the sixth embodiment, a voltage V may also be supplied to the back drain-side word line WLb. DIM Alternatively, a voltage V can be supplied to a portion of the back-side drain-side word lines WLb. DIM The read path voltage V is supplied to the other back drain-side word lines WLb. READ .

[0130] [Other Embodiments] The semiconductor memory devices of the first to sixth embodiments have been illustrated above. However, the above embodiments are merely examples, and the specific embodiments can be appropriately adjusted.

[0131] For example, in the semiconductor memory devices of embodiments 1 to 6, write operations are performed sequentially starting from the page portion located at the bottom. However, this method is merely an example. For instance, write operations may also be performed sequentially starting from the page portion located at the top.

[0132] Here, when write operations are performed sequentially starting from the page section located at the bottom, during the write operation, the memory cells MC contained in the page section corresponding to the front source-side word line WLa and the back source-side word line WLb are controlled to be in Er state, A state, B state, or other states. Furthermore, all memory cells MC contained in the page section corresponding to the front drain-side word line WLa and the back drain-side word line WLb are in Er state. Therefore, during the verification operation, by reducing the voltage of at least one of the front drain-side word line WLa and the back drain-side word line WLb, the current flowing in the bit line BL during the verification operation can be made close to the magnitude of the current flowing in the bit line BL during the read operation.

[0133] On the other hand, when write operations are performed sequentially starting from the page section located at the top, during the write operation, the memory cells MC included in the page section corresponding to the front drain-side word line WLa and the back drain-side word line WLb are controlled to Er state, A state, B state, or other states. Furthermore, all memory cells MC included in the page section corresponding to the front source-side word line WLa and the back source-side word line WLb are in the Er state. Therefore, during the verification operation, by reducing the voltage of at least one of the front source-side word line WLa and the back source-side word line WLb, the current flowing in the bit line BL during the verification operation can be made close to the magnitude of the current flowing in the bit line BL during the read operation.

[0134] Therefore, when writing operations are performed sequentially starting from the page portion located at the top, during the verification operation, the voltage supplied to the front drain-side word line WLa and the back drain-side word line WLb during the verification operation in embodiments 1 to 6 can be supplied to the front source-side word line WLa and the back source-side word line WLb. Furthermore, the voltage supplied to the front source-side word line WLa and the back source-side word line WLb during the verification operation in embodiments 1 to 6 can be supplied to the front drain-side word line WLa and the back drain-side word line WLb.

[0135] [Other] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included in the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: a first conductive layer to a third conductive layer arranged in a first direction; a fourth conductive layer to a sixth conductive layer arranged in the first direction and disposed spaced apart from the first conductive layer to the third conductive layer in a second direction intersecting the first direction; a first semiconductor layer disposed between the first conductive layer to the third conductive layer and the fourth conductive layer to the sixth conductive layer, extending along the first direction and facing the first conductive layer to the sixth conductive layer; and a charge storage layer comprising a first portion disposed between the first conductive layer to the third conductive layer and the first semiconductor layer, and a second portion disposed between the fourth conductive layer to the sixth conductive layer and the first semiconductor layer; wherein the first conductive layer is disposed between the second conductive layer and the third conductive layer. The fourth conductive layer is disposed between the fifth and sixth conductive layers. The first conductive layer is parallel to the fourth conductive layer in the second direction, the second conductive layer is parallel to the fifth conductive layer in the second direction, and the third conductive layer is parallel to the sixth conductive layer in the second direction. The semiconductor memory device is configured to perform a first write operation corresponding to the first conductive layer. The first write operation includes a first verification operation. In the first verification operation, a verification voltage is supplied to the first conductive layer, a first voltage less than the verification voltage is supplied to the fourth conductive layer, a readout path voltage greater than the verification voltage is supplied to the second and fifth conductive layers, and a second voltage less than the readout path voltage is supplied to the third or sixth conductive layer.

2. The semiconductor memory device of claim 1, wherein the second voltage is supplied to the sixth conductive layer.

3. The semiconductor memory device of claim 2, wherein the readout path voltage is supplied to the third conductive layer.

4. The semiconductor memory device of claim 2, wherein a third voltage, which is less than the readout path voltage and greater than the second voltage, is supplied to the third conductive layer.

5. The semiconductor memory device of claim 1, wherein the second voltage is supplied to the third conductive layer.

6. The semiconductor memory device of claim 5, wherein the readout path voltage is supplied to the sixth conductive layer.

7. The semiconductor memory device of claim 5, wherein a third voltage, which is less than the readout path voltage and greater than the second voltage, is supplied to the sixth conductive layer.

8. The semiconductor memory device according to any one of claims 1 to 7, wherein the first voltage is supplied as the second voltage.

9. The semiconductor memory device according to any one of claims 1 to 7, wherein a ground voltage is supplied as the second voltage.

10. The semiconductor memory device according to any one of claims 1 to 7, comprising a seventh conductive layer arranged together with the fourth to sixth conductive layers in the first direction, the first semiconductor layer facing the seventh conductive layer, the fourth conductive layer disposed between the fifth and seventh conductive layers, and the readout path voltage supplied to the seventh conductive layer during the first verification operation.

11. The semiconductor memory device of claim 10, wherein the seventh conductive layer is disposed between the fourth conductive layer and the sixth conductive layer.

12. The semiconductor memory device according to claim 11, comprising an eighth conductive layer disposed between the seventh conductive layer and the fourth conductive layer, wherein, during the first verification operation, the readout path voltage is supplied to the eighth conductive layer.

13. The semiconductor memory device according to claim 11, comprising an eighth conductive layer disposed between the seventh conductive layer and the fourth conductive layer, wherein the second voltage is supplied to the eighth conductive layer during the first verification operation.

14. The semiconductor memory device of claim 10, wherein the sixth conductive layer is disposed between the fourth conductive layer and the seventh conductive layer.

15. The semiconductor memory device according to claim 14, comprising a 9th conductive layer disposed between the 6th conductive layer and the 4th conductive layer, wherein the 2nd voltage is supplied to the 9th conductive layer during the 1st verification operation.

16. The semiconductor memory device according to any one of claims 1 to 7, configured to perform a first readout operation corresponding to the first conductive layer, wherein in the first readout operation, a readout voltage greater than the first voltage and less than the readout path voltage is supplied to the first conductive layer, the first voltage is supplied to the fourth conductive layer, and the readout path voltage is supplied to the second conductive layer, the third conductive layer, the fifth conductive layer and the sixth conductive layer.

17. The semiconductor memory device according to any one of claims 1 to 7, configured to perform a second write operation corresponding to the second conductive layer, a third write operation corresponding to the third conductive layer, and a first erase operation corresponding to the first conductive layer to the third conductive layer, wherein during the period from the execution of the first erase operation to its next execution, the first write operation can be performed after the second write operation, and the third write operation can be performed after the first write operation.

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