Multi-channel HDLC control system and data uploading method and data issuing method thereof

Abstract

The application provides a multi-channel HDLC control system and a data uploading method and a data issuing method thereof. The multi-channel HDLC control system is connected with HDLC protocol transceiving modules of each channel through a system message queue, and then the data required to be uploaded by the HDLC protocol transceiving modules of each channel is sent to an upper computer through a bus control module connected with the system message queue. A bus controller is used to control the HDLC protocol transceiving modules of multiple channels, so that the waste of resources is reduced.

Description

Technical Field

[0001] This application relates to the field of computer bus communication technology, specifically to a multi-channel HDLC control system and its data uploading and data distribution methods. Background Technology

[0002] High Level Data Link Control (HDLC) is a bit-oriented synchronous data link layer protocol developed by an international standards organization. It features: complete and transparent data packet transmission; the "0-bit insertion method" facilitates hardware implementation; full-duplex communication mode provides high transmission efficiency; and all data frames employ CRC checksums to ensure reliable transmission.

[0003] The HDLC controller communicates with the host computer via a bus. If there are multiple channels of HDLC controller communicating with the host computer, multiple buses are required to connect to the host computer, resulting in a significant waste of resources. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, this application aims to provide a multi-channel HDLC control system and its data uploading and data distribution methods.

[0005] In a first aspect, this application provides a multi-channel HDLC control system, comprising:

[0006] At least one HDLC protocol transceiver module, each HDLC protocol transceiver module being connected to an external device and configured to receive first data sent by the external device;

[0007] A system message buffer queue, which is connected to each of the HDLC protocol transceiver modules, is configured to encapsulate at least one of the first data to form first encapsulated data;

[0008] A bus control module, which is connected to the system message buffer queue, is configured to convert the first encapsulated data into second encapsulated data and upload the second encapsulated data to the host computer.

[0009] According to the technical solution provided in the embodiments of this application, the bus control module is further configured to receive second data sent by the host computer and send the second data to the system message buffer queue; the system message buffer queue is further configured to parse the second data to obtain multiple channel numbers and third data corresponding to each channel number, and send the third data to the HDLC protocol transceiver module corresponding to each channel number; the HDLC protocol transceiver module is further configured to send the third data to the external device connected to it.

[0010] According to the technical solution provided in the embodiments of this application, the HDLC protocol control module, the bus control module, and the system message buffer queue are all designed independently using PGEA.

[0011] According to the technical solution provided in the embodiments of this application, the bus control module and the host computer are connected via a PCIE bus.

[0012] According to the technical solution provided in the embodiments of this application, a first buffer module is further provided between the system message buffer queue and the bus control module. The first buffer module includes a first receive buffer memory and a first send buffer memory. The system message buffer queue sends the first encapsulated data to the first receive buffer memory and then uploads it to the bus control module. The bus control module stores the second data in the first send buffer memory and then sends it down to the system message buffer queue.

[0013] According to the technical solution provided in the embodiments of this application, the PCIE bus and the host computer communicate using the DMA read / write method.

[0014] According to the technical solution provided in the embodiments of this application, a second buffer module is further provided between each HDLC protocol transceiver module and the system message buffer queue. The second buffer module includes a second receive buffer memory and a second send buffer memory. Each HDLC protocol transceiver module stores the first data in the second receive buffer memory and then sends it to the system message buffer queue. The system message buffer queue sends the third data to the second send buffer memory and then sends it to the HDLC protocol transceiver module.

[0015] Secondly, this application provides a data uploading method for a multi-channel HDLC control system as described above, comprising the following steps:

[0016] Receive at least one first upload data sent by each of the external devices;

[0017] Extract the valid data from each of the first data sets;

[0018] At least one of the valid data is sequentially encapsulated according to the channel number to form the first encapsulated data;

[0019] The first packaged data is converted into the second packaged data through the bus control module;

[0020] Once the triggering conditions are met, the second encapsulated data is uploaded to the host computer.

[0021] Thirdly, this application provides a data transmission method for a multi-channel HDLC control system as described above, comprising the following steps:

[0022] Receive first data sent from the host computer, the first data sent includes at least one header information and data content corresponding to the header information;

[0023] Each packet header information is parsed to obtain first parameter information, which includes at least the channel number and the effective data length.

[0024] Based on the effective data length, extract the data from the data content to obtain the second data to be sent;

[0025] The second data to be sent is transmitted to the HDLC protocol transceiver module according to the channel number.

[0026] The second data is sent to the external device corresponding to each of the HDLC protocol transceiver modules.

[0027] In summary, this application proposes a multi-channel HDLC control system, which connects to the HDLC protocol transceiver modules of each channel through a system message queue, and then sends the data to be uploaded by each channel HDLC protocol transceiver module to the host computer through a bus control module connected to the system message queue. By controlling multiple channel HDLC protocol transceiver modules through a single bus controller, resource waste is reduced. Attached Figure Description

[0028] Figure 1 A schematic diagram of a multi-channel HDLC control system provided in this application embodiment;

[0029] Figure 2 A schematic diagram illustrating the connection relationships between the modules provided in the embodiments of this application;

[0030] Figure 3 A flowchart of the data upload method provided in Embodiment 2 of this application;

[0031] Figure 4 This is a flowchart of the data distribution method provided in Embodiment 3 of this application.

[0032] 1. HDLC protocol transceiver module; 2. System message buffer queue; 3. Bus control module; 4. Host computer; 51. Second transmit buffer memory; 52. Second receive buffer memory; 6. Synchronous serial port; 71. First transmit buffer memory; 72. First receive buffer memory. Detailed Implementation

[0033] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0034] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0035] As mentioned in the background section, this application proposes a multi-channel HDLC control system, comprising:

[0036] At least one HDLC protocol transceiver module 1, each HDLC protocol transceiver module 1 being connected to an external device and configured to receive first data sent by the external device;

[0037] System message buffer queue 2, which is connected to each of the HDLC protocol transceiver modules 1, is configured to encapsulate at least one of the first data to form first encapsulated data;

[0038] Bus control module 3, which is connected to the system message buffer queue 2, is configured to convert the first encapsulated data into second encapsulated data and upload the second encapsulated data to the host computer 4.

[0039] Please refer to Figure 1 and Figure 2 As shown, the multi-channel HDLC control system includes multiple HDLC controllers, each of which includes an HDLC protocol transceiver module 1. The HDLC controller selected is the Xilinx K7 series XC7K325TFTG900-2. This application, while achieving parallel data upload across multiple channels, encapsulates the data through the system message buffer queue 2 and bus control module 3, and uploads the encapsulated data to the host computer 4. This enables one bus control module 3 to control multiple channels, avoiding the problem of multiple channels being connected to the host computer 4 via multiple buses in existing technologies, thus preventing resource waste.

[0040] In a preferred embodiment, the bus control module 3 is further configured to receive second data sent by the host computer 4 and send the second data to the system message buffer queue 2; the system message buffer queue 2 is further configured to parse the second data to obtain multiple channel numbers and third data corresponding to each channel number, and send the third data to the HDLC protocol transceiver module 1 corresponding to each of the channel numbers; the HDLC protocol transceiver module 1 is further configured to send the third data to the external device connected to it.

[0041] In addition to uploading data from the external device to the host computer 4, the data sent by the host computer 4 can also be sent to each HDLC protocol transceiver module 1 through the bus control module 3 and the system message buffer queue 2, and then transmitted to the external device connected to the HDLC protocol transceiver module 1. This enables the host computer 4 to send data to multiple HDLC controllers through a bus control module 3.

[0042] In a preferred embodiment, the HDLC protocol control module, the bus control module 3, and the system message buffer queue 2 are all designed independently using PGEA.

[0043] This application uses Field Programmable Gate Array (FPGA) devices to design each module independently before performing corresponding logic bonding, which improves programming flexibility, reduces development time, and saves costs.

[0044] In a preferred embodiment, the bus control module 3 and the host computer 4 are connected via a PCIe bus. The PCIe bus and the host computer 4 communicate using a DMA read / write method.

[0045] The PCIe bus control module 33 includes a PCIe IP core and a Direct Memory Access (DMA) read / write control section. The IP core uses the 7 Series Integrated Block for PCI Express, with an AXI4-STREAM user interface, an 8KB BAR0 space, and a TLP message length of 512 bytes. The DMA read / write control section encapsulates the read / write operations of the IP core, replacing the original read / write method with a DMA method, thus improving the throughput of the HDLC controller. Optionally, the DMA single read / write length is 1KB. This read / write length must be agreed upon in advance by the software and hardware before communication to ensure data integrity by maintaining data size consistency.

[0046] In a preferred embodiment, a first buffer module is further provided between the system message buffer queue 2 and the bus control module 3. The first buffer module includes a first receive buffer memory 72 and a first transmit buffer memory 71. The system message buffer queue 2 sends the first encapsulated data to the first receive buffer memory 72 and then uploads it to the bus control module 3. The bus control module 3 stores the second data in the first transmit buffer memory 71 and then sends it down to the system message buffer queue 2. A second buffer module is further provided between each HDLC protocol transceiver module 1 and the system message buffer queue 2. The second buffer module includes a second receive buffer memory 52 and a second transmit buffer memory 51. Each HDLC protocol transceiver module 1 stores the first data in the second receive buffer memory 52 and then sends it to the system message buffer queue 2. The system message buffer queue 2 sends the third data to the second transmit buffer memory 51 and then sends it to the HDLC protocol transceiver module 1.

[0047] Among them, the first transmit buffer memory 71, the first receive buffer memory 72, the second transmit buffer memory 51, and the second receive buffer memory 52 are all FIFO (First Input First Output) memories. When uploading data, the synchronous serial port 6 on the HDLC protocol transceiver module 1 first stores the data sent by the external device into the second receive buffer memory 52, and then sends it to the system message buffer queue 2. The system message buffer queue 2 encapsulates multiple data into a first encapsulated data and sends the first encapsulated data to the bus control module 3. The bus control module 3 converts the first encapsulated data into a second encapsulated data suitable for the PCIE bus format and stores the second encapsulated data into the first receive buffer memory 72. When the trigger condition is met, the host computer 4 retrieves the data from the first receive buffer memory 72, wherein the trigger condition is the DMA single read / write size.

[0048] When the host computer 4 sends data, the bus control module 3 receives the data sent by the host computer 4 through the PCIE bus, stores it in the first transmit buffer memory 71, and then sends it to the system message buffer queue 2 for parsing. After parsing, the channel number and the data corresponding to the channel number are obtained, and this data is stored in the second transmit buffer memory 51 corresponding to the channel number. The second transmit buffer memory 51 sends the data to the HDLC protocol transceiver module 1 connected to it, and sends it to the external device through the synchronous serial port 6.

[0049] Example 2

[0050] Based on Embodiment 1, this application provides a data upload method for a multi-channel HDLC control system, such as... Figure 3 As shown, it includes the following steps:

[0051] S100: Receive at least one first upload data sent by each of the external devices;

[0052] S101. Extract the valid data from each of the first data sets;

[0053] S102. Encapsulate at least one of the valid data in sequence according to the channel number to form first encapsulated data;

[0054] S103. Convert the first packaged data into the second packaged data through the bus control module 3;

[0055] S104. After the triggering condition is met, the second encapsulated data is uploaded to the host computer 4.

[0056] The HDLC protocol transceiver module 1 receives the first uploaded data bit by bit from the synchronous serial port 6, extracts the valid data from the first uploaded data, stores it in the second receive buffer memory 52, and then pulls the recv_over signal high to indicate the end of a frame reception. The system message buffer queue 2 detects the recv_over signal under each channel to determine which channel needs to upload data, and retrieves the valid data in the order of channel 1 to n. It adds packet header information to the valid data to form first encapsulated data. The packet header information includes: valid data length, channel number, address field, and control field. The encapsulated first encapsulated data is stored in the first receive buffer memory 72. The first receive buffer memory 72 sends the first encapsulated data to the bus control module 3. The bus control module 3 converts the first encapsulated data into second encapsulated data suitable for the PCIe bus. When the data in the first buffer memory meets the DMA single read length of 1KB, the bus control module 3 sends an interrupt information to the host computer 4. The host computer 4 retrieves the second encapsulated data from the bus control module 3 through the PCIe bus.

[0057] Example 3

[0058] Based on Example 1, this application provides a data transmission method for a multi-channel HDLC control system, comprising the following steps:

[0059] S200: Receive first data sent from host computer 4, the first data sent includes at least one header information and data content corresponding to the header information;

[0060] S201. Parse each packet header information to obtain first parameter information, wherein the first parameter information includes at least the channel number and the effective data length;

[0061] S202. Extract data from the data content according to the effective data length to obtain the second data to be sent;

[0062] S203. The second data to be sent is sent to the HDLC protocol transceiver module 1 according to the channel number;

[0063] S204. The second data is sent to the external device corresponding to each of the HDLC protocol transceiver modules 1.

[0064] The host computer 4 sends the first data transmission to the bus control module 3 via the PCIe bus. The bus control module 3 stores the first data transmission in the first transmission buffer memory 71 and sends it to the system message buffer queue 2. The system message buffer queue 2 first parses the packet header information to obtain the first parameter information, which also includes address and control fields. Based on the effective data length, it extracts a specified byte of data from the data content to obtain the second data transmission information. Based on the channel number, the second data transmission information is input into the corresponding second transmission buffer memory 51 and sent to the HDLC protocol transceiver module 1 connected to it. After the HDLC protocol transceiver module 1 performs framing and transmits the data to the external device via the synchronous serial port 6, the HDLC protocol transceiver module 1 pulls the recv_over signal high to indicate that the single frame data transmission is complete. This information is fed back to the system message buffer queue 2 to instruct it to continue retrieving packet data.

[0065] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A multi-channel HDLC control system, characterized in that, include: At least one HDLC protocol transceiver module (1), each HDLC protocol transceiver module (1) is connected to an external device and configured to receive first data sent by the external device; The system message buffer queue (2) is connected to each of the HDLC protocol transceiver modules (1) and is configured to encapsulate at least one of the first data to form first encapsulated data. The system message buffer queue (2) is also configured to detect the data receiving status of each of the HDLC protocol transceiver modules (1), and to extract the valid data in sequence according to the channel order, and add packet header information before the valid data to form first encapsulated data. The packet header information includes the length of the valid data and the channel number. The bus control module (3) is connected to the system message buffer queue (2) and is configured to convert the first encapsulated data into the second encapsulated data and upload the second encapsulated data to the host computer (4); the bus control module (3) converts the first encapsulated data into the second encapsulated data suitable for the PCIE bus format; The bus control module (3) is also configured to receive second data sent by the host computer (4) and send the second data to the system message buffer queue (2); the system message buffer queue (2) is also configured to parse the second data to obtain multiple channel numbers and third data corresponding to each channel number, and send the third data to the HDLC protocol transceiver module (1) corresponding to each channel number; the HDLC protocol transceiver module (1) is also configured to send the third data to the external device connected to it.

2. The multi-channel HDLC control system according to claim 1, characterized in that, The HDLC protocol transceiver module (1), the bus control module (3), and the system message buffer queue (2) are all designed independently by PGEA.

3. The multi-channel HDLC control system according to claim 1, characterized in that, The bus control module (3) and the host computer (4) are connected via a PCIE bus.

4. The multi-channel HDLC control system according to claim 1, characterized in that, A first buffer module is provided between the system message buffer queue (2) and the bus control module (3). The first buffer module includes a first receive buffer memory (72) and a first send buffer memory (71). The system message buffer queue (2) sends the first encapsulated data to the first receive buffer memory (72) and then uploads it to the bus control module (3). The bus control module (3) stores the second data in the first send buffer memory (71) and then sends it down to the system message buffer queue (2).

5. The multi-channel HDLC control system according to claim 3, characterized in that, The PCIE bus and the host computer (4) communicate using the DMA read / write method.

6. The multi-channel HDLC control system according to claim 1, characterized in that, A second buffer module is provided between each HDLC protocol transceiver module (1) and the system message buffer queue (2). The second buffer module includes a second receive buffer memory (52) and a second send buffer memory (51). Each HDLC protocol transceiver module (1) stores the first data in the second receive buffer memory (52) and then sends it to the system message buffer queue (2). The system message buffer queue (2) sends the third data to the second send buffer memory (51) and then sends it to the HDLC protocol transceiver module (1).

7. A data upload method for a multi-channel HDLC control system according to any one of claims 1-6, characterized in that, Includes the following steps: Receive at least one first upload data sent by each of the external devices; Extract the valid data from each of the first data sets; At least one of the valid data is sequentially encapsulated according to the channel number to form the first encapsulated data; The first packaged data is converted into the second packaged data through the bus control module (3); Once the triggering condition is met, the second encapsulated data is uploaded to the host computer (4).

8. A data transmission method for a multi-channel HDLC control system according to any one of claims 1-6, characterized in that, Includes the following steps: Receive first data sent from host computer (4), the first data sent includes at least one header information and data content corresponding to the header information; Each packet header information is parsed to obtain first parameter information, which includes at least the channel number and the effective data length. Based on the effective data length, extract the data from the data content to obtain the second data to be sent; The second data to be sent to the HDLC protocol transceiver module (1) is sent according to the channel number. The second data is sent to the external device corresponding to each of the HDLC protocol transceiver modules (1).

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