A multi-path high-definition video playing device, method and storage medium

Abstract

The application discloses a multi-path high-definition video playing device, method and storage medium, which comprises a first chip and one or more second chips; the first chip and each second chip are provided with a high-speed transmission interface and a high-definition digital display interface; the first chip outputs first high-definition video data to a display device or a corresponding display area for display through the first high-definition digital display interface, and sends each second high-definition video data to the corresponding second chip through the high-speed transmission interface; and the second chip outputs second high-definition video data to the display device or the corresponding display area for display through the second high-definition digital display interface. The playing device formed by the combination of two or more chips in the application can support multi-path high-definition video playing (for example, 4-path 4K video playing), so that some high-performance PC display cards can be replaced, and the implementation cost is lower than that of the high-performance PC display card.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of video playing, in particular to a multi-channel high-definition video playing device, method and storage medium. BACKGROUND

[0002] In the field of video playing, with the popularity of large-size display screens, large-screen control and playing devices are also developing rapidly. With the increase of display screen size, the resolution of display screens is gradually developing towards high definition. Since a large display screen is likely to be of an unconventional size (for example, 36:16), a large display screen can be cut into multiple display screens of a regular size, and then displayed on each display screen or display area. In the prior art, a high-performance PC video card is mainly used to provide multi-channel high-definition (for example, 4K) data display for large-screen display. However, the high-performance PC is expensive, mainly relies on import channels, and there are unstable sources and other uncertain factors. SUMMARY

[0003] In view of the above problems, the present application provides a multi-channel high-definition video playing device to solve the technical problems of large display screens relying on high-performance PC video cards for driving.

[0004] To achieve the above-mentioned purpose, the inventors provide a multi-channel high-definition video playing device, comprising a first chip and one or more second chips.

[0005] The first chip and each second chip have a high-speed transmission interface; the first chip has a first high-definition digital display interface, and each second chip is provided with a second high-definition digital display interface.

[0006] The first chip has a high-definition video decoding unit, which can decode compressed video data into uncompressed first high-definition video data and one or more second high-definition video data. The first high-definition video data and each second high-definition video data are derived from the same data source or different data sources. The first chip outputs the first high-definition video data to the first high-definition digital display interface, and sends each second high-definition video data to the corresponding second chip through the high-speed transmission interface. The second high-definition video data corresponds to the second chip one by one.

[0007] Each second chip outputs the received second high-definition video data to the second high-definition digital display interface for display.

[0008] In some technical solutions, each second chip sends a frame synchronization signal generated by the corresponding second high-definition digital display interface to the first chip, and the first chip controls the transmission of each second high-definition video data to the high-speed transmission interface according to the frame synchronization signal.

[0009] In some technical solutions, the first chip is provided with a virtual high-definition digital display interface corresponding to the number of second chips, the virtual high-definition digital display interface supports high-definition video data transmission below a preset resolution, and the virtual high-definition digital display interface corresponds to one second chip; each second chip sends the frame synchronization signal to the first chip; the virtual high-definition digital display interface acquires the frame synchronization signal sent by the corresponding second chip, and controls the second high-definition video data received by the corresponding second chip to be transmitted to the high-speed transmission interface according to the frame synchronization signal.

[0010] In some technical solutions, a control switch is further included, which is connected with the first high-definition digital display interface and each second high-definition digital display interface, and is used to control the first high-definition digital display interface and each second high-definition digital display interface to be synchronously turned on.

[0011] In some technical solutions, the first high-definition digital display interface supports high-definition video data output of more than three channels of 4K or higher resolution; and each second high-definition digital display interface supports high-definition video data output of more than one channel of 4K or higher resolution.

[0012] In some technical solutions, the high-speed transmission interface of the first chip supports a master interface working mode, and the high-speed transmission interface of the second chip supports a slave interface working mode; or the high-speed transmission interface of the first chip supports a slave interface working mode, and the high-speed transmission interface of the second chip supports a master interface working mode.

[0013] In some technical solutions, the first high-definition video data and each channel of the second high-definition video data are obtained by dividing display areas by a same data source, the first high-definition video data includes more than two channels of high-definition video data of 4K or higher resolution, and each channel of the second high-definition video data includes more than one channel of high-definition video data of 4K or higher resolution.

[0014] To solve the above technical problems, the application further provides another technical solution:

[0015] A multi-channel high-definition video playing method, comprising the following steps:

[0016] A first chip decodes first high-definition video data and more than one channel of second high-definition video data by using a high-definition video decoding interface on the chip, the first high-definition video data includes more than two channels of high-definition video data of 4K or higher resolution, and each channel of the second high-definition video data includes more than one channel of high-definition video data of 4K or higher resolution; the first high-definition video data and each channel of the second high-definition video data are derived from a same data source or from two different data sources;

[0017] outputting and displaying the first high-definition video data by the first chip through a first high-definition video display interface;

[0018] sending each of the second high-definition video data to the corresponding second chip through a high-speed transmission interface by each of the first chips, the second high-definition video data corresponding to the second chip one by one; the high-speed transmission interface includes, but is not limited to, any one of a PCIE interface, a USB interface, a 2.5 / 5 / 10G Ethernet interface;

[0019] outputting and displaying the corresponding second high-definition video data by each of the second chips through a second high-definition video display interface on the chip.

[0020] In some technical solutions, the method further comprises the steps of:

[0021] previously setting a virtual high-definition digital display interface corresponding to the number of second chip blocks in the first chip, the virtual high-definition digital display interface supporting high-definition video data transmission below a preset resolution;

[0022] each of the second chips sends the frame synchronization signal to the first chip;

[0023] the virtual high-definition digital display interface acquires the frame synchronization signal transmitted by the corresponding second chip, and controls the transmission of each of the second high-definition video data to the high-speed transmission interface according to each of the frame synchronization signals.

[0024] The application further provides another technical solution:

[0025] A computer readable storage medium having a computer program stored thereon, the program being executed by a processor to implement the multi-channel high-definition video playing method according to any one of the above technical solutions.

[0026] Distinguish from prior art, the first chip in the above technical solution decodes the compressed video data into uncompressed first high-definition video data and one or more second high-definition video data through a high-definition video decoding unit, and sends each second high-definition video data to the corresponding second chip through a high-speed transmission interface, and then outputs and displays by the second high-definition digital display interface of each second chip, so as to combine the first high-definition digital display interface of the first chip and the second high-definition digital display interface of each second chip, and form a video playing device capable of simultaneously displaying and playing more high-definition video data. The playing device formed by the combination of two or more chips in the above technical solution can support multi-channel high-definition video data playing (such as 4K video playing), so it can replace some high-performance PC graphics cards, and the implementation cost is lower than that of high-performance PC graphics cards. By adopting the scheme of the application, a plurality of domestic chips can be selected, and mass production is easier to realize. At the same time, the scheme of the application is an embedded scheme, which greatly reduces power consumption compared with PC scheme, and has more market competitiveness.

[0027] The above invention content related records are only summaries of the technical solutions of the present application. In order for those skilled in the art to more clearly understand the technical solutions of the present application, and then can be implemented according to the content recorded in the specification and drawings, and in order for the above-mentioned purposes and other purposes, characteristics and advantages of the present application can be more easily understood, the following is described in conjunction with the specific embodiments of the present application and the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0028] The drawings are only used to show the principles, implementation modes, applications, characteristics and effects of the specific embodiments of the present application and other related contents, and cannot be considered as a limitation of the present application.

[0029] In the drawings of the specification:

[0030] Figure 1 The circuit structure framework of the multi-channel high-definition video playing device described in the specific embodiment;

[0031] Figure 2 The circuit structure framework of the multi-channel high-definition video playing device described in the specific embodiment;

[0032] Figure 3 The circuit structure framework of the multi-channel high-definition video playing device described in another specific embodiment;

[0033] Figure 4 The circuit structure framework of the multi-channel high-definition video playing device described in another specific embodiment;

[0034] Figure 5 The flowchart of the multi-channel high-definition video playing method described in the specific embodiment;

[0035] Figure 6 schematic diagram of the computer readable storage medium described in the detailed description;

[0036] The reference signs involved in the above-mentioned drawings are explained as follows:

[0037] 10, first chip; 20, second chip; 30, display device; 301, display area one; 302, display area two; 303, display area three; 304, display area four;

[0038] 600, computer readable storage medium. DETAILED DESCRIPTION

[0039] To make the possible application scenarios, technical principles, specific schemes that can be implemented, purposes and effects achieved, etc. of the present application clear, the following will be described in detail in combination with the specific embodiments listed and with the accompanying drawings. The embodiments described herein are only used to more clearly illustrate the technical schemes of the present application, and therefore only serve as examples, but cannot limit the protection scope of the present application.

[0040] In this paper, the term "embodiment" means that the specific features, structures or characteristics described in combination with the embodiment can be included in at least one embodiment of the present application. The term "embodiment" appearing at various places in the specification does not necessarily refer to the same embodiment, and does not particularly limit the independence or association between other embodiments. In principle, in the present application, as long as there is no technical contradiction or conflict, the technical features mentioned in each embodiment can be combined in any way to form a corresponding implementable technical scheme.

[0041] Unless otherwise defined, the meaning of the technical terms used herein is the same as that generally understood by those skilled in the art to which the present application belongs; the use of related terms herein is only for the purpose of describing specific embodiments, and is not intended to limit the present application.

[0042] In the description of the present application, the word "and / or" is a description of the logical relationship between the objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases: A exists, B exists, and A and B exist at the same time. In addition, the character " / " in this paper generally represents that the associated objects before and after are a kind of "or" logical relationship.

[0043] In the present application, the terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual quantity, primary and secondary or order relationship between the entities or operations.

[0044] In the present application, the terms "comprise", "contain", "include", or other similar expressions used in the description are intended to encompass non-exclusive inclusion, and the terms do not exclude the presence of additional elements, so that the process, method or product comprising a series of elements can include not only those defined elements, but also other elements not explicitly listed, or elements inherent to such process, method or product.

[0045] In the present application, the terms "greater than", "less than", "exceed" and the like are understood as not including the number itself; the terms "above", "below", "within" and the like are understood as including the number itself. In addition, in the description of the embodiments of the present application, the meaning of "multiple" is more than two (including two), and similar expressions related to "multiple" are also understood in this way, for example, "multiple groups", "multiple times" and the like, unless otherwise explicitly specified.

[0046] In the description of the embodiments of the present application, the spatial-related expressions used, such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "perpendicular", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like, indicate the orientation or positional relationship based on the orientation or positional relationship shown in the specific embodiments or the drawings, and are only for the convenience of describing the specific embodiments of the present application or for the reader to understand, and do not indicate or imply that the indicated device or component must have a specific position, a specific orientation, or be constructed or operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0047] Unless otherwise explicitly specified or limited, in the description of the embodiments of the present application, the terms "mount", "connect", "connect", "fix", "set", and the like should be understood broadly. For example, the "connection" can be fixed connection, or detachable connection, or integral setting; it can be mechanical connection, or electrical connection, or communication connection; it can be direct connection, or indirect connection through intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art to which the present application belongs, the specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0048] Please refer to Figures 1 to 4The embodiment provides a multi-channel high-definition video playing device which can be applied to simultaneous playing of multi-channel video data, for example, can simultaneously output different 4K high-definition video data for multiple display screens, or can output multi-channel high-definition video data for different display areas of one large-size display screen. The multi-channel high-definition video playing device connects two or more chips with high-definition digital display interfaces through a high-speed transmission interface such as a PCIE interface, and cooperatively outputs and displays the decoded high-definition video data by the two or more chips, so that more channels of high-definition video data can be simultaneously output. The number of high-definition video output and display supported by the multi-channel high-definition video playing device can be equivalent to that of an existing high-performance PC video card, and the performance of the multi-channel high-definition video playing device can replace that of the high-performance PC video card, while the cost of the device can be greatly reduced.

[0049] Please refer to Figure 1 The multi-channel high-definition video playing device comprises a first chip 10 and one or more second chips 20; the first chip 10 and each second chip 20 have a high-speed transmission interface.

[0050] The first chip 10 has a high-definition video decoding unit, and can decode compressed video data into uncompressed first high-definition video data and one or more second high-definition video data, wherein the first high-definition video data and each second high-definition video data are derived from the same data source or different data sources (compressed video data). That is, the first chip can decompress multiple compressed video data into first high-definition video data and multi-channel second high-definition video data, or decompress one compressed video data to obtain uncompressed high-definition video data, and then divide the high-definition video data into first high-definition video data and multi-channel second high-definition video data. The second high-definition video data corresponds to the second chip one by one.

[0051] The first chip 10 has a first high-definition digital display interface, and each second chip 20 has a corresponding second high-definition digital display interface. The performance of the first high-definition digital display interface and the second high-definition digital display interface can be the same or different (that is, the number of channels of high-definition video data and the resolution of high-definition video data supported by the display can be the same or different).

[0052] The first chip 10 outputs the first high-definition video data to a display device 30 or a corresponding display area for display through the first high-definition digital display interface, and sends each piece of second high-definition video data to the corresponding second chip 20 through the high-speed transmission interface (for example, a PCIE interface). The first chip 10 can send each piece of second high-definition video data to the corresponding second chip 20 through one high-speed transmission interface, or the first chip 10 sends each piece of second high-definition video data to the corresponding second chip 20 through multiple high-speed transmission interfaces, wherein one piece of second high-definition video data corresponds to one high-speed transmission interface.

[0053] The second high-definition digital display interface of each of the second chips 20 outputs second high-definition video data to a display device or a corresponding display area for display.

[0054] The high-speed transmission interface can be any one of a PCIE interface, a USB (high-speed USB) interface, a 2.5 / 5 / 10G Ethernet interface (that is, an Ethernet interface with a bandwidth of 2.5G or above), and the high-definition digital display interface can be an HDMI interface or a high-definition digital display interface similar to the HDMI. The first chip 10 and each of the second chips 20 can be a video decoding chip or an SOC chip (that is, an embedded processor chip). The first chip 10 and each of the second chips 20 can be two identical embedded processor chips, or the performance of the first chip 10 can be higher than that of the second chip 20.

[0055] As shown in Figure 1 The first chip 10 and each of the second chips 20 have a PCIE interface, and the first chip 10 sends each piece of second high-definition video data to the corresponding second chip 20 through the PCIE interface. The PCIE interface (English full name: peripheral component interconnect express) is a high-speed serial computer expansion bus standard. PCIE is a high-speed serial point-to-point dual-channel high-bandwidth transmission, and the connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth, mainly supporting active power management, error reporting, end-to-end reliable transmission, hot plug, and quality of service (QOS) functions. In this embodiment, the PCIE interface is used for second high-definition video data transmission, thereby ensuring the transmission rate and reliability of the second high-definition video data and avoiding second chip video data parsing and display delay and lag.

[0056] In the above embodiments, the first chip 10 can be the master chip (i.e., the master device) of the playing device, and each of the second chips can be the slave chip (i.e., the slave device). The first chip 10 and the second chips together complete the parsing and output of the multi-channel high-definition video data. That is, the high-speed transmission interface of the first chip 10 is the master interface (i.e., the master control interface), and the high-speed transmission interface of the second chip is the slave interface; or the high-speed transmission interface of the first chip 10 is the slave interface, and the high-speed transmission interface of the second chip is the master interface (i.e., the master control interface).

[0057] The first high-definition digital display interface of the first chip 10 of the multi-channel high-definition video playing device supports the output and display of three or more channels of 4K or higher resolution video data; and the second high-definition digital display interface of each second chip supports the output and display of one or more channels of 4K or higher resolution video data.

[0058] In a specific embodiment, when the second chip is one, the first chip 10 parses three channels of 4K display content in the first high-definition video data, and the other channel of 4K display content (i.e., the second high-definition video data) of the first chip is transmitted to the second chip through the PCIE3.0. In this way, the first chip and the second chip together form a playing device with four channels of 4K video data display output. The playing device formed by the combination of the two chips in the above technical solution can support multi-channel high-definition video playing (e.g., four channels of 4K video playing), and thus can replace some high-performance PC graphics cards, and the implementation cost is lower than that of the high-performance PC graphics card.

[0059] If the playing device formed by the combination of the first chip and the second chip in the embodiment is used, the device cost is lower than that of the PC graphics card with the same performance, and thus the cost of the multi-channel high-definition video playing device can be greatly reduced. In addition, the first chip and the second chip in the above embodiment can use domestic chips, and are not limited by high-end foreign chips, and have strong scalability.

[0060] In other embodiments, the performance of the first chip 10 and the second chip 20 and the number of high-definition video data parsed by each of the first chip 10 and the second chip 20 can be selected as needed. For example, the first chip 10 supports two channels of 4K video data output and display, and the second chip 20 also supports two channels of 4K video data output and display, thereby forming a playing device with four channels of 4K video data display output. Or the first chip 10 supports two channels of 4K video data output and display, and the second chip 20 supports one channel of 4K video data output and display.

[0061] For example, Figure 2As shown, in another embodiment, when the second chip 20 is two, the first chip 10 parses three 4K display contents in the first high-definition video data, and the other two 4K display contents of the first chip (i.e. two second high-definition video data) are transmitted to two different second chips through PCIE3.0, so that the first chip and the two second chips together form a playback device with 5-way 4K video data display output. The above technical solution can support multi-channel high-definition video playback (such as 5-way 4K video playback). In other embodiments, according to the requirements of the playback resources, the number of second chips is selected as needed, and then more channels of high-definition video playback are realized by combining one master chip with multiple slave chips.

[0062] In the present application, the first high-definition video data and each second high-definition video data played by the multi-channel high-definition video playback device can be synchronous data with synchronization requirements or non-synchronous data without synchronization requirements. Taking non-synchronous data as an example, the first high-definition video data and each second high-definition video data come from different data sources, and the first high-definition video data and each second high-definition video data can be independent advertising videos, so that the first chip and each second chip do not need to be synchronized when outputting and displaying. Taking synchronous data of the first high-definition video data and each second high-definition video data as an example, the first high-definition video data and each second high-definition video data can be image data of different positions of the same video, so that the first chip and each second chip need to be synchronized when outputting and displaying.

[0063] In an embodiment, in order to ensure the synchronization of the second high-definition video data output and display of each second chip 20, that is, the synchronization of the first chip sending each second high-definition video data and each second chip outputting and displaying the corresponding second high-definition video data, each second chip 20 sends a frame synchronization signal for controlling the display progress of the corresponding second high-definition video data to the first chip, and the first chip controls the high-speed transmission interface to send each second high-definition video data according to each frame synchronization signal, thereby ensuring the synchronization of each second high-definition video data sending and outputting and displaying. Each frame synchronization signal is generated by the corresponding second high-definition digital display interface when outputting and displaying the second high-definition video data, and is used to control the output and display of the corresponding second high-definition video data.

[0064] As Figure 3As shown, the first chip 10 and each of the second chips 20 are connected through a high-speed transmission interface (for example, a PCIE interface) and a GPIO or other interface or pin, wherein the high-speed transmission interface is mainly used for high-definition video data transmission, and can also transmit display control parameters and firmware updates and the like, and the GPIO or other interface or pin is used for transmitting a frame synchronization signal. The frame synchronization signal is transmitted by each of the second chips 20 to the first chip 10, and the first chip 10 performs display output according to the received frame synchronization signal. In the embodiment, each of the second chips 20 preferably uses the GPIO to send the frame synchronization signal to the first chip 10, and since the GPIO has high real-time performance, the transmission effect of the GPIO is best for the signal with high real-time performance requirement such as the frame synchronization signal.

[0065] As shown in the figure, Figure 3 The first chip 10 is provided with a virtual high-definition digital display interface corresponding to the number of second chips, the virtual high-definition digital display interface supports video data transmission below a preset resolution, and the virtual high-definition digital display interface corresponds to one second chip; the virtual high-definition digital display interface is a software function module, for example, the first chip 10 divides a certain memory space for the virtual high-definition digital display interface to exclusively use, and the virtual high-definition digital display interface supports video data with a resolution of 4K or higher. Each of the second chips 20 sends the frame synchronization signal to the first chip 10 through the GPIO; each of the virtual high-definition digital display interfaces acquires the frame synchronization signal of the corresponding second chip, and controls the transmission of the corresponding second high-definition video data according to the frame synchronization signal. That is, the virtual high-definition digital display interface sends the corresponding second high-definition video data to the high-speed transmission interface for transmission to the corresponding second chip according to the frame synchronization signal. Since the virtual high-definition digital display interface corresponds to one second chip, and the second high-definition video data corresponds to one second chip, the virtual high-definition digital display interface also corresponds to the second high-definition video data.

[0066] The first high-definition video data and each of the second high-definition video data are obtained by dividing a display area according to a same data source, the first high-definition video data includes two or more 4K video data, and each of the second high-definition video data includes one or more 4K video data; the display device or the display area is a sub-display or a display area obtained by dividing a display position of a large display screen.

[0067] As shown in the figure, Figure 4In the embodiment shown in FIG. 1, the multi-high-definition video playing device is used to display multiple video data at different positions of the same display screen. The display screen can be a large-size display screen, which is divided into multiple standard-size display areas: display area one 301, display area two 302, display area three 303, and display area four 304. The display area one 301, the display area two 302, and the display area three 303 are used to display the display output of the first chip, and the display area four 304 is used to display the display output of the second chip.

[0068] The multi-high-definition video playing device can display large high-definition video data, such as 8K high-definition video, through different display areas of the large-size display screen. Specifically, the 8K high-definition video can be evenly divided into four pieces of video data according to the display areas. The video data of one display area is sent to the virtual high-definition digital display interface, which is sent to the second chip and displayed by the corresponding display area of the second chip, i.e., displayed by the display area four 304. The video data of the other three areas of the 8K high-definition video is sent to the corresponding display areas of the first chip, i.e., the display area one 301, the display area two 302, and the display area three 303. Figure 4 Figure 4 The multi-high-definition video playing device can display large high-definition video data, such as 8K high-definition video, through different display areas of the large-size display screen. Specifically, the 8K high-definition video can be evenly divided into four pieces of video data according to the display areas. The video data of one display area is sent to the virtual high-definition digital display interface, which is sent to the second chip and displayed by the corresponding display area of the second chip, i.e., displayed by the display area four 304. The video data of the other three areas of the 8K high-definition video is sent to the corresponding display areas of the first chip, i.e., the display area one 301, the display area two 302, and the display area three 303.

[0069] In another embodiment shown in FIG. 2, the multi-high-definition video playing device is used to display multiple video data at different positions of the same display screen. The display screen can be a large-size display screen, which is divided into multiple standard-size display areas: display area one 301, display area two 302, display area three 303, display area four 304, and display area five 305. The display area one 301, the display area two 302, and the display area three 303 are used to display the display output of the first chip, the display area four 304 is used to display the display output of one of the second chips, and the display area five 305 is used to display the display output of the other second chip.

[0070] At this time, the 8K high-definition video can be evenly divided into five pieces of video data according to the display areas, and two virtual high-definition digital display interfaces are set. The video data of one display area is sent to one of the virtual high-definition digital display interfaces, and the video data of another display area is sent to the other virtual high-definition digital display interface. The virtual high-definition digital display interfaces are sent to the corresponding second chips, respectively, and the corresponding display areas of the two second chips are displayed, i.e., displayed by the display area four 304 and the display area five 305. The video data of the other three areas of the 8K high-definition video is sent to the corresponding display areas of the first chip, i.e., the display area one 301, the display area two 302, and the display area three 303. ​

[0071] To ensure synchronized display of video data, each second chip transmits the frame synchronization signal for display control to the first chip via GPIO. Each virtual high-definition digital display interface of the first chip then outputs the display based on the corresponding frame synchronization signal.

[0072] To ensure video synchronization between the multiple first chips and the various second chips, it is necessary to simultaneously enable the first high-definition digital display interface of the first chip and the second high-definition digital display interface of each second chip.

[0073] Therefore, in one embodiment, the multi-channel high-definition video playback device further includes a control switch, which is connected to the first high-definition digital display interface and each of the second high-definition digital display interfaces respectively, and is used to control the first high-definition digital display interface and each of the second high-definition digital display interfaces to be turned on synchronously.

[0074] In the above embodiments, the PCIE interface is preferably a PCIE 3.0 or higher specification PCIE interface; the first high-definition video data and each of the second high-definition video data are any one of RGB format, YUV422 format, and YUV420 format.

[0075] The PCIe 3.0 interface has a total bandwidth of 32Gbps, so it can support the expansion of several 4K displays. That is, with the bandwidth support, the first chip can send 2, 3 or even more video data channels to the second chips through the PCIe 3.0 interface, and the second chips will then parse and display them, so that the entire multi-channel high-definition video playback device can support more types of high-definition video playback.

[0076] In the above embodiments, the first high-definition video data and each of the second high-definition video data can be RGB format video data, thereby ensuring good video clarity. In some embodiments, to expand the playback of more video streams, the second high-definition video data can support transmission using YUV422 or YUV420 format. Within the PCIe 2.0 bandwidth limits, a maximum of seven channels of 4K@30fps RGB24 video can be output simultaneously. If the video transmission format is changed to 420, even more channels of 4K output can be supported.

[0077] like Figure 5 As shown, in one embodiment, a method for playing multiple high-definition videos is provided. This method includes the following steps:

[0078] S501, decoding, by a first chip, first high-definition video data and one or more second high-definition video data using a high-definition video decoding interface on the chip, the first high-definition video data comprising two or more 4K or higher resolution video data, and each of the second high-definition video data comprising one or more 4K or higher resolution video data; the first high-definition video data and each of the second high-definition video data being derived from the same data source or different data sources;

[0079] S502, outputting and displaying, by the first chip, the first high-definition video data through a first high-definition video display interface;

[0080] S503, sending, by the first chip, each of the second high-definition video data to a corresponding second chip through a high-speed transmission interface, the second high-definition video data corresponding to the second chip one by one;

[0081] S504, outputting and displaying, by each of the second chip, the corresponding second high-definition video data through a second high-definition video display interface on the chip.

[0082] In some embodiments, the first chip and each of the second chip can be connected through PCIE3.0, and each of the second high-definition video data is sent to the corresponding second chip through PCIE3.0, so that a playing device formed by two or more chips can support multi-channel high-definition video playing (e.g., 4-channel 4K video playing), thus replacing some high-performance PC video cards, and the implementation cost is lower than that of high-performance PC video cards.

[0083] In some embodiments, the multi-channel high-definition video playing method further comprises the steps of:

[0084] In the first chip, a virtual high-definition digital display interface corresponding to the number of second chips is pre-set, the virtual high-definition digital display interface supports high-definition video data transmission below a preset resolution, and the virtual high-definition digital display interface corresponds to the second chip one by one;

[0085] Each of the second chips sends the frame synchronization signal to the first chip;

[0086] Each of the virtual high-definition digital display interfaces acquires the frame synchronization signal of the corresponding second chip, and controls the transmission of the corresponding second high-definition video data to the high-speed transmission interface according to the frame synchronization signal.

[0087] In the embodiment, each second chip sends its frame synchronization signal to the first chip, and each virtual high-definition digital display interface controls the display progress of the first high-definition video data according to the frame synchronization signal of the corresponding second chip, so that the transmission of the second high-definition video data by each second chip and the first chip is synchronized with the output display. In the embodiment, each second chip 20 preferably uses a GPIO to send the frame synchronization signal to the first chip 10, and since the real-time performance of the GPIO is high, the transmission effect of the GPIO is the best for the signal with high real-time performance requirement such as the frame synchronization signal.

[0088] As shown in Figure 6 A computer readable storage medium 600 is provided, and a computer program is stored in the computer readable storage medium 600. The program is executed by a processor to implement the multi-channel high-definition video playing method in the above embodiments.

[0089] Finally, it should be noted that the above embodiments have been described in the specification and drawings of the present application, but the patent protection scope of the present application should not be limited. Any technical solution obtained by replacing or modifying the equivalent structure or equivalent process based on the essential concept of the present application, using the content described in the specification and drawings of the present application, or directly or indirectly implementing the technical solutions of the above embodiments in other related technical fields, is included in the patent protection scope of the present application.

Claims

1. A multi-channel high-definition video playing device, characterized in that, The first chip and one or more second chips are included. The first chip and each second chip have a high-speed transmission interface; the first chip has a first high-definition digital display interface, and each second chip has a second high-definition digital display interface. The first chip has a high-definition video decoding unit, which can decode compressed video data into uncompressed first high-definition video data and one or more second high-definition video data; the first high-definition video data and each second high-definition video data are derived from the same data source or different data sources; the first chip outputs the first high-definition video data to the first high-definition digital display interface, and sends each second high-definition video data to the corresponding second chip through the high-speed transmission interface; the second high-definition video data corresponds to the second chip one by one. Each second chip outputs the received second high-definition video data to the second high-definition digital display interface for display. Each second chip sends a frame synchronization signal generated by the corresponding second high-definition digital display interface to the first chip, and the first chip controls the transmission of each second high-definition video data to the high-speed transmission interface according to the frame synchronization signal.

2. The multi-channel high-definition video playing device according to claim 1, wherein, The first chip pre-sets a virtual high-definition digital display interface corresponding to the number of second chips; the virtual high-definition digital display interface supports the transmission of high-definition video data below a preset resolution, and the virtual high-definition digital display interface corresponds to the second chip one by one; each second chip sends the frame synchronization signal to the first chip; each virtual high-definition digital display interface obtains the frame synchronization signal sent by the corresponding second chip, and controls the transmission of the second high-definition video data received by the corresponding second chip to the high-speed transmission interface according to the frame synchronization signal.

3. The multi-high-definition video playing device according to any one of claims 1 to 2, wherein, A control switch is further included, which is connected with the first high-definition digital display interface and each second high-definition digital display interface, and is used to control the synchronous opening of the first high-definition digital display interface and each second high-definition digital display interface.

4. The multi-high definition video playing apparatus of claim 1, wherein, The first high-definition digital display interface supports the output of three or more high-definition video data with a resolution of 4K or higher; each second high-definition digital display interface supports the output of one or more high-definition video data with a resolution of 4K or higher.

5. The multi-high definition video playing apparatus according to claim 1, wherein, The high-speed transmission interface of the first chip supports a master interface working mode, and the high-speed transmission interface of the second chip supports a slave interface working mode; or the high-speed transmission interface of the first chip supports a slave interface working mode, and the high-speed transmission interface of the second chip supports a master interface working mode.

6. The multi-high-definition video playing device of any of claims 1-2, 4-5, wherein, The first high-definition video data and each second high-definition video data are derived from the same data source according to display areas; the first high-definition video data includes two or more high-definition video data with a resolution of 4K or higher, and each second high-definition video data includes one or more high-definition video data with a resolution of 4K or higher.

7. A method for playing multiple high-definition videos, characterized in that, The following steps are included: The first chip decodes first high-definition video data and one or more second high-definition video data using a high-definition video decoding interface on the chip, the first high-definition video data including two or more 4K or higher resolution video data, and each of the second high-definition video data including one or more 4K or higher resolution video data; the first high-definition video data and each of the second high-definition video data is from the same data source or from two different data sources; The first chip outputs and displays the first high-definition video data through a first high-definition video display interface; The first chip sends each of the second high-definition video data to a corresponding second chip through a high-speed transmission interface, and each of the second high-definition video data corresponds to a second chip; Each of the second chip outputs and displays the corresponding second high-definition video data through a second high-definition video display interface on the chip; Each of the second chip sends a frame synchronization signal generated by a corresponding second high-definition digital display interface to the first chip, and the first chip controls transmission of each of the second high-definition video data to the high-speed transmission interface according to the frame synchronization signal.

8. The method of claim 7, wherein, Further comprising steps of: Pre-setting a virtual high-definition digital display interface corresponding to the number of second chip blocks in the first chip, and the virtual high-definition digital display interface supports transmission of high-definition video data below a preset resolution; Each of the second chip sends the frame synchronization signal to the first chip; The virtual high-definition digital display interface acquires the frame synchronization signal transmitted by the corresponding second chip, and controls transmission of each of the second high-definition video data to the high-speed transmission interface according to each of the frame synchronization signal.

9. A computer-readable storage medium, characterized in that, A computer program is stored thereon, and the program is executed by a processor to implement the multi-channel high-definition video playing method of claim 7 or 8.

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