Scan driving circuit, display panel and display device

Abstract

The application relates to a scanning driving circuit, a display panel and a display device. The scanning driving circuit comprises multiple cascaded driving units. The driving unit comprises a first pull-up node, a second pull-up node, a first output module and a second output module connected with the first pull-up node, and a third output module and a fourth output module connected with the second pull-up node. The equivalent capacitance of the first output module is smaller than that of the second output module, the equivalent capacitance of the third output module is equal to that of the first output module, and the equivalent capacitance of the fourth output module is equal to that of the second output module. The gate voltages provided by the first pull-up node and the second pull-up node for the first output module, the second output module, the third output module and the fourth output module are consistent. In this way, the gate voltages of the odd-numbered row and the even-numbered row output modules are consistent when the scanning signals are output, the bright and dark stripes of the interlaced display are avoided, and the display effect is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the display technical field, and in particular to a scanning driving circuit, a display panel and a display device. BACKGROUND

[0002] Liquid Crystal Display (LCD) has been widely applied due to its advantages such as thin body, power saving, no radiation and so on. For example, it can be widely applied in television, mobile phone, Personal Digital Assistant (PDA), digital camera, computer, notebook computer and so on, and it occupies a dominant position in the display field.

[0003] In the traditional active matrix liquid crystal display, the row scanning signal is realized by an external integrated circuit board (IC), and when the Gate Driver less (GDL) technology is used for driving, a scanning driving circuit is made by using the same process as that of a Thin Film Transistor (TFT), and on the basis of providing several control signals by the external circuit, the row-by-row scanning driving function can be realized. Therefore, the GDL circuit is used for driving to save the scanning driving related integrated circuit, and the manufacturing cost of the liquid crystal display is reduced.

[0004] However, in the existing GDL circuit, a shared pull-up node is usually used to provide a gate voltage for multiple output circuits. Since the clock signals input into each output circuit are not synchronized, and the rising edge and the falling edge of each clock signal will couple the voltage of the pull-up node, the gate voltages of different output circuits are inconsistent when the scanning signals are output, so that bright and dark stripes appear on the liquid crystal display, and the display effect of the liquid crystal display is reduced.

[0005] Therefore, how to improve the bright and dark stripes on the liquid crystal display and improve the display effect has become a technical problem to be solved. SUMMARY

[0006] The present application provides a scanning driving circuit, a display panel and a display device to solve the problem that the existing GDL circuit causes bright and dark stripes on the liquid crystal display, and reduces the display effect of the liquid crystal display.

[0007] In a first aspect, the present application provides a scan driving circuit, comprising a plurality of cascaded driving units, each of the driving units comprising: a first pull-up node, a second pull-up node, a first output module and a second output module connected to the first pull-up node, a third output module and a fourth output module connected to the second pull-up node;

[0008] The first pull-up node is configured to provide a gate voltage for the first output module and the second output module, the first output module is configured to output a first scan signal according to the gate voltage and a first clock signal, and the second output module is configured to output a second scan signal according to the gate voltage and a second clock signal.

[0009] The second pull-up node is configured to provide a gate voltage for the third output module and the fourth output module, the second output module is configured to output a third scan signal according to the gate voltage and a third clock signal, and the fourth output module is configured to output a fourth scan signal according to the gate voltage and a fourth clock signal.

[0010] The first clock signal, the second clock signal, the third clock signal and the fourth clock signal are provided by a timing control circuit, and the timing control circuit is connected to the scan driving circuit through a clock signal line; the first scan signal, the second scan signal, the third scan signal and the fourth scan signal are used to drive four rows of adjacent pixel units to emit light.

[0011] The equivalent capacitance of the first output module is smaller than the equivalent capacitance of the second output module, the equivalent capacitance of the third output module is equal to the equivalent capacitance of the first output module, and the equivalent capacitance of the fourth output module is equal to the equivalent capacitance of the second output module, so that the gate voltages provided by the first pull-up node and the second pull-up node for the first output module, the second output module, the third output module and the fourth output module remain consistent.

[0012] Optionally, the rising edge of the first clock signal is synchronized with the rising edge of the second clock signal, the rising edge of the third clock signal is synchronized with the rising edge of the fourth clock signal, and the rising edges of the third clock signal and the fourth clock signal are after the rising edges of the first clock signal and the second clock signal.

[0013] The falling edge of the first clock signal is before the falling edge of the second clock signal, the falling edge of the second clock signal is before the falling edge of the third clock signal, and the falling edge of the third clock signal is before the falling edge of the fourth clock signal.

[0014] Optionally, the first output module, the second output module, the third output module and the fourth output module each comprise a first thin film transistor, the first thin film transistor comprising a substrate, a first metal layer, an insulating layer, a second metal layer, a third metal layer and a protective layer;

[0015] The protective layer covers the upper end faces of the second metal layer and the third metal layer, the second metal layer and the third metal layer cover the upper end face of the insulating layer, the insulating layer covers the upper end face of the first metal layer, and the first metal layer covers the upper end face of the substrate.

[0016] The coverage area of the second metal layer and the coverage area of the third metal layer each overlap the coverage area of the first metal layer.

[0017] The coverage area of the third metal layer in the first output module is smaller than the coverage area of the third metal layer in the second output module, and the coverage area of the third metal layer in the third output module is smaller than the coverage area of the third metal layer in the fourth output module.

[0018] Optionally, the coverage area of the third metal layer is proportional to the equivalent capacitance of the output module in which the third metal layer is located.

[0019] Optionally, the driving unit further comprises a first pull-up module and a second pull-up module.

[0020] The first pull-up module is connected with the first pull-up node, and the first pull-up module is configured to pre-charge the first pull-up node according to a first level signal.

[0021] The second pull-up module is connected with the second pull-up node, and the second pull-up module is configured to pre-charge the second pull-up node according to a second level signal, and the high level of the first level signal is earlier than the high level of the second level signal.

[0022] Optionally, the driving unit further comprises a first pull-up control module, a first pull-down maintenance module, a second pull-up control module, a second pull-down maintenance module, a first pull-down node and a second pull-down node.

[0023] The first pull-up control module and the first pull-down maintenance module are each connected with the first pull-down node, the first pull-up control module is configured to control the level of the first pull-down node according to a third level signal, and the first pull-down maintenance module is configured to control the level of the first pull-down node according to a first power supply signal.

[0024] The second pull-up control module and the second pull-down maintaining module are connected with the second pull-down node, the second pull-up control module is used for controlling the level of the second pull-down node according to the third level signal, and the second pull-down maintaining module is used for controlling the level of the first pull-down node according to the second power supply signal.

[0025] The high level signal of the third level signal is prior to the first level signal and the second level signal, the first power supply signal and the second power supply signal are provided by the timing control circuit, and the level signal of the first power supply signal and the level signal of the second power supply signal are opposite.

[0026] Optionally, the driving unit further comprises a first pull-down module, a second pull-down module, a third pull-down module, a fourth pull-down module, a fifth pull-down module, a sixth pull-down module, a seventh pull-down module and an eighth pull-down module.

[0027] The first pull-down module, the third pull-down module, the sixth pull-down module and the seventh pull-down module are connected with the first pull-down node.

[0028] The second pull-down module, the fourth pull-down module, the fifth pull-down module and the eighth pull-down module are connected with the second pull-down node.

[0029] The first pull-down module and the second pull-down module are used for pulling down the output signal of the first output module, the third pull-down module and the fourth pull-down module are used for pulling down the output signal of the second output module, the fifth pull-down module and the sixth pull-down module are used for pulling down the output signal of the third output module, and the seventh pull-down module and the eighth pull-down module are used for pulling down the output signal of the fourth output module.

[0030] Optionally, the driving unit further comprises a first pull-down control module and a second pull-down control module.

[0031] The first pull-down control module is connected with the first pull-up node, and the first pull-down control module is used for controlling the pull-down of the first pull-up node according to a fourth level signal.

[0032] The second pull-down control module is connected with the second pull-up node, and the second pull-down control module is used for controlling the pull-down of the second pull-up node according to a fifth level signal, and the high level of the fourth level signal is prior to the high level of the fifth level signal.

[0033] In a second aspect, the embodiments of the present application further provide a display panel, comprising a pixel unit and the scan driving circuit according to any one of the first aspect.

[0034] Each of the drive units in the scan driving circuit is connected with four rows of adjacent pixel units respectively.

[0035] In a third aspect, the embodiments of the present application further provide a display device, characterized in that comprising a timing control circuit and the display panel as described in the second aspect.

[0036] The timing control circuit is connected with the display panel through a clock signal line.

[0037] In the embodiments of the present application, the scan driving circuit comprises a plurality of cascaded drive units, and each drive unit comprises a first pull-up node, a second pull-up node, a first output module and a second output module connected with the first pull-up node, and a third output module and a fourth output module connected with the second pull-up node; the first pull-up node is configured to provide a gate voltage for the first output module and the second output module; the first output module is configured to output a first scan signal according to the gate voltage and a first clock signal; the second output module is configured to output a second scan signal according to the gate voltage and a second clock signal; the second pull-up node is configured to provide a gate voltage for the third output module and the fourth output module; the second output module is configured to output a third scan signal according to the gate voltage and a third clock signal; the fourth output module is configured to output a fourth scan signal according to the gate voltage and a fourth clock signal; the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are provided by a timing control circuit; the timing control circuit is connected with the scan driving circuit through a clock signal line; the first scan signal, the second scan signal, the third scan signal and the fourth scan signal are used to drive four rows of adjacent pixel units to emit light; the equivalent capacitance of the first output module is smaller than the equivalent capacitance of the second output module; the equivalent capacitance of the third output module is equal to the equivalent capacitance of the first output module; and the equivalent capacitance of the fourth output module is equal to the equivalent capacitance of the second output module, so that the gate voltages provided by the first pull-up node and the second pull-up node for the first output module, the second output module, the third output module and the fourth output module are consistent. In this way, the equivalent capacitances of the first output module, the second output module, the third output module and the fourth output module in each drive unit can be adjusted, so that the equivalent capacitances corresponding to the output modules in the odd-numbered rows are smaller than the equivalent capacitances corresponding to the output modules in the even-numbered rows, so as to keep the gate voltages of the output modules in the odd-numbered rows and the even-numbered rows consistent when the scan signals are output, and further make the amounts of charges passing through the pixels in the odd-numbered rows and the even-numbered rows in the same charging time be the same, thereby avoiding the appearance of bright and dark stripes in interlaced display, and improving the display effect. BRIEF DESCRIPTION OF DRAWINGS

[0038] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application.

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the accompanying drawings required to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

[0040] Figure 1 A structural schematic diagram of a driving unit provided by an embodiment of the present application is shown in FIG. 1.

[0041] Figure 2 A waveform diagram of a voltage of a first pull-up node provided by an embodiment of the present application is shown in FIG. 2.

[0042] Figure 3 A waveform diagram of a voltage of a first pull-up node provided by an embodiment of the present application is shown in FIG. 2.

[0043] Figure 4 A timing sequence diagram of a clock signal and a scan signal provided by an embodiment of the present application is shown in FIG. 3.

[0044] Figure 5 A structural schematic diagram of a first thin film transistor provided by an embodiment of the present application is shown in FIG. 4.

[0045] Figure 6 A circuit diagram of a driving unit provided by an embodiment of the present application is shown in FIG. 5.

[0046] Figure 7 A timing sequence diagram of signals provided by an embodiment of the present application is shown in FIG. 6.

[0047] Figure 8 A timing sequence diagram of signals in a driving unit provided by an embodiment of the present application is shown in FIG. 7.

[0048] Figure 9 A structural schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 8.

[0049] Figure 10 A structural schematic diagram of a display device provided by an embodiment of the present application is shown in FIG. 9.

[0050] The reference numerals are explained as follows: 100, driving unit; 101, first output module; 102, second output module; 103, third output module; 104, fourth output module; 105, first pull-up module; 106, second pull-up module; 107, first pull-up control module; 108, first pull-down maintenance module; 109, second pull-up control module; 110, second pull-down maintenance module; 111, first pull-down module; 112, second pull-down module; 113, third pull-down module; 114, fourth pull-down module; 115, fifth pull-down module; 116, sixth pull-down module; 117, seventh pull-down module; 118, eighth pull-down module; 119, first pull-down control module; 120, second pull-down control module; 121, first reset module; 122, second reset module; 200, display panel; 300, pixel unit; 400, display device; 500, timing control circuit. DETAILED DESCRIPTION

[0051] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0052] Reference is made to Figure 1 The scan driving circuit includes a plurality of cascaded driving units 100, and each driving unit 100 includes: a first pull-up node Q(N / N+1), a second pull-up node Q(N+2 / N+3), a first output module 101 and a second output module 102 connected with the first pull-up node Q(N / N+1), and a third output module 103 and a fourth output module 104 connected with the second pull-up node Q(N+2 / N+3).

[0053] The first pull-up node Q(N / N+1) is configured to provide a gate voltage for the first output module 101 and the second output module 102, the first output module 101 is configured to output a first scan signal Gout(n) according to the gate voltage and a first clock signal CLK(n), and the second output module 102 is configured to output a second scan signal Gout(n+1) according to the gate voltage and a second clock signal CLK(n+1).

[0054] The second pull-up node Q(N+2 / N+3) is used to provide a gate voltage for the third output module 103 and the fourth output module 104, the second output module 102 is used to output a third scan signal Gount(n+2) according to the gate voltage and a third clock signal CLK(n+2), and the fourth output module 104 is used to output a fourth scan signal Gount(n+3) according to the gate voltage and a fourth clock signal CLK(n+3).

[0055] The first clock signal CLK(n), the second clock signal CLK(n+1), the third clock signal CLK(n+2) and the fourth clock signal CLK(n+3) are all provided by a timing control circuit, and the timing control circuit is connected with the scan driving circuit through a clock signal line; the first scan signal Gount(n), the second scan signal Gount(n+1), the third scan signal Gount(n+2) and the fourth scan signal Gount(n+3) are used to drive four rows of adjacent pixel units to emit light.

[0056] The equivalent capacitance of the first output module 101 is less than the equivalent capacitance of the second output module 102, the equivalent capacitance of the third output module 103 is equal to the equivalent capacitance of the first output module 101, and the equivalent capacitance of the fourth output module 104 is equal to the equivalent capacitance of the second output module 102, so that the gate voltages provided by the first pull-up node Q(N / N+1) and the second pull-up node Q(N+2 / N+3) for the first output module 101, the second output module 102, the third output module 103 and the fourth output module 104 are consistent.

[0057] Specifically, the first output module 101, the second output module 102, the third output module 103 and the fourth output module 104 are all composed of one or more thin film transistors. The first pull-up node Q(N / N+1) is a pull-up node shared by the first output module 101 and the second output module 102, and is used to provide a gate voltage for the first output module 101 and the second output module 102. The second pull-up node Q(N+2 / N+3) is a pull-up node shared by the third output module 103 and the fourth output module 104, and is used to provide a gate voltage for the third output module 103 and the fourth output module 104.

[0058] It should be noted that the thin film transistors in each output module can be equivalent to a capacitor structure, and the equivalent capacitance will have a capacitive coupling effect on the first pull-up node Q(N / N+1) and the second pull-up node Q(N+2 / N+3). The voltage difference caused by capacitive coupling can be calculated by the following formula:

[0059] ΔV=(Von-Voff)*(CT6) / (CT6+…+CT6’)

[0060] Wherein, AV represents the size of the pressure difference caused by coupling, Von represents the opening voltage of the clock signal, Voff represents the closing voltage of the clock signal, CT6 represents the equivalent capacitance of the output module, CT6+…+CT6’ represents the sum of all relevant capacitances on the entire driving unit. According to the above formula, when the difference between the opening voltage and the closing voltage of the clock signal is constant, the greater the ratio of the equivalent capacitance of the output module to the sum of all relevant capacitances on the entire driving unit, the greater the pressure difference caused by the capacitive coupling; the smaller the ratio of the equivalent capacitance of the output module to the sum of all relevant capacitances on the entire driving unit, the smaller the pressure difference caused by the capacitive coupling.

[0061] In the prior art, the equivalent capacitances corresponding to the output modules of odd rows (equivalent to the first output module 101 and the third output module 103) and the output modules of even rows (equivalent to the second output module 102 and the fourth output module 104) are the same, so when the first clock signal CLK(n) and the second clock signal CLK(n+1) output high levels to the first output module 101 and the second output module 102 in turn, the voltage of the first pull-up node Q(N / N+1) will produce two times of capacitive coupling. Assuming that the pressure difference between the opening voltage and the closing voltage of the first clock signal CLK(n) and the second clock signal CLK(n+1) is the same, the pressure difference caused by the two times of capacitive coupling is also the same. When the first clock signal CLK(n) and the second clock signal CLK(n+1) output low levels to the first output module 101 and the second output module 102 in turn, the voltage of the first pull-up node Q(N / N+1) will also produce two times of capacitive coupling. Assuming that the pressure difference between the opening voltage and the closing voltage of the first clock signal CLK(n) and the second clock signal CLK(n+1) is the same, the pressure difference caused by the two times of capacitive coupling is also the same, so that the voltage of the first pull-up node Q(N / N+1) presents three sections, as shown in the following figure. Figure 2 As such, the gate voltage of the first output module 101 will be higher than the gate voltage of the second output module 102 (i.e. the voltage at point D is higher than the voltage at point E), causing a large difference between the rise time and the fall time of the first scan signal Gount(n) and the second scan signal Gount(n+1), and further causing the number of charges passing through the pixels of odd rows and the pixels of even rows to be different in the same charging time. In the picture display, it finally appears as a bright and dark horizontal stripe of interlaced display, which greatly affects the visual perception. Similarly, the same situation also occurs for the third output module 103 and the fourth output module 104.

[0062] In the embodiment, the equivalent capacitances of the first output module 101, the second output module 102, the third output module 103 and the fourth output module 104 in each driving unit 100 can be adjusted, so that the equivalent capacitances corresponding to the output modules in the odd-numbered rows are smaller than the equivalent capacitances corresponding to the output modules in the even-numbered rows. In this way, the capacitive coupling of the output modules in the odd-numbered rows to the first pull-up node Q(N / N+1) and the second pull-up node Q(N+2 / N+3) can be reduced as much as possible and can be ignored, and the capacitive coupling of the output modules in the even-numbered rows to the first pull-up node Q(N / N+1) and the second pull-up node Q(N+2 / N+3) can be increased, so that the voltages of the first pull-up node Q(N / N+1) and the second pull-up node Q(N+2 / N+3) are as shown in FIG. 10. In this way, the gate voltages of the output modules in the odd-numbered rows and the even-numbered rows are consistent (i.e., the voltage at the point D is equal to the voltage at the point E) when the output modules output the scanning signals, and thus the amount of charges passing through the pixels in the odd-numbered rows and the even-numbered rows in the same charging time is the same, so that the bright and dark stripes caused by the interlaced display are avoided, and thus the display effect is improved. Figure 3

[0063] Further, the rising edge of the first clock signal CLK(n) is synchronized with the rising edge of the second clock signal CLK(n+1), the rising edge of the third clock signal CLK(n+2) is synchronized with the rising edge of the fourth clock signal CLK(n+3), and the rising edges of the third clock signal CLK(n+2) and the fourth clock signal CLK(n+3) are after the rising edges of the first clock signal CLK(n) and the second clock signal CLK(n+1).

[0064] The falling edge of the first clock signal CLK(n) is before the falling edge of the second clock signal CLK(n+1), the falling edge of the second clock signal CLK(n+1) is before the falling edge of the third clock signal CLK(n+2), and the falling edge of the third clock signal CLK(n+2) is before the falling edge of the fourth clock signal CLK(n+3).

[0065] In an embodiment, the timing of the first clock signal CLK(n), the second clock signal CLK(n+1), the third clock signal CLK(n+2) and the fourth clock signal CLK(n+3) output by the timing control circuit can be adjusted, so that the timing relationship of the first clock signal CLK(n), the second clock signal CLK(n+1), the third clock signal CLK(n+2) and the fourth clock signal CLK(n+3) satisfies Figure 4 ​The first pull-up node Q(N / N+1) can directly rise from the B point voltage to the C point voltage without twice capacitive coupling when the rising edges of the first clock signal CLK(n) and the second clock signal CLK(n+1) arrive, which is more conducive to the stability of the voltage of the first pull-up node Q(N / N+1). Meanwhile, it can be ensured that the first output module 101 can normally output the first scan signal Gout(n) from the rising edge of the first clock signal CLK(n), so as to ensure the normal output of subsequent scan signals. Similarly, the voltage of the second pull-up node Q(N+2 / N+3) can directly rise from the B point voltage to the C point voltage without twice capacitive coupling when the rising edges of the third clock signal CLK(n+2) and the fourth clock signal CLK(n+3) arrive, which is more conducive to the stability of the voltage of the second pull-up node Q(N+2 / N+3).

[0066] Further, referring to Figure 5 The first output module 101, the second output module 102, the third output module 103 and the fourth output module 104 each include a first thin film transistor, and the first thin film transistor includes a substrate, a first metal layer, an insulating layer, a second metal layer, a third metal layer and a protective layer.

[0067] The protective layer covers the upper end faces of the second metal layer and the third metal layer, the second metal layer and the third metal layer cover the upper end face of the insulating layer, the insulating layer covers the upper end face of the first metal layer, and the first metal layer covers the upper end face of the substrate.

[0068] The covering area of the second metal layer and the covering area of the third metal layer each overlap the covering area of the first metal layer.

[0069] The covering area of the third metal layer in the first output module 101 is smaller than the covering area of the third metal layer in the second output module 102, and the covering area of the third metal layer in the third output module 103 is smaller than the covering area of the third metal layer in the fourth output module 104.

[0070] In the prior art, the equivalent capacitance of the output module in the odd row is equal to the equivalent capacitance of the output module in the even row, that is, the coverage area of the second metal layer in the first thin film transistor in the odd row is equal to the coverage area of the third metal layer in the even row, and the coverage area of the third metal layer in the first thin film transistor in the odd row is equal to the coverage area of the third metal layer in the even row. In the embodiment, the coverage area of the second metal layer in the first thin film transistor in the odd row is still equal to the coverage area of the third metal layer in the even row, but the coverage area of the third metal layer in the first thin film transistor in the odd row is reduced, and the coverage area of the third metal layer in the first thin film transistor in the even row is increased, so that the effect of reducing the equivalent capacitance of the output module in the odd row and increasing the equivalent capacitance of the output module in the even row is achieved.

[0071] Further, the coverage area of the third metal layer is proportional to the equivalent capacitance of the output module in which the third metal layer is located.

[0072] According to the formula for calculating the voltage difference caused by the capacitive coupling, when the difference between the on voltage and the off voltage of the clock signal is unchanged, the greater the ratio of the equivalent capacitance of the output module to the sum of all relevant capacitances on the entire driving unit 100, the greater the voltage difference caused by the capacitive coupling; the smaller the ratio of the equivalent capacitance of the output module to the sum of all relevant capacitances on the entire driving unit 100, the smaller the voltage difference caused by the capacitive coupling. Therefore, if the capacitances of other thin film transistors on the entire driving unit 100 are unchanged, and only the coverage area of the third metal layer on the first thin film transistor is adjusted, increasing the coverage area of the third metal layer will result in an increase in the equivalent capacitance of the output module in which the third metal layer is located, and further increase the voltage difference caused by the capacitive coupling; reducing the coverage area of the third metal layer will result in a decrease in the equivalent capacitance of the output module in which the third metal layer is located, and further reduce the voltage difference caused by the capacitive coupling.

[0073] Further, continuing to refer to Figure 1 , the driving unit 100 further comprises a first pull-up module 105 and a second pull-up module 106;

[0074] The first pull-up module 105 is connected with the first pull-up node Q(N / N+1), and the first pull-up module 105 is configured to pre-charge the first pull-up node Q(N / N+1) according to the first-stage transmission signal.

[0075] The second pull-up module 106 is connected with the second pull-up node Q(N+2 / N+3), and the second pull-up module 106 is configured to pre-charge the second pull-up node Q(N+2 / N+3) according to the second-stage transmission signal. The high level of the first-stage transmission signal is prior to the high level of the second-stage transmission signal.

[0076] In an embodiment, the first pull-up node Q(N / N+1) can be pre-charged by the first pull-up module 105 and the first stage transmission signal. Specifically, when the first stage transmission signal outputs a high level, the thin film transistor in the first pull-up module 105 can be turned on, and then the first pull-up node Q(N / N+1) is pre-charged. Similarly, the second pull-up node Q(N+2 / N+3) can be pre-charged by the second pull-up module 106 and the second stage transmission signal. Specifically, when the second stage transmission signal outputs a high level, the thin film transistor in the second pull-up module 106 can be turned on, and then the second pull-up node Q(N+2 / N+3) is pre-charged.

[0077] In this way, after the first pull-up node Q(N / N+1) and the second pull-up node Q(N+2 / N+3) enter the pre-charged state, the voltage of the first pull-up node Q(N / N+1) and the second pull-up node Q(N+2 / N+3) can be coupled into a high level state with the input of the clock signal, and then the corresponding output module is controlled to output the scan signal.

[0078] Further, continuing to refer to Figure 1 , the driving unit 100 further comprises: a first pull-up control module 107, a first pull-down maintenance module 108, a second pull-up control module 109, a second pull-down maintenance module 110, a first pull-down node Qb_O(N) and a second pull-down node Qb_E(N);

[0079] The first pull-up control module 107 and the first pull-down maintenance module 108 are connected with the first pull-down node Qb_O(N), the first pull-up control module 107 is used for controlling the level of the first pull-down node Qb_O(N) according to the third stage transmission signal, and the first pull-down maintenance module 108 is used for controlling the level of the first pull-down node Qb_O(N) according to the first power signal;

[0080] The second pull-up control module 109 and the second pull-down maintenance module 110 are connected with the second pull-down node Qb_E(N), the second pull-up control module 109 is used for controlling the level of the second pull-down node Qb_E(N) according to the third stage transmission signal, and the second pull-down maintenance module 110 is used for controlling the level of the first pull-down node Qb_O(N) according to the second power signal;

[0081] The high level signal of the third stage transmission signal is earlier than the first stage transmission signal and the second stage transmission signal, the first power signal and the second power signal are provided by the timing control circuit, and the level signal of the first power signal and the level signal of the second power signal are opposite.

[0082] In an embodiment, the level of the first pull-down node Qb_O(N) can be controlled by the first pull-up control module 107 and the first pull-down maintenance module 108, and the level of the second pull-down node Qb_E(N) can be controlled by the second pull-up control module 109 and the second pull-down maintenance module 110. Specifically, when the high level of the third level signal is input to the first pull-up control module 107 and the second pull-up control module 109 at the same time, the thin film transistors in the first pull-up control module 107 and the second pull-up control module 109 are turned on, so that the levels of the first pull-down node Qb_O(N) and the second pull-down node Qb_E(N) are pulled down to VSS2, so that the pull-down module connected to the first pull-down node Qb_O(N) and the second pull-down node Qb_E(N) does not work, and the subsequent first pull-up module 105 and the second pull-up module 106 can normally output, and the corresponding four output modules can also normally output. When the first power signal or the second power signal outputs a high level, the first pull-down node Qb_O(N) or the second pull-down node Qb_E(N) can obtain a high level to start the corresponding pull-down module to work, thereby realizing the function of pull-down maintenance.

[0083] Further, with reference to Figure 1 , the driving unit 100 further comprises: a first pull-down module 111, a second pull-down module 112, a third pull-down module 113, a fourth pull-down module 114, a fifth pull-down module 115, a sixth pull-down module 116, a seventh pull-down module 117 and an eighth pull-down module 118;

[0084] The first pull-down module 111, the third pull-down module 113, the sixth pull-down module 116 and the seventh pull-down module 117 are all connected to the first pull-down node Qb_O(N);

[0085] The second pull-down module 112, the fourth pull-down module 114, the fifth pull-down module 115 and the eighth pull-down module 118 are all connected to the second pull-down node Qb_E(N);

[0086] The first pull-down module 111 and the second pull-down module 112 are used for pulling down the output signal of the first output module 101, the third pull-down module 113 and the fourth pull-down module 114 are used for pulling down the output signal of the second output module 102, the fifth pull-down module 115 and the sixth pull-down module 116 are used for pulling down the output signal of the third output module 103, and the seventh pull-down module 117 and the eighth pull-down module 118 are used for pulling down the output signal of the fourth output module 104.

[0087] In an embodiment, the first power signal and the second power signal output high level alternately, that is, when the first power signal outputs high level, the second power signal outputs low level; when the first power signal outputs low level, the second power signal outputs high level. Since the first pull-down module 111, the third pull-down module 113, the sixth pull-down module 116 and the seventh pull-down module 117 are connected with the first pull-down node Qb_O(N), and the second pull-down module 112, the fourth pull-down module 114, the fifth pull-down module 115 and the eighth pull-down module 118 are connected with the second pull-down node Qb_E(N), thus, whether the first power signal is high level or the second power signal is high level, the output signal of the first output module 101, the output signal of the second output module 102, the output signal of the third output module 103 and the output signal of the fourth output module 104 can be pulled down, thereby realizing the pull-down function of the output signals. The reason for setting the first power signal and the second power signal to output high level alternately is to avoid the first pull-down maintenance module 108 or the second pull-down maintenance module 110 from being burned out due to the long-time output of high level of the first power signal or the second power signal.

[0088] In actual circuit operation, after the first scan signal Gount(n), the second scan signal Gount(n+1), the third scan signal Gount(n+2) and the fourth scan signal Gount(n+3) are output, it is assumed that the second power signal is output as high level, at this time the second pull-down maintenance module 110 continuously works, keeping the second pull-down node Qb_E(N) as high level, at this time the second pull-down module 112, the fourth pull-down module 114, the fifth pull-down module 115 and the eighth pull-down module 118 normally work, and can continuously pull down the voltage of the first scan signal Gount(n), the second scan signal Gount(n+1), the third scan signal Gount(n+2) and the fourth scan signal Gount(n+3), and the voltage of the first pull-up node Q(N / N+1) and the second pull-up node Q(N+2 / N+3) to VSS1 / VSS2. Before the first pull-up node Q(N / N+1) and the second pull-up node Q(N+2 / N+3) are pre-charged, the third level signal can be input as a pull-up control signal, at this time the second pull-up control module 109 will pull down the signal of the second pull-down node Qb_E(N) to VSS2, at this time the corresponding second pull-down module 112, the fourth pull-down module 114, the fifth pull-down module 115 and the eighth pull-down module 118 do not work, and since the first power signal is low level, the first pull-down module 111, the third pull-down module 113, the sixth pull-down module 116 and the seventh pull-down module 117 also do not work. In this way, it can be ensured that the first pull-up module 105 and the second pull-up module 106 can normally output, and the corresponding four output modules can also normally output.

[0089] Further, with continued reference to Figure 1 , the driving unit 100 further comprises a first pull-down control module 119 and a second pull-down control module 120;

[0090] The first pull-down control module 119 is connected with the first pull-up node Q(N / N+1), and the first pull-down control module 119 is configured to perform pull-down control on the first pull-up node Q(N / N+1) according to the fourth level transmission signal.

[0091] The second pull-down control module 120 is connected with the second pull-up node Q(N+2 / N+3), and the second pull-down control module 120 is configured to perform pull-down control on the second pull-up node Q(N+2 / N+3) according to the fifth level transmission signal, and the high level of the fourth level transmission signal is prior to the high level of the fifth level transmission signal.

[0092] In an embodiment, the voltage of the first pull-up node Q(N / N+1) can also be controlled by the first pull-down control module 119, and the voltage of the second pull-up node Q(N+2 / N+3) can also be controlled by the second pull-down control module 120. Specifically, when the fourth level transmission signal outputs a high level, the thin film transistor in the first pull-down control module 119 can be turned on, so that the first pull-up node Q(N / N+1) can be pulled down to VSS2 through the first pull-down control module 119. Similarly, when the fifth level transmission signal outputs a high level, the thin film transistor in the second pull-down control module 120 can be turned on, so that the second pull-up node Q(N+2 / N+3) can be pulled down to VSS2 through the second pull-down control module 120. In this way, the first pull-up node Q(N / N+1) and the second pull-up node Q(N+2 / N+3) can be pulled down to avoid leakage current accumulation.

[0093] Of course, the driving unit 100 further comprises a first reset module 121 and a second reset module 122, which are configured to perform pull-down action on the first pull-up node Q(N / N+1) and the second pull-up node Q(N+2 / N+3) according to a reset signal Reset in each frame, so as to avoid leakage current accumulation.

[0094] In an embodiment, the circuit diagram of the nth driving unit 100 in the driving circuit can be as shown in Figure 6 The nth driving unit comprises:

[0095] Output module 1, output module 2, output module 3 and output module 4 (i.e. the first output module 101, the second output module 102, the third output module 103 and the fourth output module 104 in the foregoing text): the output module includes a thin film transistor T6, or includes a thin film transistor T6+T6N; the clock signals input by the output module 1, the output module 2, the output module 3 and the output module 4 in turn are CLK(N), CLK(N+1), CLK(N+2), CLK(N+3); the scanning signals output by the output module 1, the output module 2, the output module 3 and the output module 4 in turn are Gout(n), Gout(n+1), Gout(n+2), Gout(n+3), when the first pull-up node Q(N / N+1) and the second pull-up node Q(N+2 / N+3) are high, the thin film transistor in each output module is turned on, and the periodic signals generated by the clock signals CLK(N), CLK(N+1), CLK(N+2), CLK(N+3) are sequentially flushed into each output module, so that the signal output of each output module is realized. It should be noted that the output module 1 and the output module 3 will also output the stage transmission signals Carry(n) and Carry(n+2) while outputting the scanning signals, which are used by the subsequent stage driving unit.

[0096] The pull-up module 1 and the pull-up module 2 (i.e. the first pull-up module 105 and the second pull-up module 106 in the foregoing text): the pull-up module includes a thin film transistor T1. The pull-up module 1 inputs the first stage transmission signal Carry(n-6) signal, opens the pull-up module 1 through Carry(n-6), and precharges the first pull-up node Q(N / N+1). The pull-up module 2 inputs the second stage transmission signal Carry(n-4) signal, opens the pull-up module 2 through Carry(n-4), and precharges the second pull-up node Q(N+2 / N+3).

[0097] The pull-up control module 1 and the pull-up control module 2 (i.e. the first pull-up control module 107 and the second pull-up control module 109 in the foregoing text): the pull-up control module can include a thin film transistor T5; the pull-up control module 1 inputs the third stage transmission signal Carry(n-8) signal, the third stage transmission signal Carry(n-8) opens the pull-up control module 1, pulls down the first pull-down node Qb_O(N) to VSS2, so that the pull-down module 1, the pull-down module 3, the pull-down module 6 and the pull-down module 7 do not work. The pull-up control module 2 inputs the third stage transmission signal Carry(n-8) signal, the third stage transmission signal Carry(n-8) opens the pull-up control module 2, pulls down the second pull-down node Qb_E(N) to VSS2, so that the pull-down module 2, the pull-down module 4, the pull-down module 5 and the pull-down module 8 do not work. Thus, it is ensured that the pull-up module 1 and the pull-up module 2 can normally output, and the corresponding output module 1, the output module 2, the output module 3 and the output module 4 can normally output.

[0098] Pull-down maintenance module 1 and pull-down maintenance module 2 (i.e. the first pull-down maintenance module 108 and the second pull-down maintenance module 110 in the foregoing text): the pull-down control module includes thin film transistors T4A, T4, T4Q, T5Qi and T5Q. The pull-down control module 1 is connected with the first power signal VDD_O, the pull-down control module 2 is connected with the second power signal VDD_E, and the VDD_O / VDD_E signal is used for input control, so that the first pull-down node Qb_O(N) or the second pull-down node Qb_E(N) obtains a high level, and the pull-down maintenance function is realized.

[0099] Pull-down module 1, pull-down module 2, pull-down module 3, pull-down module 4, pull-down module 5, pull-down module 6, pull-down module 7 and pull-down module 8: the pull-down module includes a thin film transistor T7, or includes thin film transistors T3, T7 and T7N. Each pull-down module mainly uses the first pull-down node Qb_O(N) or the second pull-down node Qb_E(N) signal for pull-down maintenance, so that the voltage of the first pull-up node Q(N / N+1), the voltage of the second pull-up node Q(N+2 / N+3) and each scanning signal are maintained at a low level, and the risk of circuit leakage is reduced.

[0100] Pull-down control module 1 and pull-down control module 2 (i.e. the first pull-down control module 119 and the second pull-down control module 120 in the foregoing text): the pull-down control module includes a thin film transistor T3N. The pull-down control module 1 is connected with the fourth-level transmission signal Carry(n+12), and the pull-down control module 1 mainly closes the first pull-up node Q(N / N+1) through the Carry(n+12) signal. The pull-down control module 2 is connected with the fifth-level transmission signal Carry(n+14), and mainly closes the second pull-up node Q(N+2 / N+3) through the Carry(n+14) signal, so that the Q point of the GDL circuit is closed.

[0101] Reset module 1 and reset module 2 (i.e. the first reset module 121 and the second reset module 122 in the foregoing text): the reset module includes a thin film transistor T3R. The reset module 1 and the reset module 2 respectively input the Reset signal, and perform the pull-down action on the Q point at each frame, so as to avoid the accumulation of circuit leakage.

[0102] In Figure 6The first power signal VDD_O and the second power signal VDD_E in the shown driving unit output high level alternately, and the pull-up control module 1 / 2 uses the same signal to pull down; when the second power signal VDD_E is high, the pull-down maintenance control module 2 continuously works, and the second pull-down node Qb_E(N) is kept high, at this time, the pull-down module 2, the pull-down module 4, the pull-down module 5 and the pull-down module 8 will work normally, and the voltages of the scan signals Gout(n), Gout(n+1), Gout(n+2), Gout(n+3) and the first pull-up node Q(N / N+1), the second pull-up node Q(N+2 / N+3) and the stage transfer signals Carry(n), Carry(n+2) are continuously pulled low to VSS1 / VSS2.

[0103] When Carry(n-8) is input as the pull-up control signal, the pull-up control module 2 will pull the second pull-down node Qb_E(N) signal low to VSS2, at this time, the corresponding pull-down module 2, the pull-down module 4, the pull-down module 5 and the pull-down module 8 do not work, and because VDD_O is low, the pull-down module 1, the pull-down module 3, the pull-down module 6 and the pull-down module 7 do not work. When the equivalent capacitance of the output module of the odd row is equal to the equivalent capacitance of the output module of the even row, the voltage change process of the first pull-up node Q(N / N+1) is: at point A, when Carry(n-6) is input as the pull-up signal, the first pull-up node Q(N / N+1) can be normally pulled high to enter the precharge state; when it is to point B, with the input of CLK(N), the Q(N / N+1) voltage is coupled to enter the high level state; but when it is to point C, with the input of CLK(N+1), Q(N / N+1) will be coupled again. This will cause the Q point voltage to pass through twice, and the voltage is too high to increase the risk of breakdown of the semiconductor device. When it is to point D, CLK(N) enters low, and the Q(N / N+1) point voltage is coupled to reduce; when it is to point E, CLK(N+1) enters low, and the Q(N / N+1) point voltage is coupled to further reduce. The timing relationship of the signals in the driving unit is as shown in the following table: Figure 7 As shown, the Q(N / N+1) point voltage actually shows three sections, which shows that the gate voltage of the output module 1 is higher than that of the output module 2, which causes a large difference between the falling time and the rising time of Gout1 and Gout1, which will cause the number of charges passing through the pixels of the odd row and the pixels of the even row to be different in the same charging time. In the picture display, it finally shows the bright and dark horizontal lines of interlaced display, which greatly affects the visual perception.

[0104] By layout design, by changing the M1 / M2 overlapping area of the first thin film transistor T6 in the output module, the equivalent capacitance of the odd row output module is reduced, and the equivalent capacitance of the even row output module is increased, so that the coupling effect of Q(N / N+1) to CLK(N) change is small, and the coupling effect of Q(N / N+1) to CLK(N+1) change is increased, so that Figure 8 The output circuit shown makes the gate voltage regions of the odd and even row output modules consistent.

[0105] The operation mode of the driving unit will be divided into the following stages (for example, VDD_E is at the level and VDD_O is at high voltage):

[0106] The first stage: the carry signal Carry(n-8) is input, the pull-up control module 1 is turned on, and the first pull-down node Qb_O(N) potential is pulled down in advance;

[0107] The second stage: at point A, the carry signal Carry(n-6) is input, the pull-up module 1 is turned on, the first pull-up node Q(N / N+1) voltage is raised, and the pre-charge state is entered, and the pull-down maintenance module 1 is turned on at the same time, so that the voltage of VDD_O is directly connected to VSS2;

[0108] The third stage: at point B, the carry signal Carry(n-6) ends at the same time, the clock signals CLK(N) and CLK(N+1) are turned on at the same time, and the first pull-up node Q(N / N+1) potential is further raised to the second high voltage through the coupling effect of the equivalent capacitance of the even row output module, and the output module 1 and the output module 2 are turned on, and the scan signals Gout(n) and Gout(n+1) are output;

[0109] The fourth stage: at point C, compared with the original timing diagram, the rising edge of the clock signal CLK(N+1) is advanced to the same position as the clock signal CLK(N), so it will not affect the first pull-up node Q(N / N+1) potential;

[0110] The fifth stage: at point D, the clock signal CLK(N) is switched to low level, and the scan Gout(n) output ends, but because the equivalent capacitance of the odd row output module is reduced, the coupling effect on the first pull-up node Q(N / N+1) potential is small, so the first pull-up node Q(N / N+1) potential is basically unchanged;

[0111] The sixth stage: at point E, the clock signal CLK(N+1) is switched to low level, and the scan signal Gout(n+1) output ends, and because the equivalent capacitance of the even row output module is large, the first pull-up node Q(N / N+1) potential is reduced to the voltage during pre-charge through the capacitor coupling effect;

[0112] The seventh stage: at the point F, the carry signal Carry(n+12) is input, the pull-down control module 1 is turned on, the first pull-up node Q(N / N+1) is connected to VSS2, at this time, the voltage of VDD_O is pulled high to the potential of Qb_O(N) through the pull-down maintenance module 1, the unit enters the pull-down maintenance stage, and waits for the next work.

[0113] Referring to Figure 9 The embodiment of the present application further provides a display panel 200, which comprises a pixel unit 300 and the scan driving circuit according to any one of the above-mentioned embodiments.

[0114] Each driving unit 100 in the scan driving circuit is connected with four rows of adjacent pixel units 300 respectively.

[0115] Since the display panel 200 has the scan driving circuit according to any one of the above-mentioned embodiments, the same effect can be achieved, and thus the same effect will not be repeated here.

[0116] Referring to Figure 10 The embodiment of the present application further provides a display device 400, which comprises a timing control circuit 500 and the display panel 200 according to any one of the above-mentioned embodiments.

[0117] The timing control circuit 500 is connected with the display panel 200 through a clock signal line.

[0118] Since the display device 400 has the display panel 200 according to any one of the above-mentioned embodiments, the same effect can be achieved, and thus the same effect will not be repeated here.

[0119] It should be noted that, in the present text, relationship terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between the entities or operations. Moreover, the term "comprise", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of another identical element in the process, method, article or device comprising the element.

[0120] The foregoing is considered as illustrative only of the principles of the application. Numerous modifications and changes will readily occur to those skilled in the art, and it is intended to embrace all such modifications and changes that fall within the scope of the application. Accordingly, the application is not to be restricted in scope to the specific embodiments disclosed herein but is to be accorded the full scope that the principles and novel features request appropriately granted.

Claims

1. A scan driving circuit, characterized by comprising: The scan driving circuit comprises a plurality of cascaded driving units, and each driving unit comprises a first pull-up node, a second pull-up node, a first output module and a second output module connected with the first pull-up node, and a third output module and a fourth output module connected with the second pull-up node. The first pull-up node is configured to provide a gate voltage for the first output module and the second output module, the first output module is configured to output a first scan signal according to the gate voltage and a first clock signal, and the second output module is configured to output a second scan signal according to the gate voltage and a second clock signal. The second pull-up node is configured to provide a gate voltage for the third output module and the fourth output module, the second output module is configured to output a third scan signal according to the gate voltage and a third clock signal, and the fourth output module is configured to output a fourth scan signal according to the gate voltage and a fourth clock signal. The first clock signal, the second clock signal, the third clock signal and the fourth clock signal are provided by a timing control circuit, and the timing control circuit is connected with the scan driving circuit through a clock signal line; the first scan signal, the second scan signal, the third scan signal and the fourth scan signal are configured to drive four rows of adjacent pixel units to emit light. The equivalent capacitance of the first output module is smaller than the equivalent capacitance of the second output module, the equivalent capacitance of the third output module is equal to the equivalent capacitance of the first output module, and the equivalent capacitance of the fourth output module is equal to the equivalent capacitance of the second output module, so that the gate voltages provided by the first pull-up node and the second pull-up node for the first output module, the second output module, the third output module and the fourth output module are consistent. The rising edge of the first clock signal is synchronized with the rising edge of the second clock signal, the rising edge of the third clock signal is synchronized with the rising edge of the fourth clock signal, and the rising edges of the third clock signal and the fourth clock signal are after the rising edges of the first clock signal and the second clock signal. The falling edge of the first clock signal is before the falling edge of the second clock signal, the falling edge of the second clock signal is before the falling edge of the third clock signal, and the falling edge of the third clock signal is before the falling edge of the fourth clock signal.

2. The scan driving circuit according to claim 1, wherein The first output module, the second output module, the third output module and the fourth output module each comprise a first thin film transistor, and the first thin film transistor comprises a substrate, a first metal layer, an insulating layer, a second metal layer, a third metal layer and a protective layer. The protective layer covers the upper end faces of the second metal layer and the third metal layer, the second metal layer and the third metal layer cover the upper end face of the insulating layer, the insulating layer covers the upper end face of the first metal layer, and the first metal layer covers the upper end face of the substrate. The covering area of the second metal layer and the covering area of the third metal layer both overlap with the covering area of the first metal layer; The covering area of the third metal layer in the first output module is smaller than the covering area of the third metal layer in the second output module, and the covering area of the third metal layer in the third output module is smaller than the covering area of the third metal layer in the fourth output module.

3. The scan driving circuit according to claim 2, wherein The covering area of the third metal layer is proportional to the equivalent capacitance of the output module where the third metal layer is located.

4. The scan driving circuit according to claim 1, wherein The driving unit further comprises a first pull-up module and a second pull-up module; The first pull-up module is connected with the first pull-up node, and the first pull-up module is used for pre-charging the first pull-up node according to a first level signal; The second pull-up module is connected with the second pull-up node, and the second pull-up module is used for pre-charging the second pull-up node according to a second level signal, and the high level of the first level signal is prior to the high level of the second level signal.

5. The scan driving circuit according to claim 4, wherein The driving unit further comprises a first pull-up control module, a first pull-down maintaining module, a second pull-up control module, a second pull-down maintaining module, a first pull-down node and a second pull-down node; The first pull-up control module and the first pull-down maintaining module are both connected with the first pull-down node, the first pull-up control module is used for controlling the level of the first pull-down node according to a third level signal, and the first pull-down maintaining module is used for controlling the level of the first pull-down node according to a first power signal; The second pull-up control module and the second pull-down maintaining module are both connected with the second pull-down node, the second pull-up control module is used for controlling the level of the second pull-down node according to the third level signal, and the second pull-down maintaining module is used for controlling the level of the first pull-down node according to a second power signal; The high level signal of the third level signal is prior to the first level signal and the second level signal, the first power signal and the second power signal are both provided by the timing control circuit, and the level signal of the first power signal and the level signal of the second power signal are opposite.

6. The scan driving circuit according to claim 5, wherein The driving unit further comprises a first pull-down module, a second pull-down module, a third pull-down module, a fourth pull-down module, a fifth pull-down module, a sixth pull-down module, a seventh pull-down module and an eighth pull-down module; The first pull-down module, the third pull-down module, the sixth pull-down module and the seventh pull-down module are all connected with the first pull-down node; The second pull-down module, the fourth pull-down module, the fifth pull-down module and the eighth pull-down module are all connected with the second pull-down node; The first pull-down module and the second pull-down module are used for pulling down the output signal of the first output module, the third pull-down module and the fourth pull-down module are used for pulling down the output signal of the second output module, the fifth pull-down module and the sixth pull-down module are used for pulling down the output signal of the third output module, and the seventh pull-down module and the eighth pull-down module are used for pulling down the output signal of the fourth output module.

7. The scan driving circuit according to claim 1, wherein The driving unit further comprises a first pull-down control module and a second pull-down control module. The first pull-down control module is connected with the first pull-up node, and is used for performing pull-down control on the first pull-up node according to a fourth level signaling. The second pull-down control module is connected with the second pull-up node, and is used for performing pull-down control on the second pull-up node according to a fifth level signaling.

8. A display panel, characterized by, It comprises: a pixel unit and the scanning driving circuit as claimed in any one of claims 1-7; Each driving unit in the scanning driving circuit is connected with four rows of adjacent pixel units respectively.

9. A display device, characterized by comprising: It comprises: a timing control circuit and the display panel as claimed in claim 8; The timing control circuit is connected with the display panel through a clock signal line.

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