Vcsel wafer

Abstract

Disclosed is a VCSEL wafer. The VCSEL wafer comprises a wafer main body and a test circuit structure integrated on the wafer main body at a wafer level, the wafer main body comprises a plurality of VCSEL chips and a pad, at least part of the plurality of VCSEL chips are test points, and the test circuit structure comprises a plurality of electrically connected lines electrically connected between the test points and the pad. In this way, the VCSEL wafer can be tested without cutting, packaging and other processes, the testing difficulty and cost can be reduced, the influence of the cutting, packaging and other processes on the accuracy of the test result can be avoided, the testing period can be greatly shortened, and the test result can be obtained quickly. Further, the test result can be obtained before cutting and it can be determined whether the VCSEL chip has defects, and if the VCSEL chip has defects, the VCSEL chip can be screened out in advance, and the cutting, packaging and other processes can be omitted.

Description

Technical Field

[0001] This application relates to the field of semiconductor lasers, and more specifically to VCSEL wafers. Background Technology

[0002] A VCSEL (Vertical-Cavity Surface-Emitting Laser) is a semiconductor laser that emits laser light in a direction perpendicular to its substrate. VCSELs possess characteristics such as small divergence angle, beam symmetry, high wavelength thermal stability, stable beam quality, single-mode output, high photoelectric conversion efficiency, small size, low threshold current, low power consumption, and ease of integration, making them highly promising for applications in communications, consumer electronics, and automotive fields. Currently, VCSEL products are widely used in short-range fiber optic communications, facial recognition, 3D sensing, and other industries.

[0003] In VCSEL chip manufacturing, the initial wafer is typically processed to form a VCSEL wafer with a multi-VCSEL structure. This VCSEL wafer is then diced and packaged to obtain the packaged VCSEL chip. To ensure the reliability of VCSEL chips, they require rigorous testing and screening. For example, in addition to traditional ATE (Automatic Test Equipment) testing, wafer-level accelerated aging tests are also necessary to determine the reliability of the VCSEL wafer. However, existing accelerated aging tests have several problems.

[0004] Specifically, traditional accelerated aging tests require sampling the diced VCSEL wafers, packaging the selected wafers, and then testing the packaged wafers to determine their performance. In other words, traditional accelerated aging tests test the diced and packaged VCSEL wafers. However, packaging introduces additional influencing factors, thus affecting the reliability of the test results. The reliability of the test results depends on the uniformity of the packaging, and the additional packaging also increases time costs, which is detrimental to the market competitiveness of VCSEL chips.

[0005] It's worth noting that VCSEL wafer manufacturing is done by chip manufacturers, while VCSEL packaging is done by packaging companies. VCSEL wafers pass through at least two nodes in the supply chain from chip manufacturers to packaging companies, and their performance is affected during this process. Furthermore, the inconsistency in the packaging of individual VCSEL wafers by the packaging company further impacts the test results.

[0006] In existing aging test solutions for VCSEL chips, VCSEL wafers can be tested using custom probe cards. However, custom probe card circuits are complex and the testing costs are high.

[0007] Therefore, a new VCSEL wafer aging accelerated testing solution is needed. Summary of the Invention

[0008] One advantage of this application is that it provides a VCSEL wafer that is suitable for direct testing by applying power through a probe, which can reduce the difficulty of testing.

[0009] Another advantage of this application is that it provides a VCSEL wafer in which a test circuit structure is formed at the wafer level, and testing can be performed without cutting, packaging and other processes, which can reduce testing costs.

[0010] Another advantage of this application is that it provides a VCSEL wafer, wherein the VCSEL wafer can be tested without cutting, packaging or other processes, which can avoid the impact of cutting, packaging or other processes on the accuracy of test results.

[0011] Another advantage of this application is that it provides a VCSEL wafer, wherein the VCSEL wafer can be tested without cutting, packaging and other processes, which can greatly shorten the testing cycle and obtain test results more quickly.

[0012] Another advantage of this application is that it provides a VCSEL wafer in which the VCSEL can be tested before dicing. Furthermore, the test results can be obtained before dicing to determine whether the VCSEL chip has defects. If defects are found, they can be screened out in advance, saving the dicing, packaging and other processes.

[0013] Another advantage of this application is that it provides a VCSEL wafer in which additional test points can be added and their placement positions can be selected. In some embodiments of this application, the additional test points do not occupy the original formation space of the VCSEL chip.

[0014] Another advantage of this application is that it provides a VCSEL wafer in which the test coverage is adjustable.

[0015] Another advantage of this application is that it provides a VCSEL wafer, wherein the VCSEL wafer can be manufactured using mature chip manufacturing processes, thereby improving the structural stability and reliability of the VCSEL wafer.

[0016] To achieve at least one of the above advantages or other advantages and objectives, according to one aspect of this application, a VCSEL-compatible wafer is provided, comprising: A wafer body, including pads and multiple VCSEL chips, wherein at least some of the VCSEL chips are test points; and The test circuit structure integrated at the wafer level into the wafer body includes multiple electrical connection lines electrically connected between the test point and the pad.

[0017] In the VCSEL wafer of this application, the wafer body has multiple PCM test areas, and at least one of the test points is formed in the PCM test area.

[0018] In the VCSEL wafer of this application, the wafer body has at least one dicing channel, and at least one of the test points is formed in the dicing channel.

[0019] In the VCSEL wafer of this application, the length dimension of the test point formed on the dicing track is less than or equal to 55 μm, and the width dimension is less than or equal to 55 μm.

[0020] In the VCSEL wafer of this application, all the VCSEL chips form the test point.

[0021] In the VCSEL wafer of this application, at least three of the plurality of VCSEL chips are the test points, and the at least three test points are evenly distributed.

[0022] In the VCSEL wafer of this application, the pad includes multiple solder joints, and the test circuit structure includes a first electrical connection line connecting the multiple solder joints and a second electrical connection line connecting the test point and the first electrical connection line.

[0023] In the VCSEL wafer of this application, the first electrical connection line has a closed loop structure with the ends connected.

[0024] In the VCSEL wafer of this application, a plurality of the solder joints are located adjacent to the outer edge of the VCSEL wafer.

[0025] In the VCSEL wafer of this application, the test point has a chip positive electrode and a chip negative electrode, and the second electrical connection line includes a positive electrical connection line connected to the chip positive electrode and a negative electrical connection line connected to the chip negative electrode.

[0026] The further objectives and advantages of this application will become fully apparent from the following description and accompanying drawings.

[0027] These and other objects, features and advantages of this application are fully apparent from the following detailed description, the accompanying drawings and the claims. Attached Figure Description

[0028] These and / or other aspects and advantages of this application will become clearer and more readily understood from the following detailed description of embodiments of this application taken in conjunction with the accompanying drawings, wherein: Figure 1 The figure shows a schematic diagram of the structure of a VCSEL wafer according to an embodiment of this application.

[0029] Figure 2 The illustration shows a partially enlarged schematic diagram of a VCSEL wafer according to an embodiment of this application.

[0030] Figure 3 The illustration shows another partially enlarged schematic diagram of a VCSEL wafer according to an embodiment of this application.

[0031] Figure 4 The illustration shows another partially enlarged schematic diagram of a VCSEL wafer according to an embodiment of this application. Detailed Implementation

[0032] The terms and words used in the following specification and claims are not limited to their literal meaning, but are used solely by the inventors to enable a clear and consistent understanding of this application. Therefore, it will be apparent to those skilled in the art that the following description of various embodiments of this application is provided for illustrative purposes only and not for the purpose of limiting this application as defined in the appended claims and their equivalents.

[0033] It is understood that the term "a" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple, and the term "a" should not be understood as a limitation on the number.

[0034] While ordinal numbers such as "first," "second," etc., will be used to describe various components, there is no limitation on which components are used herein. The term is used only to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the teachings of this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0035] The terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting. As used herein, the singular form also includes the plural form, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising” and / or “having” as used in this specification specify the presence of the described features, numbers, steps, operations, components, elements or combinations thereof, without excluding the presence or addition of one or more other features, numbers, steps, operations, components, elements or groups thereof.

[0036] Application Overview: As mentioned above, existing accelerated aging tests assess the performance of packaged VCSEL wafers. In other words, traditional accelerated aging tests test the diced and packaged VCSEL wafers. However, packaging introduces additional influencing factors, thus affecting the reliability of the test results. The reliability of the test results depends on the uniformity of the packaging, and the additional packaging also increases time costs, which is detrimental to the market competitiveness of VCSEL chips.

[0037] It's worth noting that VCSEL wafer manufacturing is done by chip manufacturers, while VCSEL packaging is done by packaging companies. VCSEL wafers pass through at least two nodes in the supply chain from chip manufacturers to packaging companies, and their performance is affected during this process. Furthermore, the inconsistency in the packaging of individual VCSEL wafers by the packaging company further impacts the test results.

[0038] In existing aging test solutions for VCSEL chips, VCSEL wafers can be tested using custom probe cards. However, custom probe card circuits are complex and the testing costs are high.

[0039] Considering the impact of packaging on the aging test of VCSEL wafers, this application proposes to optimize the structure of VCSEL wafers so that aging tests can be performed without packaging. Specifically, a test circuit structure can be formed at the wafer level, allowing the VCSEL wafer to be directly subjected to aging tests via probes.

[0040] Based on this, according to one aspect of this application, this application proposes a VCSEL wafer, which includes: a wafer body and a test circuit structure integrated at the wafer level on the wafer body, the wafer body including pads and a plurality of VCSEL chips, wherein at least some of the plurality of VCSEL chips are test points, and the test circuit structure includes a plurality of electrical connection lines electrically connected between the test points and the pads.

[0041] After introducing the basic principles of this application, various non-limiting embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0042] Schematic VCSEL wafer: such as Figures 1 to 4 As shown, a VCSEL wafer according to an embodiment of this application is illustrated, wherein the VCSEL wafer includes a wafer body and a test circuit structure integrated at the wafer level on the wafer body. The wafer body includes a plurality of VCSEL chips and pads formed on the surface of the wafer body. At least some of the plurality of VCSEL chips are used as test points. The pads include a plurality of solder joints, serving as connection terminals for connecting the wafer body to external devices. The test circuit structure includes a plurality of electrical connection lines electrically connected between the test point and the pads. That is, the VCSEL wafer forms a test circuit structure suitable for testing. This reduces the requirements for testing equipment and the difficulty of testing, and reduces testing costs; for example, it eliminates the need for testing using customized probe cards with complex circuitry. The VCSEL wafer described in this application can be tested using contact probes; after the probes are pressed against the pads and powered on, they can be tested using a tester connected to the probes. Furthermore, the VCSEL wafers can be tested without dicing or packaging, further reducing testing costs and avoiding the impact of dicing and packaging on the accuracy of test results. This also significantly shortens the testing cycle and allows for faster results. Moreover, since test results can be obtained and the presence of defects in the VCSEL chips can be determined before dicing, defective chips can be pre-selected, eliminating the need for dicing and packaging.

[0043] The test point and the connection method between the test point and the pad can be selected according to actual needs, thereby forming a test circuit structure suitable for testing. It should be understood that the VCSEL wafer with the test circuit structure is suitable for aging tests, and can also be made suitable for other types of performance tests by designing the test circuit structure.

[0044] It is worth mentioning that the VCSEL wafer can have VCSEL chips placed at specific locations, which can then be used as test points. For example, the wafer body has multiple PCM test areas used for PCM testing, where VCSEL chips are typically not formed. This application allows VCSEL chips to be formed in the PCM test areas during the VCSEL wafer manufacturing process, and these can be used as test points, such as... Figure 2 As shown, it is specifically used for performance testing. This way, it does not occupy the space originally intended for forming the VCSEL chip in the VCSEL package product. That is, in some embodiments of this application, at least one of the test points is formed in the PCM test area.

[0045] The test points can be set in each PCM test area, so that they are distributed in a dispersed manner throughout the VCSEL wafer, covering the entire VCSEL wafer, thereby improving the reliability of the sampling test results.

[0046] For example, the wafer body has at least one dicing track. During subsequent dicing of the VCSEL wafer, cutting will be performed along this dicing track. Therefore, VCSEL chips are typically not formed at the dicing track. This application allows the formation of VCSEL chips at the dicing track during the VCSEL wafer manufacturing process, and these chips can be used as test points, such as... Figure 3 As shown, this is specifically designed for performance testing. This way, it doesn't occupy the space originally intended for forming the VCSEL chip in the VCSEL package. Furthermore, even if the structure of the test point located at the dicing line is damaged during subsequent dicing of the VCSEL wafer, it will not affect the yield of the VCSEL chip.

[0047] The size of the test point located at the cutting path is less than 55*55μm. 2 That is, the length and width of the test points located at the dicing track are less than or equal to 55 μm. Multiple test points can be set on each dicing track, distributing them evenly across the VCSEL wafer to cover the entire wafer. Furthermore, the test points located at the dicing track are relatively small, allowing for flexible adjustment of their distribution density to adjust the coverage rate. For example, increasing the distribution density of the test points improves the coverage rate.

[0048] For VCSEL chips with high performance and reliability requirements, each VCSEL chip can be tested individually, with each VCSEL chip serving as a test point. That is, all the aforementioned VCSEL chips form the test points, achieving 100% coverage. Figure 4 As shown.

[0049] Preferably, the test points are uniformly distributed throughout the VCSEL wafer. Accordingly, in some embodiments of this application, at least three of the plurality of VCSEL chips are the test points, and the at least three test points are uniformly distributed. The distance between any two adjacent test points is substantially equal, which can be expressed as: the distance difference between any two adjacent test points is less than or equal to a preset value.

[0050] In the embodiments of this application, each VCSEL chip includes at least one VCSEL light-emitting point, that is, it includes one or more VCSEL light-emitting points. Each VCSEL light-emitting point includes a light-emitting body and a light-emitting point positive electrode and a light-emitting point negative electrode connected to the light-emitting body. The light-emitting body includes a substrate layer, an N-DBR, an active region, a P-DBR, and a confinement layer with confinement holes stacked on each other.

[0051] In this embodiment of the application, the test circuit structure includes a first electrical connection line connected between the plurality of solder joints and a second electrical connection line connected between the test point and the first electrical connection line. That is, the plurality of electrical connection lines include a first electrical connection line connected between the plurality of solder joints and a second electrical connection line connected between the test point and the first electrical connection line.

[0052] In this embodiment of the application, the test point has a chip positive electrode and a chip negative electrode, and the second electrical connection line includes a positive electrical connection line connected to the chip positive electrode and a negative electrical connection line connected to the chip negative electrode.

[0053] like Figure 1 As shown in this embodiment, the multiple solder joints are located near the outer edge of the VCSEL wafer, facilitating contact probing by probes. The first electrical connection line connects between every two adjacent solder joints, forming a closed loop structure that facilitates the power-on synchronization of each VCSEL chip.

[0054] In this embodiment, during the testing of the VCSEL wafer, the VCSEL wafer is electrically connected to a current source. It should be understood that the VCSEL wafer can also be electrically connected to a voltage source during testing. When the VCSEL wafer is electrically connected to a voltage source, the multiple solder joints and multiple test points can be connected in series or in parallel, depending on the actual situation.

[0055] It is worth mentioning that, in this embodiment, the VCSEL wafer can be manufactured using mature chip manufacturing processes, improving the structural stability and reliability of the VCSEL wafer. Specifically, during the manufacturing process of the VCSEL wafer, photolithography is performed on the wafer. By designing the photomask pattern, the formation position of the VCSEL chip can be defined, and the VCSEL chip can be formed. In the manufacturing process of the VCSEL wafer of this application, the formation position of the VCSEL chip can be defined in a specific area (e.g., the PCM test area, dicing channel) by adjusting the photomask pattern, and the VCSEL chip can be formed in this specific area as a test point. Furthermore, metal can be deposited in a preset area during the VCSEL wafer manufacturing process to form multiple electrical connection lines arranged according to a preset pattern.

[0056] In summary, the VCSEL wafer based on the embodiments of this application is explained. The VCSEL wafer forms a test circuit structure at the wafer level, allowing for testing without the need for dicing, packaging, or other processes. This reduces testing difficulty and cost, avoids the impact of dicing and packaging processes on the accuracy of test results, and significantly shortens the testing cycle, allowing for faster test results. Furthermore, since test results can be obtained and the presence of defects in the VCSEL chip can be determined before dicing, defects can be pre-selected, eliminating the need for dicing and packaging processes.

[0057] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

Claims

1. A VCSEL wafer, characterized in that, include: The wafer body includes pads and multiple VCSEL chips, wherein only some of the VCSEL chips are test points; and The test circuit structure integrated at the wafer level onto the wafer body includes multiple electrical connection lines electrically connected between the test point and the pad; The wafer body has at least one dicing track, and the wafer is adapted to be diced along the dicing track; at least one test point is formed on the dicing track, and the length dimension of the test point formed on the dicing track is less than or equal to 55 μm, and the width dimension is less than or equal to 55 μm.

2. The VCSEL wafer according to claim 1, wherein, The wafer body has multiple PCM test areas, and at least one of the test points is formed in the PCM test area.

3. The VCSEL wafer according to claim 1, wherein, At least three of the multiple VCSEL chips are the test points, and the at least three test points are evenly distributed.

4. The VCSEL wafer according to claim 1, wherein, The pads include multiple solder joints, and the test circuit structure includes a first electrical connection line connecting the multiple solder joints and a second electrical connection line connecting the test point and the first electrical connection line.

5. The VCSEL wafer according to claim 4, wherein, The first electrical connection line has a closed loop structure with the ends connected.

6. The VCSEL wafer according to claim 4, wherein, The plurality of solder joints are located adjacent to the outer edge of the VCSEL wafer.

7. The VCSEL wafer according to claim 4, wherein, The test point has a chip positive terminal and a chip negative terminal, and the second electrical connection line includes a positive electrical connection line connected to the chip positive terminal and a negative electrical connection line connected to the chip negative terminal.

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