A method and system for verifying a agile transceiver correction algorithm

Abstract

The application relates to the technical field of radio frequency circuits, and provides a method and system for verifying a correction algorithm of a frequency-agile transceiver, the method comprising the following steps: reading and writing control of registers of a target frequency-agile transceiver through a programmable module to configure a circuit state of the target frequency-agile transceiver into a target state; collecting an IQ signal of the target frequency-agile transceiver in the target state; enabling the frequency-agile transceiver correction algorithm in an upper computer to perform receiving channel correction and transmitting channel correction according to the IQ signal, and obtaining a correction value corresponding to the receiving channel correction and a correction value corresponding to the transmitting channel correction; and writing the correction value into the registers of the target frequency-agile transceiver to estimate a residual value of the receiving channel, measure sideband suppression and local oscillator suppression of the transmitting channel, and verify the correction effect of the frequency-agile transceiver correction algorithm according to the residual value, the sideband suppression and the local oscillator suppression, thereby improving the accuracy and efficiency of the verification of the frequency-agile transceiver correction algorithm.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of radio frequency circuit, in particular to a method and system for verifying a correction algorithm of a frequency-agile transceiver. BACKGROUND

[0002] Market wireless consumer products have higher and higher requirements for cost, power consumption and size, and wireless spectrum has become increasingly crowded, so the frequency-agile transceiver of ZIF (Zero-IF) architecture has highlighted its advantages. However, the biggest disadvantage of the frequency-agile transceiver is DC (Direct Current) imbalance and IQ (I: In-phase, Q: quadrature) imbalance. In order to solve the above problems, the frequency-agile transceiver usually integrates correction algorithms such as DC correction and IQ correction. At the same time, after the integration of the correction algorithm, the algorithm usually needs to be verified to promote the iteration of the correction algorithm of the frequency-agile transceiver and shorten the product listing cycle.

[0003] The traditional verification of the correction algorithm is realized in two ways in the technical field: software verification and hardware verification. When the algorithm is verified by the software verification, the main limitation comes from the accuracy of the channel model, which will seriously affect the accuracy of the correction algorithm and even produce a revolutionary problem; when the algorithm is verified by the hardware verification, the main defect is that the hardware design cycle is long, and the hardware design needs to be changed every time the algorithm is changed, which leads to a long cycle and low efficiency of algorithm verification iteration.

[0004] Therefore, how to improve the accuracy and efficiency of the algorithm verification of the frequency-agile transceiver is a problem to be solved at present. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a method and system for verifying a correction algorithm of a frequency-agile transceiver, which solves the problem of how to improve the accuracy and efficiency of the algorithm verification of the frequency-agile transceiver in the prior art.

[0006] To achieve the above-mentioned purposes and other related purposes, the present application provides a method for verifying a correction algorithm of a frequency-agile transceiver, which comprises:

[0007] The registers of a target frequency-agile transceiver are read and written by a pre-configured programmable module to configure the circuit state of the target frequency-agile transceiver to a target state;

[0008] According to the programmable module, the IQ signal of the target frequency-agile transceiver in the target state is collected;

[0009] transmit the IQ signal to a pre-configured host computer, so that a pre-constructed agile transceiver correction algorithm in the host computer performs receive channel correction and transmit channel correction according to the IQ signal, and obtains a correction value corresponding to the receive channel correction and a correction value corresponding to the transmit channel correction;

[0010] write the correction value corresponding to the receive channel correction and the correction value corresponding to the transmit channel correction into a register of the target agile transceiver through the host computer, so as to estimate a residual value of the receive channel, measure sideband suppression and local oscillator suppression of the transmit channel, and verify the correction effect of the agile transceiver correction algorithm according to the residual value, the sideband suppression and the local oscillator suppression.

[0011] In an embodiment of the present application, the receive channel correction and the transmit channel correction according to the IQ signal, and the correction value corresponding to the receive channel correction and the correction value corresponding to the transmit channel correction, include:

[0012] initialize the receive channel and the transmit channel;

[0013] perform receive channel DC correction and receive channel IQ correction according to the initialized receive channel and the IQ signal, and obtain a correction code corresponding to the receive channel DC correction and a correction code corresponding to the receive channel IQ correction, wherein the correction code corresponding to the receive channel DC correction and the correction code corresponding to the receive channel IQ correction are included in the correction value corresponding to the receive channel correction;

[0014] obtain a DC single-point correction value of the receive channel and an IQ single-point correction table according to the IQ signal, perform transmit channel DC correction on the initialized transmit channel according to the DC single-point correction value, perform transmit channel IQ correction on the initialized transmit channel according to the IQ single-point correction table, and obtain a correction value corresponding to the transmit channel DC correction and a correction value corresponding to the transmit channel IQ correction, wherein the correction value corresponding to the transmit channel DC correction and the correction value corresponding to the transmit channel IQ correction are included in the correction value corresponding to the transmit channel correction.

[0015] In an embodiment of the present application, the DC single-point correction value of the receive channel and the IQ single-point correction table obtained according to the IQ signal include:

[0016] configure the gain of the receive channel;

[0017] perform receive channel DC estimation and receive channel DC correction according to the configured gain of the receive channel and the IQ signal, and extract the DC single-point correction value corresponding to the receive channel DC correction;

[0018] The transmit local oscillator phase-locked loop is configured, and the receive channel IQ single-point estimation and the receive channel IQ single-point correction are performed according to the transmit local oscillator phase-locked loop and the IQ signal, and the IQ single-point correction table corresponding to the receive channel IQ single-point correction is extracted.

[0019] In an embodiment of the present application, the correction value corresponding to the receive channel correction is written into the register of the target agile transceiver to estimate the residual value of the receive channel, including:

[0020] The correction code corresponding to the receive channel DC correction and the correction code corresponding to the receive channel IQ correction are written into the register of the target agile transceiver through a serial port;

[0021] The gain of the receive channel of the target agile transceiver is changed through a serial port, and the input signal frequency of the receive channel is changed through an Ethernet;

[0022] The new IQ signal corresponding to the input signal frequency is collected, and the new IQ signal is transmitted to the upper computer to estimate the DC residual value and the IQ residual value of the receive channel through the upper computer.

[0023] In an embodiment of the present application, the correction value corresponding to the transmit channel correction is written into the register of the target agile transceiver to measure the sideband suppression and the local oscillator suppression of the transmit channel, including:

[0024] The correction value corresponding to the transmit channel DC correction and the correction value corresponding to the transmit channel IQ correction are written into the register of the target agile transceiver through a serial port;

[0025] The correction value corresponding to the transmit channel correction is changed through a serial port, and the pre-configured instrument test is controlled through an Ethernet interface to test the local oscillator suppression and the sideband suppression of the transmit channel output.

[0026] In an embodiment of the present application, the receive channel is initialized, including:

[0027] The always-on phase-locked loop is configured, the channel phase-locked loop is configured, the analog receive channel is configured, the analog filter is configured, the ADC is configured, the digital receive channel PFIR filter is configured, the post-filter is configured, the digital receive channel mode is configured, the BB port mode is configured, the digital clock is opened, and the AGC is reset.

[0028] In an embodiment of the present application, the transmit channel is initialized, including:

[0029] configuring a clock phase-locked loop, configuring a receive channel phase-locked loop, configuring an analog receive channel configuration, configuring an analog filter, configuring an ADC, configuring a digital receive channel PFIR filter, configuring a post-filter, configuring a digital receive channel mode, configuring a BB port mode, opening a digital clock, resetting an AGC, configuring a transmit channel phase-locked loop, configuring a transmit channel analog filter, configuring a digital transmit channel PFIR filter, configuring a pre-filter, configuring a digital transmit channel mode.

[0030] In an embodiment of the present application, according to the initialized receive channel and the IQ signal, receive channel DC correction and receive channel IQ correction are performed, and a correction code corresponding to the receive channel DC correction and a correction code corresponding to the receive channel IQ correction are obtained, including:

[0031] When there is no radio frequency input, frequency domain estimation is performed on the two baseband signals in the IQ signal, a zero frequency amplitude value in the frequency domain estimation result is extracted, coarse correction codes and fine correction codes of the I and Q channels are calculated according to the zero frequency amplitude value, and the coarse correction codes and the fine correction codes of the I and Q channels are compensated in the analog domain and the digital domain to obtain the correction code corresponding to the receive channel DC correction.

[0032] A single tone sine wave is obtained as an input test signal, frequency domain estimation is performed on the two baseband signals in the IQ signal through the single tone sine wave, parameters corresponding to IQ amplitude and phase imbalance are extracted and compensated to obtain the correction code corresponding to the receive channel IQ correction.

[0033] In an embodiment of the present application, according to the DC single-point correction value, transmit channel DC correction is performed, and according to the IQ single-point correction table, transmit channel IQ correction is performed, and a correction value corresponding to the transmit channel DC correction and a correction value corresponding to the transmit channel DC correction are obtained, including:

[0034] When there is no radio frequency input, frequency domain estimation is performed on the I and Q baseband signals in the IQ signal, and a zero frequency amplitude in the frequency domain estimation result is extracted, the DC single-point correction value is changed through bisection to make the zero frequency amplitude lowest, transmit channel DC parameters are extracted, and the transmit DC parameters are compensated in the digital domain to obtain the correction value corresponding to the transmit channel DC correction.

[0035] The single-tone sine wave output by the digital oscillator is taken as an input test signal, the I and Q baseband signals in the IQ signal are estimated in the frequency domain through the single-tone sine wave, and the mirror interference amplitude caused by IQ imbalance in the frequency domain estimation result is extracted; the single-point correction value in the IQ single-point correction table is changed through dichotomy to make the mirror interference amplitude lowest, the parameter corresponding to the transmit channel IQ amplitude and phase imbalance when the mirror interference amplitude is lowest is extracted, and the parameter is compensated in the digital domain to obtain the correction value corresponding to the transmit channel DC correction.

[0036] In an embodiment of the present application, a fast-changing transceiver correction algorithm verification system is also provided, comprising:

[0037] A target fast-changing transceiver is configured to generate an IQ signal in a target state.

[0038] A programmable module is configured to read and write control the registers of the target fast-changing transceiver to configure the circuit state of the target fast-changing transceiver to the target state.

[0039] A host computer is configured to make the pre-constructed fast-changing transceiver correction algorithm perform receive channel correction and transmit channel correction according to the IQ signal, and obtain the correction value corresponding to the receive channel correction and the correction value corresponding to the transmit channel correction, and write the correction value corresponding to the receive channel correction and the correction value corresponding to the transmit channel correction into the registers of the target fast-changing transceiver to estimate the residual value of the receive channel, measure the sideband suppression and local oscillator suppression of the transmit channel, and verify the correction effect of the fast-changing transceiver correction algorithm according to the residual value, sideband suppression and local oscillator suppression.

[0040] The present application has the following advantages:

[0041] Firstly, the registers of the target agile transceiver are read and written by a pre-configured programmable module to configure the circuit state of the target agile transceiver to a target state; then, the IQ signal of the target agile transceiver under the target state is collected according to the programmable module; then, the IQ signal is transmitted to a pre-configured host computer, so that the agile transceiver correction algorithm pre-built in the host computer receives the channel correction and the transmission channel correction according to the IQ signal, and the correction value corresponding to the receiving channel correction and the correction value corresponding to the transmission channel correction are obtained; finally, the correction value corresponding to the receiving channel correction and the correction value corresponding to the transmission channel correction are written into the registers of the target agile transceiver by the host computer, so as to estimate the residual value of the receiving channel, measure the sideband suppression and local oscillator suppression of the transmission channel, and verify the correction effect of the agile transceiver correction algorithm according to the residual value, the sideband suppression and the local oscillator suppression. In the application, the agile transceiver is taken as a carrier, the programmable module is used to realize various transmission protocols and the bottom layer driving of the agile transceiver, the algorithm and the algorithm correction function in the host computer are combined to form a verification method for the agile transceiver correction algorithm. The agile transceiver is taken as a carrier, the problem of low accuracy caused by the channel model in the prior art is solved, and the accuracy of the agile transceiver correction algorithm is improved; the programmable module is used to realize various transmission protocols and the bottom layer driving of the agile transceiver, the efficiency, real-time performance and other aspects of the complex algorithm verification system are improved, and the efficiency of the agile transceiver correction algorithm is improved; the hybrid programming in the host computer is realized, the correction and the correction algorithm verification function are realized, and the defects of long algorithm verification period and complex iterative analysis are solved.

[0042] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0043] The drawings incorporated into the specification and constituting a part of the specification show embodiments consistent with the present application and, together with the specification, serve to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor. In the drawings:

[0044] Figure 1 is a flowchart of the agile transceiver correction algorithm verification method according to an exemplary embodiment of the present application;

[0045] Figure 2 is a flowchart of the agile transceiver correction algorithm verification method according to another exemplary embodiment of the present application;

[0046] Figure 3is a schematic diagram of a flow of acquiring a DC single-point correction value and an IQ single-point correction table according to an example embodiment of the present application;

[0047] Figure 4 is a schematic diagram of a flow of initializing a receiving channel according to an example embodiment of the present application;

[0048] Figure 5 is a schematic diagram of a flow of initializing a transmitting channel according to an example embodiment of the present application;

[0049] Figure 6 is a schematic diagram of a flow of correcting a receiving channel according to an example embodiment of the present application;

[0050] Figure 7 is a schematic diagram of a flow of correcting a transmitting channel according to an example embodiment of the present application;

[0051] Figure 8 is a block diagram of a verification system for a fast hopping transceiver correction algorithm according to an example embodiment of the present application. DETAILED DESCRIPTION

[0052] Other advantages and novel features of the present application will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings wherein:

[0053] It should be noted that the drawings included herewith are included merely for illustrative purposes and therefore should not be construed as being limiting in any way. In particular, the drawings provided herein are not drawn to scale and are only meant to be a simplified representation of the various embodiments of the present application. Furthermore, the drawings provided herein are not meant to be a complete and comprehensive representation of all possible embodiments of the present application.

[0054] In the following description, numerous specific details are discussed so as to provide a thorough understanding of embodiments of the present application. However, various embodiments of the present application can be practiced without these specific details. In other instances, well-known structures and devices are not described in exhaustive detail so as to avoid unnecessarily obscuring the present application.

[0055] First of all, it needs to be pointed out that the traditional correction algorithm verification is implemented in two ways at the technical level: software and hardware. The software way is to establish a transceiver channel model of the correction algorithm, and the correction algorithm module is embedded in the model to complete the theoretical correction algorithm verification; the hardware way is to implement the algorithm in the form of hardware circuit, such as circuit design or FPGA (Field Programmable Gate Array) implementation. The circuit design method is to design the algorithm into the final hardware circuit for verification, and the FPGA method is to convert the algorithm into HDL (Hardware Description Language) language, which is downloaded to the FPGA circuit after synthesis and layout.

[0056] The main limitation of the software implementation of the algorithm verification comes from the accuracy of the channel model, which will seriously affect the accuracy of the correction algorithm, and even produce a revolutionary problem. The main defect of the hardware implementation of the algorithm verification is the long hardware design cycle, among which the sampling circuit design method implementation verification cycle is accumulated in months, and the FPGA implementation method verification cycle will be accumulated in weeks, and each time the algorithm is changed, the hardware design needs to be changed, which leads to a long iteration period of algorithm verification.

[0057] Comparing the above two methods, the software verification effect is high, but the ideal channel model is used, and the hardware method is low in efficiency, but the actual channel model is used. For the comparison algorithm convergence efficiency is low, and in the correction algorithm verification of the agile transceiver, this method is only functional verification, and cannot completely meet the state of the real product to complete the algorithm verification.

[0058] The above two ways of implementing algorithm verification, especially for complex algorithm verification (the correction algorithm of the agile transceiver needs to configure the state of the agile transceiver circuit, control the instrument, and call multiple algorithm modules), have defects that cannot be solved in terms of verification efficiency, accuracy, etc.

[0059] The following describes the technical terms in this application:

[0060] The agile transceiver is a high-performance and high-integration radio frequency transceiver. The RF transceiver is a key device in wireless communication systems, which is mainly responsible for converting digital signals into radio frequency signals suitable for transmission and restoring them into digital signals at the receiving end. RF transceivers are widely used in various wireless communication systems, such as mobile phones, satellite communications, vehicle communications, etc.

[0061] Zero IF: The traditional modulation and demodulation method is that the radio signal RF (radio frequency) enters the antenna, is converted into IF (intermediate frequency), and then is converted into baseband (I, Q signal). Zero IF is a modulation and demodulation method in which the signal is directly converted from RF to baseband and then demodulated without passing through the intermediate frequency. The characteristics of zero IF are: (1) there is no mirror frequency interference, and no high Q value band-pass filter outside the chip is needed, so it is easy to realize single-chip integration; (2) there are problems such as DC bias and local oscillator leakage.

[0062] UART: UART has no clock signal, cannot control when to send data, and cannot guarantee that both parties receive data at exactly the same speed. Therefore, if both parties receive and send data at different speeds, problems will occur. If you want to solve this problem, UART adds extra start bits and stop bits to each byte to help the receiver synchronize when the data arrives; both parties must also agree on the transmission speed in advance (set the same baud rate, such as 9600 bits per second). If there is a slight difference in transmission rate, it is not a problem because the receiver will resynchronize at the beginning of each byte.

[0063] SPI: Serial Peripheral Interface, a high-speed, full-duplex, synchronous data bus, that is, it uses a separate data line and a separate clock signal to ensure perfect synchronization between the sending end and the receiving end. The clock is an oscillation signal that tells the receiving end to sample the signal on the data line at the exact time. The side that generates the clock is called the host, and the other side is called the slave. There is always only one host (generally a microcontroller / MCU), but there can be multiple slaves; the sampling time of the data may be the rising edge (from low to high) or the falling edge (from high to low) of the clock signal.

[0064] To solve the problem of how to improve the accuracy and efficiency of the agile transceiver algorithm verification in the prior art, embodiments of the present application respectively propose an agile transceiver correction algorithm verification method and an agile transceiver correction algorithm verification system, which will be described in detail below.

[0065] Please refer to Figure 1 , Figure 1 is a flowchart of an agile transceiver correction algorithm verification method according to an exemplary embodiment of the present application. As shown in Figure 1 , in an exemplary embodiment, the agile transceiver correction algorithm verification method at least includes steps S110 to S140, which are described in detail as follows:

[0066] In step S110, the registers of the target agile transceiver are read and written by the pre-configured programmable module to configure the circuit state of the target agile transceiver to the target state.

[0067] Exemplarily, the agile transceiver circuit state is configured, that is, the FPGA-based hardware platform controls the register of the agile transceiver through the UART (Universal Asynchronous Receiver / Transmitter) protocol for read-write control.

[0068] In step S120, according to the programmable module, the IQ signal of the target agile transceiver in the target state is collected.

[0069] Exemplarily, the FPGA-based hardware platform collects the IQ (I: In-phase component; Q: quadrature component) data of the agile transceiver through TCP / IP (Transmission Control Protocol / Internet Protocol).

[0070] In step S130, the IQ signal is transmitted to the pre-configured host computer, so that the agile transceiver correction algorithm pre-built in the host computer receives the receive channel correction and the transmit channel correction according to the IQ signal, and obtains the correction value corresponding to the receive channel correction and the correction value corresponding to the transmit channel correction.

[0071] Exemplarily, the collected IQ data is taken as the input of the to-be-verified algorithm, and the algorithm module is run, that is, the receive DC correction, the receive IQ correction, the transmit DC correction (direct current imbalance estimation), and the transmit IQ correction (IQ amplitude and phase error estimation) of the agile transceiver are completed.

[0072] In step S140, through the host computer, the correction value corresponding to the receive channel correction and the correction value corresponding to the transmit channel correction are written into the register of the target agile transceiver, so as to estimate the residual value of the receive channel, measure the sideband suppression and local oscillator suppression of the transmit channel, and verify the correction effect of the agile transceiver correction algorithm according to the residual value, the sideband suppression and the local oscillator suppression.

[0073] Exemplarily, the correction value is written into the correction register of the agile transceiver by using the host computer interface, the DC residual value and the IQ residual value of the receive channel are estimated, and the sideband suppression and the local oscillator suppression of the transmit channel are measured, so as to complete the effect verification after correction.

[0074] From the above steps S310 to S350, it can be known that the scheme provided in the embodiment is divided into two processes: a receiving channel algorithm verification process and a transmitting channel algorithm verification process. The receiving channel algorithm verification process is used to perform DC correction and IQ correction on the receiving channel of the agile transceiver, and to estimate the DC residual value and the IQ residual value of the corrected result. The transmitting channel algorithm verification process is used to perform DC correction and IQ correction on the transmitting channel of the agile transceiver, and to verify the result of the transmitting algorithm by observing the improvement of the local oscillator suppression and the sideband suppression of the transmission, so as to verify the result of the transmitting algorithm. In the application, the agile transceiver is taken as a carrier, a programmable module is used to realize various transmission protocols and the bottom layer driving of the agile transceiver, the algorithm and the algorithm correction function in the upper computer are combined, and a correction algorithm verification method for the agile transceiver is formed. The agile transceiver is taken as a carrier, the problem of low accuracy caused by the channel model in the prior art is solved, and the accuracy of the correction algorithm of the agile transceiver is improved. The programmable module is used to realize various transmission protocols and the bottom layer driving of the agile transceiver, the defects of the efficiency, the real-time performance and the like of the complex algorithm verification system are solved, and the efficiency of the correction algorithm of the agile transceiver is improved. The hybrid programming in the upper computer is realized, the functions of correction and correction algorithm verification are realized, and the defects of long algorithm verification period and complex iterative analysis are solved.

[0075] In an embodiment of the present application, the receiving channel correction and the transmitting channel correction are performed according to the IQ signal, and the correction value corresponding to the receiving channel correction and the correction value corresponding to the transmitting channel correction are obtained, comprising:

[0076] The receiving channel and the transmitting channel are initialized;

[0077] The receiving channel DC correction and the receiving channel IQ correction are performed according to the initialized receiving channel and the IQ signal, the correction code corresponding to the receiving channel DC correction and the correction code corresponding to the receiving channel IQ correction are obtained, and the correction code corresponding to the receiving channel DC correction and the correction code corresponding to the receiving channel IQ correction are included in the correction value corresponding to the receiving channel correction.

[0078] The DC single-point correction value of the receiving channel and the IQ single-point correction table are obtained according to the IQ signal, the transmitting channel DC correction is performed on the initialized transmitting channel according to the DC single-point correction value, the transmitting channel IQ correction is performed on the initialized transmitting channel according to the IQ single-point correction table, the correction value corresponding to the transmitting channel DC correction and the correction value corresponding to the transmitting channel IQ correction are obtained, and the correction value corresponding to the transmitting channel DC correction and the correction value corresponding to the transmitting channel IQ correction are included in the correction value corresponding to the transmitting channel correction.

[0079] For example, refer to Figure 2 , Figure 2is another exemplary embodiment of the application shown in the flow diagram of the agile transceiver correction algorithm verification method. Agile transceiver correction algorithm verification method is divided into two processes: receiving channel algorithm verification process and transmitting channel algorithm verification process, wherein the receiving channel algorithm verification process is used to initialize the RX (receiving channel) of the agile transceiver receiving channel, and then perform DC (Direct Cuurent, direct current) coarse correction, DC fine correction and IQ correction, and finally the correction value is imported into the agile transceiver to estimate the DC residual value and IQ residual value of RX; the transmitting channel algorithm verification process is used to initialize the TRX (transmitting channel) of the agile transceiver transmitting channel, and then perform receiving channel correction, TX-DC correction (transmitting channel DC correction) and TX-IQ correction (transmitting channel IQ correction), and the results of the correction are observed to improve the improvement of the transmitting local oscillator suppression and the sideband suppression, so as to verify the results of the transmitting algorithm.

[0080] In an embodiment of the application, according to the IQ signal, the DC single-point correction value of the receiving channel and the IQ single-point correction table are obtained, comprising:

[0081] Configuring the gain of the receiving channel;

[0082] According to the receiving channel after configuring the gain and the IQ signal, the receiving channel DC estimation and the receiving channel DC correction are performed, and the DC single-point correction value corresponding to the receiving channel DC correction is extracted;

[0083] Configuring the transmitting local oscillator phase-locked loop, and according to the transmitting local oscillator phase-locked loop and the IQ signal, the receiving channel IQ single-point estimation and the receiving channel IQ single-point correction are performed, and the IQ single-point correction table corresponding to the receiving channel IQ single-point correction is extracted.

[0084] For example, see Figure 3 , Figure 3 is a flow diagram of the acquisition of the DC single-point correction value and the IQ single-point correction table according to an exemplary embodiment of the application. Configure the receiving channel gain, collect IQ data, receive DC estimation, receive DC correction, configure the transmitting local oscillator phase-locked loop, receive IQ single-point estimation, receive IQ single-point correction, and receive IQ correction. If no, loop configuration transmitting local oscillator phase-locked loop, receive IQ single-point estimation, receive IQ single-point correction and other processes, if yes, jump out of the loop and execute the next step, calculate the receiving channel DC single-point correction value and the IQ single-point correction table.

[0085] In an embodiment of the application, the correction value corresponding to the receiving channel correction is written into the register of the target agile transceiver to estimate the residual value of the receiving channel, comprising:

[0086] write the corresponding correction code of the receive channel DC correction and the correction code of the receive channel IQ correction into the register of the target agile transceiver through a serial port;

[0087] change the gain of the receive channel of the target agile transceiver through a serial port, and change the input signal frequency of the receive channel through an Ethernet;

[0088] collect a new IQ signal corresponding to the input signal frequency, and transmit the new IQ signal to the host computer, so as to estimate the DC residual value and the IQ residual value of the receive channel through the host computer.

[0089] For example, the DC correction code and the IQ correction code are configured into the register of the agile transceiver through a serial port; finally, the DC residual value and the IQ residual value of the receive channel are calculated, that is, the gain of the receive channel is changed through a serial port, the input signal frequency of the receive channel is changed through an Ethernet interface control instrument, and IQ data is collected, and a MATLAB (MathWorks company's commercial mathematical software, used in data processing, wireless communication, deep learning, etc.) library file is called to complete the analysis of the DC residual value and the IQ residual value of the receive channel, so as to judge the advantages and disadvantages of the algorithm, and the algorithm verification process of the receive channel is completed here.

[0090] In an embodiment of the present application, the correction value corresponding to the transmit channel correction is written into the register of the target agile transceiver to measure the sideband suppression and local oscillator suppression of the transmit channel, including:

[0091] write the correction value corresponding to the transmit channel DC correction and the correction value corresponding to the transmit channel IQ correction into the register of the target agile transceiver through a serial port;

[0092] change the correction value corresponding to the transmit channel correction through a serial port, and test the local oscillator suppression and the sideband suppression of the transmit channel output through an Ethernet interface control pre-configured instrument.

[0093] For example, the DC correction code and the IQ correction code are configured into the register of the DUT (agile transceiver) through a serial port; finally, the local oscillator suppression and the sideband suppression of the transmission are observed, that is, the correction value of the transmit channel is changed through a serial port, the local oscillator suppression and the sideband suppression of the transmission output are tested through an Ethernet interface control instrument, and the advantages and disadvantages of the two indicators before and after correction are analyzed, so as to judge the advantages and disadvantages of the algorithm, and the algorithm verification process of the transmit channel is completed here.

[0094] In an embodiment of the present application, the receive channel is initialized, including:

[0095] configure the phase-locked loop of the clock, configure the phase-locked loop of the channel, configure the analog receiving channel, configure the analog filter, configure the ADC, configure the PFIR filter of the digital receiving channel, configure the post-filter, configure the mode of the digital receiving channel, configure the mode of the BB port, open the digital clock, and reset the AGC.

[0096] For example, referring to Figure 4 , Figure 4 is a flowchart of the initialization of the receiving channel according to an example embodiment of the present application. After the operations of configuring the phase-locked loop of the clock, configuring the phase-locked loop of the channel, configuring the analog receiving channel, configuring the analog filter, configuring the ADC, configuring the PFIR filter of the digital receiving channel, configuring the post-filter, configuring the mode of the digital receiving channel, configuring the mode of the BB port, opening the digital clock, and resetting the AGC, the initialization configuration of the receiving channel of the agile transceiver is completed.

[0097] In an embodiment of the present application, the initialization of the transmitting channel comprises:

[0098] configure the phase-locked loop of the clock, configure the phase-locked loop of the receiving channel, configure the analog receiving channel, configure the analog filter, configure the ADC, configure the PFIR filter of the digital receiving channel, configure the post-filter, configure the mode of the digital receiving channel, configure the mode of the BB port, open the digital clock, reset the AGC, configure the phase-locked loop of the transmitting channel, configure the analog filter of the transmitting channel, configure the PFIR filter of the digital transmitting channel, configure the pre-filter, and configure the mode of the digital transmitting channel.

[0099] For example, referring to Figure 5 , Figure 5 is a flowchart of the initialization of the transmitting channel according to an example embodiment of the present application. The operations include configuring the phase-locked loop of the clock, configuring the phase-locked loop of the receiving channel, configuring the analog receiving channel, configuring the analog filter, configuring the ADC, configuring the PFIR filter of the digital receiving channel, configuring the post-filter, configuring the mode of the digital receiving channel, configuring the mode of the BB port, opening the digital clock, resetting the AGC, configuring the phase-locked loop of the transmitting channel, configuring the analog filter of the transmitting channel, configuring the PFIR filter of the digital transmitting channel, configuring the pre-filter, and configuring the mode of the digital transmitting channel.

[0100] In an embodiment of the present application, according to the initialized receiving channel and the IQ signal, the receiving channel DC correction and the receiving channel IQ correction are performed, and the correction code corresponding to the receiving channel DC correction and the correction code corresponding to the receiving channel IQ correction are obtained, which comprises:

[0101] When there is no radio frequency input, frequency domain estimation is performed on the two baseband signals in the IQ signal, the zero frequency amplitude value in the frequency domain estimation result is extracted, the coarse correction code and the fine correction code of the I and Q channels are calculated according to the zero frequency amplitude value, and the coarse correction code and the fine correction code of the I and Q channels are compensated in the analog domain and the digital domain to obtain the correction code corresponding to the DC correction of the receiving channel.

[0102] A single-tone sinusoidal wave is obtained as an input test signal, frequency domain estimation is performed on the two baseband signals in the IQ signal through the single-tone sinusoidal wave, the parameters corresponding to the IQ amplitude and phase imbalance are extracted and compensated to obtain the correction code corresponding to the IQ correction of the receiving channel.

[0103] For example, referring to Figure 6 , Figure 6 is a flowchart of the receiving channel correction according to an example embodiment of the present application. DC correction, that is, configuring the receiving channel gain, collecting IQ data, receiving DC estimation, judging whether to end the estimation (if no, repeating the processes of configuring the receiving channel gain, collecting IQ data, receiving DC estimation, etc.; if yes, jumping out of the loop and executing the next step), calculating the RF and IF coarse correction code and the fine correction code of the receiving DC. It should be noted that when there is no radio frequency input, frequency domain estimation is performed on the received I and Q baseband signals, the zero frequency amplitude value is extracted and the coarse and fine correction codes of the I and Q channels are calculated, which are compensated in the analog and digital domains to suppress the influence of DC; for the problem that the I and Q DC errors change with the radio frequency and gain when multiple radio frequencies and multiple gains are input, the receiving channel adopts an analog plus digital DC single-point correction lookup table structure.

[0104] IQ correction, that is, configuring the receiving channel gain, collecting IQ data, receiving IQ estimation, judging whether to end the estimation (if no, repeating the processes of configuring the receiving channel gain, collecting IQ data, receiving IQ estimation, etc.; if yes, jumping out of the loop and executing the next step), calculating the correction code of the receiving IQ. It should be noted that a single-tone sinusoidal wave is used as an input test signal, frequency domain estimation is performed on the received I and Q baseband signals, the IQ amplitude and phase imbalance parameters are extracted and compensated, and the image interference caused by IQ imbalance is suppressed in the digital domain; for the problem that the I and Q amplitude and phase change with the intermediate frequency, radio frequency and gain when wideband input is used, the receiving channel adopts a digital filter plus IQ single-point correction lookup table structure.

[0105] In an embodiment of the present application, the DC single-point correction value is used for transmitting channel DC correction, and the IQ single-point correction table is used for transmitting channel IQ correction, and the correction value corresponding to the transmitting channel DC correction and the correction value corresponding to the transmitting channel DC correction are obtained, including:

[0106] When there is no radio frequency input, frequency domain estimation is performed on the I and Q baseband signals in the IQ signal, and the zero frequency amplitude in the frequency domain estimation result is extracted. The DC single-point correction value is changed by dichotomy to make the zero frequency amplitude lowest, the transmit channel DC parameter is extracted, and digital domain compensation is performed on the transmit DC parameter to obtain the correction value corresponding to the transmit channel DC correction.

[0107] A single tone sine wave output by a digital oscillator is obtained as an input test signal. Frequency domain estimation is performed on the I and Q baseband signals in the IQ signal through the single tone sine wave, and the mirror interference amplitude caused by IQ imbalance in the frequency domain estimation result is extracted. The single-point correction value in the IQ single-point correction table is changed by dichotomy to make the mirror interference amplitude lowest. The parameter corresponding to the transmit channel IQ amplitude and phase imbalance when the mirror interference amplitude is lowest is extracted, and digital domain compensation is performed on the parameter to obtain the correction value corresponding to the transmit channel DC correction.

[0108] For example, see Figure 7 , Figure 7 is a flowchart of the transmit channel correction according to an exemplary embodiment of the present application. TX_DC correction, i.e. configuring the receive channel single-point DC correction value, using dichotomy, changing the transmit channel DC register, collecting IQ data, estimating the DC residual value, judging whether to end the estimation (if no, loop execution using dichotomy, changing the transmit channel DC register), collecting IQ data, estimating the DC residual value, etc. If no, jump out of the loop and execute the next step), output the TX_DC correction value. It should be noted that after receiving DC correction, when there is no radio frequency input, frequency domain estimation is performed on the received I and Q baseband signals, the zero frequency amplitude is extracted, the transmit DC single-point correction value is changed by dichotomy to make the receive zero frequency amplitude lowest, the transmit DC parameter is obtained and digital domain compensation is performed to improve the transmit local oscillator suppression. For the problem that the I and Q two-way DC error changes with the radio frequency when multiple radio frequencies are input, the transmit channel uses a digital DC single-point correction lookup table structure.

[0109] TX_IQ correction, that is, configuring a transmit channel NCO configuration word, configuring a receive channel DC single-point correction value, an IQ single-point correction value, using a bisection method, changing the transmit channel NCO configuration word, collecting IQ data, estimating an IQ residual value, judging whether to end the estimation (if no, cyclically executing the processes of using the bisection method, changing the transmit channel IQ register, collecting IQ data, estimating the IQ residual value, etc.; if yes, jumping out of the loop and executing the next process), outputting the TX_IQ single-point correction value, judging whether the transmit IQ correction is completed (if no, cyclically executing the processes of configuring the transmit channel NCO configuration word, configuring the receive channel DC single-point correction value, the IQ single-point correction value, using the bisection method, changing the transmit channel NCO configuration word, collecting IQ data, estimating the IQ residual value, judging whether to end the estimation, outputting the TX_IQ single-point correction value, etc.; if yes, jumping out of the loop and executing the next process), and calculating a transmit channel TX_IQ correction value. It should be noted that after the receive IQ correction, the NCO outputs a single-tone sine wave as an input test signal, the I and Q two-way baseband signals received are estimated in the frequency domain, the mirror interference amplitude caused by the IQ imbalance is extracted, the transmit IQ single-point correction value is changed through the bisection method to make the received mirror interference amplitude the lowest, the transmit IQ amplitude and phase imbalance parameters are obtained and compensated in the digital domain, and the transmit sideband suppression is improved; for the problem that the I and Q two-way amplitudes and phases change with the intermediate frequency and radio frequency when a wideband input is used, the transmit side adopts a digital filter plus an IQ single-point correction lookup table structure.

[0110] Figure 8 is a block diagram of a fast-changing transceiver correction algorithm verification system according to an example embodiment of the present application. As shown in the figure, Figure 8 the example fast-changing transceiver correction algorithm verification system includes:

[0111] a target fast-changing transceiver configured to generate an IQ signal in a target state;

[0112] a programmable module configured to read and write control a register of the target fast-changing transceiver to configure a circuit state of the target fast-changing transceiver to the target state;

[0113] a host computer configured to make a pre-constructed fast-changing transceiver correction algorithm perform receive channel correction and transmit channel correction according to the IQ signal, and obtain a correction value corresponding to the receive channel correction and a correction value corresponding to the transmit channel correction, and write the correction value corresponding to the receive channel correction and the correction value corresponding to the transmit channel correction into the register of the target fast-changing transceiver to estimate a residual value of the receive channel, measure sideband suppression and local oscillator suppression of the transmit channel, and verify a correction effect of the fast-changing transceiver correction algorithm according to the residual value, the sideband suppression and the local oscillator suppression.

[0114] Exemplarily, the system is composed of four parts, wherein the agile transceiver is an algorithm verification platform, which can generate input excitation for running the algorithm and write the final verification conclusion; the instrument provides hardware support for reference and measurement of the agile transceiver in the algorithm verification stage; the FPGA development board is used for completing data analysis of the agile transceiver and transmitting the data to the PC (Personal Computer) and reading and writing the state of the agile transceiver circuit; the PC provides the core library of the algorithm verification system, realizes the functions of agile transceiver circuit state configuration, algorithm analysis of the collected IQ data, writing of the analysis results obtained by the algorithm into the agile transceiver verification, and control of the instrument to provide excitation required by the algorithm.

[0115] Exemplarily, in the embodiment of the present application, the XND1500MBU agile transceiver is adopted, which is a single-chip integrated circuit integrating two receiving channels and one transmitting channel, and has the characteristics of high integration, flexible configuration, and strong versatility; the receiving channel is composed of units such as a low-noise amplifier, a down converter, an intermediate frequency filter, an analog-to-digital converter, and a digital filter, has a zero intermediate frequency data communication mode, a channel gain control range of 73 dB, a gain control step of 1 dB, and can support automatic gain control and manual gain control functions; the transmitting channel is composed of units such as a digital filter, a digital-to-analog converter, an intermediate frequency filter, and an up converter, has a channel gain control range of 90 dB, a gain control step of 0.5 dB. The main performance indicators of the XND1500MBU agile transceiver are as follows: it has a 0.5-2.5 GHz radio frequency signal transceiving capability; the maximum intermediate frequency bandwidth supports 20 MHz; it integrates two receiving channels and one transmitting channel; each channel has an independent local oscillator source and flexible configuration; it supports TDD and FDD working modes; it integrates a temperature sensor and a transmitting power detection unit; it integrates two auxiliary DACs and one auxiliary ADC; and it supports CMOS / LVDS communication interfaces.

[0116] Exemplarily, in the embodiment of the present application, the AV7K325 core board is selected, which is composed of an XC7K325, four DDR3s, one QSPI FLASH minimum system, and two crystal oscillators providing clocks, one single-ended 200 MHz crystal oscillator providing a DDR control reference clock for the FPGA logic, and the other differential 125 MHz crystal oscillator providing a reference clock for the GTX transceiver. The requirements of the application for the FPGA signal processing capability and port rate are met. It should be noted that the FPGA development platform can use a development board or an FPGA chip configuration peripheral circuit with similar functions to complete, and the present application does not limit this.

[0117] Exemplarily, in the embodiment of the present application, CH395 PHY (Physical Layer) chip is adopted to realize the analysis of TCP / IP protocol. CH395 is an Ethernet protocol stack management chip, which is used for single-chip microcomputer or DSP system to perform Ethernet communication. CH395 chip has 10 / 100M Ethernet media transmission layer (MAC) and physical layer (PHY) by itself, is fully compatible with IEEE802.310 / 100M protocol, and has built-in PPPOE, IP, DHCP, ARP, ICMP, IGMP, UDP, TCP and other Ethernet protocol stack firmware, which meets the requirement of the application on rate transmission.

[0118] Exemplarily, in the embodiment of the present application, Microsoft Visual Studio 2019 IDE Community Edition is adopted in the host computer. Microsoft Visual Studio 2019 (hereinafter referred to as VS2019) is a development kit series of American Microsoft Corporation, which includes most of the tools required in the entire software life cycle. The application takes C#.NET as the host software architecture platform, uses C# language to complete the UI interface programming on the architecture platform, realizes the interoperation of the interface and the database and the calling of the underlying driver through the reference of integrated API (Application Programming Interface), and realizes the logical control of the algorithm verification system by using the Microsoft.Net (a free open source development platform for building various applications) environment as the programming platform and the visual UI program written by C#. The different algorithm modules are debugged by using the powerful and professional data model analysis capability of Matlab language, are called by the UI in the form of dynamic link library (dll file), and realize the correction algorithm estimation. It should be noted that the host computer software can be realized by using other object-oriented UI programming languages (such as JAVA), and the present application does not limit this.

[0119] It should be noted that Matlab: the core correction algorithm for data processing in the embodiment of the present application is realized by using the commercial mathematical software MATLAB of American MathWorks Company. The application software realizes the IQ calculation and direct current offset calculation of collected information by calling MATLAB, and finally saves the calculation results (multi-layer feature information) to the local PC.

[0120] It should be noted that in the embodiments of the present application, the FPGA design process is completed by Vivado 2018.3, Vivado 2018.3 is a development kit series of the United States Xilinx Corporation, which is an integrated development environment customized for its products, supports Block Design, Verilog, VHDL and other design input methods, and can complete the complete FPGA design process from design input, synthesis adaptation, simulation to download.

[0121] In an embodiment of the present application, the hardware platform is composed of two parts of lower machine and upper machine. The lower machine includes FPGA development board, agile transceiver, instruments and meters, etc. The FPGA development board is mainly composed of an FPGA development environment with XC7K325 circuit as the core. The instruments and meters mainly use the E4438C vector signal source of Agilent Corporation. The upper machine is mainly composed of a PC host. The communication between the lower machine and the upper machine is connected by Ethernet cable and USB to UART cable.

[0122] The software platform of the upper machine is a C# style GUI interface and a man-machine operation interface. It is used to receive the signal of the lower machine, collect the measurement data of the instruments and meters, call the.Net DLL algorithm library generated by Matlab to realize the correction and related algorithm verification, and simultaneously issue the calculation conclusion to the lower machine for hardware verification and matching, so as to realize the cyclic iteration and visual operation of the agile transceiver algorithm verification. The hardware platform is the basis for the realization of system functions. The FPGA development platform takes XC7K325 as the core, communicates with peripherals through the interface on the development board, the PC collects the IQ data of the DUT (Device Under Test) through the Ethernet interface, the PC uses the serial port protocol to send data to the FPGA cache through the UART, and the FPGA sends the configuration information of the upper machine to the DUT through the FMC interface to complete the setting of the DUT state. The hardware part of the upper machine includes a PC host. The upper machine part connects each subsystem through Ethernet, and realizes data interaction with the lower machine through TCP / IP protocol and UART protocol; the communication between each component of the upper machine realizes algorithm verification and historical data extraction.

[0123] The software platform is the core of the realization of the functions of the whole system, which is composed of the upper machine UI interface, the MATLAB correction algorithm library and the lower machine communication interface. The upper machine UI interface provides the system total monitoring and man-machine interaction window. This software platform is written by Microsoft C#.NET, and the underlying program realizes algorithm encapsulation, data calling, instrument and meter data acquisition visualization and other functions, and simultaneously realizes data interaction with the lower machine and instruments and meters through Ethernet communication; through the software platform, man-machine monitoring and controllable iteration of algorithm verification can be realized. This platform is the carrier of mixed programming of.Net and Matlab, and is also the data support of the algorithm.

[0124] It should be noted that the specific indicators of the agile transceiver correction algorithm verification system in the embodiments of the present application are as follows: the PCB size of the FPGA development environment is ≤350cm2, 200mm*170mm; the data processing efficiency is 100Mb / s; the system reliability is ≥99.999%; the algorithm verification efficiency is 2min / received DC correction, 2min / received IQ correction, the total time of received correction is 5min, 5min / transmitted DC correction, 30min / transmitted IQ correction, and the total time of received correction is 40min.

[0125] In the exemplary agile transceiver correction algorithm verification system, the agile transceiver is taken as a carrier, various transmission protocols and the bottom layer driver of the agile transceiver are realized through a programmable module, the algorithm and the algorithm correction function in the host computer are combined to form an agile transceiver correction algorithm verification method. Taking the agile transceiver as a carrier can solve the problem of low accuracy caused by the channel model in the prior art and improve the accuracy of the agile transceiver correction algorithm; realizing various transmission protocols and the bottom layer driver of the agile transceiver through the programmable module can solve the defects of the efficiency and real-time performance of the complex algorithm verification system and improve the efficiency of the agile transceiver correction algorithm; and realizing hybrid programming in the host computer can realize the functions of correction and correction algorithm verification and solve the defects of long algorithm verification period and complex iterative analysis.

[0126] It should be noted that the agile transceiver correction algorithm verification system provided by the above embodiments and the agile transceiver correction algorithm verification method provided by the above embodiments belong to the same concept, and the specific manner in which each module and unit performs operations has been described in detail in the method embodiments, which will not be repeated here. The agile transceiver correction algorithm verification system provided by the above embodiments can be completed by different functional modules according to the above functions in actual application, that is, the internal structure of the system is divided into different functional modules to complete all or part of the functions described above, and this is not limited here.

[0127] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.

Claims

1. A method for verifying a fast transceiver calibration algorithm, characterized in that, The method includes: The registers of the target agile transceiver are read and written using a pre-configured programmable module to configure the circuit state of the target agile transceiver to the target state. According to the programmable module, the IQ signal of the target agile transceiver in the target state is acquired; The IQ signal is transmitted to a pre-configured host computer so that the pre-built agile transceiver correction algorithm in the host computer performs receive channel correction and transmit channel correction according to the IQ signal, and obtains the correction value corresponding to the receive channel correction and the correction value corresponding to the transmit channel correction. The host computer writes the correction values ​​corresponding to the receiving channel correction and the transmitting channel correction into the register of the target agile transceiver to estimate the residual value of the receiving channel, measure the sideband suppression and local oscillator suppression of the transmitting channel, and verify the correction effect of the agile transceiver correction algorithm based on the residual value, sideband suppression and local oscillator suppression. Based on the IQ signal, receive channel correction and transmit channel correction are performed, and correction values ​​corresponding to receive channel correction and transmit channel correction are obtained, including: Initialize the receiving channel and the transmitting channel; Based on the initialized receiving channel and the IQ signal, DC correction and IQ correction of the receiving channel are performed to obtain the correction code corresponding to the DC correction and the correction code corresponding to the IQ correction of the receiving channel. The correction code corresponding to the DC correction and the correction code corresponding to the IQ correction of the receiving channel are included in the correction value corresponding to the receiving channel correction. Based on the IQ signal, the DC single-point correction value and IQ single-point correction table of the receiving channel are obtained. The DC single-point correction value is used to perform DC correction on the initialized transmitting channel, and the IQ correction table is used to perform IQ correction on the initialized transmitting channel. The correction values ​​corresponding to the DC correction and IQ correction of the transmitting channel are obtained, wherein the correction values ​​corresponding to the DC correction and IQ correction of the transmitting channel are included in the correction values ​​corresponding to the transmitting channel correction.

2. The method for verifying the agile transceiver calibration algorithm according to claim 1, characterized in that, Based on the IQ signal, the DC single-point correction value and IQ single-point correction table of the receiving channel are obtained, including: Configure the gain of the receiving channel; Based on the received channel with the configured gain and the IQ signal, DC estimation and DC correction of the received channel are performed, and the DC single-point correction value corresponding to the DC correction of the received channel is extracted. Configure a transmit local oscillator phase-locked loop, and perform single-point estimation and single-point correction of the receive channel IQ based on the transmit local oscillator phase-locked loop and the IQ signal, and extract the IQ single-point correction table corresponding to the single-point correction of the receive channel IQ.

3. The method for verifying the agile transceiver calibration algorithm according to claim 1, characterized in that, The correction value corresponding to the received channel correction is written into the register of the target agile transceiver to estimate the residual value of the received channel, including: The correction code corresponding to the DC correction of the receiving channel and the correction code corresponding to the IQ correction of the receiving channel are written into the register of the target agile transceiver via serial port; The receiver channel gain of the target agile transceiver is changed via serial port, and the input signal frequency of the receiver channel is changed via Ethernet. A new IQ signal corresponding to the frequency of the input signal is acquired, and the new IQ signal is transmitted to the host computer so that the host computer can estimate the DC residual value and IQ residual value of the receiving channel.

4. The method for verifying the agile transceiver calibration algorithm according to claim 1, characterized in that, The correction value corresponding to the transmission channel correction is written into the register of the target agile transceiver to measure the sideband suppression and local oscillator suppression of the transmission channel, including: The correction values ​​corresponding to the DC correction of the transmission channel and the correction values ​​corresponding to the IQ correction of the transmission channel are written into the register of the target agile transceiver via the serial port. The corresponding correction value of the transmission channel is changed via serial port, and the pre-configured instrument is controlled via Ethernet interface to test the local oscillator suppression and sideband suppression of the transmission channel output.

5. The method for verifying the agile transceiver calibration algorithm according to claim 1, characterized in that, Initializing the receiving channel includes: Configure the always-locked loop (PLL), configure the channel PLL, configure the analog receive channel, configure the analog filter, configure the ADC, configure the digital receive channel PFIR filter, configure the post-filter, configure the digital receive channel mode, configure the BB port mode, enable the digital clock, and reset the AGC.

6. The method for verifying the agile transceiver calibration algorithm according to claim 1, characterized in that, Initializing the transmission channel includes: Configure clock phase-locked loop, configure receive channel phase-locked loop, configure analog receive channel configuration, configure analog filter, configure ADC, configure digital receive channel PFIR filter, configure post-filter, configure digital receive channel mode, configure BB port mode, enable digital clock, reset AGC, configure transmit channel phase-locked loop, configure transmit channel analog filter, configure digital transmit channel PFIR filter, configure pre-filter, configure digital transmit channel mode.

7. The method for verifying the agile transceiver calibration algorithm according to claim 1, characterized in that, Based on the initialized receiving channel and the IQ signal, perform receiving channel DC correction and receiving channel IQ correction to obtain the correction code corresponding to the receiving channel DC correction and the correction code corresponding to the receiving channel IQ correction, including: When there is no radio frequency input, frequency domain estimation is performed on the two baseband signals in the IQ signal, the zero frequency amplitude value is extracted from the frequency domain estimation result, the coarse correction code and fine correction code of the I and Q channels are calculated according to the zero frequency amplitude value, and the coarse correction code and fine correction code of the I and Q channels are compensated in the analog domain and digital domain to obtain the correction code corresponding to the DC correction of the receiving channel. A single-tone sine wave is obtained as the input test signal. The frequency domain of the two baseband signals in the IQ signal is estimated using the single-tone sine wave. The parameters corresponding to the IQ amplitude and phase imbalance are extracted and compensated to obtain the correction code corresponding to the IQ correction of the receiving channel.

8. The method for verifying the agile transceiver calibration algorithm according to claim 1, characterized in that, Perform DC correction on the transmit channel based on the DC single-point correction value, perform IQ correction on the transmit channel based on the IQ single-point correction table, and obtain the correction value corresponding to the DC correction of the transmit channel and the correction value corresponding to the DC correction of the transmit channel, including: When there is no radio frequency input, frequency domain estimation is performed on the I and Q baseband signals in the IQ signal and the zero frequency amplitude is extracted from the frequency domain estimation result. The DC single-point correction value is changed by the bisection method to make the zero frequency amplitude the lowest. The DC parameters of the transmission channel are extracted and digital domain compensation is performed on the DC parameters of the transmission channel to obtain the correction value corresponding to the DC correction of the transmission channel. A single-tone sine wave output from a digital oscillator is used as the input test signal. The I and Q baseband signals in the IQ signal are estimated in the frequency domain using the single-tone sine wave, and the image interference amplitude caused by the IQ imbalance is extracted from the frequency domain estimation result. The single-point correction value in the IQ single-point correction table is changed by the bisection method to minimize the image interference amplitude. The parameter corresponding to the IQ amplitude and phase imbalance of the transmission channel when the image interference amplitude is minimized is extracted, and the parameter is digitally compensated to obtain the correction value corresponding to the DC correction of the transmission channel.

9. A verification system for agile transceiver calibration algorithm, characterized in that, include: Target agile transceiver, used to generate IQ signals in target state; A programmable module is used to read and write the registers of the target agile transceiver in order to configure the circuit state of the target agile transceiver to the target state. The host computer is used to enable the pre-built agile transceiver calibration algorithm to perform receive channel calibration and transmit channel calibration based on the IQ signal, and to obtain the calibration values ​​corresponding to the receive channel calibration and the transmit channel calibration, and to write the calibration values ​​corresponding to the receive channel calibration and the transmit channel calibration into the register of the target agile transceiver, so as to estimate the residual value of the receive channel, measure the sideband suppression and local oscillator suppression of the transmit channel, and verify the calibration effect of the agile transceiver calibration algorithm based on the residual value, sideband suppression and local oscillator suppression; The host computer is specifically used to initialize the receiving channel and the transmitting channel; based on the initialized receiving channel and the IQ signal, it performs receiving channel DC correction and receiving channel IQ correction, and obtains the correction code corresponding to the receiving channel DC correction and the correction code corresponding to the receiving channel IQ correction, wherein the correction code corresponding to the receiving channel DC correction and the correction code corresponding to the receiving channel IQ correction are included in the correction value corresponding to the receiving channel correction; based on the IQ signal, it obtains the receiving channel DC single-point correction value and the receiving channel IQ single-point correction table, performs transmitting channel DC correction on the initialized transmitting channel based on the DC single-point correction value, performs transmitting channel IQ correction on the initialized transmitting channel based on the IQ single-point correction table, and obtains the correction value corresponding to the transmitting channel DC correction and the correction value corresponding to the transmitting channel IQ correction, wherein the correction value corresponding to the transmitting channel DC correction and the correction value corresponding to the transmitting channel IQ correction are included in the correction value corresponding to the transmitting channel correction.

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