System and method for cross-tier key-value storage architecture with compute storage devices

Abstract

A data storage system is provided, comprising: a host including a host cache portion of a mirror cache, the host cache portion to store metadata indicating locations of data nodes stored in a core cache portion of the mirror cache; and a storage device including the core cache portion located in a common memory region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and interest in U.S. Provisional Application No. 63 / 332,161, filed April 18, 2022, entitled “ARCHITECTURE OF CROSS-LAYER KEY-VALUE STORE WITH COMPUTATIONAL STORAGE DEVICE”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more aspects of embodiments of this disclosure relate to systems and methods for data storage. Background Technology

[0004] This background section is intended to provide context only, and the disclosure of any embodiments or concepts in this section does not constitute an admission that the embodiments or concepts are prior art.

[0005] In the field of computer storage, key-value storage can be implemented on a storage system (e.g., a system) that includes a host (e.g., a host computer) and storage devices (e.g., devices including storage media for storing data). The system can store data nodes in the memory (e.g., non-volatile memory) of the storage devices. Data nodes can be accessed by users of the system. The system can perform various operations at the data nodes based on requests from users. The system can identify the data node location of a data node and the key value location within the data node to which an operation is to be performed, based on key-value pairs. For example, the system can process requests associated with a key to (i) search for and find the location of a value (e.g., a data object) corresponding to the key, and (ii) perform the operation associated with the request on the value.

[0006] Therefore, there is a need for methods, devices, and systems for efficiently handling requests for key-value storage. Summary of the Invention

[0007] Various aspects of embodiments of this disclosure relate to computer storage systems and provide improvements to key-value storage.

[0008] According to some embodiments of the present disclosure, a data storage system is provided, including: a host, the host including a host cache portion of a mirror cache, the host cache portion being used to store metadata indicating the location of data nodes stored in a kernel cache portion of the mirror cache; and a storage device including a kernel cache portion located in a common memory region.

[0009] The data storage system may also include: a search layer, located on the host and configured to be processed by the host; and a data layer, located on the storage device and configured to be processed by the storage device.

[0010] The search layer may include a tree structure, and the data layer includes data nodes corresponding to leaf nodes in a doubly linked list that corresponds to leaf nodes in the tree structure.

[0011] The storage device may also include: persistent memory coupled to a common memory region; and processing circuitry coupled to the common memory region.

[0012] The processing circuitry can be configured to perform data operations on the data nodes and can be configured to write the data nodes to the kernel cache portion as updated data nodes.

[0013] The host can be configured to: determine when updated data nodes are populated in the common memory area; and to cause peer-to-peer writes from the common memory area to persistent memory.

[0014] The host can be configured to: determine that the amount of available space in a data node is less than the amount of space needed to accommodate data access requests corresponding to the data node; and allocate extension nodes to data nodes.

[0015] The storage device may also include processing circuitry configured to update the metadata of data nodes to point to extension nodes, the metadata of data nodes indicating a first version number, and the metadata of extension nodes indicating a first version number.

[0016] The processing circuitry can be configured to: update extended nodes; update the metadata of data nodes to indicate a second version number, thereby identifying the data node as an updated data node; update the metadata of extended nodes to indicate a second version number, thereby identifying the extended node as an updated extended node; and update the metadata of the updated data node to point to the updated extended node.

[0017] The processing circuitry can be configured to: write updated extension nodes to storage in a non-in-place manner; and write updated data nodes to storage in an in-place manner.

[0018] The host can be configured to manage concurrent access to the storage device by receiving read requests and acquiring read locks on the data nodes, or by receiving write requests and acquiring write locks on the data nodes.

[0019] According to other embodiments of this disclosure, a data storage method is provided, the method comprising: locating metadata in a host cache portion of a mirror cache indicating the location of a data node stored in a storage device, the host cache portion being stored on a host; and determining that the data node exists in a kernel cache portion of the mirror cache, the kernel cache portion being stored on a common memory region of the storage device.

[0020] The method may also include the host locating a partial key in the search layer to find metadata indicating the location of a data node.

[0021] The method may further include: determining that the data node has an available amount of space less than the amount of space required to accommodate data access requests; and assigning an extension node to the data node.

[0022] The storage device may include: persistent memory coupled to a common memory region; and processing circuitry coupled to the common memory region.

[0023] The method may further include: updating the metadata of the data node by the processing circuit to point to the extended node, wherein the metadata of the data node and the metadata of the extended node indicate a first version number.

[0024] The method may further include: updating the extended node; updating the metadata of the data node to indicate a second version number; updating the metadata of the extended node to indicate a second version number, the second version number being able to identify the data node as an updated data node and the extended node as an updated extended node; and updating the metadata of the updated data node to point to the updated extended node.

[0025] The method may further include: writing the updated extension node to the storage of the storage device in a non-in-situ manner; and writing the updated data node to the storage in an in-situ manner.

[0026] According to other embodiments of this disclosure, a non-transitory computer-readable medium implemented on a key-value store is provided, the non-transitory computer-readable medium having computer code that, when executed on a processor, implements a method for data storage, the method comprising: locating host cache metadata in a host cache portion of a mirror cache indicating the location of a data node stored in a storage device; and determining, based on the host cache metadata, that the data node exists in a kernel cache portion of a mirror cache, the kernel cache portion being stored on a common memory region of the storage device.

[0027] The method also includes locating partial keys in the search layer to find host cache metadata. Attached Figure Description

[0028] Non-limiting and non-exhaustive embodiments of this disclosure are described with reference to the following drawings, in which, unless otherwise specified, the same reference numerals refer to the same parts in the various views.

[0029] Figure 1 This is a system diagram depicting a data storage system including a search layer and a data layer according to some embodiments of the present disclosure;

[0030] Figure 2 This is a system diagram depicting a data storage system including a host cache and a kernel cache according to some embodiments of the present disclosure;

[0031] Figure 3A These are combined flowcharts and system diagrams describing the operation of data storage methods within a data storage system according to some embodiments of the present disclosure;

[0032] Figure 3B This describes some embodiments of the present disclosure and Figure 3A The flowchart of the data storage method corresponding to the operation;

[0033] Figure 4 This is a combined flowchart and system diagram of operations of a data storage method within a data storage system that supports variable-length key-value pairs, as described in some embodiments of this disclosure;

[0034] Figure 5 This is a combined flowchart and system diagram of operations for providing a data storage method within a data storage system that supports variable key-value pairs and version-based crash consistency, as described in some embodiments of this disclosure;

[0035] Figure 6 This is a flowchart describing a data storage method (including host-side concurrency control) for a read (or lookup) request according to some embodiments of the present disclosure; and

[0036] Figure 7 This is a flowchart describing a data storage method for write requests, including host-side concurrency control, according to some embodiments of the present disclosure.

[0037] Corresponding reference numerals indicate corresponding components throughout the various views of the figures. Those skilled in the art will understand that the elements in the figures are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements, layers, and regions in the figures may be exaggerated relative to other elements, layers, or regions to aid in clarity and understanding of the various embodiments. Furthermore, common but well-understood elements and components unrelated to the description of the embodiments may not be shown in order to provide less obstructive views of these different embodiments and to make the description clearer. Detailed Implementation

[0038] The features of the inventive concept and methods of its implementation can be more readily understood through the detailed description of the embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments may be embodied in various different forms and should not be construed as limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art aspects and features of the inventive concept. Therefore, processes, elements, and techniques that are not essential for a full understanding of the aspects and features of the inventive concept by those skilled in the art are not described.

[0039] Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements in the drawings and written description, and therefore their description will not be repeated. Furthermore, portions unrelated to the description of the embodiments may be omitted to make the description clearer. In the drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity.

[0040] In this detailed description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the various embodiments. However, it will be apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements.

[0041] It should be understood that although the terms "zeroth," "first," "second," "third," etc., may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or portion described below may be referred to as the second element, component, region, layer, or portion.

[0042] It should be understood that when a component or assembly is referred to as being "on another component or assembly," "connected to," or "coupled to" another component or assembly, it can be directly on, connected to, or coupled to other components or assemblies, or there may be one or more intermediate components or assemblies. However, "direct connection / direct coupling" means that one component is directly connected to or coupled to another component without any intermediate components. Similarly, other expressions describing the relationship between components, such as "between," "immediately adjacent," or "nearby" and "directly adjacent," can be interpreted similarly. Furthermore, it should be understood that when a component or assembly is referred to as being "between" two components or assemblies, it can be the only component or assembly between the two components or assemblies, or there may be one or more intermediate components or assemblies.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “one” also include the plural forms unless the context clearly specifies otherwise. It will be further understood that, when used in this specification, the terms “comprising,” “including,” “having,” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0044] As used herein, the terms “substantially,” “approximately,” “approximately,” and similar terms are used as approximate terms rather than terms of degree, intended to describe the inherent bias of a measured or calculated value that will be recognized by one of ordinary skill in the art. “Approximately” or “approximately” as used herein includes the value and refers to an acceptable range of deviation for a particular value, determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “approximately” may mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the value. Furthermore, the use of “may” in describing embodiments of this disclosure means “one or more embodiments of this disclosure.”

[0045] When one or more embodiments can be implemented differently, a particular processing order may be performed in a manner different from that described. For example, two consecutively described processes may be performed substantially simultaneously, or in the reverse order of their description.

[0046] Any component or combination of components described herein (e.g., in any system diagram included herein) may be used to perform one or more operations of any flowchart included herein. Furthermore, (i) the operations are merely examples and may involve various additional operations not explicitly covered, and (ii) the temporal order of the operations may be changed.

[0047] Electronic or electrical devices and / or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of such devices can be formed on an integrated circuit (IC) chip or a separate IC chip. Furthermore, various components of such devices can be implemented on flexible printed circuit films, tape-on packages (TCPs), printed circuit boards (PCBs), or formed on a substrate.

[0048] Furthermore, the various components of these devices may be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which may be implemented in the computing device using standard memory devices such as random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. Moreover, those skilled in the art will recognize that, without departing from the spirit and scope of the embodiments of this disclosure, the functionality of various computing devices may be combined or integrated into a single computing device, or the performance of a particular computing device may be distributed across one or more other computing devices.

[0049] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the concepts of this invention pertain. It will be further understood that terms such as those defined in common dictionaries should be interpreted as having the same meaning as they have in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0050] As described above, in the field of computer storage, key-value stores can be implemented on a storage system (e.g., a system). This system may include a host (e.g., a host computer) and storage devices (e.g., devices including storage media for storing data). The storage devices may store data nodes in their memory (e.g., non-volatile or persistent memory). Users of the system can request access to the data nodes. For example, a user can instruct the system to receive data access requests (e.g., write requests, read requests, etc.). The system can locate the data nodes based on the data access requests and perform operations on the data nodes (e.g., write operations, read operations, etc.).

[0051] Data nodes may include a set of key-value pairs corresponding to the same partial key. The partial key may be stored in the system's search layer. Data nodes may include metadata portions and a range of key-value pairs. For example, each data node may maintain a series of key-value pairs such that the maximum key in the current data node (e.g., the first data node) is less than the minimum key in the next data node (e.g., the second data node adjacent to the first data node). Therefore, an ascending order of key ranges between adjacent data nodes can be maintained (e.g., provided).

[0052] The system can be configured to perform various operations on data nodes. For example, the system can perform insert (key, value), update (key, value), delete (key), lookup (key), or scan (key, range) operations on data nodes based on user requests. Based on the received key-value pairs, the system can identify the data node and then identify the precise location within the data node where the operation can be performed. The system can then perform the operation associated with the received key-value pairs. For example, the system can process a request associated with the key of a key-value pair to (i) locate the value corresponding to the key (e.g., an object) and (ii) perform the operation associated with the request on the value at the data node.

[0053] Therefore, it may be suitable to develop methods, devices, and systems for more efficiently handling requests for key-value storage.

[0054] Some key-value stores can be designed to use only the host's computing resources or only the computing resources of the storage device (e.g., a solid-state drive (SSD)). For example, some key-value stores can use host computing resources to perform control plane operations and data manipulation (e.g., data processing) operations. In such a key-value store, the host processor (e.g., a central processing unit (CPU)) can receive a request from a user (e.g., from an application corresponding to the user) to look up (e.g., locate) a key and retrieve the requested data into the host dynamic random access memory (DRAM). The CPU can then use this data to perform computations.

[0055] Some key-value stores may have computational storage capabilities. That is, key-value stores can be implemented using storage devices that include processing circuitry, such as accelerators, like field-programmable gate arrays (FPGAs). FPGAs can be used to operate (e.g., process) the data layer only as a "service" (e.g., performing pure computations, such as encoding or decoding).

[0056] Some key-value stores that utilize computational storage capabilities can use storage device resources to perform control plane operations and data manipulation (e.g., data processing) operations. In other words, key-value stores can be fully implemented on the storage device. In such key-value stores, the storage device's processing circuitry can receive a lookup (e.g., location) key from a user application and extract the requested data into the storage device's DRAM for the processing circuitry to perform computational requests.

[0057] To provide data durability and operational atomicity, such as preventing data loss due to device failure, key-value stores can be implemented based on crash consistency strategies for data recovery.

[0058] Some key-value stores can leverage crash consistency strategies such as merge write-ahead log (WAL) records (e.g., UNDO and REDO log records). For example, in WAL, any writes to the key-value store can be stored in a log file (e.g., a write-ahead log) persisted to non-volatile memory on the storage device before the corresponding data location can be modified based on the write operation.

[0059] With the rapid development of data storage, key-value store designs that rely solely on the computing resources of host or storage devices may encounter computational and / or network bottlenecks (e.g., CPU bottlenecks). That is, although storage devices are becoming faster and smarter, their performance may not be fully realized because, for example, the CPU cannot process and transfer data efficiently enough. In key-value stores implemented using storage devices with computational storage capabilities (hereinafter referred to as computational storage devices), traditional host-based caches may not fully utilize the advantages offered by peer-to-peer (P2P) transfers between the processing circuitry of the computational storage device (e.g., FPGA) and the memory of the storage device (e.g., non-volatile memory or RAM). Therefore, the computing power of the FPGA may be underutilized.

[0060] Regarding crash consistency strategies, key-value stores implemented using log-based consistency strategies may cause various problems, such as increased write amplification, input / output (I / O) interdependencies, and slow request processing speed.

[0061] To improve key-value storage performance, various aspects of embodiments of this disclosure provide a key-value store that can be logically partitioned to utilize both the host processor and the processing circuitry of the computing storage device. For example, the key-value store according to this disclosure can have reduced CPU bottlenecks and reduced data acquisition pauses in the preprocessing pipeline (e.g., preprocessing pipelines for artificial intelligence (AI) and machine learning (ML) applications).

[0062] In some embodiments, data plane computing can be offloaded from the host processor to the compute storage device to take advantage of the high-speed bandwidth of the compute storage device.

[0063] In some embodiments, the key-value store can be divided into two parts: (1) a search layer (e.g., internal nodes in a B-tree) processed by the host processor; and (2) a data layer (e.g., leaf nodes in a B-tree) processed by processing circuitry on the computing storage device. Although examples of the search layer and data layer disclosed herein may refer to a B-tree index structure, it should be understood that this disclosure is not limited thereto. For example, the search layer and data layer of various aspects of embodiments of this disclosure may be implemented via any suitable sorted index structure (e.g., B+ tree, trie, or adaptive radix tree).

[0064] The search layer can store partial keys. The data layer can store key fingerprints corresponding to keys belonging to specific data nodes. Therefore, key fingerprints can identify the precise location of the value corresponding to a key-value pair in the data storage.

[0065] As discussed in further detail below with reference to the accompanying drawings, a key-value store according to one or more embodiments (e.g., a cross-layer key-value store) can utilize a cross-layer approach to employ the host processor in the control plane and offload data plane computation to the processing circuitry of the compute storage device. Therefore, the key-value store can leverage the high bandwidth of the compute storage device.

[0066] Key-value stores can also incorporate one or more of the following features, which are discussed in further detail below: (1) cross-layer approaches for improving throughput and scalability; (2) cross-layer caching (e.g., mirrored caching) for improving data locality (e.g., reducing or eliminating unnecessary (e.g., redundant) data movement); and (3) version-based crash consistency for simplifying crash consistency (e.g., crash consistency strategies based on version numbers rather than write-ahead log entries).

[0067] In addition to improved efficiency, key-value stores can be integrated into compute pipelines to significantly reduce data retrieval pauses and achieve the benefits of offloading preprocessing to compute storage devices.

[0068] Furthermore, although this disclosure relates to a host coupled to a computing storage device, it is not limited thereto. For example, in some embodiments, the key-value store according to this disclosure can utilize a heterogeneous system having multiple storage devices and accelerators connected in a server.

[0069] Systems and methods for cross-tier key-value storage with compute storage devices can provide key-value storage with reduced bottlenecks (e.g., greater overall system bandwidth), improved throughput, scalability, and data locality. This improvement can be achieved by logically partitioning the key-value storage into: (1) a search layer stored on host memory and manipulated (e.g., processed) by the host processor; and (2) a data layer stored on compute storage devices and processed by the processing circuitry of the compute storage devices. Furthermore, in some embodiments, cross-tier key-value storage can provide simplified crash consistency by using version-based crash consistency instead of log-based crash consistency.

[0070] For example, key-value stores can be implemented as or on a system including a host and a storage device, the storage device including persistent memory (e.g., a solid-state drive (SSD) or other non-volatile memory portion of the storage device), processing circuitry (e.g., an FPGA), and a common memory region (CMA) linked to the persistent memory and the processing circuitry (e.g., via P2P memory).

[0071] The host can store and manipulate (e.g., process) a search layer that includes sorted indexes (e.g., tree structures). The host can also store and manipulate (e.g., process) a host cache portion of a key-value store's "mirror cache." The storage device can store and manipulate a data layer that includes leaf nodes (e.g., data nodes) of a tree structure. The storage device can also store and manipulate a kernel cache portion of the mirror cache.

[0072] The host cache can be implemented as a two-dimensional (2D) array. Each entry in the host cache that stores the metadata corresponding to the data node can be stored on a storage device.

[0073] The kernel cache can be implemented as a one-dimensional (1D) array of data nodes stored in the CMA. The host can store each entry of the host cache in the host cache at the same offset as the data node stored in the kernel cache (e.g., to reduce the amount of data movement within the system).

[0074] Key-value stores can distribute responsibility between the host processor (e.g., CPU) and processing circuitry (e.g., FPGA) of the storage device. For example, key-value stores can decentralize control over processing requests to access data nodes stored on the storage device. Therefore, the host processor can act in the control plane to trigger (e.g., cause or emit) kernel calls, issue data transfers to or from persistent memory, and manage crash consistency. The storage device's processing circuitry can handle data plane operations, allowing key-value stores to leverage the relatively high access throughput of the computational storage device.

[0075] Furthermore, key-value stores can be implemented to provide variable-length key-value support by leveraging a version-based crash consistency mechanism that maintains version metadata to avoid the overhead of logging technologies such as WAL.

[0076] Therefore, the key-value stores according to various aspects of the present disclosure can provide several improvements and advantages compared to other key-value store designs, including: (1) reducing bottlenecks by logically dividing them into a search layer and a data layer, so that only the host processor is used as the control plane and data plane tasks are offloaded to the processing circuitry; (2) improving I / O bandwidth utilization by transferring data to the processing circuitry through P2P memory, thereby reducing network hops (e.g., reducing the amount of data transfer between storage and the host), thereby increasing overall throughput; (3) achieving version-based crash consistency by using atomic updates (e.g., 4KB-sized updates), avoiding journaling (e.g., computationally expensive / data-intensive log-based recovery); and (4) allowing scalability without synchronization issues because the search layer and data layer are logically and physically separated between the host processor and the processing circuitry.

[0077] Figure 1 This is a system diagram depicting a data storage system including a search layer and a data layer according to some embodiments of the present disclosure.

[0078] refer to Figure 1 System 1 may include host 100, which may be coupled to storage device 200 (e.g., computing storage device). Host 100 may include host processor 110 (e.g., host CPU) and host memory 120 (e.g., host DRAM).

[0079] Storage device 200 may include (e.g., may be) computing storage device, including storage 210 (e.g., permanent or non-volatile memory), storage controller 212 (e.g., non-volatile fast memory (NVMe) auxiliary controller), processing circuitry 220 (e.g., accelerator, such as FPGA) and common memory region (CMA) 230 (e.g., P2P memory of computing storage device, which may be part of DRAM of processing circuitry 220, linked or shared with storage 210 and processing circuitry 220).

[0080] Storage device 200 can store one or more data node DNs (see also...) Figure 4 Each data node (DN) can include a set of key-value pairs (e.g., multiple key-value pairs that can be ordered in ascending order and...). Figure 1 and Figure 4(These are described as "AAA" and "AAB", etc.). The set of key-value pairs in the corresponding data node can correspond to the same set of keys in the search layer 150 of the host memory 120.

[0081] System 1 may include (e.g., may be) a key-value store with a cross-layer architecture, wherein responsibilities such as handling data access requests are divided between host processor 110 and processing circuitry 220 to improve performance compared to conventional key-value stores. For example, search layer 150 may be stored on host memory 120, and data layer 250 may be stored on storage device 200 (e.g., in storage device 210). Search layer 150 may be manipulated (e.g., processed, maintained, or controlled) by host processor 110. Data layer 250 may be processed by processing circuitry 220.

[0082] Therefore, the host processor 110 can act as a control plane and perform appropriate operations, such as triggering FPGA kernel calls (e.g., kernel calls pointing to processing circuitry 220), issuing (e.g., initiating) data transfers to and from storage 210, and managing concurrency control (e.g., managing concurrent access to storage device 200 from multiple requests). Additionally, processing circuitry 220 can manage operations on the data plane, such as manipulating (e.g., processing) and processing data (e.g., performing data node updates and updating the corresponding metadata of the updated data nodes).

[0083] By delegating the manipulation (e.g., processing) of the search layer 150 to the host processor 110, while delegating the manipulation of the data layer 250 to the processing circuitry 220, different sources of computational power can be used more appropriately. For example, system 1 can utilize the internal bandwidth (e.g., high internal bandwidth) between storage 210 and processing circuitry 220, while also reducing (e.g., minimizing) data movement caused by P2P data transfer (e.g., direct data transfer) between storage 210 and processing circuitry 220.

[0084] Search layer 150 can be implemented as, for example, a tree structure on host memory 120, which stores partial keys (e.g., storing partial keys as internal nodes in a B-tree metastructure). Although search layer 150 and data layer 250 are described herein as corresponding to a tree structure, it should be understood that this disclosure is not limited thereto, and other sorted index structures may be appropriate.

[0085] Data layer 250 can be implemented as a doubly linked list of leaf nodes (e.g., leaf nodes in a B-tree structure) corresponding to data nodes DN on storage device 200. The search layer (e.g., a tree structure) can facilitate fast lookup of point queries. Since the data layer is a doubly linked list, key-value pairs can be stored in ascending order, enabling fast range queries. Therefore, unlike some conventional key-value stores that are not operable for range operations, cross-layer key-value storage allows system 1 to be suitable for both point queries (e.g., operations corresponding to a single key-value pair) and range queries (e.g., operations corresponding to more than one consecutive key-value pair).

[0086] Various aspects of the cross-layer key-value storage embodiment can provide the flexibility of host CPU processing (e.g., range query processing) and a framework for near-data processing (e.g., lookup operations in leaf nodes, data compression, and deep learning preprocessing) utilizing processing circuitry 220 (e.g., FPGA on storage). Furthermore, through the cross-layer key-value storage with decoupled search and data layers, this architecture can be easily scaled to non-uniform memory access (NUMA) nodes connected to multiple storage devices 200 on a network.

[0087] Figure 2 This is a system diagram depicting a data storage system including a host cache and a kernel cache according to some embodiments of the present disclosure.

[0088] refer to Figure 2 System 1 may include a mirrored cache 7 (or a cross-tier cache) that spans a CMA 230 partition across host memory 120 of host 100 and storage device 200. Mirrored cache 7 may include a host cache 170 (e.g., a metadata cache) on host memory 120 and a kernel cache 270 (e.g., a data cache) on CMA 230. Mirrored cache 7 provides data locality (e.g., improved data locality).

[0089] Maintaining the metadata cache on host 100 enables host processor 110 to operate in the control plane and allows the data cache on CMA 230 to utilize high-speed peer-to-peer data transfer provided by compute storage device 200. By offloading data layer computation to storage device 200 (which can typically be performed by a host that uses a traditional key-value store), the granularity of data access from storage device 210 can be the size of a data page (e.g., 4KB).

[0090] While a conventional host-based cache may provide sufficient capacity to store data nodes (DNs) (e.g., data pages) in this context, using a cross-layer cache offers several advantages and improvements compared to a host-based cache. For example, using a cross-layer cache can: (1) reduce latency in accessing data pages; (2) reduce network traffic because the number of hops (e.g., the amount of data transfer between storage 210 and host 100) will be reduced; and (3) take advantage of the P2P transmission between processing circuitry 220 and storage device 200, thereby utilizing the computing power of processing circuitry 200.

[0091] Computational storage device 200 can connect storage 210 and processing circuitry 220 via an internal data path, enabling high-speed data transfer known as peer-to-peer data transfer. This connection can be implemented via an on-chip soft PCIe switch and device memory of processing circuitry 220. Computational storage device 200 can map the memory (e.g., DRAM) of storage 210 and processing circuitry 220 onto peripheral component interconnect fast (PCIe) stripe 260 (e.g., PCIe stripe memory). The memory portion of processing circuitry 220 exposed to PCIe stripe 260 may include (e.g., may be) CMA 230.

[0092] Host cache 170 can be stored on host memory 120 as a storage metadata storage mechanism and allows host processor 110 to operate in the control plane to handle cache maintenance operations and manage concurrent access to the set-associative cache. Host cache 170 can be a hash table storing metadata for the corresponding data node DN. For example, each host cache entry 172 can store metadata such as logical block address (LBA), timestamp, flags for checking occupancy, least recently used (LRU) information for eviction, and lock information for concurrent cache access. Host cache 170 can be a two-dimensional (2D) array.

[0093] Kernel cache 270 can be stored on CMA 230 to store data node DNs and enable cross-layer key-value storage to take advantage of the benefits provided by compute storage device 200, such as P2P access and reduced network latency. Kernel cache 270 can be a flat one-dimensional (1D) array (e.g., a large P2P buffer).

[0094] The name "Mirror Cache" indicates its layout characteristics. For example, each host cache entry 172 on host cache 170 may store its respective metadata at the same offset as the corresponding actual data node DN on kernel cache 270 (e.g., the tenth entry in host cache 170 may include the data node DN corresponding to the tenth entry stored in the kernel cache). Therefore, the layout of host cache 170 can mirror the layout of kernel cache 270. Thus, mirroring cache 7 can reduce the amount of data movement because, for example, the presence of LBA in host cache 170 can indicate the presence of the corresponding data node DN in kernel cache 270.

[0095] Figure 3A This is a combination of flowcharts and system diagrams describing the operation of data storage methods within a system according to some embodiments of the present disclosure.

[0096] refer to Figure 3A A method 3000A for processing data access requests to access data node DN stored on storage device 200 in a cross-tier key-value storage system 1 may include the following operations.

[0097] Host 100 can receive data access requests (e.g., insert operations with key-value pairs) (Operation 3001A).

[0098] Control can be passed to host processor 110, which may have a search layer 150 inside host memory 120 to enable the search layer 150 to look up a key (e.g., a partial key). Note that the search layer 150 may be narrowed down to the leaf node of the LBA that points to the data node DN (operation 3002A).

[0099] The host processor 110 can use LBA to look up (e.g., search) the host cache 170, which also exists on the host memory 120, to determine whether the corresponding data node DN exists in the kernel cache 270 of the mirror cache 7 (operation 3003A).

[0100] The host processor 110 may search the metadata of the host cache 170, and the search may cause (i) a cache miss, wherein the corresponding data node DN is not present in the kernel cache 270 or not present in the kernel cache 270, or (ii) a cache hit, wherein the data node DN is present in the kernel cache 270 (Operation 3004A).

[0101] Based on the determination that a cache miss has occurred, the host processor 110 may issue (e.g., trigger or cause) a read from storage 210 to kernel cache 270 located on CMA 230 (e.g., P2P read) (operation 3005A).

[0102] In response to a P2P read request, control can be passed to storage device 200 to populate kernel cache 270 with data node DN (operation 3006A). After populating kernel cache 270 with data node DN, control can be passed back to host 100.

[0103] Based on the determination that a cache hit has occurred, or based on the determination that a data node DN has been filled in the kernel cache 270, the host 100 may issue (e.g., may trigger or cause) a kernel call (e.g., insert kernel call), which may pass control to the processing circuitry 220 (operation 3007A).

[0104] In response to a kernel call, the processing circuit 220 can read the data node DN from the kernel cache 270 (e.g., the data node DN can be read into local memory in the processing circuit 220), and can retrieve or generate a fingerprint (fp) of a specific key to narrow down the exact location of the key-value pair within the data node DN (operation 3008A).

[0105] Based on the exact location of the key-value pair, the processing circuit 220 can perform operations on the data node DN (e.g., insertion operations) (e.g., the processing circuit 220 can manipulate the data node DN in the local memory of the processing circuit 220 (e.g., process or perform one or more operations), and can populate the updated data node DN back into the kernel cache 270) (operation 3009A).

[0106] Based on the completion of the operation of the data node DN by the processing circuit 220, control can be returned to the host 100 to persist (e.g., write) the updated data node DN to the storage 210 (e.g., by issuing a P2P write from CMA 230 to storage 210) (operation 3010A).

[0107] Once the updated data node DN has been persisted to storage 210, the method can complete and exit (operation 3011A).

[0108] Figure 3B This describes some embodiments of the present disclosure and Figure 3A The flowchart shows the data storage method operation corresponding to the operation.

[0109] refer to Figure 3B The above is about Figure 3AThe operations discussed (e.g., operations 3001A to 3011A) are discussed in a simplified manner in flowchart format, without describing the structure of System 1.

[0110] For example, host processor 110 can receive a request for access to data node DN associated with a key (operation 3001B).

[0111] The host 100 (e.g., the host processor 110 of the host 100) can search (e.g., locate) a key in the search layer 150 to find information indicating the location of the data node DN (e.g., find the LBA in the data node DN) (operation 3002B).

[0112] Host 100 can look up (e.g., search or locate) the LBA (Operation 3003B) in the host cache 170 section of the mirror cache 7.

[0113] Based on the search host cache 170, host 100 can determine whether data node DN exists in the kernel cache 270 portion of mirror cache 7 (operation 3004B).

[0114] Based on the determination of a cache miss, host 100 may issue (e.g., trigger or cause) a P2P read from storage 210 to CMA230 (operation 3005B).

[0115] Storage device 200 can populate data node DN from storage 210 onto kernel cache 270 (operation 3006B).

[0116] Based on the determination of a cache hit, or based on the determination that the data node DN has been filled into the kernel cache 270, the host 100 may issue (e.g., trigger or cause) a kernel call (operation 3007B) based on a request (e.g., a request received at operation 3001B).

[0117] In response to a kernel call, control can be passed to processing circuitry 220 to perform the requested data manipulation (e.g., data processing) operation on the data node DN, and processing circuitry 220 can obtain a fingerprint (fp) to determine the exact location of the key-value pair within the data node DN (operation 3008B).

[0118] Processing circuit 220 can perform requested data manipulation (e.g., data processing) operations (operation 3009B) on data node DN.

[0119] Host 100 can issue (e.g., trigger or cause) a P2P write to persist the updated data node DN from CMA 230 to storage 210 (Operation 3010B).

[0120] Once the updated data node DN has been persisted to storage 210, the method can be completed and the operation can be exited (operation 3011A).

[0121] Figure 4 This is a combined flowchart and system diagram of operations for providing a data storage method within a system that supports variable-length key values, as described in some embodiments of this disclosure.

[0122] refer to Figure 4 In some embodiments, system 1 can provide variable-length key-value support. Furthermore, see the following references... Figure 5 The variable-length key-value support discussed can be implemented as a method to support version-based crash consistency.

[0123] In some embodiments, AI / ML applications can utilize a cross-layer key-value storage system 1, which processes relatively large amounts of data (such as images, videos, etc.) spanning multiple data pages. Because each data node DN can have a fixed size equal to the size of a data page (e.g., 4KB) according to various aspects of embodiments of this disclosure, system 1 can be configured to support variable-length key-value pairs by allocating (e.g., dispatching or chaining) extension nodes EN to corresponding data node DNs to accommodate larger key-value pairs. Extension nodes EN can be provided and dispatched by a slab allocator SA (e.g., a host-side assistant function) from a pool of data pages of different sizes (e.g., 4KB, 8KB, 16KB, 32KB, etc.) to chain to the corresponding data node DN.

[0124] Therefore, the method 4000 for providing variable-length key-value support may include: receiving at host 100 a request for access to a data node DN stored at storage device 200 (e.g., an insertion operation with key-value pairs) (operation 4001); finding (e.g., locating) the corresponding data node DN corresponding to the key-value pairs (operation 4002); determining that the free space of the data node DN is insufficient (e.g., determining that the amount of available space in the data node DN is less than the amount of space to accommodate the request) (operation 4003); updating the metadata MD of the data node DN to mark the existence of the extension node EN and adding the fingerprint of the extension node EN to the data node DN (e.g., implementing a pointer from the data node DN to the extension node EN within the data node DN) (operation 4004); and retrieving the extension page from the slice allocator SA and adding the metadata and key-value pairs to the extension node EN (operation 4005).

[0125] Figure 5 This is a combined flowchart and system diagram of operations for providing a data storage method within a system that offers variable key-value support and version-based crash consistency, based on descriptions of some embodiments of this disclosure.

[0126] refer to Figure 5 In some embodiments, the cross-tier key-value storage system 1 can provide a version-based crash consistency strategy, using version control and atomic reads / writes (e.g., 4KB atomic reads / writes) to avoid the overhead associated with traditional log-based crash consistency techniques. Version-based crash consistency models according to various aspects of this disclosure can utilize atomic block reads / writes (e.g., 4KB block reads / writes) for out-of-place updates (discussed below) and identify valid data pages by scanning the entire disk (e.g., storage 210) at the time of a crash.

[0127] With version control, System 1 can utilize atomic read / write using the following scheme. Updates to data node DNs can be written in-place. For example, updates to data node DNs can be written to storage at the same file offset as their previous versions (e.g., at the original location of the previous version of the data node DN).

[0128] Updates to extended node ENs that are larger than a data page and are assigned to data node DNs can be updated to storage in a "non-in-situ" manner. For example, a previous version of the extended node EN can remain in its original location (e.g., it can be unaltered), and the updated extended node EN can be written to a different location than the previous version of the extended node EN.

[0129] Furthermore, to provide correctness (e.g., to guarantee correctness), in the presence of the extended node EN, the data node DN can be appropriately written after the extended node EN is fully persisted on storage 210 to provide crash consistency. In the event of a crash in any state (e.g., power failure), previous versions of the data node DN can be preserved (e.g., undisturbed), and if a newer version of the extended node EN exists on storage 210, it can be garbage collected by the slice allocator SA (e.g., making it available to other processes running on system 1).

[0130] Still referencing Figure 5 The method 5000 for providing variable-length key-value support and version-based crash consistency may include the following. System 1 can handle the operation of updating an extension node EN (e.g., extension node 3) that has been assigned to a data node DN (e.g., data node 3) by a slice allocator SA, wherein each of the data node DN and the extension node EN is located in storage 210 and has the same version number VN (e.g., 0) (operation 5001).

[0131] System 1 can create copies of the data node DN and its extension node EN on the CMA 230 (Operation 5002).

[0132] Processing circuit 220 can be triggered based on copies of data node DN and extension node EN present in CMA 230 to (i) read data node DN and extension node EN into their local memory, (ii) perform the requested computation based on the operation, and (iii) update extension node EN based on the operation (operation 5003).

[0133] Based on the completion of the operation, the processing circuit 220 can write the value (e.g., the new data node DN and the updated extended node EN) back to CMA 230 (operation 5004) with the updated version number VN (e.g., updated to 1, such that the metadata MD of the updated data node DN points to the updated extended node EN).

[0134] The updated extended node EN can be persisted (e.g., written) to storage 210 in a non-in-place manner, so that the previous version of the extended node EN is preserved (e.g., not tampered with) (Operation 5005).

[0135] Based on the updated extended node EN being fully written to storage 210, the updated data node DN can be persisted in-situ (e.g., where the previous version of the data node DN existed) to storage 210, such that the previous version of the data node DN will be overwritten by the updated data node DN, causing the data node DN to point to the updated extended node EN, because its internal metadata MD (see...) Figure 4 It has been internally updated to point to the updated extended node EN (Operation 5006).

[0136] By implementing method 5000, system 1 can be resilient in the event of a crash. For example, if a crash occurs while the updated extension node EN is being persisted to storage 210 (e.g., in operation 5005), the operation can be aborted and restarted because the updated extension node is persisted to storage 210 in a non-in-place manner, with some of the written extension nodes being garbage collected.

[0137] If a crash occurs while persisting the updated data node DN to storage 210 in-situ (e.g., during operation 5006), the operation can be simply aborted and restarted (with the partially written extension node being garbage collected), and system 1 can roll back to a previous version of both the data node DN and the extension node EN. Therefore, data loss can be reduced (e.g., prevented).

[0138] Figure 6This is a flowchart describing the operation of a data storage method for a read (or lookup) request according to some embodiments of the present disclosure, including host-side concurrency control.

[0139] refer to Figure 6 Host 100 (for example, see Figure 1 and Figure 2 Concurrent access to storage device 200 can be controlled by implementing a method for concurrent read operations (e.g., for lookup operations). This method may include: initiating a lock-free lookup at the search layer (operation 6001); having host 100 traverse the metastructure of data node DN to acquire a read lock on data node DN (operation 6002); having host 100 use the found LBA to look up (e.g., locate or search) the LBA in host cache 170 to find the location of data node DN on kernel cache 270 (operation 6003); acquiring a read lock on the host cache slot in the case of a cache hit (operation 6004A); and issuing (e.g., triggering or causing) a P2P read I / O call to remove data node DN from storage in the case of a cache miss. Storage 210 is loaded into kernel cache 270 (operation 6004B1) and a write lock is acquired on the host cache slot (operation 6004B2); based on the kernel cache being ready and the data node DN being located at the found offset, a lookup kernel is triggered on the processing circuit 220 (e.g., FPGA) (System 1 may issue (e.g., trigger or cause) multiple compute units for each kernel function to achieve concurrency on the kernel side) (operation 6005); based on the completion of kernel execution, control can be passed back to host 100, and before exiting the application, host 100 can release the read / write (mirror cache) lock on the host cache slot (operation 6006) and the read lock on the data node DN metastructure (operation 6007); and can exit the method (operation 6008).

[0140] Figure 7 This is a flowchart depicting the operation of a data storage method for a write (or insert) request according to some embodiments of the present disclosure, including host-side concurrency control.

[0141] refer to Figure 7 Host 100 (for example, see Figure 1 and Figure 2Concurrent access to storage device 200 can be controlled by implementing write concurrency method 7000 (e.g., for insert operations), which may include: initiating a lock-free lookup at the search layer (operation 7001); having host 100 traverse the metastructure of data node DN to acquire a write lock on data node DN (operation 7002); having host 100 use the found LBA to look up (e.g., locate or search) the LBA in host cache 170 to find the location of data node DN on kernel cache 270 (operation 7003); in the event of a cache miss, issuing (e.g., initiating or triggering) a P2P read I / O call to load data node DN from storage 210 into kernel cache 270 (operation 7004A) and acquiring a write lock on the host cache slot (operation 7004). B); In the event of a cache hit, acquire a write lock on the host cache slot without issuing (e.g., without triggering or causing) a P2P read I / O call (Operation 7004B); Based on the kernel cache being ready and the data node DN being located at the found offset, trigger the insertion of a kernel on the processing circuitry 220 (e.g., FPGA) (System 1 may issue (e.g., trigger or cause) multiple compute units for each kernel function to achieve concurrency on the kernel side) (Operation 7005); Based on the completion of kernel execution, control can be transferred back to host 100, and before exiting the application, host 100 may release the write (mirror cache) lock on the host cache slot (Operation 7006) and the write lock on the data node DN metastructure (Operation 700); and may exit the application (Operation 7008).

[0142] Therefore, and return to the reference. Figure 2 The embodiments of this disclosure can provide advantages and improvements over conventional key-value stores, such as reducing bottlenecks at the host processor 110 and utilizing the high internal bandwidth and near-data computation of the compute storage device 200. Such advantages and improvements can be achieved by logically and physically partitioning the key-value stores between the host 100 and the compute storage device 200. Therefore, responsibilities associated with the search layer 150 can be performed by the host 100, while responsibilities associated with the data layer 250 can be performed by the compute storage device 200. The disclosed embodiments also provide structural advantages for the mirrored cache 7, including a host cache 170 stored on the host 100 and a kernel cache 270 stored on the CMA 230 of the compute storage device 200.

[0143] While embodiments of the present disclosure have been specifically shown and described with reference to the examples described herein, those skilled in the art will understand that various changes to form and detail therein, including functional equivalents, may be made without departing from the spirit and scope of the disclosure as set forth in the appended claims.

Claims

1. A data storage system, comprising: The host includes a host cache portion of the image cache, the host cache portion being used to store metadata indicating the location of data nodes stored in the kernel cache portion of the image cache; as well as The storage device includes the kernel cache portion located in the common memory region, wherein: The first host cache entry in the host cache portion includes metadata associated with the first kernel cache entry in the kernel cache portion; The second host cache entry in the host cache portion includes metadata associated with the second kernel cache entry in the kernel cache portion; and The order of the first host cache entry and the second host cache entry in the host cache portion is the same as the order of the first kernel cache entry and the second kernel cache entry in the kernel cache portion.

2. The data storage system according to claim 1 further includes: The search layer is located on the host; as well as The data layer is located on the storage device.

3. The data storage system according to claim 2, wherein, The search layer includes a tree structure, and The data layer includes data nodes corresponding to leaf nodes in a doubly linked list corresponding to leaf nodes in the tree structure.

4. The data storage system according to claim 1, wherein, The storage device also includes: Persistent memory, coupled to the common memory region; and The processing circuitry is coupled to the common memory region.

5. The data storage system according to claim 4, wherein, The processing circuit is configured to perform data operations on the data node and to write the data node into the kernel cache portion as an updated data node.

6. The data storage system according to claim 5, wherein, The host is configured as follows: It is determined that the updated data node is populated into the common memory region; and This causes a peer-to-peer write from the common memory region to the persistent memory.

7. The data storage system according to claim 1, wherein, The host is configured as follows: It is determined that the amount of available space in the data node is less than the amount of space needed to accommodate the data access requests corresponding to the data node; and The extension node is assigned to the data node.

8. The data storage system according to claim 7, wherein, The storage device also includes processing circuitry configured to update the metadata of the data nodes to point to the extended nodes. The metadata of the data node indicates a first version number, and The metadata of the extended node indicates the first version number.

9. The data storage system according to claim 8, wherein, The processing circuit is configured as follows: Update the extended node; The metadata of the data node is updated to indicate a second version number, thereby identifying the data node as an updated data node; Update the metadata of the extended node to indicate the second version number, thereby identifying the extended node as the updated extended node; as well as Update the metadata of the updated data node to point to the updated extended node.

10. The data storage system according to claim 9, wherein, The processing circuit is configured as follows: Write the updated extended node to the storage of the storage device in a non-in-place manner; and The updated data node is written to the storage in situ.

11. The data storage system according to claim 1, wherein, The host is configured to manage concurrent access to the storage device in the following manner: Receive a read request and acquire a read lock on the data node; or Receive a write request and acquire a write lock on the data node.

12. A method for data storage, the method comprising: Metadata indicating the location of data nodes stored in the storage device is located in the host cache portion of the mirror cache, which is stored on the host. as well as It is determined that the data node exists in the kernel cache portion of the mirror cache, and the kernel cache portion is stored on the common memory region of the storage device, wherein: The first host cache entry in the host cache portion includes metadata associated with the first kernel cache entry in the kernel cache portion; The second host cache entry in the host cache portion includes metadata associated with the second kernel cache entry in the kernel cache portion; and The order of the first host cache entry and the second host cache entry in the host cache portion is the same as the order of the first kernel cache entry and the second kernel cache entry in the kernel cache portion.

13. The method of claim 12, further comprising the host locating a partial key in the search layer to find the metadata indicating the location of the data node.

14. The method of claim 12, further comprising: It is determined that the data node has an available space that is less than the amount of space needed to accommodate data access requests; as well as The extension node is assigned to the data node.

15. The method according to claim 14, wherein, The storage device includes: Persistent memory, coupled to the common memory region; and The processing circuitry is coupled to the common memory region.

16. The method of claim 15, further comprising updating the metadata of the data node by the processing circuit to point to the extended node. in, The metadata of the data node and the metadata of the extension node indicate the first version number.

17. The method of claim 16, further comprising: Update the extended node; Update the metadata of the data node to indicate the second version number; Update the metadata of the extended node to indicate the second version number, which identifies the data node as the updated data node and the extended node as the updated extended node; as well as Update the metadata of the updated data node to point to the updated extended node.

18. The method of claim 17, further comprising: The updated extended node is written to the storage of the storage device in a non-in-place manner; as well as The updated data node is written to the storage in situ.

19. A non-transitory computer-readable medium implemented on a key-value store, the non-transitory computer-readable medium having computer code that, when executed on a processor, implements a method for data storage, the method comprising: The host cache metadata, which indicates the location of the data node stored in the storage device, is located in the host cache portion of the mirror cache. as well as Based on the host cache metadata, it is determined that the data node exists in the kernel cache portion of the mirror cache, and the kernel cache portion is stored on the common memory area of ​​the storage device, wherein: The first host cache entry in the host cache portion includes metadata associated with the first kernel cache entry in the kernel cache portion; The second host cache entry in the host cache portion includes metadata associated with the second kernel cache entry in the kernel cache portion; and The order of the first host cache entry and the second host cache entry in the host cache portion is the same as the order of the first kernel cache entry and the second kernel cache entry in the kernel cache portion.

20. The non-transitory computer-readable medium according to claim 19, wherein, The method also includes locating partial keys in the search layer to find the host cache metadata.

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