A flying capacitor minimization method for hybrid multi-level converters

Abstract

This invention provides a method for minimizing the flying capacitor design of a hybrid multilevel converter (HCC). The method includes: Step 1: Obtaining the system parameters of the HCC during operation; Step 2: Based on the power factor during HCC operation, if the system power factor is less than 0.3, proceed to Step 3; if the system power factor is greater than or equal to 0.3, proceed to Step 4; Step 3: When the system power factor is less than 0.3, calculate the impedance Z based on the load conditions, and use this impedance Z to determine the maximum load current amplitude I. Based on the maximum load current amplitude I and the system parameters, determine the minimum flying capacitor value C. fx_min Step 4: When the system power factor is greater than or equal to 0.3, calculate the load current amplitude at the time when the maximum fluctuation of the flying capacitor occurs. Based on the corresponding load current amplitude and system parameters, determine the minimum flying capacitor value C. fx_min This method enables rapid and accurate design of the minimum flying capacitor in an HCC converter.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more specifically to a method for minimizing the flying capacitor design of a hybrid multilevel converter. Background Technology

[0002] Multilevel converters are widely used in industrial applications due to their advantages such as lower dv / dt, better harmonic performance, and higher voltage and power ratings. However, the capacitors inside multilevel converters charge and discharge during power conversion, resulting in voltage ripple. To address the issues of longer capacitor charging and discharging times and increased voltage fluctuations under low-frequency operating conditions, the most common solution is to increase the capacitor capacitance. However, for high-voltage capacitors (e.g., capacitors with voltage values ​​>1kV), increasing the capacitance significantly increases their size and price. Therefore, this inevitably increases system cost, reduces system power density, and renders multilevel converters unsuitable for practical applications.

[0003] For hybrid clamped converters (HCCs), three-phase HCCs contain three flying capacitors, one for each phase of the HCC system. These flying capacitors directly affect the main circuit size of the HCC converter. When HCC capacitor voltage fluctuations are effectively controlled, a complex relationship exists between the flying capacitor voltage fluctuation, capacitance size, and system parameters. In recent years, HCCs have attracted widespread attention from researchers as an emerging medium-to-high voltage multilevel converter. Extensive research has been conducted on several challenging issues, including HCC modeling, voltage balance control, and pre-charging methods. However, few studies have addressed the minimization of flying capacitors in HCCs, making the design of flying capacitors in high-power HCC systems extremely difficult.

[0004] Therefore, how to propose an effective design method for minimizing the flying capacitor of HCC, and obtain the minimum flying capacitor of the system within the allowable capacitor voltage fluctuation range, so as to reduce its volume by more than half compared with the traditional design, is a key scientific problem for realizing the miniaturization and lightweighting of HCC multilevel converter systems. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide an effective design method for minimizing the flying capacitor in hybrid multilevel converters (HCCs). This invention aims to solve the problem of difficult selection of flying capacitors for HCCs, and through the proposed HCC flying capacitor minimization design method, quickly obtain the flying capacitor parameters for high-power HCC system design.

[0006] To achieve the above objectives, the present invention provides a method for minimizing the flying capacitance of a hybrid multilevel converter, characterized by comprising the following steps:

[0007] Step 1: Obtain the system parameters of the hybrid multilevel converter during operation. The system parameters include the DC bus voltage V. dc Reference wave frequency f ac Carrier frequency f c Modulation ratio m a Power factor and the system capacitor voltage fluctuation limit ΔV limit ;

[0008] Step 2: Based on the power factor when the HCC is operating, determine the next calculation step. If the system power factor is less than 0.3, proceed to step 3; if the system power factor is greater than or equal to 0.3, proceed to step 4.

[0009] Step 3: When the system power factor is less than 0.3, calculate the impedance Z based on the load conditions, and use this impedance Z to determine the maximum load current amplitude I. Based on the maximum load current amplitude I and the system parameters, determine the minimum flyover capacitance value C. fx_min ;

[0010] Step 4: When the system power factor is greater than or equal to 0.3, calculate the load current amplitude at the time when the maximum fluctuation of the flying capacitor occurs. Based on the corresponding load current amplitude and system parameters, determine the minimum flying capacitor value C. fx_min .

[0011] Furthermore, in step 3, the minimum flying capacitor value C is determined based on the system's maximum load current amplitude I and the system parameters. fx_min This can be expressed as a formula:

[0012]

[0013] Among them, T c For carrier frequency f c The reciprocal of.

[0014] Furthermore, the maximum load current amplitude I satisfies

[0015] Furthermore, the moment when the maximum voltage fluctuation of the flying capacitor occurs is the first switch S after the modulated wave enters the 1 / 3 to 2 / 3 range. 2x -S 3x The time corresponding to the pulse that is 1, where S 2x -S 3x Indicates the internal switch S of HCC 2x and S 3xThe difference in logical values, where x represents phase a, b, or c of the HCC, the start time of the pulse is defined as t1, and the end time as t2, where t1 satisfies t2 satisfies T c For carrier frequency f c The reciprocal of V ref_x (t1) represents the modulation amplitude value in HCC phase-shift pulse width modulation at time t1.

[0016] Furthermore, in step 4, the minimum flyover capacitance value C is determined based on the corresponding load current amplitude and system parameters. fx_min The formula is expressed as:

[0017]

[0018] in, i is the average current at the moment when the maximum voltage fluctuation of the flying capacitor occurs. ox (t1) and i ox (t2) represents the load current amplitude at times t1 and t2, respectively.

[0019] Furthermore, the modulating wave is the modulating wave V in HCC phase-shift pulse width modulation. ref_x (t), modulated wave V ref_x (t) and load current i ox (t) are respectively represented as:

[0020]

[0021]

[0022] Where I represents the maximum load current amplitude.

[0023] Furthermore, this method is applicable to wide modulation frequency ranges of 1-200Hz, wide carrier frequency ranges of 500-10000Hz, and wide power factor ranges of 0-1.

[0024] The beneficial effects of this invention are as follows:

[0025] 1) The HCC flying capacitor minimization design method provided by the present invention directly calculates the minimum flying capacitor that meets the voltage fluctuation requirements of HCC capacitor through the constructed mathematical model, avoiding the introduction of excessively large flying capacitors and significantly reducing the design complexity and size of HCC system.

[0026] 2) The HCC flying capacitor minimization design method provided by this invention is applicable to a wide frequency range and a wide power factor operating condition. It effectively solves the problem of selecting the minimum flying capacitor for HCC under various common operating conditions, greatly reducing the design and construction cost of high-power HCC converters. It has promotion and application value in the fields of medium-voltage large-capacity new energy grid connection, motor drive and power transmission.

[0027] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0028] Figure 1 This is a flowchart of the hybrid multilevel converter flying capacitor minimization design method of the present invention;

[0029] Figure 2 This is a schematic diagram of the circuit connection of a three-phase four-level HCC converter;

[0030] Figure 3 The simulation waveforms of the voltages of each flying capacitor in the HCC system under the flying capacitor parameters obtained using the flying capacitor minimization design method of this invention are shown. Detailed Implementation

[0031] To make the technical solutions, advantages, and objectives of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention without creative effort are within the protection scope of this application.

[0032] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0033] Figure 2 This is a schematic diagram of a three-phase four-level HCC converter circuit. As shown in Figure 2, the circuit includes a DC power supply V. dc The three-phase HCC and three-phase load Z (each phase includes a resistor R and an inductor L connected in series). The three phases are phase a, phase b, and phase c (also written as phase A, phase B, and phase C).

[0034] The three-phase HCC includes three DC bus capacitors C connected in series. d1 C d2 and C d3 Three flying capacitors C fa(corresponding to phase a), C fb (corresponding to phase b) and C fc (Corresponding to phase C) and three bridge arms, each containing four sets of switches. Among them, the DC bus capacitor C... d1 It can also be called the upper DC bus capacitor, DC bus capacitor C d3 It can also be called the lower DC bus capacitor, DC bus capacitor C d2 It can also be called the intermediate DC bus capacitor.

[0035] For any phase x (phase a, phase b, or phase c), its corresponding flying capacitor C fx and bridge arm switch S 1x and S 1x ', S 2x and S 2x ', S 3x and S 3x ', S 4x and S 4x For example, such as Figure 2 As shown, for phase a, its corresponding flying capacitor C fa and bridge arm switch S 1a and S 1a ', S 2a and S 2a ', S 3a and S 3a ', S 4a and S 4a '. Among them, S 1a The first terminal is connected to the DC bus terminal capacitor C d1 The positive electrode is connected, S 1a The second end is connected to S 1a 'The first end and S 2a The first end, S 1a The first end of ' is also related to S 2a The first end is connected, S 1a The second end is connected to the DC bus capacitor C. d1 The negative electrode, S 2a The second end is connected to S 3a The first end, S 4a The first terminal is connected to the DC bus capacitor C. d3 The positive electrode, S 4a The second end is connected to S 2a 'The first end and S 4a The first end of 'S' 4a The second end is connected to the DC bus capacitor C. d3 The negative electrode, S 2a The second end of ' is connected to S 3a The first end of 'S' 3a The second end and S 3aThe second end of each of the S's terminals is connected to a load. 2a The second end and S 3a The first end is connected to the flying capacitor C fa The positive electrode is connected, S 2a 'The second end and S 3a The first end of ' is connected to the flying capacitor C fa The negative terminal is connected.

[0036] It should be noted that, Figure 2 Only the specific connection method of phase a is shown; the specific connection methods of phases b and c are not shown. For those skilled in the art, according to... Figure 2 Based on the above description, it is easy to understand that the specific connection methods of phases b and c are similar to those of phase a, so they will not be repeated here.

[0037] Figure 1 This is a flowchart of the hybrid multilevel converter flying capacitor minimization design method of the present invention. Figure 1 As shown, the method may include:

[0038] Step 1: Obtain the system parameters of the hybrid multilevel converter during operation. The system parameters include the DC bus voltage V. dc Reference wave frequency f ac Carrier frequency f c Modulation ratio m a Power factor and the system capacitor voltage fluctuation limit ΔV limit .

[0039] System capacitor voltage fluctuation limit ΔV limit It is the percentage of the system's maximum allowable capacitor voltage fluctuation relative to the capacitor's rated operating voltage. The rated operating voltage is one-third of the DC bus voltage, ΔV. limit The range is generally between 0% and 100%.

[0040] Step 2: Based on the power factor when the HCC is working, determine the next calculation step. If the system power factor is less than 0.3, proceed to step 3; if the system power factor is greater than or equal to 0.3, proceed to step 4.

[0041] Step 3: When the system power factor is less than 0.3, calculate the impedance Z based on the load conditions, and use this impedance Z to determine the maximum load current amplitude I. Based on the maximum load current amplitude I and the system parameters, determine the minimum flyover capacitance value C. fx_min .

[0042] In some embodiments, the minimum flying capacitance value C fx_min This can be expressed as a formula:

[0043]

[0044] Among them, T c For carrier frequency f c The reciprocal of.

[0045] In some embodiments, the maximum load current amplitude I satisfies

[0046] Step 4: When the system power factor is greater than or equal to 0.3, calculate the load current amplitude at the time when the maximum fluctuation of the flying capacitor occurs. Based on the corresponding load current amplitude and system parameters, determine the minimum flying capacitor value C. fx_min .

[0047] In some embodiments, the maximum voltage fluctuation of the flying capacitor occurs at the first switch S after the modulated wave enters the 1 / 3 to 2 / 3 range. 2x -S 3x The time corresponding to a pulse with a value of 1. Where S 2x -S 3x Indicates the internal switch S of HCC 2x and S 3x The difference in logical values, where x represents phase a, b, or c of the HCC, the start time of the pulse is defined as t1, and the end time as t2, where t1 satisfies t2 satisfies T c For carrier frequency f c The reciprocal of V ref_x (t1) represents the modulation amplitude value in HCC phase-shift pulse width modulation at time t1.

[0048] After determining the load current amplitudes at times t1 and t2, the minimum flyover capacitance value C can be determined based on the corresponding load current amplitudes and system parameters. fx_min This can be expressed as a formula:

[0049]

[0050] in, i is the average current at the moment when the maximum voltage fluctuation of the flying capacitor occurs. ox (t1) and i ox (t2) represents the load current amplitude at times t1 and t2, respectively.

[0051] In some embodiments, the modulation wave is the modulation wave V in HCC phase-shift pulse width modulation. ref_x (t), modulated wave V ref_x (t) and load current i ox (t) can be expressed by formulas (3) and (4) respectively:

[0052]

[0053]

[0054] Where I represents the maximum load current amplitude.

[0055] The method provided by this invention is applicable to wide modulation frequency ranges of 1-200Hz, wide carrier frequency ranges of 500-10000Hz, and wide power factor ranges of 0-1. By extracting parameters such as the voltage level, reference frequency, carrier frequency, modulation ratio, power factor, and system capacitor voltage fluctuation limits of the HCC system, the minimum flying capacitor value that meets the system capacitor voltage fluctuation requirements is calculated based on the proposed design method, enabling rapid and accurate design of the minimum flying capacitor in the HCC converter. The flying capacitor minimization design method provided by this invention is applicable to wide frequency ranges and wide power factor operating conditions, reducing the complexity and cost of high-power HCC system design, reducing the weight and volume of the flying capacitor, and thus improving the system power density.

[0056] The following is an illustration through specific examples.

[0057] Example 1

[0058] The proposed method for minimizing the flying capacitor is used to design the minimum flying capacitor for a specific three-phase HCC system. The specific parameters of the HCC system are as follows:

[0059] DC power supply V dc It is used to provide DC power supply voltage of 3.3kV;

[0060] The HCC system has a modulation ratio of 1, a modulation frequency of 50Hz, and a carrier frequency of 1kHz.

[0061] The three-phase load consists of three resistors and inductors connected in series. The load resistor RL has a resistance of 7.35Ω and an inductance of 11mH. The system power factor is 0.9.

[0062] HCC system capacitor voltage fluctuation limit ΔV limit It is 10%.

[0063] The HCC flying capacitor minimization design method in this embodiment is as follows: Figure 1 As shown, the specific steps are as follows:

[0064] First, obtain the following parameters for the operation of the hybrid multilevel converter: DC bus voltage 3.3kV, reference frequency 50Hz, carrier frequency 1kHz, modulation ratio 1, power factor 0.9, and system capacitor voltage fluctuation limit of 10%.

[0065] Secondly, based on the power factor when the HCC is operating, determine the next calculation step.

[0066] Since the system power factor is 0.9 in this embodiment, which is greater than 0.3, we proceed to step 4, that is, when the system power factor is greater than 0.3, we calculate the load current amplitude at the corresponding time based on the time when the maximum fluctuation of the flying capacitor occurs.

[0067] The maximum voltage fluctuation of the flying capacitor occurs at the first switch S after the modulated wave enters the 1 / 3 to 2 / 3 range. 2x -S 3x The time corresponding to a pulse with a value of 1. Where S 2x -S 3x Indicates the internal switch S of HCC 2x and S 3x The difference in logical values, where x represents phase a, b, or c of the HCC. Define the start time of this pulse as t1 and the end time as t2, where t1 satisfies... t2 satisfies T c For carrier frequency f c The reciprocal of V ref_x (t1) represents the modulation amplitude value in HCC phase-shift pulse width modulation at time t1. According to formula (3), t1 is 0.0089s and t2 is 0.0092s.

[0068] The load current amplitude i at the two times is obtained according to formula (4). ox (t1) is 146.14A, i ox (t2) is 130.31A. The average current at the moment of the maximum voltage fluctuation of the flying capacitor. It is 138.23A.

[0069] Substituting the relevant system parameters into formula (2) yields the following:

[0070]

[0071] The above method is used to obtain the limit ΔV of capacitor voltage fluctuation in the HCC system. limit The minimum flying capacitance value at 10% is 0.42mF.

[0072] Figure 3 The simulation waveforms of the voltages of each flying capacitor in the HCC system under the flying capacitor parameter of 0.42mF obtained by using the flying capacitor minimization design method of the present invention are shown.

[0073] from Figure 3Analysis shows that when the minimum flying capacitor of 0.42mF is obtained using the flying capacitor minimization design method provided by this invention, the maximum voltage fluctuation of the system's flying capacitor is around 110V, which is 10% of the rated operating voltage of 1100V. This is consistent with the 10% limit on the voltage fluctuation of the HCC system capacitor required by the system design. This proves that the HCC flying capacitor minimization method of this invention can effectively obtain the minimum flying capacitor value that meets the system capacitor voltage fluctuation requirements, achieving rapid and accurate design of the minimum flying capacitor in the HCC converter.

[0074] In summary, the flying capacitor minimization design method for hybrid multilevel converters provided by this invention directly calculates the minimum flying capacitor that meets the voltage fluctuation requirements of the HCC capacitor through the constructed mathematical model, thereby avoiding the introduction of excessively large flying capacitors and significantly reducing the design complexity and size of the HCC system. Furthermore, the HCC flying capacitor minimization design method provided by this invention is applicable to a wide frequency range and wide power factor operating conditions, effectively solving the problem of selecting the minimum flying capacitor for HCC under common operating conditions. It has significant application value in fields such as medium-voltage large-capacity new energy grid connection and motor drives.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the protection scope of the present invention.

Claims

1. A method for minimizing the flying capacitance of a hybrid multilevel converter, characterized in that, Includes the following steps: Step 1: Obtain the system parameters of the hybrid multilevel converter during operation. The system parameters include the DC bus voltage V. dc Reference wave frequency f ac Carrier frequency f c Modulation ratio m a Power factor and system capacitor voltage fluctuation limit ; Step 2: Based on the power factor of the hybrid multilevel converter during operation, determine the next calculation step. If the system power factor is less than 0.3, proceed to step 3; if the system power factor is greater than or equal to 0.3, proceed to step 4. Step 3: When the system power factor is less than 0.3, calculate the impedance Z based on the load conditions, and use this impedance Z to determine the maximum load current amplitude I. Based on the maximum load current amplitude I and the system parameters, determine the minimum flyover capacitance value. ; Step 4: When the system power factor is greater than or equal to 0.3, calculate the load current amplitude at the time when the maximum fluctuation of the flying capacitor occurs. Based on the corresponding load current amplitude and system parameters, determine the minimum flying capacitor value. ; The three phases of the hybrid multilevel converter are respectively Mutually, Harmony The hybrid multilevel converter includes three DC bus capacitors connected in series. , and Three flying capacitors , and And three bridge arms, each containing four sets of switches; among them, the DC bus capacitor For the upper DC bus capacitor, DC bus capacitor For the lower DC bus capacitor, the DC bus capacitor For intermediate DC bus capacitor; For any Mutually, Its corresponding flying capacitor and bridge arm switch and , and , and , and ;for Phase, corresponding flying capacitor and bridge arm switch and , and , and , and ;in, The first terminal is connected to the DC bus terminal capacitor. The positive electrode is connected. Second end connection The first end and The first end, The first end is also with The first end is connected. The second end is connected to the DC bus capacitor. The negative electrode, Second end connection The first end, The first end is connected to the DC bus capacitor. The positive electrode, Second end connection The first end and The first end, The second end is connected to the DC bus capacitor. The negative electrode, Second end connection The first end, The second end and The second end of each is connected to a load. The second end and The first end is connected to the flying capacitor The positive electrode is connected. The second end and The first end is connected to the flying capacitor The negative terminal is connected.

2. The method for minimizing the flying capacitance of a hybrid multilevel converter according to claim 1, characterized in that, In step 3, the minimum flyover capacitance value is determined based on the system's maximum load current amplitude I and the system parameters. This can be expressed as a formula: ， Among them, T c For carrier frequency f c The reciprocal of.

3. The method for minimizing the flying capacitance of a hybrid multilevel converter according to claim 1 or 2, characterized in that, The maximum load current amplitude I satisfies .

4. The method for minimizing the flying capacitance of a hybrid multilevel converter according to claim 1, characterized in that, The maximum voltage fluctuation of the flying capacitor occurs at the first switch after the modulated wave enters the 1 / 3 to 2 / 3 range. The time corresponding to the pulse with a value of 1, where, Indicates the internal switch S of the hybrid multilevel converter 2x and S 3x The difference in logic values, where x represents phase a, b, or c of the hybrid multilevel converter, the start time of the pulse is defined as t1, and the end time as t2, where t1 satisfies t2 satisfies T c For carrier frequency f c The reciprocal, This represents the modulation amplitude value in the phase-shifting pulse width modulation of the hybrid multilevel converter at time t1.

5. The method for minimizing the flying capacitance of a hybrid multilevel converter according to claim 4, characterized in that, In step 4, the minimum flyover capacitance value is determined based on the corresponding load current amplitude and system parameters. The formula is expressed as: ， in, This represents the average current at the moment when the maximum voltage fluctuation of the flying capacitor occurs. and These represent the load current amplitudes at times t1 and t2, respectively.

6. The method for minimizing the flying capacitance of a hybrid multilevel converter according to claim 5, characterized in that, The modulation wave is the modulation wave in the phase-shift pulse width modulation of a hybrid multilevel converter. Modulated wave and load current They are represented as follows: ， ， in, This indicates the maximum load current amplitude.

7. The method for minimizing the flying capacitance of a hybrid multilevel converter according to claim 1, characterized in that, This method is applicable to wide modulation frequency ranges of 1-200 Hz, wide carrier frequency ranges of 500-10000 Hz, and wide power factor ranges of 0-1.

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