Slope stabilization auxiliary circuit in local slope buffer circuit

Abstract

The present disclosure relates to a slope stabilization assist circuit in a local slope buffer circuit. The slope buffer circuit includes an input device having an input coupled to receive a slope signal. A bias current source is coupled to an output of the input device. The input device and the bias current source are coupled between a power supply line and ground. An assist current source is coupled between the output of the input device and ground. The assist current source is configured to conduct an assist current from the output of the input device to ground only during a slope event generated in the slope signal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to image sensors, and in particular, but not exclusively, to a ramp generator in an image sensor. BACKGROUND

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance the functionality, performance metrics, etc. (e.g., resolution, power consumption, dynamic range, etc.) of the image sensors in as many ways as possible through both device architecture design and image acquisition processing. The technology for manufacturing image sensors continues to progress rapidly. For example, the demand for higher resolution and lower power consumption has prompted further miniaturization and integration of these devices.

[0003] A typical complementary metal-oxide-semiconductor (CMOS) image sensor operates in response to image light from an external scene incident on the image sensor. The image sensor includes an array of pixels having a light-sensitive element (e.g., a photodiode) that absorbs a portion of the incident image light and generates image charge upon absorbing the image light. The image charge photo-generated by a pixel can be measured as an analog output image signal on a column bit line that varies with the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, read out from the column bit line as an analog signal, and converted to a digital value to produce a digital image (i.e., image data) representing the external scene.

[0004] An analog-to-digital converter (ADC) is typically used in a CMOS image sensor (CIS) to convert charge to a digital representation of charge by the image sensor. The ADC generates the digital representation of charge based on a comparison of the image charge signal to a reference voltage signal. Conventionally, the reference voltage signal can be a ramp signal provided by a ramp generator, and conventionally, the comparison can be performed by a comparator that provides an output that can be used with a counter to generate the digital representation of the image charge.

[0005] It should be appreciated that the ramp settling time or delay of the ramp signal generated by the ramp generator and received by the comparator can limit the maximum frame rate of the image sensor. Accordingly, reducing the ramp settling time of the ramp signal received by the comparator can increase the maximum frame rate and thus the performance of the image sensor. SUMMARY

[0006] In one aspect, the present invention relates to a ramp buffer circuit comprising: an input device having an input coupled to receive a ramp signal; a bias current source coupled to an output of the input device, wherein the input device and the bias current source are coupled between a power line and ground; and an auxiliary current source coupled between the output of the input device and ground, wherein the auxiliary current source is configured to conduct auxiliary current from the output of the input device to ground only during a ramp event generated in the ramp signal.

[0007] In another aspect, the present invention relates to an imaging system comprising: a pixel array for receiving image light and generating an image charge voltage signal in response; and a readout circuit system coupled to receive the image charge voltage signal from the pixel array and providing a digital representation of the image charge voltage signal in response, the readout circuit system including a comparator for receiving the image charge voltage signal, comparing the image charge voltage signal with a ramp signal from a ramp generator, and providing the digital representation of the image charge voltage signal in response, wherein the comparator is coupled to receive the ramp signal via a ramp buffer circuit, wherein the ramp buffer circuit includes: an input device having an input coupled to receive the ramp signal; a bias current source coupled to an output of the input device, wherein the input device and the bias current source are coupled between a power line and ground; and an auxiliary current source coupled between the output of the input device and ground, wherein the auxiliary current source is configured to conduct auxiliary current from the output of the input device to ground only during a ramp event generated in the ramp signal. Attached Figure Description

[0008] Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following figures, wherein, unless otherwise specified, reference numerals refer to similar parts.

[0009] Figure 1 The illustration illustrates an example of an imaging system including a readout circuit according to the teachings of the present invention, the readout circuit including a low-power ramp stabilization auxiliary circuit, the low-power ramp stabilization auxiliary circuit being included in a local ramp buffer circuit in the analog-to-digital converter of the readout circuit.

[0010] Figure 2 This is a block diagram illustrating an example analog-to-digital converter coupled to receive a ramp signal from a ramp generator via a local ramp buffer, according to the teachings of the present invention.

[0011] Figure 3AAn example of a schematic diagram of a local ramp buffer circuit including a ramp stabilization auxiliary circuit prior to a ramp event, as shown in the teachings of the present invention.

[0012] Figure 3B An example of a schematic diagram of a local ramp buffer circuit including ramp stabilization auxiliary circuitry during a ramp event, as taught in the present invention, is shown.

[0013] Figure 3C This is a timing diagram illustrating the signals in an example local ramp buffer circuit with a ramp stabilization auxiliary circuit according to the teachings of the present invention.

[0014] Figure 4A An example of a schematic diagram of a local ramp buffer circuit including a ramp stabilization auxiliary circuit according to the teachings of the present invention is shown, illustrating the power consumption from the power line before a ramp event.

[0015] Figure 4B An example of a schematic diagram of a local ramp buffer circuit including a ramp stabilization auxiliary circuit according to the teachings of the present invention is shown, illustrating the power consumption from the power line during a ramp event.

[0016] Several views throughout the figures correspond to reference characters indicating the respective components. Those skilled in the art will understand that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, to aid in understanding the various embodiments of the invention, the dimensions of some elements in the figures may be enlarged relative to other elements. Additionally, common and well-known elements that are not typically depicted in commercially viable embodiments are shown to facilitate a less obstructed view of these various embodiments of the invention. Detailed Implementation

[0017] This document describes examples of imaging systems incorporating readout circuitry with ramp stabilization auxiliary circuitry included in a local ramp buffer circuit. Numerous specific details are set forth in the following description to provide a thorough understanding of the examples. However, those skilled in the art will recognize that the techniques described herein can be practiced without one or more of the stated specific details or with the aid of other methods, components, materials, etc. In other examples, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring certain aspects.

[0018] Throughout this specification, references to "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with that example is included in at least one embodiment of the invention. Therefore, the appearance of the phrase "in one example" or "in one embodiment" in various places throughout this specification does not necessarily refer to the same example. Furthermore, the particular feature, structure, or characteristic may be combined in any suitable manner in one or more examples.

[0019] For example, spatial relative terms such as “below,” “under,” “above,” “below,” “above,” “upper,” “top,” “bottom,” “left,” “right,” “center,” “middle,” etc., are used herein for ease of explanation to describe the relationship of one element or feature relative to another element (or other elements) or feature (or several features) as illustrated in the figures. It should be understood that, in addition to the orientations depicted in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. For example, if the device in the figure is rotated or flipped, then an element described as “below” or “under” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can cover both the above and below orientations. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptors used herein may be interpreted accordingly. Furthermore, it should be understood that when an element is described as “between” two other elements, it may be the only element between the two other elements or there may be one or more intervening elements.

[0020] Several technical terms are used throughout this specification. These terms will be given their general meaning in the field of their respective domains, unless otherwise specifically defined herein or the context in which they are used will clearly imply otherwise. It should be noted that in this document, component names and symbols are used interchangeably (e.g., Si and silicon); however, they have the same meaning.

[0021] As will be discussed, various examples of imaging systems incorporating readout circuitry with a low-power ramp stabilization auxiliary circuitry included in local ramp buffer circuitry are described. In various examples, a ramp generator is configured to generate a system-level ramp signal, which is coupled to be received by an analog-to-digital converter (ADC) included in the readout circuitry. Each ADC includes a comparator coupled to receive analog image data from a pixel array via column lines and the ramp signal via the local ramp buffer circuitry. In examples, the low-power ramp stabilization auxiliary circuitry includes an auxiliary current source included in each local ramp buffer and coupled between the output of the local ramp buffer circuitry and ground. In examples, the low-power ramp stabilization auxiliary circuitry provides an auxiliary current from the output of the local ramp buffer circuitry to ground, the auxiliary current being turned on during a ramp event or ramp phase of the output ramp signal of the local ramp buffer circuitry. For the purposes of this invention, it should be understood that a ramp event of the output ramp signal is the period during which the ramp signal continuously decreases. In another instance, it should be understood that a ramp event of the output ramp signal can also be considered as the period during which the ramp signal continuously increases. According to the teachings of the invention, the output capacitor coupled to the output of the local ramp buffer circuit is charged by an auxiliary current, which thus reduces the ramp stabilization time delay of the ramp signal due to the load on the output of the local ramp buffer circuit, thereby improving the maximum frame rate and image sensor performance. Additionally, in various instances, the charge in the power line current is also reduced because the low-power ramp stabilization auxiliary circuit is activated during the ramp event and deactivated before the ramp event. According to the teachings of the invention, since the low-power ramp stabilization auxiliary circuit is coupled between ground and the output of the local ramp buffer circuit, and the charging current of the output capacitor is supplied from the low-power ramp stabilization auxiliary circuit, the capacitance between the output of the local ramp buffer circuit and ground does not cause a change in the power line current during a ramp event.

[0022] For illustration purposes, Figure 1 An example of an imaging system 100 including readout circuitry according to the teachings of the present invention is shown, the readout circuitry including low-power ramp stabilization auxiliary circuitry included in a local ramp buffer circuit. As shown in the illustrated example, the imaging system 100 includes a pixel array 102, control circuitry 110, readout circuitry 106, and functional logic 108. In one example, the pixel array 102 is a two-dimensional (2D) array comprising a plurality of pixel circuits 104 (e.g., P1, P2, ..., Pn) arranged in rows (e.g., R1 to Ry) and columns (e.g., C1 to Cx) to acquire image data of people, places, objects, etc., which can then be used to reproduce images of people, places, objects, etc.

[0023] In various embodiments, each pixel circuit 104 may include one or more photodiodes configured to generate image charge in response to incident light. The image charge generated in each photodiode is transferred to a floating diffuser included in each pixel circuit 104, converted into an image signal, and then read out from each pixel circuit 104 by the readout circuit 106 via column lines 112. In various embodiments, the readout circuit 106 may read out one line of image data at a time along the readout column lines 112 (illustrated) or may use various other techniques (not illustrated) to read out image data, such as serial readout or simultaneous fully parallel readout of all pixel circuits 104.

[0024] In various examples, the readout circuit 106 may include an amplifier circuit system, an analog-to-digital converter (ADC), or others. In the depicted example, the ADC 118 includes a comparator circuit 116 coupled to receive an image signal from the pixel array 102 via bit lines 112. In one example, the comparator circuit 116 may include multiple comparators coupled to receive the image signal via bit lines 112. In one example, each of the comparators included in the comparator circuit 116 is also coupled to receive a ramp signal 140 from a ramp generator 114, as shown. In various examples, each of the comparators is coupled to receive the ramp signal 140 via a local ramp buffer circuit. Each comparator included in the comparator circuit 116 can be used to determine a digital representation of the image signal using a counter based on a comparison of the ramp signal 140 with the voltage level of the image signal received via bit lines 112. As will be discussed, in various instances, each local ramp buffer circuit includes a low-power ramp stabilization auxiliary circuit that reduces the ramp stabilization time or delay of the ramp signal 140 to increase the maximum frame rate and thus improve the performance of the imaging system 100 according to the teachings of the present invention.

[0025] In this example, the digital image data values ​​generated by the ADC 118 can then be received by functional logic 108. Functional logic 108 can store the digital image data or even manipulate it by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or others).

[0026] In one example, control circuitry 104 is coupled to pixel array 102 to control the operation of multiple photodiodes within pixel array 102. For instance, control circuitry 104 may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal for simultaneously activating all pixel circuits 104 within pixel array 102 to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal, such that each row, column, or group of pixels is sequentially activated during successive acquisition windows. In yet another example, image acquisition is synchronized with lighting effects such as flash.

[0027] In one example, imaging system 100 may be included in a digital camera, mobile phone, laptop computer, etc. Additionally, imaging system 100 may be coupled to other hardware, such as a processor (general purpose or other), memory elements, outputs (USB port, wireless transmitter, HDMI port, etc.), lighting devices / flash, electrical inputs (keyboard, touchscreen, tracking pad, mouse, microphone, etc.), and / or a display. Other hardware can deliver instructions to imaging system 100, retrieve image data from imaging system 100, or manipulate image data supplied by imaging system 100.

[0028] Figure 2 This is a block diagram illustrating an example analog-to-digital converter coupled to receive a ramp signal from a ramp generator via a local ramp buffer, according to the teachings of the present invention. It should be understood that... Figure 2 The analog-to-digital converter shown can be included in Figure 1 The illustrations in the diagram illustrate an example of an analog-to-digital converter in a readout circuit, and similarly named and numbered components described above are coupled and function in a similar manner below.

[0029] For illustration purposes, Figure 2 Multiple analog-to-digital converters (ADCs) 218 ​​are shown, coupled to receive analog image data from pixel array 202 via corresponding bit lines 212. It should be understood that... Figure 2 Each of the ADCs in the 218 illustrated in the diagram is essentially similar to the others, and Figure 2 For simplicity, only one of the ADCs 218 is designated. As shown in the illustrated example, ramp generator 214 is configured to generate a system-level ramp signal V. RAMP 220. Each ADC 218 includes a comparator 216 having a first input (e.g., an inverting input) coupled to receive analog image data from the pixel array 202 via bit line 212 and a ramp signal V coupled to receive a local ramp buffer circuit 222. RAMPThe second input of 220. In operation, each comparator is configured to receive the ramp signal V received by comparator 216 through local ramp buffer circuit 222. RAMP The counter 220 flips when its voltage reaches or equals the voltage of the analog image data received from bit line 212. The output of counter 220 is coupled to the output of comparator 216 to respond to a ramp signal V received by comparator 216 via local ramp buffer circuit 222. RAMP When 220 is flipped by comparing the voltage of the analog image data received from bit line 212 with the voltage of the analog image data received from bit line 212, a digital representation of the voltage of the analog image data received from bit line 212 is provided.

[0030] Figure 3A This illustration shows an example of a schematic diagram of a local ramp buffer circuit including a ramp stabilization auxiliary circuit prior to a ramp event, according to the teachings of the present invention. It should be understood that... Figure 3A The local ramp buffer circuit illustrated in the figure can be used as... Figure 2 The example of the local ramp buffer circuit illustrated in the figure above, and the similarly named and numbered components described above are coupled and function in a similar manner below.

[0031] like Figure 3A As illustrated in the example, the ramp buffer circuit 322 includes components coupled to receive a ramp signal V. RAMP Input device 390 of input 320. In the depicted example, input device 390 is illustrated as an NMOS transistor having a connection to power line 388 (e.g., V). DD The drain of the signal is coupled to receive the ramp signal V. RAMP The gate of 320 and the source of the input device 390 are configured as the output of the input device 390. A bias current source 392 is coupled to the output of the input device 390, such that the input device 390 and the bias current source 392 are coupled between the power supply line 388 and ground. In operation, the input current I... IN 307 is an input device 390 configured to conduct the drain-source current through the input device 390, and the bias current I B 301 is configured to conduct through the bias current source 392.

[0032] In the described example, the output capacitor C O A load capacitor 398 is coupled between the output of input device 390 and ground. An auxiliary current source 394 is also coupled between the output of input device 390 and ground. In various instances, the auxiliary current source 394 is configured to operate only on the ramp signal V. RAMP During the ramp event generated in 320, the auxiliary current I will be... ASSIST309 is conducted from the output of input device 390 to ground. In the illustrated example, auxiliary current switch 396 is coupled to auxiliary current source 394, such that auxiliary current switch 396 and auxiliary current source 394 are coupled between the output of input device 390 and ground. In various examples, auxiliary current switch 396 is configured to operate only on ramp signal V. RAMP During the ramp event generated in 320, the auxiliary current source 394 is configured to operate only on the ramp signal V. RAMP Activated during the ramp event generated in 320 to activate the auxiliary current I ASSIST 309 is conducted from the output of input device 390 to ground. In various instances, the auxiliary current source 394 is located at the ramp signal V. RAMP The auxiliary current I conducted during the ramp event generated in 320 ASSIST 309 is essentially equal to the output capacitor C coupled to the output of the input device 390. O 398 lies in the ramp signal V RAMP The charging current during the ramp event generated in 320.

[0033] Figure 3A The example illustration depicted illustrates the ramp signal V during the process. RAMP No ramp event occurred in 320 (e.g., before the ramp event or in ramp signal V). RAMP An example of this (during the non-slope event of 320). Therefore, in Figure 3A In the example depicted, the auxiliary current switch 396 is turned off and the auxiliary current source 394 is deactivated, causing the auxiliary current I... ASSIST 309 is zero. At this point, it should also be understood that the output capacitor C... O 398 was not charged or discharged, and the input current I IN 307 is basically equal to the bias current I B 301.

[0034] Figure 3B An example of a schematic diagram of a local ramp buffer circuit including ramp stabilization auxiliary circuitry during a ramp event, according to the teachings of the present invention, is shown. It should be understood that... Figure 3B The local ramp buffer circuit illustrated in the figure can be used as... Figure 2 The example partial ramp buffer circuit illustrated in the diagram above, and the similarly named and numbered components described above, are coupled and function in a similar manner below. Further understanding is warranted. Figure 3B The partial ramp buffer circuit illustrated in the figure is related to... Figure 3A The local ramp buffer circuit illustrated in the figure is the same, except that... Figure 3B In this case, the auxiliary current switch 396 is therefore in the slope signal V RAMPA ramp event occurs in 320, causing it to connect. Therefore, auxiliary current source 394 is activated, and auxiliary current I... ASSIST 309 is conducted from the output of input device 390 to ground via auxiliary current source 394. As mentioned, auxiliary current I... ASSIST 309 only on ramp signal V RAMP During a ramp event in 320, the output of input device 390 is drawn to ground.

[0035] In the described example, the ramp signal V RAMP During the ramp event in 320, at the output of input device 390 and across output capacitor C O 398's output voltage V O 303 follows the ramp signal V RAMP 320 and therefore continuously decreases with respect to time. Therefore, according to the following equation, the output capacitor C... O 398 is charged by a charging current of 311:

[0036]

[0037] In various instances, during a ramp event, the auxiliary current I provided by the auxiliary current source 394... ASSIST The value of 309 is basically equal to that of the output capacitor C. O The charging current is 311 for 398. Therefore, the auxiliary current I can also be determined according to the following equation. ASSIST 309:

[0038]

[0039] Therefore, during the ramp event, the bias current I of bias current source 392 B 301 does not require an output capacitor C. O 398 provides a charging current 311. Therefore, according to the teachings of the present invention, during and before a ramp event, the input current I of input device 390... IN The 307 series all maintain a value essentially equal to the bias current I. B 301. In this manner, according to the teachings of the present invention, the input current I of the input device 390... IN 307 remains constant and unchanged before, during, and after the ramp event, and is independent of the ramp signal V. RAMP The signal slope is 320 or the load capacitance of the output capacitor is 398.

[0040] Figure 3C This is a timing diagram illustrating the signals in an example partial ramp buffer circuit with a ramp stabilization auxiliary circuit according to the teachings of the present invention. It should be understood that...Figure 3C The signals illustrated in the timing diagram can be those existing in Figure 3A and Figure 3B The examples depicted herein are of signals in a local ramp buffer circuit, and similarly named and numbered components described above are coupled and function in a similar manner below. Specifically, the examples depicted illustrate a ramp signal V. RAMP 320. Output voltage signal V O 303. Input current I IN 307 and auxiliary current I ASSIST 309.

[0041] like Figure 3C The example depicted in the text illustrates the ramp voltage signal V. RAMP 320 and output voltage V O 303 Both are constant before the ramp event, which occurs at time T0. During this non-ramp event period before time T1, the input current I... IN 307 equals the bias current I B And auxiliary current I ASSIST 309 equals zero because auxiliary current source 394 was deactivated.

[0042] At time T1, at the ramp signal V RAMP A ramp event occurs in 320, which can be detected via the ramp signal V. RAMP The voltage at 320V drops steadily and continuously after time T1, indicating this. During this time period, the auxiliary current I... ASSIST 309 changes from zero to equal the output capacitor C O The value of the charging current of 398 - (dV) O / dt)*C O As shown. Therefore, according to the teachings of the present invention, the output capacitor C O The charging current of 398 is determined by the auxiliary current I. ASSIST 309 is provided, and the input current I IN 307 remains constant and equal to the bias current I during the ramp event. B Therefore, it should be understood that, according to the teachings of the present invention, and due to the absence of auxiliary current I... ASSIST Input current I in case of 346 IN 307 decreases -(dV) O / dt)*C O Compared to the non-ideal ramp event 307 that causes ramp stabilization delay, the output voltage V O 303 has an ideal slope event 305 with no slope stabilization time delay.

[0043] Figure 4A An example of a schematic diagram of a local ramp buffer circuit incorporating a ramp stabilization auxiliary circuit according to the teachings of the present invention is shown, illustrating the power consumption from the power line prior to a ramp event. It should be understood that... Figure 4A The local ramp buffer circuit illustrated in the figure can be used as... Figure 2 The example partial ramp buffer circuit illustrated in the diagram above, and the similarly named and numbered components described above, are coupled and function in a similar manner below. Further understanding is warranted. Figure 4A The partial ramp buffer circuit illustrated in the figure is related to... Figure 3A The local ramp buffer circuits illustrated in the figure share many similarities.

[0044] For example, such as Figure 4A As illustrated in the example, the ramp buffer circuit 422 includes components coupled to receive a ramp signal V. RAMP Input device 490 of input 420. In the depicted example, input device 490 is illustrated as an NMOS transistor having a coupling to power line 488 (e.g., V). DD The drain of the signal is coupled to receive the ramp signal V. RAMP The gate of 420 and the source of the input device 490 are configured as the output of the input device 490. A bias current source 492 is coupled to the output of the input device 490, such that the input device 490 and the bias current source 492 are coupled between the power supply line 488 and ground. In operation, it is assumed that the input current I of the input device 490 is... IN Equal to bias current I B 401, the bias current is configured to conduct through both the input device 490 and the bias current source 492, as shown.

[0045] In the depicted example, the auxiliary current source 494 is coupled between the output of the input device 490 and ground. In various examples, the auxiliary current source 494 is configured to operate only on the ramp signal V. RAMP During the ramp event generated in 420, the auxiliary current I will be... ASSIST 494 is conducted from the output of input device 490 to ground. In the illustrated example, auxiliary current switch 496 is coupled to auxiliary current source 494, such that auxiliary current switch 496 and auxiliary current source 494 are coupled between the output of input device 490 and ground. In various examples, auxiliary current switch 496 is configured to be connected to ramp signal V. RAMP During the ramp event generated in 420, the auxiliary current source 494 is configured to operate only on the ramp signal V. RAMP Activated during the ramp event generated in 420 to activate the auxiliary current I ASSIST409 is conducted from the output of input device 490 to ground.

[0046] In various instances, the auxiliary current source 494 is located at the ramp signal V. RAMP The auxiliary current I conducted during the ramp event generated in 420 ASSIST 409 is essentially equal to the capacitor coupled to the output of input device 490 at the ramp signal V. RAMP The charging current during the ramp event generated in 420.

[0047] Figure 4A The local ramp buffer circuit 422 shown in the figure and Figure 3A One of the differences between the local ramp buffer circuit 322 shown in the figure is that Figure 3A The output capacitor C shown in the figure O 398 Figure 4A The partial ramp buffer circuit 422 shown in the figure consists of a power line capacitor C coupled between the power line 488 and the output of the input device 490. VDD 415 and the grounding capacitor C coupled between the output of input device 490 and ground. GND 417 indicates.

[0048] Similar to Figure 3A The examples described in the text, Figure 4A The example illustration depicted illustrates the ramp signal V during the process. RAMP No ramp event occurred in 420 (e.g., before the ramp event or in ramp signal V). RAMP An instance during the non-slope event of 420. Therefore, in Figure 4A In the example depicted, the auxiliary current switch 496 is turned off and the auxiliary current source 494 is deactivated, causing the auxiliary current I... ASSIST 409 is zero. At this point, it should also be understood that the power line capacitor C... VDD 415 and grounding capacitor C GND 417 was not charged or discharged.

[0049] Figure 4B An example of a schematic diagram of a local ramp buffer circuit including a ramp stabilization auxiliary circuit according to the teachings of the present invention is shown, illustrating the power consumption from the power line during a ramp event. It should be understood that... Figure 4B The local ramp buffer circuit illustrated in the figure can be used as... Figure 2 The example partial ramp buffer circuit illustrated in the diagram above, and the similarly named and numbered components described above, are coupled and function in a similar manner below. Further understanding is warranted. Figure 4B The partial ramp buffer circuit illustrated in the figure is related to... Figure 4AThe local ramp buffer circuit illustrated in the figure is the same, except that... Figure 4B In the middle, the auxiliary current switch 496 is due to the ramp signal V at this time. RAMP A ramp event occurs in 420, causing it to connect. Therefore, auxiliary current source 494 is activated, and auxiliary current I... ASSIST 409 is conducted from the output of input device 490 to ground via auxiliary current source 494. As mentioned, auxiliary current I... ASSIST 409 only on ramp signal V RAMP During a ramp event in 420, the output of input device 490 is drawn to ground.

[0050] In the described example, the ramp signal V RAMP During the ramp event in 420, at the output of input device 490 and across ground capacitor C GND 417 output voltage V O 403 follows the ramp signal V RAMP 420 and therefore continuously decreases with respect to time. Therefore, according to the following equation, the grounding capacitor C... GND 417 is charged by charging current 421:

[0051]

[0052] In various instances, during a ramp event, the auxiliary current I supplied by the auxiliary current source 494... ASSIST The value of 409 is basically equal to the output capacitor C. O The charging current is 421, which is the grounding capacitor C. GND 417 and power line capacitor C VDD Therefore, the auxiliary current I can also be determined according to the following equation. ASSIST 409:

[0053]

[0054] As further illustrated in the example depicted, in the ramp signal V RAMP During the ramp event in 420, according to the following equation, the power line capacitor C VDD 415 is also charged by the charging current:

[0055]

[0056] It should be understood that capacitor C passes through the power line. VDD 415 of C VDD The charging current is at the ramp signal V RAMP During the ramp event in 420, it draws from power line 488 and passes through power line capacitor C. VDD415 of this C VDD The charging current is received by ground. Therefore, in the ramp signal V RAMP During a ramp event in 420, the total current supplied by power line 488 and the total current absorbed by ground are equal to:

[0057]

[0058] Therefore, it should be further understood that, according to the teachings of the present invention, a charging current -(dV) is provided in the auxiliary current source 494. O / dt)*C O In the case of a ramp event generated in ramp signal 420, the current in power line 488 is therefore essentially unaffected by the grounding capacitor C. GND The charging current has an impact.

[0059] The above description of the illustrated examples of the invention, including the content described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention have been described herein for illustrative purposes, those skilled in the art will recognize that various modifications can be made within the scope of the invention.

[0060] These modifications can be made to the invention in light of the above detailed description. The terminology used in the appended claims should not be construed as limiting the invention to the specific instances disclosed in this specification. Rather, the scope of the invention will be determined entirely by the appended claims, which will be interpreted in accordance with the established principles of claim interpretation.

Claims

1. A ramp buffer circuit, comprising: An input device having an input coupled to receive a ramp signal; A bias current source coupled to the output of the input device, wherein the input device and the bias current source are coupled between a power line and ground; and An auxiliary current source is coupled between the output of the input device and ground, wherein the auxiliary current source is configured to conduct auxiliary current from the output of the input device to ground only during a ramp event generated in the ramp signal.

2. The ramp buffer circuit of claim 1, wherein the auxiliary current conducted by the auxiliary current source during the ramp event generated in the ramp signal is substantially equal to the charging current of the output capacitor coupled to the output of the input device during the ramp event generated in the ramp signal.

3. The ramp buffer circuit of claim 2, wherein during the ramp event generated in the ramp signal, the current in the power line is substantially unaffected by the charging current of the output capacitor coupled to the output of the input device.

4. The ramp buffer circuit of claim 1, further comprising an auxiliary current switch coupled to the auxiliary current source, wherein the auxiliary current switch is configured to turn on only during the ramp event generated in the ramp signal, such that the auxiliary current source is configured to conduct the auxiliary current from the output of the input device to ground only during the ramp event generated in the ramp signal.

5. The ramp buffer circuit of claim 1, wherein during the ramp event generated in the ramp signal, the current through the input device is substantially equal to the bias current conducted by the bias current source, wherein during the non-ramp event generated in the ramp signal, the current through the input device is substantially equal to the bias current conducted by the bias current source.

6. The ramp buffer circuit of claim 1, wherein the input device includes an input transistor having a gate coupled to receive the ramp signal, wherein the drain of the input transistor is coupled to the power supply line, and wherein the source of the input transistor is coupled to the bias current source and the auxiliary current source.

7. The ramp buffer circuit of claim 6, wherein during the ramp event generated in the ramp signal, the drain-source current through the input transistor is substantially equal to the bias current conducted by the bias current source, and wherein during the non-ramp event generated in the ramp signal, the drain-source current through the input transistor is substantially equal to the bias current conducted by the bias current source.

8. An imaging system comprising: A pixel array that receives image light and generates an image charge voltage signal in response; and A readout circuit system coupled to receive the image charge voltage signal from the pixel array and, in response, provide a digital representation of the image charge voltage signal. The readout circuit system includes a comparator for receiving the image charge voltage signal, comparing the image charge voltage signal with a ramp signal from a ramp generator, and, in response, providing the digital representation of the image charge voltage signal. The comparator is coupled to receive the ramp signal via a ramp buffer circuit, wherein the ramp buffer circuit includes: An input device having an input coupled to receive the ramp signal; A bias current source coupled to the output of the input device, wherein the input device and the bias current source are coupled between a power line and ground; and An auxiliary current source is coupled between the output of the input device and ground, wherein the auxiliary current source is configured to conduct auxiliary current from the output of the input device to ground only during a ramp event generated in the ramp signal.

9. The imaging system of claim 8, wherein the auxiliary current conducted by the auxiliary current source during the ramp event generated in the ramp signal is substantially equal to the charging current of the output capacitor coupled to the output of the input device during the ramp event generated in the ramp signal.

10. The imaging system of claim 9, wherein during the ramp event generated in the ramp signal, the current in the power line is substantially unaffected by the charging current of the output capacitor coupled to the output of the input device.

11. The imaging system of claim 8, wherein the ramp buffer circuit further includes an auxiliary current switch coupled to the auxiliary current source, wherein the auxiliary current switch is configured to turn on only during the ramp event generated in the ramp signal, such that the auxiliary current source is configured to conduct the auxiliary current from the output of the input device to ground only during the ramp event generated in the ramp signal.

12. The imaging system of claim 8, wherein during the ramp event generated in the ramp signal, the current through the input device is substantially equal to the bias current conducted by the bias current source, wherein during the non-ramp event generated in the ramp signal, the current through the input device is substantially equal to the bias current conducted by the bias current source.

13. The imaging system of claim 8, wherein the input device comprises an input transistor having a gate coupled to receive the ramp signal, wherein the drain of the input transistor is coupled to the power supply line, and wherein the source of the input transistor is coupled to the bias current source and the auxiliary current source.

14. The imaging system of claim 13, wherein during the ramp event generated in the ramp signal, the drain-source current through the input transistor is substantially equal to the bias current conducted by the bias current source, wherein during the non-ramp event generated in the ramp signal, the drain-source current through the input transistor is substantially equal to the bias current conducted by the bias current source.

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