A parallel demodulation timing synchronization method for high-speed coherent spread spectrum

Abstract

The application discloses a parallel demodulation timing synchronization method for high-speed coherent spread spectrum, and relates to the field of wideband satellite communication covert communication and anti-jamming communication systems. The application adopts parallel processing demodulation to reduce processing clock, adopts a mode of adjusting the timing error of a spread spectrum communication delay-locked loop output to realize tracking timing synchronization of the spread spectrum communication, and the mode is that multiple parallel outputs are adopted to reduce processing clock, and the output clock of resampling is adjusted to realize synchronization of the local clock and the received data clock, which is beneficial to low signal-to-noise ratio demodulation, suitable for high chip rate or high bandwidth spread spectrum, and can be used for wideband satellite spread spectrum communication.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of satellite communication, in particular to a parallel demodulation timing synchronization method for high-speed coherent spread spectrum, which can improve the anti-interference ability of spread spectrum system in wideband satellite communication. BACKGROUND

[0002] With the continuous development of anti-interference technology, increasing spread spectrum code rate and developing wideband or even ultra-wideband spread spectrum TT&C communication system are an important trend in future development. However, high spread spectrum code rate means wideband of signal bandwidth, especially for ultra-wideband direct spread spectrum TT&C communication signal, the sampling cost, design difficulty and implementation complexity of the receiving system will increase sharply.

[0003] The typical spread spectrum signal tracking method is to use delay lock loop method. Delay lock loop uses cross-correlation in feedback loop, which is a very good non-linear negative feedback system for tracking time delay difference of correlation waveform. However, higher sampling clock is needed for tracking timing of spread spectrum signal by using delay lock loop. In addition, even if the receiving system can realize ultra-wideband signal acquisition according to the classical sampling theory, the obtained signal data rate will be very high, and high data rate will put higher requirements on signal storage, transmission, capture tracking and data demodulation design. SUMMARY

[0004] The purpose of the present application is to provide a parallel demodulation timing synchronization method for high-speed coherent spread spectrum. The present application can ensure correct reception of low spectral density high bandwidth signal and solve the problem of high data rate leading to difficulty in signal capture tracking and data demodulation.

[0005] The purpose of the present application is achieved as follows:

[0006] A parallel demodulation timing synchronization method for high-speed coherent spread spectrum, comprising the following steps:

[0007] (1) converting baseband demodulation data received by the demodulator into 16 parallel data, and controlling the sampling rate in the range of 2 to 8 times the sampling rate;

[0008] (2) digitally resampling the 16 parallel data under the control of initial frequency control word init_fcw and frequency adjustment control word delta_fcw, outputting 16 4 times sampling data, and realizing spread spectrum demodulation timing adjustment; wherein the initial delta_fcw is 0, and the subsequent delta_fcw is the output of step (6);

[0009] (3) performing parallel matched filtering on the parallel digitally resampled data to eliminate inter-code interference, and then ensuring the stability of in-band signal power through digital AGC;

[0010] (4) Parallel data of digital AGC output is captured by parallel pseudo code to realize phase coarse synchronization of local code word and received data;

[0011] (5) Correlation despread is performed on local code word and received data after capture synchronization to output three branches of leading, lagging and middle demodulation data;

[0012] (6) Timing error is extracted from three branches of leading, lagging and middle demodulation data, and frequency adjustment control word delta_fcw is outputted to step (2) after second loop filtering.

[0013] Further, the specific mode of step (2) is as follows:

[0014] (201) Coefficient selection: the coefficient of digital resampling is designed as low pass filter coefficient with roll-off of 0.35, and is stored in coefficient buffer;

[0015] (202) Clock generation: frequency control word dds_fcw and frequency adjustment frequency control word delta_fcw are initialized, and the sum of the two controls the generation of parallel resampling output clock by digital frequency synthesizer;

[0016] (203) Control word generation: initial frequency control word init_fcw and frequency adjustment frequency control word delta_fcw are periodically accumulated, and the phase difference between output clock and input clock is also accumulated to obtain 32-bit frequency control word fcw;

[0017] (204) Data generation: the high 7 bits of fcw are taken as the integer part to control the selection of data, and the low 25 bits are taken as the decimal part to select resampling filter coefficient from coefficient buffer, then the selected coefficient is used to filter data to obtain data output.

[0018] Further, in step (5), correlation despread is realized as follows: code generator generates four parallel spread codes c1, c2, c3 and c4 under the drive of clock and sends them to correlator to make correlation accumulation with 16 parallel data d i,1 , d i,2 ……d i,15 , d i,16 of the i-th time, and the formula is as follows:

[0019]

[0020] Wherein, N / 4 is less than or equal to the maximum integer of spread ratio.

[0021] Compared with the background art, the present application has the following advantages:

[0022] 1. The present application adopts a multi-path data parallel processing mode to reduce the processing clock rate, adjusts the parallel digital resampling mode according to the error extracted by code tracking to realize timing synchronization, and can be used for continuous signal demodulation.

[0023] 2. The present application is suitable for spread spectrum sequence capture and pseudo code tracking timing of high-speed spread spectrum transmission signals, is very suitable for FPGA implementation, and has the characteristics of fast synchronization and low power consumption.

[0024] 3. The tracking error extraction algorithm adopted by the present application is independent of the spread spectrum ratio and has universality.

[0025] 4. The present application adopts a parallel multi-path processing mode to reduce the process processing clock, and is suitable for the case that the chip rate is high and the chip clock cannot be generated by adjusting the high clock. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a schematic diagram of the demodulation timing synchronization principle of the present application. DETAILED DESCRIPTION

[0027] In the following, the present application will be further described in detail in combination with the drawings.

[0028] A parallel demodulation timing synchronization method for high-speed coherent spread spectrum, comprising the following steps:

[0029] (1) converting the baseband demodulation data received by the demodulator into 16 parallel data, and controlling the sampling rate in the range of 2 to 8 times the sampling rate;

[0030] (2) the parallel digital resampling module digitally resamples the 16 parallel data under the control of the initial frequency control word init_fcw and the frequency adjustment control word delta_fcw, outputs 16 4 times sampling data, and realizes spread spectrum demodulation timing adjustment; the initial error is 0, and the subsequent error is the error extracted in step (6);

[0031] (3) after the digital resampling data are parallel matched filtered to eliminate inter-code interference, the in-band signal power is ensured to be stable by digital AGC;

[0032] (4) the parallel data output by the digital AGC realizes the phase coarse synchronization of the local code word and the received data through parallel pseudo code capture;

[0033] (5) after the capture synchronization, the local code word and the received data are correlated and despread, and the leading, lagging and intermediate branch demodulation data are output;

[0034] (6) the error extraction module extracts the timing error according to the leading, lagging and intermediate branch demodulation data, and outputs the frequency adjustment control word delta_fcw to step (2) after the second order loop filtering.

[0035] In step (2), the parallel number is 16, the output sampling rate is 4 times, the digital frequency synthesizer generates a resampling output clock with a frequency of about 1 / 4 chip rate under the drive of high-speed clock, and the processing clock frequency is reduced.

[0036] The specific implementation of step (2) is as follows:

[0037] (201) Coefficient selection: the coefficient of digital resampling is designed as a low-pass filter coefficient with a roll-off of 0.35, and is stored in a coefficient buffer;

[0038] (202) Clock generation: the sum of the initial frequency control word dds_fcw and the frequency adjustment frequency control word delta_fcw controls the digital frequency synthesizer to generate a parallel resampling output clock;

[0039] (203) Control word generation: the initial frequency control word init_fcw and the frequency adjustment frequency control word delta_fcw are periodically accumulated, and the phase difference between the output clock and the input clock is also accumulated, to obtain a 32-bit frequency control word fcw;

[0040] (204) Data generation: the high 7 bits of fcw are used as the integer part to control the selection of data, and the low 25 bits are used as the decimal part to select the resampling filter coefficient in the coefficient buffer, then the data is filtered with the coefficient to obtain the data output.

[0041] In step (5), the correlation despreading is implemented as follows: the code generator generates four parallel spread codes c1, c2, c3 and c4 under the drive of the clock, and sends them to the correlator to correlate and accumulate with the 16th incoming parallel data (d i,1 , d i,2 ……d i,15 , d i,16 ), and the formula is:

[0042]

[0043] Wherein, N / 4 is less than or equal to the maximum integer of the spreading ratio.

[0044] The method uses parallel processing demodulation to reduce the processing clock, and uses the timing error of the spread spectrum communication delay-locked loop output to adjust the multi-channel parallel digital resampling output clock to realize the tracking timing synchronization of spread spectrum communication. This method does not need to rely on the high-chip clock adjustment to generate the chip clock, but uses the parallel multi-channel way to reduce the processing clock, and adjusts the resampling output clock to realize the synchronization of the local clock and the received data clock, which is beneficial to low SNR demodulation, suitable for high-chip rate or high-bandwidth spread spectrum, and can be used for wideband satellite spread spectrum communication.

[0045] The following is a more specific example:

[0046] A timing synchronization method suitable for high-speed spread spectrum signals, a demodulation timing synchronization diagram of a received spread spectrum signal is shown as Figure 1 After the satellite communication system ground station is started, the spread spectrum sequence capture synchronization is first completed, and then the code tracking timing synchronization based on parallel resampling is performed.

[0047] The specific steps of the method are as follows:

[0048] (1) Convert the baseband demodulation data received by the demodulator into 16 parallel data, and control the sampling rate in the range of 2 to 8 times the sampling rate.

[0049] (2) The parallel digital resampling module controls the 16 parallel data under the control of the initial frequency control word init_fcw and the frequency adjustment control word delta_fcw, and outputs 16 4 times sampling data, realizing spread spectrum demodulation timing adjustment; The initial error is 0, and the subsequent error is the error extracted in step (6). The specific method is:

[0050] 1) Coefficient selection: the coefficient of digital resampling is designed as the coefficient of a low-pass filter with a roll-off of 0.35, and is stored in the coefficient buffer;

[0051] 2) Clock generation: the sum of the initial frequency control word dds_fcw and the frequency adjustment frequency control word delta_fcw controls the digital frequency synthesizer to generate a parallel resampling output clock;

[0052] 3) Control word generation: periodically accumulate the initial frequency control word init_fcw and the frequency adjustment frequency control word delta_fcw, and at the same time accumulate the phase difference between the output clock and the input clock, to obtain a 32-bit frequency control word fcw;

[0053] 4) Data generation: take the high 7 bits in fcw as the integer part to control the selection of data, and the low 25 bits as the decimal part to select the resampling filter coefficient in the coefficient buffer, then filter the data with this coefficient to obtain the data output.

[0054] The number of parallel paths is 16, and the output sampling rate is 4 times. The digital frequency synthesizer generates a resampling output clock with a frequency of about 1 / 4 chip rate under the drive of a high-speed clock, reducing the processing clock frequency.

[0055] (3) After parallel matched filtering to eliminate inter-code interference, the data after digital resampling is guaranteed to have stable in-band signal power by digital AGC;

[0056] (4) The parallel data output by the digital AGC realizes the phase coarse synchronization of the local code word and the received data through parallel pseudo code capture;

[0057] (5) Capture synchronization after the local code word and the received data for correlation despreading, and output the leading, lagging and intermediate branch demodulation data;

[0058] (6) The error extraction module extracts the timing error according to the leading, lagging and intermediate branch demodulation data and outputs the frequency adjustment control word delta_fcw to step (2) after second-order loop filtering.

[0059] The pilots of the leading, intermediate and lagging branches are accumulated according to the length L, and the multiple pilot accumulation results are non-coherently accumulated with the length N to improve the anti-interference ability. The non-coherent accumulation values of the leading, intermediate and lagging branches are represented by C1, C0 and C -1 , and the three non-coherent accumulation results are error-extracted, and the formula is The extracted error Δτ is second-order loop filtered to extract the error information, thereby completing the code tracking error extraction.

[0060] The method realizes the interpolation tracking timing in step 2, and step 6 is used to extract the error information, thereby providing the continuous tracking timing for step 2.

[0061] In summary, the present application proposes a timing synchronization method suitable for high-speed spread spectrum signals for the timing synchronization problem in the communication system with high chip rate and high spreading ratio. The method adopts parallel multi-path demodulation, the clock uses 1 / 4 chip clock, and the demodulation timing synchronization is realized by adjusting the local data, without the need to adjust the local chip clock according to the high multiple chip clock. The method is suitable for the case that the chip rate is high and the chip clock cannot be generated by adjusting the high multiple clock. The present application can be used in wideband satellite anti-interference communication, and is very suitable for FPGA implementation.

Claims

1. A parallel demodulation timing synchronization method for high speed coherent spread spectrum, characterized in that, The method comprises the following steps: (1) converting the baseband demodulation data received by the demodulator into 16 parallel data, and controlling the sampling rate in the range of 2 to 8 times the sampling rate; (2) digitally resampling the 16 parallel data under the control of an initial frequency control word init_fcw and a frequency adjustment control word delta_fcw, outputting 16 parallel 4 times sampling data, and realizing spread spectrum demodulation timing adjustment; wherein the initial delta_fcw is 0, and the subsequent delta_fcw is the output of step (6); the specific method is: (201) coefficient selection: the coefficient of digital resampling is designed as the coefficient of a low-pass filter with a roll-off of 0.35, and is stored in a coefficient buffer; (202) clock generation: initializing a frequency control word dds_fcw and a frequency adjustment control word delta_fcw, and adding them to control the digital frequency synthesizer to generate a parallel resampling output clock; (203) control word generation: periodically accumulating the initial frequency control word init_fcw and the frequency adjustment control word delta_fcw, and accumulating the phase difference between the output clock and the input clock at the same time, to obtain a 32-bit frequency control word fcw; (204) data generation: taking the high 7 bits in fcw as the integer part for controlling the selection of data, and taking the low 25 bits as the decimal part for selecting the resampling filter coefficient from the coefficient buffer, then filtering the data with the selected coefficient to obtain the data output; (3) performing parallel matched filtering on the parallel digital resampled data to eliminate inter-symbol interference, and then ensuring the stability of the in-band signal power through digital AGC; (4) performing parallel pseudo-code capture on the parallel data output by the digital AGC, to realize the phase coarse synchronization of the local code word and the received data; (5) correlatively despread the local code word after capture synchronization and the received data, and output the leading, lagging and intermediate three branch demodulation data; wherein the correlatively despread is implemented as follows: the code generator generates four parallel spread codes under the clock driving 、 、 、 and sends them to the correlator to be correlated with the 16-way parallel data of the ith time 、 … 、 , and the formula is: ， wherein, a maximum integer less than or equal to the spreading ratio; (6) extracting the timing error from the demodulation data of the three branches of the leading, lagging and intermediate, and outputting the frequency adjustment control word delta_fcw to step (2) after second-order loop filtering.

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