Encryption device and encryption method

Abstract

The present application provides an encryption device and an encryption method. The encryption device includes a controller, a random controller, a first functional unit and a second functional unit. The controller is used to generate a first enable signal and a second enable signal. When at least one of the first enable signal and the second enable signal is a first logic level, the random controller generates a first random signal and a second random signal. The first functional unit performs corresponding operation according to the first enable signal and the first random signal. The second functional unit performs corresponding operation according to the second enable signal and the second random signal.

Description

Technical Field

[0001] This invention relates to an encryption device and encryption method, and more particularly to an encryption device and encryption method implemented using a clock gating unit and a random number generator. Background Technology

[0002] Since IoT devices are mostly unattended, they are vulnerable to hacking, making their physical security increasingly important. Side-channel attacks (SCA) exploit the physical characteristics of a device, such as power, electromagnetic waves, and temperature, to reveal secret keys and other information about the target device. Therefore, preventing the theft of critical information through power analysis is a crucial issue today. Summary of the Invention

[0003] This invention proposes an encryption device and method that randomly enables functional units that are not currently performing operations by using a clock gating unit and random number generation, thereby disrupting the power trace of the encryption device. Furthermore, the encryption device and method proposed in this invention are very simple and can be implemented without requiring a background in cryptography. In addition, when it is desired to increase the power trace of the encryption device, the original functional units can be divided into more and smaller hardware modules, and each module can be inserted with a clock gating unit, easily increasing the complexity of the power trace. Therefore, overall, the encryption device and method proposed in this invention can achieve a greater possibility of power traces at a relatively low cost, thereby improving encryption security.

[0004] In view of this, the present invention proposes an encryption device, comprising a controller, a random controller, a first functional unit, and a second functional unit. The controller generates a first enable signal and a second enable signal. When at least one of the first enable signal and the second enable signal is a first logic level, the random controller generates a first random signal and a second random signal. The first functional unit performs corresponding operations based on the first enable signal and the first random signal. The second functional unit performs corresponding operations based on the second enable signal and the second random signal.

[0005] According to an embodiment of the present invention, the encryption device further includes a first clock gating unit and a second clock gating unit. The first clock gating unit generates a first internal clock signal based on the first enable signal, the first random signal, and a system clock signal, wherein the first functional unit performs corresponding operations based on the first internal clock signal. The second clock gating unit generates a second internal clock signal based on the second enable signal, the second random signal, and the system clock signal, wherein the second functional unit performs corresponding operations based on the second internal clock signal.

[0006] According to an embodiment of the present invention, the encryption device further includes a third clock gating unit and a third functional unit. The third clock gating unit generates a third internal clock signal based on a third enable signal, a third random signal, and the system clock signal. The third functional unit performs corresponding operations based on the third internal clock signal, wherein the controller is further configured to generate the third enable signal, and when at least one of the first enable signal, the second enable signal, and the third enable signal is at the first logic level, the random controller generates the first random signal, the second random signal, and the third random signal.

[0007] According to an embodiment of the present invention, when the first enable signal is the first logic level, the first functional unit performs a corresponding operation to enable it, and the random controller generates the first random signal, the second random signal, and the third random signal, so that the second functional unit and the third functional unit are randomly enabled according to the second random signal and the third random signal, respectively, to disrupt the power trace of the encryption device.

[0008] According to one embodiment of the present invention, one of the first clock gating unit, the second clock gating unit, and the third clock gating unit includes an OR gate and an AND gate. The OR gate receives an enable signal and a random signal to generate a logic signal. The AND gate outputs the system clock signal as an internal clock signal based on the logic signal.

[0009] According to an embodiment of the present invention, the random controller includes a random number controller and a random number generator. The random number controller determines whether any one of the first enable signal, the second enable signal, and the third enable signal is at the first logic level. When any one of the first enable signal, the second enable signal, and the third enable signal is at the first logic level, the random number controller issues a decision signal. The random number generator generates a first random number, a second random number, and a third random number based on the decision signal and the system clock signal.

[0010] According to an embodiment of the present invention, the random number generator regenerates the first random number, the second random number, and the third random number at a predetermined time, wherein the predetermined time is an integer multiple of the period of the system clock signal.

[0011] According to one embodiment of the present invention, the random controller further includes a first AND gate, a second AND gate, and a third AND gate. The first AND gate receives the decision signal and the first random number to generate the first random signal. The second AND gate receives the decision signal and the second random number to generate the second random signal. The third AND gate receives the decision signal and the third random number to generate the third random signal.

[0012] According to another embodiment of the present invention, the random number controller further includes a first AND gate, a second AND gate, and a third AND gate. The first AND gate receives a first random number control signal and the first random number to generate the first random signal. The second AND gate receives a second random number control signal and the second random number to generate the second random signal. The third AND gate receives a third random number control signal and the third random number to generate the third random signal, wherein the random number controller further generates the first random number control signal, the second random number control signal, and the third random number control signal to control whether to output any one of the first random number, the second random number, and the third random number.

[0013] The present invention further proposes an encryption method applicable to an encryption device, wherein the encryption device includes a first functional unit and a second functional unit. The encryption method includes generating a first enable signal to enable the first functional unit, wherein the first enable signal is a first logic level; generating a first random signal and a second random signal based on the first enable signal being the first logic level; and randomly enabling a second functional unit using the second random signal.

[0014] According to an embodiment of the present invention, the encryption device further includes a first clock gating unit and a second clock gating unit, wherein the encryption method further includes generating a first internal clock signal using the first clock gating unit based on the first enable signal, the first random signal, and a system clock signal; enabling the first functional unit using the first internal clock signal; generating a second internal clock signal using the second clock gating unit based on a second enable signal, the second random signal, and the system clock signal; and enabling the second functional unit using the second internal clock signal.

[0015] According to an embodiment of the present invention, the encryption device further includes a third functional unit. The encryption method further includes generating a third random signal based on the first enable signal which is the first logic level; and randomly enabling the third functional unit using the third random signal.

[0016] According to an embodiment of the present invention, the encryption device further includes a third clock gating unit. The encryption method further includes generating a third internal clock signal using the third clock gating unit based on a third enable signal, a third random signal, and a system clock signal; and enabling the third functional unit using the third internal clock signal.

[0017] According to an embodiment of the present invention, any one of the steps of generating the first internal clock signal using the first clock gating unit based on the first enable signal, the first random signal, and the system clock signal, generating the second internal clock signal using the second clock gating unit based on the second enable signal, the second random signal, and the system clock signal, and generating the third internal clock signal using the third clock gating unit based on the third enable signal, the third random signal, and the system clock signal, further includes performing a logical OR operation on an enable signal and a random signal to generate a logic signal; outputting the system clock signal as an internal clock signal based on the logic signal; and enabling the corresponding functional unit using the internal clock signal.

[0018] According to an embodiment of the present invention, the step of generating the first random signal, the second random signal, and the third random signal based on the first enable signal that is the first logic level further includes generating a decision signal using a random number controller when any one of the first enable signal, the second enable signal, and the third enable signal is the first logic level; and generating a first random number, a second random number, and a third random number based on the decision signal and the system clock signal.

[0019] According to one embodiment of the present invention, the first random number, the second random number, and the third random number are regenerated at a predetermined time, wherein the predetermined time is an integer multiple of the period of the system clock signal.

[0020] According to an embodiment of the present invention, the step of generating the first random signal, the second random signal, and the third random signal based on the decision signal and the system clock signal further includes performing a logical AND operation on the decision signal and the first random number to generate the first random signal; performing the logical AND operation on the decision signal and the second random number to generate the second random signal; and performing the logical AND operation on the decision signal and the third random number to generate the third random signal.

[0021] According to another embodiment of the present invention, the step of generating the first random signal, the second random signal, and the third random signal based on the decision signal and the system clock signal further includes using the random number controller to generate a first random number control signal, a second random number control signal, and a third random number control signal; performing a logical AND operation on the first random number control signal and the first random number to generate the first random signal; performing the logical AND operation on the second random number control signal and the second random number to generate the second random signal; and performing the logical AND operation on the third random number control signal and the third random number to generate the third random signal. Attached Figure Description

[0022] Figure 1 This is a block diagram of an encryption device according to an embodiment of the present invention;

[0023] Figure 2 This is a block diagram of a clock gating unit according to an embodiment of the present invention;

[0024] Figure 3 This is a block diagram of a clock gating unit according to another embodiment of the present invention;

[0025] Figure 4 This is a block diagram of a random controller according to an embodiment of the present invention;

[0026] Figure 5 A block diagram of a random controller according to another embodiment of the present invention; and

[0027] Figure 6 This is a flowchart of an encryption method according to an embodiment of the present invention.

[0028] Explanation of icon numbers:

[0029] 100: Encryption device

[0030] 110: Controller

[0031] 120: Random Controller

[0032] 131: First Clock Gating Unit

[0033] 132: Second clock gating unit

[0034] 133: Third Clock Gating Unit

[0035] 134: Fourth Clock Gating Unit

[0036] 135: Fifth Clock Gating Unit

[0037] 141: First Functional Unit

[0038] 142: Second Functional Unit

[0039] 143: Third Functional Unit

[0040] 144: Fourth Functional Unit

[0041] 145: Fifth Functional Unit

[0042] 200, 300: Clock gating unit

[0043] 210: OR gate

[0044] 220: with the door

[0045] 330: Type D flip-flop

[0046] 400, 500: Random controller

[0047] 410: Random Number Controller

[0048] 420: Random Number Generator

[0049] 430: The First and the Gate

[0050] 440: The Second AND Gate

[0051] 450: The Third and the Gate

[0052] 460: The Fourth Gate

[0053] 470: The Fifth and the Gate

[0054] 600: Encryption Method

[0055] SCLK: System clock signal

[0056] EN1: First enable signal

[0057] EN2: Second enable signal

[0058] EN3: Third enable signal

[0059] EN4: Fourth enable signal

[0060] EN5: Fifth enable signal

[0061] SR1: First random signal

[0062] SR2: Second random signal

[0063] SR3: Third random signal

[0064] SR4: Fourth random signal

[0065] SR5: Fifth random signal

[0066] CLKI: Internal clock signal

[0067] CLKI1: First internal clock signal

[0068] CLKI2: Second internal clock signal

[0069] CLKI3: Third internal clock signal

[0070] CLKI4: Fourth internal clock signal

[0071] CLKI5: Fifth internal clock signal

[0072] EN: Enable signal

[0073] SR: Random signal

[0074] SL: Logic Signal

[0075] D: Input terminal

[0076] E: Trigger end

[0077] Q: Output terminal

[0078] SD: Determining signal

[0079] RN1: First random number generator

[0080] RN2: Second random number generator

[0081] RN3: Third random number generator

[0082] RN4: Fourth Random Number

[0083] RN5: Fifth random number

[0084] RC1: First random number control signal

[0085] RC2: Second random number control signal

[0086] RC3: Third random number control signal

[0087] RC4: Fourth random number control signal

[0088] RC5: Fifth random number control signal

[0089] S610~S630: Procedure Flow

[0090] LTCH: Latch signal Detailed Implementation

[0091] The following description is an embodiment of the present invention. Its purpose is to illustrate the general principles of the invention and should not be considered as a limitation thereof. The scope of the invention should be defined by the claims.

[0092] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or portions. Therefore, a first element, component, region, layer, and / or portion discussed below may be referred to as a second element, component, region, layer, and / or portion without departing from the teachings of some embodiments disclosed herein.

[0093] It is worth noting that the following disclosure provides multiple embodiments or examples for practicing different features of the invention. The specific examples and arrangements of elements described below are merely for briefly illustrating the spirit of the invention and are not intended to limit its scope. Furthermore, the same element symbols or words may be repeated in multiple examples in the following description. However, the purpose of repetition is only to provide a simplified and clear description and is not intended to limit the relationship between the various embodiments and / or configurations discussed below. Moreover, descriptions in the following description of a feature being connected to, coupled to, and / or formed on top of another feature may actually encompass multiple different embodiments, including those features being in direct contact, or those including additional features formed between those features, such that the features are not in direct contact.

[0094] Figure 1 This is a block diagram of an encryption device according to an embodiment of the present invention. Figure 1As shown, the encryption device 100 includes a controller 110 and a random controller 120. The controller 110 is used to generate a first enable signal EN1, a second enable signal EN2, a third enable signal EN3, a fourth enable signal EN4, and a fifth enable signal EN5 according to the system clock signal SCLK.

[0095] The random controller 120 generates a first random signal SR1, a second random signal SR2, a third random signal SR3, a fourth random signal SR4, and a fifth random signal SR5 based on the system clock signal SCLK, a first enable signal EN1, a second enable signal EN2, a third enable signal EN3, a fourth enable signal EN4, and a fifth enable signal EN5. According to one embodiment of the present invention, when at least one of the first enable signal EN1, the second enable signal EN2, the third enable signal EN3, the fourth enable signal EN4, and the fifth enable signal EN5 is at a first logic level, the random controller 120 generates the first random signal SR1, the second random signal SR2, the third random signal SR3, the fourth random signal SR4, and the fifth random signal SR5. According to one embodiment of the present invention, the first logic level is a high logic level. According to another embodiment of the present invention, the first logic level may also be a low logic level. The following explanation uses the first logic level as a high logic level for illustrative purposes only and is not intended to limit the scope in any way.

[0096] like Figure 1 As shown, the encryption device 100 further includes a first clock gating unit 131, a second clock gating unit 132, a third clock gating unit 133, a fourth clock gating unit 134, and a fifth clock gating unit 135. The first clock gating unit 131 generates a first internal clock signal CLKI1 based on a first enable signal EN1, a first random signal SR1, and a system clock signal SCLK. The second clock gating unit 132 generates a second internal clock signal CLKI2 based on a second enable signal EN2, a second random signal SR2, and a system clock signal SCLK.

[0097] The third clock gating unit 133 generates the third internal clock signal CLKI3 based on the third enable signal EN3, the third random signal SR3, and the system clock signal SCLK. The fourth clock gating unit 134 generates the fourth internal clock signal CLKI4 based on the fourth enable signal EN4, the fourth random signal SR4, and the system clock signal SCLK. The fifth clock gating unit 135 generates the fifth internal clock signal CLKI5 based on the fifth enable signal EN5, the fifth random signal SR5, and the system clock signal SCLK.

[0098] like Figure 1As shown, the encryption device 100 further includes a first functional unit 141, a second functional unit 142, a third functional unit 143, a fourth functional unit 144, and a fifth functional unit 145. The first functional unit 141, the second functional unit 142, the third functional unit 143, the fourth functional unit 144, and the fifth functional unit 145 perform corresponding operations based on the first internal clock signal CLKI1, the second internal clock signal CLKI2, the third internal clock signal CLKI3, the fourth internal clock signal CLKI4, and the fifth internal clock signal CLKI5, respectively.

[0099] According to many embodiments of the present invention, any one of the first functional unit 141, the second functional unit 142, the third functional unit 143, the fourth functional unit 144, and the fifth functional unit 145 may be various encryption algorithms such as Data Encryption Standard (DES), International Data Encryption Algorithm (IDEA), Advanced Encryption Standard (AES), and Triple DES. According to other embodiments of the present invention, any one of the first functional unit 141, the second functional unit 142, the third functional unit 143, the fourth functional unit 144, and the fifth functional unit 145 may also be any known or unknown analog or digital circuit.

[0100] According to some embodiments of the present invention, the encryption device 100 may include more encryption units, thereby further disrupting the power trace of the encryption device 100 and providing further protection for the data processed by the encryption device 100. According to some embodiments of the present invention, the functional units may be further divided into smaller functional units (e.g., adders, logic gates, etc.), thereby increasing the possibilities and complexity of the power trace of the encryption device 100. According to other embodiments of the present invention, the encryption device 100 may also include any number of functional units; only five functional units are described herein, and this is not intended to limit the invention in any way.

[0101] According to an embodiment of the present invention, when the random controller 120 determines that the first enable signal EN1 is at a first logic level, the first functional unit 141 performs a corresponding operation based on the first enable signal EN1. Simultaneously, the random controller 120 generates a first random signal SR1, a second random signal SR2, a third random signal SR3, a fourth random signal SR4, and a fifth random signal SR5, causing the second functional unit 142, the third functional unit 143, the fourth functional unit 144, and the fifth functional unit 145 to be randomly enabled, thereby disrupting the power trace of the encryption device 100.

[0102] For example, when controller 110 enables the first functional unit 141 via the first enable signal EN1, random controller 120 can enable the second functional unit 142 and the fourth functional unit 144 via the second random signal SR2 and the fourth random signal SR4, respectively, and then enable the fifth functional unit 145 via the fifth random signal SR5 after a predetermined time. According to an embodiment of the present invention, the predetermined time is an integer multiple of the period of the system clock signal SCLK. In other words, random controller 120 can also update the generated first random signal SR1, second random signal SR2, third random signal SR3, fourth random signal SR4, and fifth random signal SR5 after each predetermined time, thereby randomly enabling different functional units.

[0103] According to one embodiment of the present invention, the functional unit enabled by the enable signal is not affected by the corresponding random signal. In the above embodiment, since the first functional unit 141 is enabled by the first enable signal EN1, the first functional unit 141 will not be affected by the first random signal SR1 and will continue to operate normally.

[0104] In detail, the first functional unit 141, the second functional unit 142, the third functional unit 143, the fourth functional unit 144, and the fifth functional unit 145 are enabled by corresponding first enable signals EN1, second enable signals EN2, third enable signals EN3, fourth enable signals EN4, and fifth enable signals EN5, and perform corresponding operations according to the system clock signal SCLK. Furthermore, any one of the disabled first functional unit 141, second functional unit 142, third functional unit 143, fourth functional unit 144, and fifth functional unit 145 will be randomly enabled by corresponding first random signals SR1, second random signals SR2, third random signals SR3, fourth random signals SR4, and fifth random signals SR5 according to the system clock signal SCLK, thereby achieving the purpose of disrupting the power trace of the encryption device 100.

[0105] Figure 2This is a block diagram of a clock gating unit according to an embodiment of the present invention. Figure 2 As shown, the clock gating unit 200 further includes an OR gate 210 and an AND gate 220. According to an embodiment of the present invention, the clock gating unit 200 corresponds to... Figure 1 Any one of the first clock gating unit 131, the second clock gating unit 132, the third clock gating unit 133, the fourth clock gating unit 134, and the fifth clock gating unit 135.

[0106] OR gate 210 receives an enable signal EN and a random signal SR, and performs a logical OR operation on the enable signal EN and the random signal SR to generate a logic signal SL. According to an embodiment of the present invention, Figure 2 The enable signal EN corresponds to... Figure 1 Any one of the first enable signal EN1, the second enable signal EN2, the third enable signal EN3, the fourth enable signal EN4, and the fifth enable signal EN5. Figure 2 The random signal SR corresponds to Figure 1 Any one of the first random signal SR1, the second random signal SR2, the third random signal SR3, the fourth random signal SR4, and the fifth random signal SR5.

[0107] AND gate 220 receives the logic signal SL and the system clock signal SCLK, and performs a logical AND operation on the logic signal SL and the system clock signal SCLK to generate the internal clock signal CLKI. In other words, when the logic signal SL is at a high logic level, AND gate 220 outputs the system clock signal SCLK as the internal clock signal CLKI.

[0108] According to one embodiment of the present invention, Figure 2 The internal clock signal CLKI corresponds to... Figure 1 The first internal clock signal CLKI1, the second internal clock signal CLKI2, the third internal clock signal CLKI3, the fourth internal clock signal CLKI4, and the fifth internal clock signal CLKI5.

[0109] like Figure 2 As shown, the enable signal EN and the random signal SR are transmitted to the AND gate 220 after passing through the OR gate 210 to generate the logic signal SL. Figure 1 The first functional unit 141, the second functional unit 142, the third functional unit 143, the fourth functional unit 144, and the fifth functional unit 145 are enabled by an enable signal EN and / or a random signal SR. In other words, when a functional unit is enabled by the enable signal EN, it will not be affected by the random signal SR and will maintain normal operation, and both the enable signal EN and the random signal SR can individually enable the corresponding functional unit.

[0110] For example, in the above embodiment, the first functional unit 141 is enabled by the first enable signal EN1. Even if the random controller 120 generates the first random signal SR1 at the same time, the first functional unit 141 is still enabled by the first enable signal EN1 and will not be affected by the first random signal SR1.

[0111] Figure 3 This is a block diagram of a clock gating unit according to another embodiment of the present invention. Figure 3 Clock gating unit 300 and Figure 2 Compared to the clock gating unit 200, the clock gating unit 300 further includes a D-type flip-flop 330, wherein the D-type flip-flop 330 is coupled between the OR gate 210 and the AND gate 220. According to an embodiment of the present invention, the clock gating unit 300 corresponds to... Figure 1 Any one of the first clock gating unit 131, the second clock gating unit 132, the third clock gating unit 133, the fourth clock gating unit 134, and the fifth clock gating unit 135.

[0112] like Figure 3 As shown, the D-type flip-flop 330 includes an input terminal D, a trigger terminal E, and an output terminal Q. The input terminal D receives the logic signal SL, the trigger terminal E receives the system clock signal SCLK, and the output terminal Q outputs the latch signal LTCH. Figure 3 As shown, the D-type flip-flop 330 is triggered by the falling edge of the system clock signal SCLK, latches the logic signal SL for one cycle of the system clock signal SCLK, and outputs a latch signal LTCH.

[0113] AND gate 220 receives the latch signal LTCH and the system clock signal SCLK, and performs a logical AND operation on the latch signal LTCH and the system clock signal SCLK to generate an internal clock signal CLKI. According to one embodiment of the present invention, when both the latch signal LTCH and the system clock signal SCLK are at a high logic level, the internal clock signal CLKI generated by AND gate 220 is also at a high logic level. According to one embodiment of the present invention... Figure 3 The internal clock signal CLKI corresponds to... Figure 1 The first internal clock signal CLKI1, the second internal clock signal CLKI2, the third internal clock signal CLKI3, the fourth internal clock signal CLKI4, and the fifth internal clock signal CLKI5.

[0114] According to other embodiments of the present invention, Figure 1The first clock gating unit 131, the second clock gating unit 132, the third clock gating unit 133, the fourth clock gating unit 134, and the fifth clock gating unit 135 can also be any other clock gating unit. Here, it is... Figure 2 The clock gating unit 200 and Figure 3 The explanation is based on the clock gating unit 300, but is not limited to it in any way.

[0115] Figure 4 This is a block diagram of a random controller according to an embodiment of the present invention. Figure 4 As shown, the random controller 400 includes a random number controller 410, a random number generator 420, a first AND gate 430, a second AND gate 440, a third AND gate 450, a fourth AND gate 460, and a fifth AND gate 470.

[0116] The random number controller 410 determines whether any one of the first enable signal EN1, the second enable signal EN2, the third enable signal EN3, the fourth enable signal EN4, and the fifth enable signal EN5 is at a first logic level. When any one of these signals is at the first logic level, the random number controller 410 issues a judgment signal SD. According to an embodiment of the present invention, the first logic level is a high logic level.

[0117] Random number generator 420 generates a first random number RN1, a second random number RN2, a third random number RN3, a fourth random number RN4, and a fifth random number RN5 based on a decision signal SD and a system clock signal SCLK. According to one embodiment of the present invention, random number generator 420 regenerates the first random number RN1, the second random number RN2, the third random number RN3, the fourth random number RN4, and the fifth random number RN5 after a predetermined time, wherein the predetermined time is an integer multiple of the period of the system clock signal SCLK.

[0118] First AND gate 430 receives the decision signal SD and the first random number RN1, and performs a logical AND operation on the decision signal SD and the first random number RN1 to generate a first random signal SR1. Second AND gate 440 receives the decision signal SD and the second random number RN2, and performs a logical AND operation on the decision signal SD and the second random number RN2 to generate a second random signal SR2. Third AND gate 450 receives the decision signal SD and the third random number RN3, and performs a logical AND operation on the decision signal SD and the third random number RN3 to generate a third random signal SR3.

[0119] The fourth AND gate 460 receives the decision signal SD and the fourth random number RN4, and performs a logical AND operation on the decision signal SD and the fourth random number RN4 to generate the fourth random signal SR4. The fifth AND gate 470 receives the decision signal SD and the fifth random number RN5, and performs a logical AND operation on the decision signal SD and the fifth random number RN5 to generate the fifth random signal SR5.

[0120] According to an embodiment of the present invention, since the first random number RN1, the second random number RN2, the third random number RN3, the fourth random number RN4, and the fifth random number RN5 are all controlled by the decision signal SD and output as the first random signal SR1, the second random signal SR2, the third random signal SR3, the fourth random signal SR4, and the fifth random signal SR5 respectively, it is possible to avoid erroneously outputting any of the first random number RN1, the second random number RN2, the third random number RN3, the fourth random number RN4, and the fifth random number RN5, thereby incorrectly enabling the corresponding first functional unit 141, the second functional unit 142, the third functional unit 143, the fourth functional unit 144, and the fifth functional unit 145.

[0121] Figure 5 This is a block diagram of a random controller according to another embodiment of the present invention. Figure 5 The random controller 500 and Figure 4 Compared to the random number controller 400, the random number controller 410 further generates a first random number control signal RC1, a second random number control signal RC2, a third random number control signal RC3, a fourth random number control signal RC4, and a fifth random number control signal RC5, and transmits them to the first AND gate 430, the second AND gate 440, the third AND gate 450, the fourth AND gate 460, and the fifth AND gate 470, respectively.

[0122] According to one embodiment of the present invention, the random number controller 410 can determine whether to output the random value generated by the random number generator 420 as the corresponding first random signal SR1, second random signal SR2, third random signal SR3, fourth random signal SR4, and fifth random signal SR5 through the first random number control signal RC1, the second random signal RC2, the third random signal SR3, the fourth random signal SR4, and the fifth random signal SR5, thereby randomly enabling at least one of the first functional unit 141, the second functional unit 142, the third functional unit 143, the fourth functional unit 144, and the fifth functional unit 145. In other words, the random number controller 410 can select the first random number control signal RC1, the second random number control signal RC2, the third random number control signal RC3, the fourth random number control signal RC4, and the fifth random number control signal RC5. Figure 1Whether any one of the first functional unit 141, the second functional unit 142, the third functional unit 143, the fourth functional unit 144, and the fifth functional unit 145 is randomly enabled.

[0123] According to another embodiment of the present invention, the random number controller 410 may add other algorithms to the first random number control signal RC1, the second random number control signal RC2, the third random number control signal RC3, the fourth random number control signal RC4, and the fifth random number control signal RC5, making it more difficult for attackers to predict the random values ​​of the first random signal SR1, the second random signal SR2, the third random signal SR3, the fourth random signal SR4, and the fifth random signal SR5.

[0124] Figure 6 This is a flowchart of an encryption method according to an embodiment of the present invention. The following description of encryption method 600 will be accompanied by… Figure 1 For detailed explanation. First, the controller 110 generates at least one of the first enable signal EN1, the second enable signal EN2, the third enable signal EN3, the fourth enable signal EN4, and the fifth enable signal EN5 as the first logic level to enable the corresponding first functional unit 141, the second functional unit 142, the third functional unit 143, the fourth functional unit 144, and the fifth functional unit 145 (step S610).

[0125] When at least one of the first enable signal EN1, the second enable signal EN2, the third enable signal EN3, the fourth enable signal EN4, and the fifth enable signal EN5 is at the first logic level, the first random signal SR1, the second random signal SR2, the third random signal SR3, the fourth random signal SR4, and the fifth random signal SR5 are generated by the random controller 120 (step S620).

[0126] Using the first random signal SR1, the second random signal SR2, the third random signal SR3, the fourth random signal SR4, and the fifth random signal SR5, at least one of the disabled first functional unit 141, the second functional unit 142, the third functional unit 143, the fourth functional unit 144, and the fifth functional unit 145 is randomly enabled (step S630) to disrupt the power trace of the encryption device 100.

[0127] For example, in step S610, the first functional unit 141 is enabled using the first enable signal EN1. In step S620, the random controller 120 generates a first random signal SR1, a second random signal SR2, a third random signal SR3, a fourth random signal SR4, and a fifth random signal SR5 based on the first enable signal EN1, which is at a first logic level. Then, in step S630, at least one of the disabled second functional units 142, 143, 144, and 145 is randomly enabled using the second random signal SR2, SR3, SR4, and SR5. According to an embodiment of the present invention, the random controller 120 can update the random values ​​of the first random signal SR1, SR2, SR3, SR4, and SR5 at predetermined intervals, wherein the predetermined interval is an integer multiple of the period of the system clock signal SCLK.

[0128] This invention proposes an encryption device and method that randomly enables functional units that are not currently performing operations by using a clock gating unit and random number generation, thereby disrupting the power trace of the encryption device. Furthermore, the encryption device and method proposed in this invention are very simple and can be implemented without requiring a background in cryptography. In addition, when it is desired to increase the power trace of the encryption device, the original functional units can be divided into more and smaller hardware modules, and each module can be inserted with a clock gating unit, easily increasing the complexity of the power trace. Therefore, overall, the encryption device and method proposed in this invention can achieve a greater possibility of power traces at a relatively low cost, thereby improving encryption security.

[0129] While the embodiments and advantages of this disclosure have been disclosed above, it should be understood that any person skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of the specification. Any person skilled in the art can understand, from the disclosure of some embodiments of this disclosure, current or future developed processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to some embodiments of this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claim claims and embodiments.

Claims

1. An encryption device, characterized in that, include: A controller for generating a first enable signal and a second enable signal; A random controller, wherein when at least one of the first enable signal and the second enable signal is a first logic level, the random controller generates a first random signal and a second random signal; A first functional unit performs a corresponding operation based on the first enable signal and the first random signal; and A second functional unit performs corresponding operations based on the second enable signal and the second random signal; When the first functional unit is enabled according to the first enable signal, the second functional unit is randomly enabled according to the second random signal, thereby disrupting the power trace of the encryption device.

2. The encryption device as described in claim 1, characterized in that, Including: A first clock gating unit generates a first internal clock signal based on the first enable signal, the first random signal, and a system clock signal, wherein the first functional unit further performs corresponding operations based on the first internal clock signal; and A second clock gating unit generates a second internal clock signal based on the second enable signal, the second random signal, and the system clock signal, wherein the second functional unit further performs corresponding operations based on the second internal clock signal.

3. The encryption device as described in claim 2, characterized in that, Including: A third clock gating unit generates a third internal clock signal based on a third enable signal, a third random signal, and the system clock signal; and A third functional unit performs corresponding operations according to the third internal clock signal, wherein the controller is further configured to generate the third enable signal, and when at least one of the first enable signal, the second enable signal and the third enable signal is at the first logic level, the random controller generates the first random signal, the second random signal and the third random signal.

4. The encryption device as described in claim 3, characterized in that, include: When the first enable signal is at the first logic level, the first functional unit performs a corresponding operation to enable it, and the random controller generates the first random signal, the second random signal, and the third random signal, so that the second functional unit and the third functional unit are randomly enabled according to the second random signal and the third random signal, respectively, to disrupt the power trace of the encryption device.

5. The encryption device as described in claim 3, characterized in that, One of the first clock gating unit, the second clock gating unit, and the third clock gating unit includes: An OR gate that receives an enable signal and a random signal to generate a logic signal; and An AND gate outputs the system clock signal as an internal clock signal based on the logic signal.

6. The encryption device as described in claim 3, characterized in that, The random controller includes: A random number controller determines whether any one of the first enable signal, the second enable signal, and the third enable signal is at the first logic level, wherein when any one of the first enable signal, the second enable signal, and the third enable signal is at the first logic level, the random number controller issues a decision signal; and A random number generator generates a first random number, a second random number, and a third random number based on the decision signal and the system clock signal.

7. The encryption device as described in claim 6, characterized in that, The random number generator regenerates the first random number, the second random number, and the third random number at a predetermined time, wherein the predetermined time is an integer multiple of the period of the system clock signal.

8. An encryption method applicable to an encryption device, characterized in that, The encryption device includes a first functional unit, a second functional unit, and a third functional unit, wherein the encryption method includes: A first enable signal is generated to enable the first functional unit, wherein the first enable signal is a first logic level; Based on the first enable signal at the first logic level, a first random signal, a second random signal, and a third random signal are generated; and By using the second random signal, a second functional unit is randomly enabled, and by using the third random signal, a third functional unit is randomly enabled, thereby disrupting the power trace of the encryption device.

9. The encryption method as described in claim 8, characterized in that, The encryption device further includes a first clock gating unit and a second clock gating unit, wherein the encryption method further includes: The first clock gating unit generates a first internal clock signal based on the first enable signal, the first random signal, and a system clock signal. The first functional unit is enabled using the first internal clock signal; The second clock gating unit generates a second internal clock signal based on a second enable signal, a second random signal, and the system clock signal; and The second functional unit is enabled using the second internal clock signal.

10. The encryption method as described in claim 9, characterized in that, The encryption device further includes a third functional unit and a third clock gating unit, wherein the encryption method further includes: A third random signal is generated based on the first enable signal which is the first logic level; The third functional unit is randomly enabled using the third random signal; The third clock gating unit generates a third internal clock signal based on a third enable signal, the third random signal, and the system clock signal; and The third functional unit is enabled using the third internal clock signal.

Images