Method and program for calculating vc dimension boundaries in quantum circuits

Abstract

A method for calculating a VC dimension boundary in a quantum circuit, comprising the steps of: obtaining, by a computer, a depth L of a quantum circuit, obtaining a width n of the quantum circuit, and determining a boundary of a VC dimension of the quantum circuit according to the depth L and the width n.

Description

[0001] Related applications

[0002] This application is based on U.S. Provisional Patent Application 63 / 158743, filed on March 9, 2021, the contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to a method and program for calculating the VC dimension boundary in quantum circuits. Background Technology

[0004] Machine learning models hold promise for solving complex problems across various scenarios. Overlearning has historically been a major obstacle to improving the accuracy of machine learning models. Overlearning refers to the phenomenon where, after reaching a certain level of accuracy, the model loses its ability to handle unknown data, thus reducing its learning capacity. To address this issue, previous machine learning models used regularization and temporary retirement to impose restrictions on learning and prevent overlearning. Therefore, in classical computer machine learning, overlearning has become a bottleneck for improving model accuracy.

[0005] On the other hand, while quantum computers have disclosed properties that utilize quantum characteristics to suppress overlearning, theoretical verification and detailed validation have not yet been completed (e.g., non-patent literature 1). Therefore, it is impossible to determine the actual degree to which overlearning is not easily induced in quantum circuits, making them unreliable replacements for existing machine learning models.

[0006] Existing technical documents

[0007] Non-patent literature

[0008] Non-patent literature 1: Kosuke Mitarai, Makoto Negoro, Masahiro Kitagawa, Keisuke Fujii, “Quantum Circuit Learning”, Phys. Rev. A98 (2018) 032309, September 10, 2018. Summary of the Invention

[0009] Therefore, the purpose of this invention is to provide a technical solution that demonstrates that overlearning is not easily induced in quantum circuits.

[0010] One aspect of the present invention relates to a method for calculating the VC dimension boundary in a quantum circuit, comprising: obtaining the depth L of the quantum circuit by a computer, obtaining the width n of the quantum circuit, and determining the VC dimension boundary of the quantum circuit based on the depth L and the width n.

[0011] Invention Effects

[0012] According to the present invention, a technical solution can be provided to demonstrate that overlearning is not easily induced in quantum circuits. Attached Figure Description

[0013] Figure 1 This is a diagram illustrating an example of a quantum learning circuit according to this embodiment.

[0014] Figure 2 This is a diagram illustrating the light cone constraint of the tensor network of the HEA quantum circuit in this embodiment.

[0015] Figure 3 This is a diagram representing the boundary of the VC dimension in the quantum circuit of this embodiment.

[0016] Figure 4 This is an example of the upper limit of the VC dimension (d*) for the depth of the circuit in this implementation. VC ), KL performance probability (D*) KL A graph of saturation.

[0017] Figure 5 This example implementation considers the upper limit (d*) of the VC dimension for circuit depth under the condition of light cone constraint. VC ), KL performance probability (D*) KL A graph of saturation.

[0018] Figure 6 This is an example of the upper limit d* of the VC dimension for the depth of the circuit in this embodiment. VC KL performance probability D* KL A graph showing the relationship between training error, testing error, and generalization error.

[0019] Figure 7 This is a diagram showing a schematic structure of an information processing device 100 that incorporates a quantum circuit according to an embodiment of the present invention. Detailed Implementation

[0020] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0021] (Application of quantum circuits in machine learning algorithms)

[0022] As a subroutine of a classical machine learning algorithm, quantum circuits are used. One of the problems in classical machine learning is overlearning. One cause of overlearning is the complexity of the model. In classical machine learning, overlearning is prevented by limiting the model's expressiveness through methods such as regularization. On the other hand, in quantum machine learning using quantum circuits, although the property of suppressing overlearning by utilizing quantum properties has been disclosed, theoretical verification and detailed validation have not yet been achieved.

[0023] In this embodiment, the effects of the number of qubits (width of the quantum circuit) and the number of computational steps (depth of the quantum circuit) on overlearning were verified, particularly regarding the common quantum circuits used in most quantum algorithms. The depth of the quantum circuit corresponds to the number of layers in a neural network in classical machine learning.

[0024] The validation results confirm that the expressiveness of the learning model saturates at a certain value when the depth of the quantum circuit is increased. The higher the expressiveness of the model, the lower the generalization performance. In other words, expressiveness saturation means that even if the circuit parameters (depth and width) are further increased, the model no longer becomes more complex and does not lead to overlearning.

[0025] (VC dimension of quantum circuits)

[0026] In this embodiment, to quantify the likelihood of overlearning in the quantum circuit's learning model, the upper limit of the VC (Vapnik-Chervonenkis) dimension in the quantum circuit is quantified. The VC dimension is an indicator of the complexity of the learning model, used to numerically represent the maximum number of data points that the learning model can completely classify in classification problems. For example, in two-dimensional space, a linear classifier can classify up to 3 data points, so the VC dimension of a linear classifier in two-dimensional space is "3". It is known that a large VC dimension can easily lead to overlearning. In this embodiment, the VC dimension is calculated based on the quantum circuit's depth L and width n.

[0027] (Learning about circuits)

[0028] Figure 1 This is a diagram illustrating an example of the quantum learning circuit of this embodiment. In the diagram, (a) represents the portion where the input vector x is encoded as a rotation angle for a qubit. Specifically, the input vector x (x∈[-1,1]) has feature dimension d. d Each of the qubits is encoded one by one through the Ry gate (12) and the Rz gate (13) according to the feature dimension shown in the following equation.

[0029] [Mathematical Expression 1]

[0030]

[0031] When the number of qubits n is greater than the feature dimension d (e.g., ... Figure 1 As shown in (d), in the case of n=6 qubits and d=2 feature dimensions, encoding is performed repeatedly. In this case, the i-th qubit pairs with x... i mod d Encode the input state ψ. Thus, the input state ψ in (x)(14) is represented by the following formula.

[0032] [Mathematical Expression 2]

[0033]

[0034] θ i，in =arcsin(x) i ).

[0035]

[0036] {φ i，in θ i，in |i = 0, ..., d-1}

[0037] Figure (b) shows a portion of the learning circuit (variational circuit). The learning circuit alternately and repeatedly performs single-qubit rotation gate U(θ)(15) with variational parameter θ and unlearned entangled gate U. ent (16). The rotating gate layer is represented as shown in the first line below. Furthermore, the variational circuit obtained by combining the rotating gate layer and the entangled gate layer can be represented by the formula in the second line below.

[0038] [Mathematical Expression 3]

[0039]

[0040]

[0041] Furthermore, in this embodiment, the entanglement gate layer U ent (16) As shown in example (c) in the figure, the quantum circuit of Hardware Efficient Ansatz (HEA) obtained by coupling the two nearest qubits with periodic boundary conditions (PBC) is represented as follows.

[0042] [Mathematical Expression 4]

[0043]

[0044] Using the output state ψ obtained through the circuit described above out (x)(17), calculate the expected value Z according to the following formula.

[0045] [Mathematical Expression 5]

[0046]

[0047]

[0048] Using the calculated expected value Z, classification is performed using the following learning model.

[0049] [Mathematical Expression 6]

[0050]

[0051] (Calculation of the VC dimension boundary of HEA quantum circuit)

[0052] The following describes the method for calculating the boundary of the VC dimension of the HEA quantum circuit in this embodiment. First, the upper limit of the VC dimension of a quantum circuit with a one-dimensional feature space and an input consisting only of Ry gates will be explained. Specifically, it is calculated by a computer performing the following calculation steps.

[0053] (Step 1)

[0054] First, assume a shallow quantum circuit where the number of qubits (width) is n and the layer depth is L, satisfying L+1 < n. Here, in the case of an L-layer circuit, only L+1 qubits participate, independent of the number of qubits n. This is based on the locality and singleton property of HEA quantum circuits; specifically, it is based on... Figure 2 The limitations of the light cone (LC) tensor network shown are illustrated. In the HEA quantum circuit where the entanglement gates are short-range control Z-gates (CZ gates), all 1-qubit gates are canceled out by uniformity in the region not covered by the light cone. Furthermore, all CZ gates are canceled out on the outer side of the light cone. Based on these properties, in an L-layer circuit, only L+1 qubits participate in the computation, independent of the number of qubits.

[0055] (Step 2)

[0056] Under the above assumptions, the density matrix of the effective input states can be obtained as follows.

[0057] [Mathematical Expression 7]

[0058]

[0059] (Step 3)

[0060] By calculation, d is derived. VC ≤2(L+1)+1 (or <z0>(The self-evident zero matrix).

[0061] (Step 4)

[0062] Furthermore, when considering deeper quantum circuits, since it also depends on n, d can be obtained. VC ≤2min(n, L+1)+1. This boundary is the boundary for the case of short-range 2-qubit entanglement gates. Furthermore, assuming the data is one-dimensional, the input encoding gate must be the same Ry(θ) for all qubits. in (x)). Furthermore, the gate U containing parameters IOC (θ q，l The value is arbitrary. Furthermore, when the boundary condition is an open boundary condition (OBC), the value for a periodic boundary condition is d. VC ≤2min(n, 2L+1)+1. Furthermore, in the case of long-distance qubit entanglement gates, only d can be obtained. VC ≤2n+1.

[0063] The following describes the calculation process for the VC dimension when the feature space is high-dimensional. Specifically, it can be calculated by a computer performing the following calculation process (steps).

[0064] (Step 1)

[0065] First, assume the following (1) to (4).

[0066] (1) The dimension of the feature space is d. For simplicity, let n ≥ d and n mod d = 0.

[0067] (2) The input gate is set to Ry only. In each qubit, such as x0, ..., x... d-1 x0, ..., x d-1 ...that way, only one feature x i Encoded as Ry(θ) in (x i )).

[0068] (3) Their respective characteristics are encoded into the same number of qubits (n / d).

[0069] (4) The following function f( <Z i > is defined as the threshold. f( <Z i >) is <Z i The linear associativity of >, γ i It is a real number.

[0070] [Mathematical Expression 8]

[0071]

[0072] (Step 2)

[0073] Under the above assumptions, the function f is a real trigonometric polynomial of dimension d, so the maximum degree of each dimension is (n / d), and the maximum number of linearly independent vectors is (2(n / d)+1). d .

[0074] (Step 3)

[0075] Based on the above, the upper limit of the VC dimension is calculated to be d. VC ≤(2(n / d)+1) d .

[0076] (Step 4)

[0077] Furthermore, the calculation takes into account the upper limit of the light cone constraint. Specifically, under the assumption of iterative encoding, the density matrix can be obtained as follows.

[0078] [Mathematical Expression 9]

[0079]

[0080] (Step 5)

[0081] Through calculation, the following upper limit can be derived under one-dimensional periodic boundary conditions.

[0082] [Mathematical Expression 10]

[0083]

[0084] (Step 6)

[0085] Furthermore, with inputs based on Ry and Rz gates, the density matrix can be obtained as follows.

[0086] [Mathematical Expression 11]

[0087]

[0088] Therefore, we can obtain trigonometric polynomials with the same highest degree for two-dimensional variables. As a result, the upper limit in the general case is expressed by the following formula.

[0089] [Mathematical Expression 12]

[0090]

[0091] Furthermore, the upper limit for one-dimensional periodic boundary conditions is expressed by the following formula.

[0092] [Mathematical Expression 13]

[0093]

[0094] Furthermore, using calculations performed only for the Ry gate in a 1-qubit system, the lower bound of the VC dimension in the HEA quantum circuit can be obtained as 2≤d. VC Specifically, it can be calculated by a computer performing the following calculation steps 1 to 3.

[0095] (Step 1)

[0096] Choosing θ as the identity operator, with the 0th qubit of the 0th layer being Ry(θ) and all other 1-qubit quantum gates being used as the identity operators. q，l .

[0097] (Step 2)

[0098] Simplifying all the way down to the case of 0 layers and 1 qubit (L=0, n=1), the lower limit becomes 2≤dVC.

[0099] (Step 3)

[0100] In the case of d dimensions, consider the data on the first feature axis x = (x0, 0, ..., 0).

[0101] Based on the above, the boundary of the VC dimension in quantum circuits can be summarized as follows: Figure 3 That way. Figure 4 This represents the upper bound (d*) of the VC dimension used to calculate the depth of the circuit. VC The performance probability (D*) of the learning model used for the KL (Kullback-Leibler) divergence. KL The following is a graph of the saturation of the KL (Knowledge, Liability, and Potential) dimension. The upper limit of the VC dimension (d*) VC )according to Figure 3 Calculate using the formula (CZ-HEA1D PBC) shown.

[0102] Figure 4 (a) represents d* when the number of qubits n is 4, 8, or 12. VC The picture, Figure 4 (b) to (d) are comparisons of d* when n is 4, 8, and 12. VC and D* KL The image. Figure 4 In (b) to (d), for ease of comparison, D* is expressed by the following formula. KL Rescale.

[0103] [Mathematical Expression 14]

[0104]

[0105] like Figure 4 As clearly stated in (b) to (d), the rescaled D* KL The saturation method and the upper limit d* of the VC dimension VC The saturation pattern is similar. This demonstrates that the VC dimension can serve as an auxiliary measure of model complexity.

[0106] in addition, Figure 5 It will be like Figure 2 The KL performance probability D*, as shown, takes into account the light cone constraint. KL and d* VC A comparison diagram. Figure 5 Examples (a) to (c) represent the cases when the number of qubits n is 4, 8, and 12, respectively.

[0107] (Inhibition of overlearning)

[0108] Figure 6 It represents the upper bound d* of the VC dimension for the depth of quantum circuits. VC and KL's performance probability D* KL Training error, testing error, and generalization error (E) out -E in A diagram showing the relationship between . Figure 6 Examples (a) to (b) illustrate the case where the number of qubits n is 4. Figure 6 Examples (c) to (d) illustrate the case where the number of qubits n is 8. Furthermore, Figure 6 (e) indicates Figure 6 The generalization error (E) in (a) to (d) out -E in The larger the generalization error, the greater the degree of overlearning. Figure 6 Show the upper limit d* in the VC dimension VC and KL's performance probability D* KL When saturation occurs, overlearning is suppressed.

[0109] As described above, according to this embodiment, the boundary of the VC dimension of the quantum circuit can be determined based on the depth L (number of steps) and width n (number of qubits). Furthermore, it has been demonstrated that saturation through the upper limit of the VC dimension does not easily lead to overlearning in the quantum learning circuit. Therefore, it can be quantitatively stated that the quantum circuit is a model that prevents overlearning in machine learning.

[0110] (Hardware Structure)

[0111] Figure 7 This diagram illustrates a structural example of a computer system 10 equipped with the quantum circuits involved in this invention. The computer system 10 includes a classical computer 100 and a quantum computer 200. Therefore, the computer system 10 is configured as a hybrid system possessing both classical and quantum computer functions. The classical computer 100 and the quantum computer 200 can be communicatively connected via a communication network N. The communication network N is a wired or wireless communication network, such as the Internet or a LAN (Local Area Network).

[0112] The classical computer 100 executes classical programs and performs various information processing tasks. A classical program is code that describes algorithms that can be executed by the classical computer. Classical programs are written in programming languages ​​such as C. The classical computer 100 includes a storage unit 110, a processing unit 120, and a communication unit 130.

[0113] Storage unit 110 stores various types of information. Specifically, storage unit 110 stores classical programs executed by processing unit 120, information that is the object of processing by processing unit 120, the results of processing by processing unit 120, and data generated by quantum computer 200. The various types of information stored in storage unit 110 are referenced by processing unit 120 as needed.

[0114] The processing unit 120 has the function of performing various information processing. Furthermore, the processing unit 120 is able to store the processing results in the storage unit 100.

[0115] The communication unit 130 is capable of sending and receiving various types of information. The communication unit 130 can send data generated by the processing unit 120 to the quantum computer 200. Furthermore, the communication unit 130 can receive the execution results of the quantum computing algorithm of the quantum computer 200. Additionally, the communication unit 130 can store the received information in the storage unit 100.

[0116] A quantum computer 200 is a computer that performs calculations using the phenomena of quantum mechanics of matter, and can also be a quantum computer using quantum gates. A quantum computer 200 can also be constructed from any type of hardware.

[0117] The quantum computer 200 is capable of executing quantum computing algorithms based on quantum programs. A quantum program is code that describes various quantum algorithms. For example, a quantum program can be described as a quantum circuit as described in this invention. Alternatively, a quantum program can also contain a program written in a programming language, just like a classical program.

[0118] The quantum computer 200 includes a storage unit 210, a control unit 220, a quantum unit 230, and a communication unit 240. Here, the storage unit 210, the control unit 220, and the communication unit 240 may also include classical computer functions.

[0119] Storage unit 210 stores various types of information. For example, storage unit 210 stores the quantum program used by quantum unit 230 to execute quantum computing algorithms. The various types of information stored in storage unit 210 are referenced by control unit 220 as needed.

[0120] The control unit 220 can control the quantum unit 230 according to the quantum program. Specifically, the control unit 220 can enable the quantum unit 230 to execute a quantum computing algorithm based on the characteristic data corresponding to the parameters generated by the processing unit 120 and the input data.

[0121] The quantum unit 230 is the core part of the quantum computer 200 and is able to execute quantum computing algorithms under the control of the control unit 220.

[0122] The communication unit 240 has the function of sending and receiving various types of information. For example, the communication unit 240 sends the execution results of the quantum unit 230 to the classical computer 10.

[0123] Furthermore, the present invention is not limited to the embodiments described above, and can be implemented in various other ways without departing from the spirit of the invention. Therefore, the above embodiments are merely simple examples among all aspects and should not be interpreted in a limiting way.

[0124] Explanation of reference numerals in the attached figures

[0125] 11…Initial state; 12…Ry gate; 13…Rz gate; 14…Input state ψ in ;15…Single-qubit rotation gate U(θ);16…Entangled gate U ent ;17…output state ψ out ; 10… Computer system; 100… Classical computer; 110… Storage unit; 120… Processing unit; 130… Communication unit; 200… Quantum computer; 210… Storage unit; 220… Control unit; 230… Quantum unit; 240… Communication unit.

Claims

1. A method for calculating the VC dimension boundary in a quantum circuit, comprising the following steps performed by a computer: The steps to obtain the depth L of a quantum circuit; The steps for obtaining the width n of the quantum circuit; and The step of determining the boundary of the VC dimension of the quantum circuit based on the depth L and the width n. When the dimension of the feature space is set to d, The VC dimension d VC The boundary is determined by the following equation (1): 。 2. A method for calculating the VC dimension boundary in a quantum circuit, comprising the following steps performed by a computer: The steps to obtain the depth L of a quantum circuit; The steps for obtaining the width n of the quantum circuit; and The step of determining the boundary of the VC dimension of the quantum circuit based on the depth L and the width n. The quantum circuit is a HEA quantum circuit. When the dimension of the feature space is set to d, When the periodic boundary condition of the quantum circuit is one-dimensional, The VC dimension d VC The boundary is determined by the following equation (2): 。 3. The method for calculating the VC dimension boundary in a quantum circuit according to claim 1 or 2, wherein, The depth L is the number of computation steps, and the width n is the number of qubits.

4. The method for calculating the VC dimension boundary in a quantum circuit according to claim 1 or 2, wherein, The calculation method includes calculating based on the determined VC dimension d. VC The step of obtaining the upper limit of the generalization error of learning in the quantum circuit.

5. A program product comprising a program that causes a computer to execute: The steps to obtain the depth L of a quantum circuit; The steps for obtaining the width n of the quantum circuit; and The step of determining the boundary of the VC dimension of the quantum circuit based on the depth L and the width n. When the dimension of the feature space is set to d, The VC dimension d VC The boundary is determined by the following equation (1): 。 6. A program product comprising a program that causes a computer to execute: The steps to obtain the depth L of a quantum circuit; The steps for obtaining the width n of the quantum circuit; and The step of determining the boundary of the VC dimension of the quantum circuit based on the depth L and the width n. The quantum circuit is a HEA quantum circuit. When the dimension of the feature space is set to d, When the periodic boundary condition of the quantum circuit is one-dimensional, The VC dimension d VC The boundary is determined by the following equation (2): 。

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