A 3D packaged optical transceiver assembly and method of use

Abstract

The application provides a 3D packaged optical transceiver assembly and a use method thereof, which comprises a circuit substrate, a silicon-based photoelectric chip, a peripheral electric chip and a piezoelectric ceramic sheet, the silicon-based photoelectric chip is electrically connected with the circuit substrate in a flip-chip manner, the peripheral electric chip is electrically connected with the silicon-based photoelectric chip in a flip-chip manner, and the piezoelectric ceramic sheet is arranged between the circuit substrate and the peripheral electric chip and is used for detecting the mechanical deformation degree of the circuit substrate. The application can detect the mechanical deformation degree of the circuit substrate, improves the reliability of practical application, reduces the packaging area of the optical transceiver assembly through the multiple flip-chip packaging mode, shortens the signal transmission distance between chips, overcomes the dependence of the traditional packaging process on the TSV / TGV technology, simplifies the packaging process and reduces the production cost. Meanwhile, in cooperation with multiple heat dissipation approaches, the application can also meet the application scene of high power and improve the applicable range.

Description

Technical Field

[0001] The invention relates to the field of optical communication technology, and in particular to a 3D packaged optical transceiver component and its usage method. Background Technology

[0002] The trend towards high-speed and miniaturized optical devices has led to increasingly dense packaging and shorter signal traces. Traditional wire bonding packaging is finding it increasingly difficult to reduce chip area or shorten signal line length. Flip chip packaging is an advanced packaging technology that can effectively reduce package area. The thermal performance of flip chip packaging technology is significantly superior to that of conventional wire bonding processes, and its bump connection method can greatly shorten signal trace length. It is gradually becoming the mainstream packaging technology in the future, and flip chip packaging is the inevitable choice for high-speed, highly integrated optical device packaging.

[0003] Currently, most BGA (Ball Grid Array) devices use 2D packaging, where both optical and electrical chips are flip-chip mounted onto the packaging substrate. The electrical signals are then transmitted to the module board through the packaging substrate. Some devices also use 2.5D / 3D packaging based on TSV (Through Silicon Via) or TGV (Through Glass Via). In this case, both optoelectronic and electrical chips are flip-chip mounted onto a silicon or glass adapter board, or the electrical chip is directly flip-chip mounted onto the optoelectronic chip. The signal is then conducted from the upper surface of the chip or adapter board to the lower surface using TSV / TGV technology. The signal is then flip-chip mounted onto the packaging substrate using copper pillar bumps or solder balls. Finally, the electrical signals are transmitted to the module board through the packaging substrate.

[0004] Compared to traditional wire bonding, 2D packaging offers significant improvements in both packaging density and high-frequency performance. However, it is still larger than 2.5D / 3D packaging, and the connection between the electrical and optical chips is still via conductive wires on the substrate, resulting in relatively high high-frequency losses. Furthermore, existing 2.5D / 3D packaging technologies rely on TSV / TGV technology, which places higher demands on packaging technology, makes raw material manufacturing more difficult, and increases costs. Multilayer flip-chip packaging also places higher demands on the packaging process, and it cannot detect the mechanical deformation of the externally sensitive optoelectronic chip during application, among other issues.

[0005] Therefore, overcoming the shortcomings of existing technologies and solving the aforementioned technical problems is a difficult problem to be solved in this technical field. Summary of the Invention

[0006] In view of the shortcomings of the prior art, the primary technical problem to be solved by the present invention is:

[0007] This invention provides a solution to the problem that existing 2.5D / 3D packaging methods cannot detect the mechanical deformation of optoelectronic chips during use.

[0008] In view of the shortcomings of the prior art, the technical problem to be further solved by the present invention is:

[0009] This invention provides a solution to the problems of existing 2.5D / 3D packaging methods, such as reliance on TSV / TGV technology, higher requirements for packaging technology, greater difficulty in raw material production, higher costs, higher requirements for packaging processes in multilayer flip-chip packaging, and unsatisfactory heat dissipation.

[0010] To solve the above-mentioned technical problems, the present invention adopts the following technical solution to achieve the above-mentioned technical objectives:

[0011] In a first aspect, the present invention provides a 3D-packaged optical transceiver component, comprising:

[0012] Circuit board 100;

[0013] A silicon-based optoelectronic chip 200 is provided on the bottom surface of the silicon-based optoelectronic chip 200, and the silicon-based optoelectronic chip 200 is electrically connected to the circuit board 100 in a flip-chip manner through the first set of flip-chip bumps 201.

[0014] The peripheral electrical chip 300 has a second set of flip bumps 301 on its bottom surface. The peripheral electrical chip 300 is electrically connected to the silicon-based optoelectronic chip 200 in a flip-chip manner through the second set of flip bumps 301.

[0015] A piezoelectric ceramic sheet 400 is disposed between the circuit board 100 and the peripheral electrical chip 300 and is in contact with the circuit board 100. The piezoelectric ceramic sheet 400 is used to detect the degree of mechanical deformation of the circuit board 100.

[0016] The silicon-based optoelectronic chip 200 has an optical port on one side, which is used to receive and transmit light signals.

[0017] Preferably, the circuit board 100 is provided with a rectangular groove 101, the silicon-based optoelectronic chip 200 is located on the upper part of the rectangular groove 101, and the peripheral electrical chip 300 is disposed inside the rectangular groove 101; wherein, the area of ​​the silicon-based optoelectronic chip 200 is larger than the area of ​​the rectangular groove 101.

[0018] Preferably, the rectangular groove 101 has an opening on one side, and the opening is in the same direction as the optical port of the silicon-based optoelectronic chip 200.

[0019] Preferably, the device further includes thermally conductive adhesive 500 and a heat dissipation pad 600. The thermally conductive adhesive 500 is located on the top surface of the silicon-based optoelectronic chip 200 and the top surface of the peripheral electrical chip 300, respectively, and the heat dissipation pad 600 is located inside the rectangular groove 101. The thermally conductive adhesive 500 is in contact with the top surface of the silicon-based optoelectronic chip 200 and the top surface of the peripheral electrical chip 300, respectively, and the heat dissipation pad 600 is in contact with the circuit board 100.

[0020] Preferably, the peripheral electrical chip 300 includes a driving electrical chip 302 and an amplifying electrical chip 303, wherein the driving electrical chip 302 and the amplifying electrical chip 303 are located on the same horizontal plane; wherein the driving electrical chip 302 is used for modulation of optical signals, and the amplifying electrical chip 303 is used for amplification of electrical signals.

[0021] Preferably, the piezoelectric ceramic sheet 400 includes a first piezoelectric ceramic sheet 401 and a second piezoelectric ceramic sheet 402, wherein the first piezoelectric ceramic sheet 401 and the second piezoelectric ceramic sheet 402 are located on the same horizontal plane.

[0022] Preferably, it further includes a filler adhesive 700, which fills the spaces between the first group of inverted bumps 201 and the second group of inverted bumps 301 respectively; wherein the first group of inverted bumps 201 and the second group of inverted bumps 301 are respectively arranged in an array.

[0023] Preferably, it also includes a cover plate 800, which together with the circuit board 100 forms an accommodating space; wherein the silicon-based optoelectronic chip 200, the peripheral electrical chip 300 and the piezoelectric ceramic sheet 400 are respectively located inside the accommodating space.

[0024] Preferably, it further includes a coupling structure 900, which is connected to the optical port of the silicon-based optoelectronic chip 200 for communication; wherein the coupling structure 900 extends out from the cover plate 800.

[0025] Secondly, the present invention provides a method of using a 3D-packaged optical transceiver component, comprising:

[0026] The peripheral electrical chip 300 is electrically connected to the silicon-based optoelectronic chip 200 in a flip-chip manner through the second set of flip-chip bumps 301;

[0027] The piezoelectric ceramic sheet 400 is disposed between the circuit board 100 and the peripheral electrical chip 300 and is in contact with the circuit board 100.

[0028] The silicon-based optoelectronic chip 200 is electrically connected to the circuit board 100 in a flip-chip manner through the first set of flip-chip bumps 201;

[0029] The degree of mechanical deformation of the circuit board 100 is detected by the piezoelectric ceramic sheet 400.

[0030] Compared with the prior art, the above technical solutions adopted in this invention have the following beneficial effects:

[0031] This invention utilizes a piezoelectric ceramic sheet to detect any minute mechanical deformation of the circuit board during use in real time. When the degree of mechanical deformation exceeds a preset value (i.e., when it will have a significant impact on the normal operation of the silicon-based optoelectronic chip), an alarm signal is generated to facilitate timely handling measures. The invention also features high detection sensitivity and good results.

[0032] Furthermore, this invention overcomes the dependence of traditional 2.5D / 3D packaging methods on TSV / TGV technology through a novel 3D packaging method, simplifying the manufacturing process and reducing production costs.

[0033] Furthermore, by combining thermally conductive adhesive and heat dissipation pads, this invention provides multiple heat dissipation pathways for optical transceiver components, ensuring their heat dissipation efficiency.

[0034] Overall, this invention can indirectly detect the degree of mechanical deformation of silicon-based optoelectronic chips by detecting the mechanical deformation of the circuit board, thereby improving the reliability of practical applications. Through multiple flip-chip packaging methods, the packaging area of ​​optical transceiver components is reduced, the signal transmission distance between chips is shortened, the dependence of traditional packaging processes on TSV / TGV technology is overcome, the packaging process is simplified, and the production cost is reduced. At the same time, with multiple heat dissipation methods, it can also meet the needs of high-power application scenarios and expand the scope of application. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a cross-sectional view of a 3D-packaged optical transceiver assembly provided in Embodiment 1 of the present invention;

[0037] Figure 2This is a schematic diagram of a silicon-based optoelectronic chip structure for a 3D-packaged optical transceiver component provided in Embodiment 1 of the present invention;

[0038] Figure 3 This is a schematic diagram of the peripheral electrical chip structure of a 3D packaged optical transceiver component provided in Embodiment 1 of the present invention;

[0039] Figure 4 This is a schematic diagram of the circuit board structure of a 3D packaged optical transceiver component provided in Embodiment 1 of the present invention;

[0040] Figure 5 This is a schematic diagram of the assembly structure of a 3D packaged optical transceiver component provided in Embodiment 1 of the present invention;

[0041] Figure 6 This is a cross-sectional view of a 3D-packaged optical transceiver assembly provided in Embodiment 2 of the present invention;

[0042] Figure 7 This is an exploded view of a 3D-packaged optical transceiver component provided in Embodiment 2 of the present invention;

[0043] Figure 8 This is a flowchart illustrating a method for using a 3D-packaged optical transceiver component, as provided in Embodiment 3 of the present invention.

[0044] In the accompanying drawings, the same reference numerals are used to denote the same parts or structures, wherein:

[0045] 100 - Circuit board; 101 - Rectangular groove; 102 - BGA solder ball; 200 - Silicon-based optoelectronic chip; 201 - First set of flip-chip bumps; 300 - Peripheral electrical chip; 301 - Second set of flip-chip bumps; 302 - Driver electrical chip; 303 - Amplifier electrical chip; 400 - Piezoelectric ceramic sheet; 401 - First piezoelectric ceramic sheet; 402 - Second piezoelectric ceramic sheet; 500 - Thermally conductive adhesive; 600 - Heat dissipation pad; 700 - Filler adhesive; 800 - Cover plate; 801 - Upper cover plate; 802 - Lower cover plate; 900 - Coupling structure. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] In the description of this invention, the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and do not require that this invention must be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0048] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0049] Example 1:

[0050] To address the issue that existing 2.5D / 3D packaging methods cannot detect the mechanical deformation of silicon-based optoelectronic chips during use, this embodiment 1 provides a 3D-packaged optical transceiver component, such as... Figures 1-3 As shown, the circuit includes: a circuit board 100, a silicon-based optoelectronic chip 200, a peripheral electrical chip 300, and a piezoelectric ceramic sheet 400. The silicon-based optoelectronic chip 200 has a first set of flip-chip bumps 201 on its bottom surface, and the silicon-based optoelectronic chip 200 is electrically connected to the circuit board 100 in a flip-chip manner through the first set of flip-chip bumps 201. The peripheral electrical chip 300 has a second set of flip-chip bumps 301 on its bottom surface, and the peripheral electrical chip 300 is electrically connected to the silicon-based optoelectronic chip 200 in a flip-chip manner through the second set of flip-chip bumps 301. The piezoelectric ceramic sheet 400 is disposed between the circuit board 100 and the peripheral electrical chip 300 and abuts against the circuit board 100. The piezoelectric ceramic sheet 400 is used to detect the degree of mechanical deformation of the circuit board 100. The silicon-based optoelectronic chip 200 has a light port on one side for receiving and transmitting light signals. Due to the thermal expansion and contraction characteristic of the circuit board 100, it undergoes a certain degree of mechanical deformation when the temperature reaches a certain threshold. This mechanical deformation is directly transmitted to the piezoelectric ceramic sheet 400, thereby indirectly detecting the stress experienced by the silicon-based optoelectronic chip 200 during use. This mechanical deformation, when acting on the silicon-based optoelectronic chip 200, will affect the transmission quality and efficiency of the photoelectric signal to a certain extent, especially in COC (Chip-on-Chip). In scenarios involving on-chip (chip-on-chip) or PLC (Planar Lightwave Circuit), such mechanical deformation will directly cause the performance of the silicon-based optoelectronic chip 200 to fail. This mechanical deformation is almost impossible to detect effectively by the human eye. Therefore, in this embodiment, the application of the piezoelectric ceramic sheet 400 ensures the transmission quality and efficiency of the optoelectronic signal of the silicon-based optoelectronic chip 200.

[0051] In this embodiment, the circuit board 100 can be made of ceramic, glass, organic substrate, or PCB board. Preferably, the circuit board 100 uses an organic substrate, whose coefficient of thermal expansion is much smaller than that of a conventional PCB board. The circuit board 100 includes upper and lower surfaces. Both the upper and lower surfaces of the circuit board 100 have exposed solder joints (pads). The size and distribution of the exposed solder joints are set according to the requirements of the actual application. To reduce the overall assembly volume and obtain suitable assembly space, on the upper surface of the circuit board 100, as one implementation method, such as... Figure 4 As shown, the circuit board 100 has a rectangular groove 101. The silicon-based optoelectronic chip 200 is located on the upper part of the rectangular groove 101, and the peripheral electrical chip 300 is disposed inside the rectangular groove 101. The area of ​​the silicon-based optoelectronic chip 200 is larger than the area of ​​the rectangular groove 101. To facilitate the mounting and alignment of the silicon-based optoelectronic chip 200 and the peripheral electrical chip 300, the rectangular groove 101 is preferably located on the center line of the upper surface of the circuit board 100, and the bottom of the rectangular groove 101 needs to be machined flat. The area and depth of the rectangular groove 101 are set according to the actual application requirements. In actual application, the area of ​​the silicon-based optoelectronic chip 200 is larger than the area of ​​the rectangular groove 101. When the silicon-based optoelectronic chip 200 completely covers the rectangular groove 101, the portion of the silicon-based optoelectronic chip 200 extending beyond the rectangular groove 101 can be electrically connected to the solder joints (pads) on the upper surface of the circuit board 100 in a flip-chip manner through the first set of flip-chip bumps 201. At the same time, the area of ​​the peripheral electrical chip 300 is smaller than the area of ​​the rectangular groove 101, so that the peripheral electrical chip 300 can be disposed inside the rectangular groove 101. To facilitate the subsequent installation of the circuit board 100, on the lower surface of the circuit board 100, as one implementation method, such as... Figure 4 The circuit board 100 has uniformly distributed BGA solder joints on its lower surface. The BGA solder joints are used for mounting the BGA solder balls 102. The BGA solder balls 102 are preferably lead-free solder balls. The diameter of the BGA solder balls 102 can be different specifications depending on the actual application requirements.

[0052] To facilitate the coupling and light-finding of the silicon-based optoelectronic chip 200, as one preferred method, such as Figure 4 As shown, an opening is provided on one side of the rectangular groove 101. The opening is located in the same direction as the optical port of the silicon-based optoelectronic chip 200. In this embodiment, the depth of the opening is preferably the same as the depth of the rectangular groove 101. The shape of the opening is not specifically required; it can be rectangular, square, or trapezoidal. Figure 4As shown, the trapezoidal shape is presented, and the length of the upper base of the trapezoid is equal to the length of the opening side of the rectangular groove 101. The reason for placing the opening and the optical port of the silicon-based optoelectronic chip 200 in the same direction is to make the coupling and light-finding process of the silicon-based optoelectronic chip 200 more convenient and efficient.

[0053] In this embodiment, the silicon-based optoelectronic chip 200 is a flip chip. The bottom surface of the silicon-based optoelectronic chip 200 is roughly divided into two regions, including an epitaxial region and an intermediate region, as shown below. Figure 3 As shown, the epitaxial region of the bottom surface of the silicon-based optoelectronic chip 200 is provided with a first set of flip-chip bumps 201, and the middle region of the bottom surface of the silicon-based optoelectronic chip 200 is provided with flip-chip solder joints for electrical connection with the peripheral electrical chip 300. The flip-chip solder joints in the middle region of the bottom surface of the silicon-based optoelectronic chip 200 correspond to the second set of flip-chip bumps 301 on the peripheral electrical chip 300 according to the actual application requirements. In the implementation process, the first set of flip-chip bumps 201 on the epitaxial region of the bottom surface of the silicon-based optoelectronic chip 200 surrounds the middle region of the bottom surface of the silicon-based optoelectronic chip 200 on three sides. Specifically, the first set of flip-chip bumps 201 is pre-designed and processed, and the first set of flip-chip bumps 201 is not limited to... Copper pillars, gold balls, solder, etc. The first set of flip bumps 201 corresponds to the solder joints (pads) on the upper surface of the circuit board 100. During assembly, the first set of flip bumps 201 is aligned with the solder joints (pads) on the upper surface of the circuit board 100 by hot pressing. The silicon-based optoelectronic chip 200 is electrically connected to the circuit board 100 in a flip-chip manner through the first set of flip bumps 201 located on the epitaxial region of the bottom surface of the silicon-based optoelectronic chip 200. After flipping, the middle region of the bottom surface of the silicon-based optoelectronic chip 200 faces the rectangular groove 101.

[0054] In this embodiment, the design concept and installation method of the peripheral electrical chip 300 are basically the same as those of the silicon-based optoelectronic chip 200. The peripheral electrical chip 300 is also a flip chip, and the bottom surface of the peripheral electrical chip 300 is roughly divided into two regions, including an epitaxial region and an intermediate region. The epitaxial region of the bottom surface of the peripheral electrical chip 300 is provided with a second set of flip bumps 301. In the implementation process, the second set of flip bumps 301 located in the epitaxial region of the bottom surface of the peripheral electrical chip 300 surrounds the peripheral electrical chip 300 on all four sides. In the middle area of ​​the bottom surface, the second set of flip-chip bumps 301 are also pre-designed and processed. The second set of flip-chip bumps 301 are not limited to copper pillars, gold balls, solder, etc. The second set of flip-chip bumps 301 correspond to the flip-chip solder joints in the middle area of ​​the bottom surface of the silicon-based optoelectronic chip 200 according to the actual application requirements. During assembly, the second set of flip-chip bumps 301 are aligned with the flip-chip solder joints in the middle area of ​​the bottom surface of the silicon-based optoelectronic chip 200. The peripheral electrical chip 300 is electrically connected to the silicon-based optoelectronic chip 200 in a flip-chip manner through the second set of flip-chip bumps 301 located in the outer extension area of ​​the bottom surface of the peripheral electrical chip 300. During the assembly process, the top surface of the peripheral electrical chip 300 faces the rectangular groove 101.

[0055] As a preferred implementation, the first set of flip-chip bumps 201 and the second set of flip-chip bumps 301 are respectively arranged in an array. This array-arranged flip-chip bump design improves integration and reduces application area. To ensure the reliability of the flip-chip process between the silicon-based optoelectronic chip 200 and the peripheral electrical chip 300, and to guarantee the welding strength of the flip-chip method, such as... Figure 1 As shown, it also includes a filler adhesive 700, which fills the spaces between the first set of flip bumps 201 and the second set of flip bumps 301. In this embodiment, the filler adhesive 700 can be a single-component or two-component resin potting compound, commonly including polyurethane, epoxy resin, and silicone rubber. It can achieve the effects of bonding, fixing, encapsulation, and sealing. Its application principle is to use capillary action to allow the adhesive to flow in rapidly and fill the gap between the first set of flip bumps 201 and the second set of flip bumps 301, filling a large area of ​​the gap between the first set of flip bumps 201 and the second set of flip bumps 301, thereby achieving the purpose of reinforcing the silicon-based optoelectronic chip 200 and the peripheral electrical chip 300. The minimum space range of its capillary flow is 8-12 μm, preferably 10 μm. The filler adhesive 700 can be cured after heating, with a curing temperature of 80℃-150℃, thereby increasing the welding strength of the silicon-based optoelectronic chip 200 and the peripheral electrical chip 300.

[0056] In this embodiment, the piezoelectric ceramic sheet 400, also known as a buzzer, is an electronic sound-emitting element. A piezoelectric ceramic dielectric material is placed between two copper circular electrodes. Piezoelectric ceramics possess the information function of converting mechanical energy into electrical energy—the piezoelectric effect. The voltage is proportional to the degree of mechanical deformation. Besides piezoelectricity, piezoelectric ceramics also exhibit dielectric properties and elasticity. Under external mechanical stress, the piezoelectric ceramic causes relative displacement of the internal positive and negative charge centers, resulting in polarization and the appearance of bound charges of opposite signs on the surfaces at both ends of the material—the piezoelectric effect. It has sensitive characteristics; when an external force causing mechanical deformation is applied to the two copper circular electrodes, an electrical signal is generated. The piezoelectric ceramic sheet 400 is disposed between the circuit board 100 and the peripheral electrical chip 300 and is connected to the circuit board 100. In this contact connection, when the circuit board 100 is subjected to external force or deforms due to thermal expansion and contraction, this deformation is directly transmitted to the piezoelectric ceramic sheet 400. In this embodiment, the piezoelectric ceramic sheet 400 preferably uses a piezoelectric ceramic sheet with a high resonant frequency. By acquiring and utilizing the electrical signal generated by the mechanical deformation, the degree of mechanical deformation of the circuit board 100 can be detected and monitored, thereby indirectly detecting the stress borne by the silicon-based optoelectronic chip 200 during use. When the degree of mechanical deformation exceeds a preset value, an alarm reminder signal is generated so that timely processing measures can be taken. Moreover, the detection sensitivity is high and the effect is good.

[0057] To further address the heat dissipation issue, such as Figure 1As shown, it also includes thermally conductive adhesive 500 and a heat dissipation pad 600. The thermally conductive adhesive 500 is located on the top surface of the silicon-based optoelectronic chip 200 and the top surface of the peripheral electrical chip 300, respectively. The heat dissipation pad 600 is located inside the rectangular groove 101. The thermally conductive adhesive 500 is in contact with the top surface of the silicon-based optoelectronic chip 200 and the top surface of the peripheral electrical chip 300, respectively. The heat dissipation pad 600 is in contact with the circuit board 100. In this embodiment, the thermally conductive adhesive 500 can be thermally conductive silicone grease or a thermally conductive pad, etc. Preferably, the material is soft and has good elasticity and plasticity. The thickness of the thermally conductive adhesive 500 is moderate, considering the silicon-based optoelectronic chip 200 and the peripheral electrical chip 300. To address the heat generation issue, in practical applications, multiple thermally conductive adhesives 500 can be used. These adhesives 500 are located on the top surface of the silicon-based optoelectronic chip 200 and the top surface of the peripheral electrical chip 300, respectively. The thermally conductive adhesives 500 are in contact with both the top surface of the silicon-based optoelectronic chip 200 and the top surface of the peripheral electrical chip 300. Specifically, regarding the heat dissipation path of the silicon-based optoelectronic chip 200, one of the thermally conductive adhesives 500 (located on the top surface of the silicon-based optoelectronic chip 200 and parallel to it) is in close contact with the top surface of the silicon-based optoelectronic chip 200. Simultaneously, this thermally conductive adhesive 500 is also in close contact with the cover plate 800 (upper cover plate 801, e.g., Figure 7 As shown, the silicon-based optoelectronic chip 200 is in close contact with the cover plate 800 (upper cover plate 801, as shown). Therefore, the silicon-based optoelectronic chip 200 has two heat dissipation paths. One heat dissipation path is through the cover plate 800 (upper cover plate 801, as shown). Figure 7 (As shown) Another heat dissipation path is through the circuit substrate 100, thereby ensuring the heat dissipation of the silicon-based optoelectronic chip 200; in the same way, regarding the heat dissipation path of the peripheral electrical chip 300, one of the thermally conductive adhesives 500 (located on the top surface of the peripheral electrical chip 300 and parallel to the top surface of the peripheral electrical chip 300) is in close contact with the top surface of the peripheral electrical chip 300, while at the same time, the other thermally conductive adhesive 500 (located on the right side of the peripheral electrical chip 300 and perpendicular to the top surface of the peripheral electrical chip 300) is also in close contact with the cover plate 800 (lower cover plate 802, as shown) respectively. Figure 7 As shown, the silicon-based optoelectronic chip 200 is in close contact with the heat dissipation pad 600. The silicon-based optoelectronic chip 200 also has two heat dissipation pathways: one is through the cover plate 800 (lower cover plate 802, as shown) and the heat dissipation pad 600. Figure 7 (As shown) Another heat dissipation path is through the circuit board 100, thereby ensuring the heat dissipation of the peripheral electrical chip 300; in this embodiment, the upper and lower surfaces of the heat dissipation pad 600 are flat, have a certain thickness, and have good thermal conductivity. Its material is not limited to metal or ceramic. The heat dissipation pad 600 is located inside the rectangular groove 101, such as... Figure 7As shown, the heat dissipation pad 600 has openings for mounting the piezoelectric ceramic sheet 400. The number of openings corresponds to the number of piezoelectric ceramic sheets 400, and the size of the openings corresponds to the size of the piezoelectric ceramic sheets 400 (it can be slightly smaller than the piezoelectric ceramic sheets 400). The heat dissipation pad 600 is in contact with the circuit board 100. It should be noted that this embodiment uses one heat dissipation pad 600 as an example. In actual applications, multiple heat dissipation pads 600 can be used. For example, the heat dissipation pad 600 can also be placed on the top surface of the silicon-based optoelectronic chip 200 and connected to the cover plate 800. The ultimate purpose of the heat dissipation pad 600 is to solve the heat generation problem of the silicon-based optoelectronic chip 200 and the peripheral electrical chip 300. In this embodiment, the heat generation problem of the silicon-based optoelectronic chip 200 and the peripheral electrical chip 300 is solved through the combined application of the thermally conductive adhesive 500 and the heat dissipation pad 600. With multiple heat dissipation methods, the overall heat dissipation effect is improved, and it can also meet the needs of high-power application scenarios, thus expanding the practical application range.

[0058] Considering that both the silicon-based optoelectronic chip 200 and the peripheral electrical chip 300 are valuable electronic components, in addition to the aforementioned influence of temperature on the silicon-based optoelectronic chip 200 and the peripheral electrical chip 300, the humidity and dust of the external environment will also affect the operation of the silicon-based optoelectronic chip 200 and the peripheral electrical chip 300 to varying degrees. To protect the packaging structure from the influence of the external environment, in this embodiment, as... Figure 1 and Figures 5-6 As shown, it also includes a cover plate 800, which, together with the circuit board 100, forms an accommodating space. The silicon-based optoelectronic chip 200, the peripheral electrical chip 300, and the piezoelectric ceramic sheet 400 are respectively located within the accommodating space. In this embodiment, the cover plate 800 needs to have good thermal conductivity to dissipate heat from the silicon-based optoelectronic chip 200 and the peripheral electrical chip 300. The cover plate 800 is not limited to various geometric shapes, as long as it can fit well with the circuit board 100 and form an accommodating space, while ensuring that the silicon-based optoelectronic chip 200, the peripheral electrical chip 300, and the piezoelectric ceramic sheet 400 are respectively located within the accommodating space. In specific implementation, to simplify the manufacturing process and facilitate installation, such as... Figure 7The cover plate 800 includes an upper cover plate 801 and a lower cover plate 802. The upper cover plate 801 and the lower cover plate 802 need to be machined and fixed together. In a preferred embodiment, the upper cover plate 801, as the main part, is aligned with the edge of the circuit board 100, and the lower cover plate 802 is aligned with the edge of the opening of the rectangular groove 101. The lower cover plate 802 just seals the opening of the rectangular groove 101. In this embodiment, the cover plate 800 effectively prevents the humidity and dust of the external environment from affecting the working condition of the silicon-based optoelectronic chip 200 and the peripheral electrical chip 300.

[0059] In order to achieve the reception and transmission of optical signals, such as Figures 5-7 As shown, it also includes a coupling structure 900, which is communicatively connected to the optical port of the silicon-based optoelectronic chip 200. The coupling structure 900 extends through the cover plate 800 and includes at least one optical channel, not limited to FA (Fiber Array) and PLC, etc. In this embodiment, the optical channel has three paths, including two optical inlets and one optical outlet. Specifically, to further enhance sealing, a through hole matching the size of the coupling structure 900 is provided on the cover plate 800, and the through hole is preferably located on the upper cover plate 801.

[0060] In Example 1, the silicon-based optoelectronic chip 200, the peripheral electrical chip 300, and the piezoelectric ceramic sheet 400 are each one, and the silicon-based optoelectronic chip 200 is flip-chip packaged with the circuit board 100, the peripheral electrical chip 300 is flip-chip packaged with the silicon-based optoelectronic chip 200, the piezoelectric ceramic sheet 400 is used to detect the degree of mechanical deformation of the circuit board 100, and the coupling structure 900 includes two light inlets and one light outlet for illustration. However, the actual application situation is much more complex.

[0061] Example 2:

[0062] In Example 1, taking the flip-chip configuration of a silicon-based optoelectronic chip 200 and a peripheral electrical chip 300 as an example, after the silicon-based optoelectronic chip 200 and the peripheral electrical chip 300 are flip-chip configured, a piezoelectric ceramic sheet 400 is placed between the circuit substrate 100 and the peripheral electrical chip 300 to detect the degree of mechanical deformation of the silicon-based optoelectronic chip 200. However, in actual applications, the functions and integration levels of the peripheral electrical chips 300 are not entirely the same. Depending on the function or integration level of the peripheral electrical chips 300, the number of peripheral electrical chips 300 usually includes one or more. In this case, because the area of ​​the circuit substrate 100 is relatively large, it is difficult to accurately detect the overall degree of mechanical deformation of the circuit substrate 100 using only one piezoelectric ceramic sheet 400.

[0063] Based on the same technical concept as in Embodiment 1, in this embodiment, as Figure 6 As shown, the peripheral electrical chip 300 includes a driving electrical chip 302 and an amplifying electrical chip 303, which are located on the same horizontal plane. The driving electrical chip 302 is used for optical signal modulation, and the amplifying electrical chip 303 is used for electrical signal amplification. Specifically, the driving electrical chip 302 is a power driving chip. In practice, the driving electrical chip 302 modulates the high-frequency electrical signal from the external control circuit onto the light wave for transmission. Therefore, its input terminal is connected to the high-frequency input terminal of the silicon-based optoelectronic chip 200, and its output terminal is connected to the modulator electrode of the silicon-based optoelectronic chip 200. The amplifying electrical chip 303 is specifically a transimpedance amplifying chip. For modulation of optical signals, specifically, the amplifying chip 303 amplifies the received electrical signal before outputting it. Therefore, its input terminal is connected to the detector output of the receiving end of the silicon-based optoelectronic chip 200, and its output terminal is connected to the high-frequency output terminal of the silicon-based optoelectronic chip 200 via a high-frequency trace. To ensure a more reliable flip-chip process between the driving chip 302 and the amplifying chip 303 and the silicon-based optoelectronic chip 200, and to facilitate subsequent detection of mechanical deformation of the circuit board 100 using multiple piezoelectric ceramic sheets 400, as a preferred implementation, the driving chip 302 and the amplifying chip 303 are located on the same horizontal plane. Correspondingly, to achieve detection of mechanical deformation of the circuit board 100, such as... Figure 6As shown, the piezoelectric ceramic sheet 400 includes a first piezoelectric ceramic sheet 401 and a second piezoelectric ceramic sheet 402, which are located on the same horizontal plane. In a specific implementation, the first piezoelectric ceramic sheet 401 is disposed between the circuit board 100 and the driving chip 302, and the second piezoelectric ceramic sheet 402 is disposed between the circuit board 100 and the amplifying chip 303. To make the detection structure more accurate and reliable, the first piezoelectric ceramic sheet 401 and the second piezoelectric ceramic sheet 402 are also located on the same horizontal plane.

[0064] In Embodiment 2, when there is more than one peripheral electrical chip 300, the mechanical deformation of the silicon-based optoelectronic chip 200 is detected by separately arranged first piezoelectric ceramic sheet 401 and second piezoelectric ceramic sheet 402. By comprehensively considering the detection results of the first piezoelectric ceramic sheet 401 and the second piezoelectric ceramic sheet 402, the mechanical deformation of the entire circuit board 100 is detected.

[0065] Example 3:

[0066] Based on the same technical concept as Embodiments 1-2, Embodiment 5 provides a method for using a 3D-packaged optical transceiver component, such as... Figure 8 As shown, the method includes:

[0067] Step S101: The peripheral electrical chip 300 is electrically connected to the silicon-based optoelectronic chip 200 in a flip-chip manner through the second set of flip-chip bumps 301.

[0068] The peripheral electrical chip 300 is a flip chip, including an epitaxial region and a middle region. The epitaxial region on the bottom surface of the peripheral electrical chip 300 is provided with a second set of flip bumps 301. The second set of flip bumps 301 on the epitaxial region on the bottom surface of the peripheral electrical chip 300 surrounds the middle region on the bottom surface of the peripheral electrical chip 300. The second set of flip bumps 301 corresponds to the flip solder joints in the middle region on the bottom surface of the silicon-based optoelectronic chip 200 according to the actual application requirements. The second set of flip bumps 301 is not limited to copper pillars, gold balls, solder, etc. The second set of flip bumps 301 is distributed in an array. During assembly, the second set of flip bumps 301 is aligned with the flip solder joints in the middle region on the bottom surface of the silicon-based optoelectronic chip 200 by hot pressing.

[0069] In step S102, the piezoelectric ceramic sheet 400 is disposed between the circuit board 100 and the peripheral electrical chip 300 and is in contact with the circuit board 100.

[0070] The circuit board 100 can be made of ceramic, glass, organic substrate or PCB board. The circuit board 100 is preferably made of organic substrate. The circuit board 100 includes upper and lower surfaces. Both the upper and lower surfaces of the circuit board 100 are provided with exposed solder joints (pads). The size and distribution of the exposed solder joints are set according to the actual application requirements. The circuit board 100 is provided with a rectangular groove 101. The silicon-based optoelectronic chip 200 is located in the upper part of the rectangular groove 101, and the peripheral electrical chip 300 is located inside the rectangular groove 101.

[0071] Step S103: The silicon-based optoelectronic chip 200 is electrically connected to the circuit board 100 in a flip-chip manner through the first set of flip-chip bumps 201.

[0072] The silicon-based optoelectronic chip 200 is a flip chip, including an epitaxial region and an intermediate region. The epitaxial region on the bottom surface of the silicon-based optoelectronic chip 200 is provided with a first set of flip bumps 201. The first set of flip bumps 201 on the epitaxial region on the bottom surface of the silicon-based optoelectronic chip 200 surrounds the intermediate region on the bottom surface of the silicon-based optoelectronic chip 200 on three sides. The flip solder joints in the intermediate region on the bottom surface of the silicon-based optoelectronic chip 200 correspond to the second set of flip bumps 301 on the peripheral chip 300 according to the actual application requirements. The first set of flip bumps 201 is not limited to copper pillars, gold balls, solder, etc. The first set of flip bumps 201 is distributed in an array. During assembly, the first set of flip bumps 201 is aligned with the solder joints (pads) on the upper surface of the circuit board 100 by hot pressing.

[0073] Step S104: The degree of mechanical deformation of the circuit board 100 is detected by the piezoelectric ceramic sheet 400.

[0074] Preferably, the piezoelectric ceramic sheet 400 uses a piezoelectric ceramic sheet with a high resonant frequency. The piezoelectric ceramic sheet 400 can convert mechanical energy and electrical energy into each other. By acquiring and utilizing the electrical signals generated by the mechanical deformation, the degree of mechanical deformation of the circuit board 100 can be detected and monitored. This allows for real-time detection of the stress of the silicon-based optoelectronic chip 200 during use, and generates an alarm signal when the degree of mechanical deformation exceeds a preset value, so that timely handling measures can be taken.

[0075] It should be noted that the 3D-packaged optical transceiver component provided by this invention is described using a silicon-based optoelectronic chip 200 as the main embodiment. The silicon-based optoelectronic chip 200 integrates both transmitting and receiving functions, and is used in conjunction with one peripheral electrical chip 300 and one piezoelectric ceramic sheet 400 (e.g., embodiment 1) or two peripheral electrical chips 300 and two piezoelectric ceramic sheets 400 (e.g., embodiment 2). In practical applications, on the one hand, there are also single-function optical receiving components and optical transmitting components; on the other hand, the silicon-based optoelectronic chip 200 can also... The peripheral electrical chip 300 and the piezoelectric ceramic sheet 400 can be one or more, respectively. However, as a basic independent unit, it includes at least one silicon-based optoelectronic chip 200, one peripheral electrical chip 300, and one piezoelectric ceramic sheet 400. Under the technical guidance of the relevant embodiments and accompanying drawings of this invention, it can also meet the application needs of single-function optical receiving components and optical transmitting components, and can also realize the combined application of any number of silicon-based optoelectronic chips 200, peripheral electrical chips 300, and piezoelectric ceramic sheets 400.

[0076] In summary, this invention can detect the degree of mechanical deformation of silicon-based optoelectronic chips, improving the reliability of practical applications. Through multiple flip-chip packaging methods, it reduces the packaging area of ​​optical transceiver components, shortens the signal transmission distance between chips, overcomes the dependence of traditional packaging processes on TSV / TGV technology, simplifies the packaging process, and reduces production costs. At the same time, with multiple heat dissipation methods, it can also meet the needs of high-power application scenarios, expanding the scope of applications.

[0077] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A 3D-packaged optical transceiver component, characterized in that, include: Circuit board (100); A silicon-based optoelectronic chip (200) has a first set of flip bumps (201) on its bottom surface. The silicon-based optoelectronic chip (200) is electrically connected to the circuit board (100) in a flip-chip manner through the first set of flip bumps (201). The peripheral electrical chip (300) has a second set of flip bumps (301) on its bottom surface. The peripheral electrical chip (300) is electrically connected to the silicon-based optoelectronic chip (200) in a flip-chip manner through the second set of flip bumps (301). A piezoelectric ceramic sheet (400) is disposed between the circuit board (100) and the peripheral electrical chip (300) and is in contact with the circuit board (100). The piezoelectric ceramic sheet (400) is used to detect the degree of mechanical deformation of the circuit board (100). The silicon-based optoelectronic chip (200) has an optical port on one side, which is used to receive and transmit light signals; It also includes thermally conductive adhesive (500) and heat dissipation pad (600), the heat dissipation pad (600) having openings for mounting the piezoelectric ceramic sheet (400), the number of openings corresponding to the number of piezoelectric ceramic sheets (400), the size of the openings corresponding to the size of the piezoelectric ceramic sheet (400), the heat dissipation pad (600) being in contact with the circuit board (100); The circuit board (100) is provided with a rectangular groove (101), which is located on the center line of the upper surface of the circuit board (100), and the heat dissipation pad (600) is located inside the rectangular groove (101).

2. The 3D-packaged optical transceiver component according to claim 1, characterized in that, The silicon-based optoelectronic chip (200) is located on the upper part of the rectangular groove (101), and the peripheral electrical chip (300) is disposed inside the rectangular groove (101); wherein, the area of ​​the silicon-based optoelectronic chip (200) is larger than the area of ​​the rectangular groove (101).

3. The 3D-packaged optical transceiver component according to claim 2, characterized in that, An opening is provided on one side of the rectangular groove (101), and the opening is in the same direction as the optical port of the silicon-based optoelectronic chip (200).

4. The 3D-packaged optical transceiver component according to claim 3, characterized in that, The thermally conductive adhesive (500) is in contact with the top surface of the silicon-based optoelectronic chip (200) and the top surface of the peripheral electrical chip (300), respectively, and the heat dissipation pad (600) is in contact with the circuit board (100).

5. The 3D-packaged optical transceiver component according to any one of claims 1-4, characterized in that, The peripheral electrical chip (300) includes a driving electrical chip (302) and an amplifying electrical chip (303), which are located on the same horizontal plane; wherein, the driving electrical chip (302) is used for the modulation of optical signals, and the amplifying electrical chip (303) is used for the amplification of electrical signals.

6. The 3D-packaged optical transceiver component according to claim 5, characterized in that, The piezoelectric ceramic sheet (400) includes a first piezoelectric ceramic sheet (401) and a second piezoelectric ceramic sheet (402), wherein the first piezoelectric ceramic sheet (401) and the second piezoelectric ceramic sheet (402) are located on the same horizontal plane.

7. The 3D-packaged optical transceiver component according to claim 5, characterized in that, It also includes filler adhesive (700), which fills the spaces between the first set of inverted bumps (201) and the second set of inverted bumps (301); wherein the first set of inverted bumps (201) and the second set of inverted bumps (301) are arranged in an array.

8. The 3D-packaged optical transceiver component according to claim 7, characterized in that, It also includes a cover plate (800), which together with the circuit board (100) forms a receiving space; wherein the silicon-based optoelectronic chip (200), the peripheral electrical chip (300) and the piezoelectric ceramic sheet (400) are respectively located inside the receiving space.

9. The 3D-packaged optical transceiver component according to claim 8, characterized in that, It also includes a coupling structure (900) that is connected to the optical port of the silicon-based optoelectronic chip (200) for communication; wherein the coupling structure (900) extends out from the cover plate (800).

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