Light emitting drive circuit and display panel

Abstract

The application relates to the field of display panels, and provides a light-emitting driving circuit and a display panel, wherein the light-emitting driving circuit comprises multiple-stage light-emitting driving units and a timing controller, each stage of the light-emitting driving units comprises 12 transistors, 3 capacitors, a signal input end, a signal output end and two timing control ends, and the timing controller comprises a first timing control signal line and a second timing control signal line. The light-emitting driving circuit and the display panel of the application provide a new light-emitting driving unit circuit, so that each node is independently controlled, mutual restraint is avoided, the output stability of the light-emitting driving unit is improved, display abnormalities of the display panel are reduced, and the service life of the display panel is improved. In addition, the application reduces the use of the timing control signal line, so that the frame width of the display panel is reduced.

Description

Technical Field

[0001] This invention relates to the field of display panels, and more specifically, to a light-emitting driving circuit and a display panel. Background Technology

[0002] The display panel includes a pixel array and a scanning drive circuit and a light-emitting drive circuit for controlling the pixel array. The display panel adopts a line-by-line scanning display method. The scanning drive circuit is used to generate scanning signals to turn on each row of pixels in sequence, while the light-emitting drive circuit is used to provide data signals to a row of pixels when it is turned on to realize the display of the pixels.

[0003] The light-emitting driving circuit includes multiple cascaded light-emitting driving units. Each stage of the light-emitting driving unit is typically composed of several transistors and capacitors. By inputting a clock signal and a start pulse signal to the light-emitting driving unit, a level signal is output at the output terminal.

[0004] Chinese patent CN105741749A provides a light-emitting driving circuit, such as Figure 1 and 2 As shown, Figure 1 A circuit diagram of a prior art light-emitting driving unit is shown; Figure 2 Show Figure 1 The waveform diagram shown is displayed when the light-emitting driving unit is working. Figure 3 Show Figure 2 A schematic diagram showing the conduction state of the light-emitting driving unit in Step 5. Here, "H" represents a high-level signal, and "L" represents a low-level signal. (Reference) Figure 2 and 3 When the circuit transitions from Step 5 to Step 6, the ideal circuit operation is as follows: the second node N2, due to the low potential of the second timing control signal c2, turns on the eighth transistor M8, writing a low potential to the signal input terminal in, which in turn turns on the third transistor M3. Meanwhile, the first node N1, written with a high potential of the first power supply VDD, turns off the seventh transistor M7. However, if this circuit is used for a long time, or if manufacturing process errors cause changes in the transistor aspect ratio, resulting in a shift in the transistor's threshold voltage Vth, or if the timing control signal impedance is too high, the potential written to the second node N2 may be too high when the circuit enters Step 6. This could prevent the third transistor M3 from effectively turning on, prevent the first node N1 from reaching the high potential of the first power supply VDD, and prevent the seventh transistor M7 from turning off, keeping it on. Because the seventh transistor M7 is turned on, the second node N2 writes a high potential of the first power supply VDD, resulting in an even higher potential for the second node N2. Ultimately, the signal output terminal out outputs an undesirable low potential, causing the panel to display an abnormal image.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] In view of this, the present invention provides a light-emitting driving circuit and a display panel.

[0007] One aspect of the present invention provides a light-emitting driving circuit, including a multi-stage light-emitting driving unit, wherein the light-emitting driving unit includes a control module, a reset module and an output setting module;

[0008] The control module includes:

[0009] A fourth transistor, the second terminal of which is connected to the first node;

[0010] The fifth transistor has its first terminal connected to the third node, its second terminal connected to the first timing control terminal, and its gate connected to the signal input terminal.

[0011] The sixth transistor has its first terminal connected to the third node, its second terminal connected to the second power supply, and its gate connected to the first timing control terminal.

[0012] The reset module includes:

[0013] The third transistor has a first terminal connected to a first power supply, a second terminal connected to the first node, and a gate connected to a second node;

[0014] The seventh transistor, the second terminal of which is connected to the second node;

[0015] The twelfth transistor has its first terminal connected to the first power supply and its second terminal connected to the first terminal of the seventh transistor.

[0016] The output setting module includes:

[0017] The first transistor has a first terminal connected to the first power supply, a second terminal connected to the signal output terminal, and a gate connected to the first node;

[0018] The second transistor has its first terminal connected to the signal output terminal, its second terminal connected to the second power supply, and its gate connected to the fourth node;

[0019] The eighth transistor has its first terminal connected to the signal input terminal, its second terminal connected to the second node, and its gate connected to the second timing control terminal.

[0020] The ninth transistor has its second terminal connected to the fourth node and its gate connected to the second power supply;

[0021] The eleventh transistor has its first terminal connected to the second power supply, its second terminal connected to the first terminal of the fourth transistor, and its gate connected to the second timing control terminal.

[0022] In some embodiments,

[0023] The output setting module also includes:

[0024] The tenth transistor has its first terminal connected to the second node, its second terminal connected to the first terminal of the ninth transistor, and its gate connected to the second power supply.

[0025] In some embodiments,

[0026] The gate of the fourth transistor is connected to the third node;

[0027] The gate of the seventh transistor is connected to the first node;

[0028] The gate of the twelfth transistor is connected to the first timing control terminal.

[0029] In some embodiments,

[0030] The control module also includes:

[0031] The tenth transistor has its first terminal connected to the gate of the fourth transistor, its second terminal connected to the third node, and its gate connected to the second power supply.

[0032] In some embodiments,

[0033] The gate of the seventh transistor is connected to the third node;

[0034] The first terminal of the ninth transistor is connected to the second node;

[0035] The gate of the twelfth transistor is connected to the second timing control.

[0036] In some embodiments, the light-emitting driving unit further includes:

[0037] A first capacitor, wherein the first terminal of the first capacitor is connected to the first timing control terminal, and the second terminal is connected to the fourth node;

[0038] The second capacitor has its first terminal connected to the first terminal of the fourth transistor and its second terminal connected to the gate of the fourth transistor.

[0039] The third capacitor has its first terminal connected to the first power source and its second terminal connected to the first node.

[0040] In some embodiments, a timing controller is further included, the timing controller including a first timing control signal line and a second timing control signal line.

[0041] In some embodiments, the first timing control signal line is used to output a first timing control signal; the second timing control signal line is used to output a second timing control signal.

[0042] In some embodiments, the first timing control signal and the second timing control signal are square wave signals with the same output frequency and a phase difference of 180°.

[0043] In some embodiments, the previous stage light-emitting driving unit outputs a light-emitting driving signal to the next stage light-emitting driving unit, and the last stage light-emitting driving unit outputs a light-emitting driving signal.

[0044] In some embodiments, in the odd-numbered light-emitting driving units, the first timing control terminal is connected to the first timing control signal line, and the second timing control terminal is connected to the second timing control signal line.

[0045] In some embodiments, in the even-numbered light-emitting driving units, the first timing control terminal is connected to the second timing control signal line, and the second timing control terminal is connected to the first timing control signal line.

[0046] In some embodiments, the first transistor to the eleventh transistor are all P-type MOS transistors.

[0047] Another aspect of the present invention provides a display panel, characterized in that it includes the light-emitting driving circuit described in any one of the preceding claims.

[0048] The beneficial effects of this invention compared to the prior art include at least the following:

[0049] The light-emitting driving circuit and display panel of the present invention provide a new light-emitting driving unit circuit, which enables the first node N1, the second node N2 and the third node N3 to be controlled independently, avoiding mutual interference among the three, thereby improving the output stability of the light-emitting driving unit, reducing display abnormalities of the display panel and extending the service life of the display panel; in addition, the present invention reduces the number of components in the light-emitting driving circuit by reducing the use of timing control signal lines, thereby reducing the bezel width of the display panel and adapting to the trend of narrow bezels in display panels.

[0050] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0051] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0052] Figure 1 A circuit diagram of a prior art light-emitting driving unit is shown;

[0053] Figure 2 Show Figure 1 The waveform diagram shown is displayed when the light-emitting driving unit is working.

[0054] Figure 3 Show Figure 2 A schematic diagram of the conduction state of the light-emitting driving unit in Step 5 of the middle stage;

[0055] Figure 4 A schematic diagram of the display panel of the present invention is shown;

[0056] Figure 5 A schematic diagram of the cascaded light-emitting driving circuit of the present invention is shown;

[0057] Figure 6 A circuit diagram of the light-emitting driving unit according to a first embodiment of the present invention is shown;

[0058] Figure 7 Show Figure 6 The waveform diagram shown is displayed when the light-emitting driving unit is working.

[0059] Figure 8 Show Figure 7 A schematic diagram of the conduction state of the light-emitting driving unit in Step 11 of the middle stage;

[0060] Figure 9 Show Figure 7 A schematic diagram of the conduction state of the light-emitting driving unit in Step 12 of the middle stage;

[0061] Figure 10 Show Figure 7 A schematic diagram of the conduction state of the light-emitting driving unit in Step 13 of the middle stage;

[0062] Figure 11 Show Figure 7 A schematic diagram of the conduction state of the light-emitting driving unit in Step 14 of the middle stage;

[0063] Figure 12 Show Figure 7 A schematic diagram of the conduction state of the light-emitting driving unit in Step 15 of the middle stage;

[0064] Figure 13 Show Figure 7 A schematic diagram of the conduction state of the light-emitting driving unit in Step 16 of the middle stage;

[0065] Figure 14 Show Figure 7 A schematic diagram of the conduction state of the light-emitting driving unit in Step 17 of the middle stage;

[0066] Figure 15 A circuit diagram of the light-emitting driving unit according to a second embodiment of the present invention is shown;

[0067] Figure 16 Show Figure 15 The waveform diagram shown is displayed when the light-emitting driving unit is working.

[0068] Figure 17 Show Figure 16 A schematic diagram of the conduction state of the light-emitting driving unit in Step 21.

[0069] Figure 18 Show Figure 16 A schematic diagram of the conduction state of the light-emitting driving unit in Step 22;

[0070] Figure 19 Show Figure 16 A schematic diagram of the conduction state of the light-emitting driving unit in Step 23.

[0071] Figure 20 Show Figure 16 A schematic diagram of the conduction state of the light-emitting driving unit in Step 24.

[0072] Figure 21 Show Figure 16 A schematic diagram of the conduction state of the light-emitting driving unit in Step 25.

[0073] Figure 22 Show Figure 16 A schematic diagram of the conduction state of the light-emitting driving unit in Step 26.

[0074] Figure 23 Show Figure 16 A schematic diagram of the conduction state of the light-emitting driving unit in Step 27.

[0075] Figure label:

[0076] 10 Display Panel

[0077] 11 Display Area

[0078] 20. Timing Controller

[0079] 30 Light-emitting driving circuit

[0080] CKE1 First Timing Control Signal Line

[0081] CKE2 Second Timing Control Signal Line

[0082] c1 First timing control terminal

[0083] c2 Second timing control terminal

[0084] IN signal input terminal

[0085] Enout signal output terminal

[0086] M1 First Transistor

[0087] M2 Second Transistor

[0088] M3 Third Transistor

[0089] M4 fourth transistor

[0090] M5 fifth transistor

[0091] M6 sixth transistor

[0092] M7 Seventh Transistor

[0093] M8 Eighth Transistor

[0094] M9 Ninth Transistor

[0095] M10 Tenth Transistor

[0096] M11 Eleventh Transistor

[0097] M12 Twelfth Transistor

[0098] C1 First capacitor

[0099] C2, the second capacitor

[0100] C3 Third capacitor

[0101] VDD First Power Supply

[0102] VEE Second Power Supply

[0103] N1 First Node

[0104] N2 Second Node

[0105] N3 Third Node

[0106] N4 Fourth Node Detailed Implementation

[0107] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted.

[0108] The use of terms such as "first," "second," and similar terms in the specific description does not indicate any order, quantity, or importance, but is merely used to distinguish different components. Furthermore, in the description of this invention, terms such as "upper," "lower," etc., indicate orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings. These are merely for ease of description and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on the invention.

[0109] It should be noted that, unless otherwise specified, the embodiments of the present invention and the features in different embodiments can be combined with each other.

[0110] Through meticulous and in-depth research, the inventors in this case have provided a solution to the problems existing in the prior art. Figure 4 A schematic diagram of the display panel of the present invention is shown; Figure 5 A schematic diagram of the cascaded light-emitting driving circuit of the present invention is shown; Figure 6 A circuit diagram of the light-emitting driving unit according to a first embodiment of the present invention is shown; Figure 15 A circuit diagram of the light-emitting driving unit according to a second embodiment of the present invention is shown. (As shown) Figure 4 , 5 As shown in Figures 6 and 15, this invention discloses a light-emitting driving circuit 30 and a display panel 10. The light-emitting driving circuit 30 includes a multi-stage light-emitting driving unit and a timing controller 20. Each stage of the light-emitting driving unit includes a control module, a reset module, and an output setting module, specifically including 12 transistors, 3 capacitors, a signal input terminal, a signal output terminal, and two timing control terminals. The timing controller 20 includes two timing control signal lines. Furthermore, the light-emitting driving unit includes three nodes. This invention's light-emitting driving circuit and display panel, by providing a new light-emitting driving unit circuit, allow the first node N1, the second node N2, and the third node N3 to be independently controlled, avoiding mutual interference among them, thereby improving the output stability of the light-emitting driving unit, reducing display abnormalities of the display panel, and extending the lifespan of the display panel. In addition, this invention reduces the number of components in the light-emitting driving circuit by reducing the use of timing control signal lines, thereby reducing the bezel width of the display panel and adapting to the trend of narrow bezels in display panels.

[0111] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0112] like Figure 4 As shown, the present invention provides a display panel 10, which includes a display area 11 and a non-display area. A light-emitting driving circuit 30, a data driver, and a scan driving circuit are located in the non-display area of ​​the display panel 10. The display area 11 includes an array of light-emitting pixels and pixel circuits. The light-emitting pixels emit light under the combined action of the light-emitting driving circuit 30, the data driver, the scan driving circuit, and the pixel circuits.

[0113] like Figure 4 and 5 As shown, the present invention also provides a light-emitting driving circuit 30, which includes a multi-level light-emitting driving unit and a timing controller 20.

[0114] In some embodiments, the light-emitting driving unit includes 12 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Enout, a first timing control terminal c1, and a second timing control terminal c2. Each stage of the light-emitting driving unit outputs a light-emitting driving signal, which is input to a row of pixel circuits in the display area 11 of the display panel 10 to drive that row of pixels to emit light. The previous stage of the light-emitting driving unit also outputs its light-emitting driving signal to the signal input terminal IN of the next stage of the light-emitting driving unit as a start signal. Since the last stage of the light-emitting driving unit does not have a next stage, the light-emitting driving signal it outputs is only input to the pixel circuit of that row.

[0115] Specifically, Figure 5Taking a cascaded array of five LED driving units as an example, the first-stage LED driving unit E1 receives a start pulse signal STE at its input terminal IN1. The first-stage LED driving unit E1 outputs an LED driving signal at its output terminal E1out, which serves as the input signal for the second-stage LED driving unit E2. The output terminal E1out of the first-stage LED driving unit E1 is connected to the input terminal IN2 of the second-stage LED driving unit E2. The second-stage LED driving unit E2 outputs an LED driving signal at its output terminal E2out, which serves as the input signal for the third-stage LED driving unit E3. The output terminal E2out of the second-stage LED driving unit E2 is connected to the input terminal IN3 of the third-stage LED driving unit E3. The third-stage LED driving unit E3 outputs an LED driving signal at its output terminal E3out, which serves as the input signal for the fourth-stage LED driving unit E4. The output terminal E3out of the third-stage LED driving unit E3 is connected to the input terminal IN4 of the fourth-stage LED driving unit E4. The signal output terminal E4out of the fourth-stage light-emitting driving unit E4 outputs a light-emitting driving signal as the input signal of the fifth-stage light-emitting driving unit E5. The signal output terminal E4out of the fourth-stage light-emitting driving unit E4 is connected to the signal input terminal IN5 of the fifth-stage light-emitting driving unit E5... Subsequent light-emitting driving units repeat this process to form the light-emitting driving circuit 30.

[0116] Figure 7 Show Figure 6 The waveform diagram shown is displayed when the light-emitting driving unit is working. Figure 16 Show Figure 15 The waveform diagram shown illustrates the operation of the light-emitting driving unit. In some embodiments, such as... Figure 5 , 7 As shown in Figure 15, the timing controller 20 includes a first timing control signal line CKE1 and a second timing control signal line CKE2. The first timing control signal line CKE1 is used to output a first timing control signal. The second timing control signal line CKE2 is used to output a second timing control signal. The first and second timing control signals are square wave signals with the same output frequency and a phase difference of 180°.

[0117] In some embodiments, such as Figure 5As shown, in the first-stage light-emitting driving unit, the first timing control terminal c1 is connected to the first timing control signal line CKE1 to receive the first timing control signal. The second timing control terminal c2 is connected to the second timing control signal line CKE2 to receive the second timing control signal. In the second-stage light-emitting driving unit, the first timing control terminal c1 is connected to the second timing control signal line CKE2 to receive the second timing control signal. The second timing control terminal c2 is connected to the first timing control signal line CKE1 to receive the first timing control signal. In the third-stage light-emitting driving unit, the first timing control terminal c1 is connected to the first timing control signal line CKE1 to receive the first timing control signal. The second timing control terminal c2 is connected to the second timing control signal line CKE2 to receive the second timing control signal. In the fourth-stage light-emitting driving unit, the first timing control terminal c1 is connected to the second timing control signal line CKE2 to receive the second timing control signal. The second timing control terminal c2 is connected to the first timing control signal line CKE1 and is used to receive the first timing control signal. In the fifth-level light-emitting driving unit, the first timing control terminal c1 is connected to the first timing control signal line CKE1 and is used to receive the first timing control signal. The second timing control terminal c2 is connected to the second timing control signal line CKE2 and is used to receive the second timing control signal... and so on, resulting in: In odd-numbered-level light-emitting driving units, the first timing control terminal c1 is connected to the first timing control signal line CKE1 and is used to receive the first timing control signal, and the second timing control terminal c2 is connected to the second timing control signal line CKE2 and is used to receive the second timing control signal. In even-numbered-level light-emitting driving units, the first timing control terminal c1 is connected to the second timing control signal line CKE2 and is used to receive the second timing control signal, and the second timing control terminal c2 is connected to the first timing control signal line CKE1 and is used to receive the first timing control signal.

[0118] In the first embodiment of the present invention, reference is made to... Figures 4 to 14 , Figure 8 Show Figure 7 A schematic diagram of the conduction state of the light-emitting driving unit in Step 11 of the middle stage; Figure 9 Show Figure 7 A schematic diagram of the conduction state of the light-emitting driving unit in Step 12 of the middle stage; Figure 10 Show Figure 7 A schematic diagram of the conduction state of the light-emitting driving unit in Step 13 of the middle stage; Figure 11 Show Figure 7 A schematic diagram of the conduction state of the light-emitting driving unit in Step 14 of the middle stage; Figure 12 Show Figure 7 A schematic diagram of the conduction state of the light-emitting driving unit in Step 15 of the middle stage; Figure 13 Show Figure 7A schematic diagram of the conduction state of the light-emitting driving unit in Step 16 of the middle stage; Figure 14 Show Figure 7 A schematic diagram of the conduction state of the light-emitting driving unit in Step 17.

[0119] In this embodiment, as Figure 6 As shown, each stage of the light-emitting driving unit includes a control module, a reset module, and an output setting module. Specifically, the light-emitting driving unit includes 12 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Enout, a first timing control terminal c1, and a second timing control terminal c2.

[0120] In this embodiment, as Figure 6 As shown, the control module includes: a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The second terminal of the fourth transistor M4 is connected to the first node N1. The first terminal of the fifth transistor M5 is connected to the third node N3, the second terminal is connected to the first timing control terminal c1, and the gate is connected to the signal input terminal IN. The first terminal of the sixth transistor M6 is connected to the third node N3, the second terminal is connected to the second power supply VEE, and the gate is connected to the first timing control terminal c1.

[0121] In this embodiment, as Figure 6 As shown, the reset module includes: a third transistor M3, a seventh transistor M7, and a twelfth transistor M12. The first terminal of the third transistor M3 is connected to the first power supply VDD, the second terminal is connected to the first node N1, and the gate is connected to the second node N2. The second terminal of the seventh transistor M7 is connected to the second node N2. The first terminal of the twelfth transistor M12 is connected to the first power supply VDD, and the second terminal is connected to the first terminal of the seventh transistor M7.

[0122] In this embodiment, as Figure 6 As shown, the output setting module includes: a first transistor M1, a second transistor M2, an eighth transistor M8, a ninth transistor M9, and an eleventh transistor M11. The first transistor M1 has its first terminal connected to the first power supply VDD, its second terminal connected to the signal output terminal Enout, and its gate connected to the first node N1. The second transistor M2 has its first terminal connected to the signal output terminal Enout, its second terminal connected to the second power supply VEE, and its gate connected to the fourth node N4. The eighth transistor M8 has its first terminal connected to the signal input terminal IN, its second terminal connected to the second node N2, and its gate connected to the second timing control terminal c2. The ninth transistor M9 has its second terminal connected to the fourth node N4, and its gate connected to the second power supply VEE. The eleventh transistor M11 has its first terminal connected to the second power supply VEE, its second terminal connected to the first terminal of the fourth transistor M4, and its gate connected to the second timing control terminal c2.

[0123] In this embodiment, as Figure 6 As shown, other embodiments of the present invention also possess the above-described features. Specifically, the output setting module of the first embodiment further includes a tenth transistor M10. The first terminal of the tenth transistor M10 is connected to the second node N2, the second terminal is connected to the first terminal of the ninth transistor M9, and the gate is connected to the second power supply VEE. Furthermore, the gate of the fourth transistor M4 is connected to the third node N3. The gate of the seventh transistor M7 is connected to the first node N1. The gate of the twelfth transistor M12 is connected to the first timing control terminal c1.

[0124] In this embodiment, as Figure 6 As shown, the light-emitting driving unit further includes: a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first terminal of the first capacitor C1 is connected to the first timing control terminal C1, and the second terminal is connected to the fourth node N4. The first terminal of the second capacitor C2 is connected to the first terminal of the fourth transistor M4, and the second terminal is connected to the gate of the fourth transistor M4. The first terminal of the third capacitor C3 is connected to the first power supply VDD, and the second terminal is connected to the first node N1.

[0125] In this embodiment, the first transistor M1 to the twelfth transistor M12 are all P-type MOS transistors. The control terminal of the PMOS transistor is the gate, and its first terminal is the source and its second terminal is the drain, or vice versa. The PMOS transistor's on-state level is low, and its off-state level is high. In other embodiments, those skilled in the art will readily recognize that the light-emitting driving unit provided by this invention can be easily modified to consist entirely of N-type MOS transistors. Furthermore, the light-emitting driving unit provided by this invention can also be easily modified to use CMOS transistors, etc.

[0126] In this embodiment, refer to Figure 7 , Figure 7 The waveform diagram shown includes seven specific processes: Steps 11 to 17, and subsequent processes not shown. During these processes, the output signal of the Enout terminal of the aforementioned light-emitting driving unit completes a set-to-reset cycle. It should be noted that, for ease of understanding, a high-level signal is represented by "H" and a low-level signal by "L" in the attached diagram. The following section will further explain... Figure 7 waveform diagram and Figure 6 The circuit diagram is used to analyze the relationship between the input and output of the light-emitting driving unit in the above seven processes:

[0127] In this embodiment, refer to Figure 7 and 8In Step 11, the signal input terminal IN is high, the first timing control signal line CKE1 is low, and the second timing control signal line CKE2 is high. At this time, the second transistor M2, the third transistor M3, the fourth transistor M4, the sixth transistor M6, the ninth transistor M9, the tenth transistor M10, and the twelfth transistor M12 are turned on, while the first transistor M1, the fifth transistor M5, the seventh transistor M7, the eighth transistor M8, and the eleventh transistor M11 are turned off. Specifically, when the first timing control signal line CKE1 is low, the sixth transistor M6 and the twelfth transistor M12 are turned on, the third node N3 is written with the low potential of the second power supply VEE, and the fourth transistor M4 is turned on. Simultaneously, when the second timing control signal line CKE2 is high, the eighth transistor M8 and the eleventh transistor M11 are turned off, the second node N2 maintains the low potential of the previous moment, the second transistor M2 and the third transistor M3 are turned on, and the first node N1 is written with the high potential of the first power supply VDD because the third transistor M3 is turned on, while the first transistor M1 and the seventh transistor M7 are turned off. Therefore, the first transistor M1 is turned off, and the second transistor M2 is turned on. Finally, the signal output terminal Enout outputs a low potential of the second power supply VEE.

[0128] In this embodiment, refer to Figure 7 and 9 In Step 12, the signal input terminal IN is high, the first timing control signal line CKE1 is high, and the second timing control signal line CKE2 is low. At this time, the first transistor M1, the fourth transistor M4, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are turned on, while the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, and the twelfth transistor M12 are turned off. Specifically, the first timing control signal line CKE1 is high, the sixth transistor M6 and the twelfth transistor M12 are off, the third node N3 maintains the low potential of the previous moment, and the fourth transistor M4 is turned on. Simultaneously, the second timing control signal line CKE2 is input at a low level, turning on the eighth transistor M8 and the eleventh transistor M11. Because the eighth transistor M8 is turned on, the second node N2 receives a high potential from the signal input terminal IN, turning off the second transistor M2 and the third transistor M3. The first node N1 receives a low potential from the second power supply VEE because the fourth transistor M4 and the eleventh transistor M11 are turned on, thus turning on the first transistor M1. Therefore, the first transistor M1 is turned on, and the second transistor M2 is turned off. Finally, the signal output terminal Enout outputs a high potential from the first power supply VDD.

[0129] In this embodiment, refer to Figure 7 and 10In Step 13, the signal input terminal IN is high, the first timing control signal line CKE1 is low, and the second timing control signal line CKE2 is high. At this time, the first transistor M1, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the ninth transistor M9, the tenth transistor M10, and the twelfth transistor M12 are turned on, while the second transistor M2, the third transistor M3, the fifth transistor M5, the eighth transistor M8, and the eleventh transistor M11 are turned off. Specifically, when the first timing control signal line CKE1 is low, the sixth transistor M6 and the twelfth transistor M12 are turned on, the third node N3 is written with a low potential of the second power supply VEE, and the fourth transistor M4 is turned on. Simultaneously, the second timing control signal line CKE2 inputs a high level, turning off the eighth transistor M8 and the eleventh transistor M11. The first node N1 maintains its previous low potential, while the first transistor M1 and the seventh transistor M7 turn on. The second node N2, due to the turn-on of the seventh transistor M7 and the twelfth transistor M12, receives a high potential from the first power supply VDD, causing the second transistor M2 and the third transistor M3 to turn off. Thus, the first transistor M1 turns on, and the second transistor M2 turns off. Finally, the signal output terminal Enout outputs a high potential from the first power supply VDD.

[0130] In this embodiment, refer to Figure 7 and 11 In Step 14, the signal input terminal IN is high, the first timing control signal line CKE1 is high, and the second timing control signal line CKE2 is low. At this time, the first transistor M1, the fourth transistor M4, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are turned on, while the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, and the twelfth transistor M12 are turned off. Specifically, the first timing control signal line CKE1 is high, the sixth transistor M6 and the twelfth transistor M12 are off, the third node N3 maintains the low potential of the previous moment, and the fourth transistor M4 is on. Simultaneously, the second timing control signal line CKE2 is input at a low level, turning on the eighth transistor M8 and the eleventh transistor M11. Because the eighth transistor M8 is turned on, the second node N2 receives a high potential from the signal input terminal IN, turning off the second transistor M2 and the third transistor M3. The first node N1 receives a low potential from the second power supply VEE because the fourth transistor M4 and the eleventh transistor M11 are turned on, thus turning on the first transistor M1. Therefore, the first transistor M1 is turned on, and the second transistor M2 is turned off. Finally, the signal output terminal Enout outputs a high potential from the first power supply VDD.

[0131] In this embodiment, refer to Figure 7 and 12In Step 15, the signal input terminal IN is low, the first timing control signal line CKE1 is low, and the second timing control signal line CKE2 is high. At this time, the first transistor M1, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the ninth transistor M9, the tenth transistor M10, and the twelfth transistor M12 are turned on, while the second transistor M2, the third transistor M3, the eighth transistor M8, and the eleventh transistor M11 are turned off. Specifically, when the signal input terminal IN and the first timing control signal line CKE1 are low, the fifth transistor M5, the sixth transistor M6, and the twelfth transistor M12 are turned on. Due to the turn-on of the fifth transistor M5 and the sixth transistor M6, the third node N3 simultaneously writes a low potential to the first timing control signal line CKE1 and the second power supply VEE, and the fourth transistor M4 is turned on. Simultaneously, the second timing control signal line CKE2 inputs a high level, turning off the eighth transistor M8 and the eleventh transistor M11. The first node N1 maintains its previous low potential, while the first transistor M1 and the seventh transistor M7 turn on. The second node N2, due to the turn-on of the seventh transistor M7 and the twelfth transistor M12, receives a high potential from the first power supply VDD, causing the second transistor M2 and the third transistor M3 to turn off. Thus, the first transistor M1 turns on, and the second transistor M2 turns off. Finally, the signal output terminal Enout outputs a high potential from the first power supply VDD.

[0132] In this embodiment, refer to Figure 7 and 13 In Step 16, the signal input terminal IN is low, the first timing control signal line CKE1 is high, and the second timing control signal line CKE2 is low. At this time, the second transistor M2, the third transistor M3, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 are turned on, while the first transistor M1, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, and the twelfth transistor M12 are turned off. Specifically, when the first timing control signal line CKE1 is high, the sixth transistor M6 and the twelfth transistor M12 are turned off. The low potential at the signal input terminal IN of the third node N3 causes the fifth transistor M5 to turn on, writing a high potential to the first timing control signal line CKE1, and the fourth transistor M4 is turned off. Simultaneously, the second timing control signal line CKE2 inputs a low level, turning on the eighth transistor M8 and the eleventh transistor M11. Because the eighth transistor M8 is turned on, the second node N2 receives a low potential written to the signal input terminal IN, turning on the second transistor M2 and the third transistor M3. Because the third transistor M3 is turned on, the first node N1 receives a high potential written to the first power supply VDD, turning off the first transistor M1. Thus, the first transistor M1 turns off, and the second transistor M2 turns on. Finally, the signal output terminal Enout outputs a low potential from the second power supply VEE.

[0133] In this embodiment, refer to Figure 7 and 14 In Step 17, the signal input terminal IN is low, the first timing control signal line CKE1 is low, and the second timing control signal line CKE2 is high. At this time, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the ninth transistor M9, the tenth transistor M10, and the twelfth transistor M12 are turned on, while the first transistor M1, the seventh transistor M7, the eighth transistor M8, and the eleventh transistor M11 are turned off. Specifically, when the signal input terminal IN and the first timing control signal line CKE1 are low, the fifth transistor M5, the sixth transistor M6, and the twelfth transistor M12 are turned on. Due to the turn-on of the fifth transistor M5 and the sixth transistor M6, the third node N3 simultaneously writes a low potential to the first timing control signal line CKE1 and the second power supply VEE, and the fourth transistor M4 is turned on. Simultaneously, the second timing control signal line CKE2 inputs a high level, the eighth transistor M8 and the eleventh transistor M11 are turned off, the second node N2 maintains the low potential from the previous moment, the second transistor M2 and the third transistor M3 are turned on, and the first node N1, due to the third transistor M3 being turned on, writes a high potential to the first power supply VDD, causing the first transistor M1 to turn off. Thus, the first transistor M1 turns off, and the second transistor M2 turns on. Finally, the signal output terminal Enout outputs a low potential of the second power supply VEE.

[0134] In this embodiment, the light-emitting driving unit repeats the process from Step 16 to Step 17 after Step 17 until the next frame of the image begins to be displayed. At this time, the starting pulse signal STE or the signal input terminal IN is input with a high potential, and the process re-enters the next round of Step 11.

[0135] In this embodiment, the relationship between the input and output of the light-emitting driving unit is as follows: when the start pulse signal STE or the signal input terminal IN inputs a high-level signal at the beginning of a certain process, the signal output terminal Enout outputs a high-level signal at the start of the next process; when the start pulse signal STE or the signal input terminal IN inputs a low-level signal at a certain moment, the signal output terminal Enout outputs a low-level signal at the start of the second process following that moment. At other times, the signal output terminal Enout and the signal input to the start pulse signal STE or the signal input terminal IN are both low-level signals.

[0136] In a second embodiment of the present invention, reference is made to... Figures 4 to 5 15 to 23 Figure 17 Show Figure 16 A schematic diagram of the conduction state of the light-emitting driving unit in Step 21. Figure 18Show Figure 16 A schematic diagram of the conduction state of the light-emitting driving unit in Step 22; Figure 19 Show Figure 16 A schematic diagram of the conduction state of the light-emitting driving unit in Step 23. Figure 20 Show Figure 16 A schematic diagram of the conduction state of the light-emitting driving unit in Step 24. Figure 21 Show Figure 16 A schematic diagram of the conduction state of the light-emitting driving unit in Step 25. Figure 22 Show Figure 16 A schematic diagram of the conduction state of the light-emitting driving unit in Step 26. Figure 23 Show Figure 16 A schematic diagram of the conduction state of the light-emitting driving unit in Step 27.

[0137] In this embodiment, as Figure 15 As shown, each stage of the light-emitting driving unit includes a control module, a reset module, and an output setting module. Specifically, the light-emitting driving unit includes 12 transistors, 3 capacitors, a signal input terminal IN, a signal output terminal Enout, a first timing control terminal c1, and a second timing control terminal c2.

[0138] In this embodiment, as Figure 15 As shown, in addition to the same technical features as the first embodiment of the present invention, the second embodiment differs from the first embodiment in that the control module further includes a tenth transistor M10. The first terminal of the tenth transistor M10 is connected to the gate of the fourth transistor M4, the second terminal is connected to the third node N3, and the gate is connected to the second power supply VEE. The gate of the seventh transistor M7 is connected to the third node N3. The first terminal of the ninth transistor M9 is connected to the second node N2. The gate of the twelfth transistor M12 is connected to the second timing control. The similarities between the second embodiment and the first embodiment of the present invention will not be repeated.

[0139] In this embodiment, the light-emitting driving unit further includes a first capacitor C1, a second capacitor C2, and a third capacitor C3. Their connection method is the same as in the first embodiment, and will not be described again here.

[0140] In this embodiment, the specific selection of the first transistor M1 to the twelfth transistor M12 is the same as in the first embodiment, and will not be repeated here.

[0141] In this embodiment, refer to Figure 16 , Figure 16The waveform diagram shown includes seven processes: Step 21 to Step 27, and subsequent processes not shown. During these processes, the output signal of the Enout terminal of the aforementioned light-emitting driving unit completes one cycle from set to reset. It should be noted that, for ease of understanding, a high-level signal is represented by "H" and a low-level signal by "L" in the attached diagram. The following section will further explain... Figure 16 waveform diagram and Figure 15 The circuit diagram is used to analyze the relationship between the input and output of the light-emitting driving unit in the above seven processes:

[0142] In this embodiment, refer to Figure 16 and 17 In Step 21, the signal input terminal IN is high, the first timing control signal line CKE1 is low, and the second timing control signal line CKE2 is high. At this time, the second transistor M2, the third transistor M3, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the ninth transistor M9, and the tenth transistor M10 are turned on, while the first transistor M1, the fifth transistor M5, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 are turned off. Specifically, when the first timing control signal line CKE1 is low, the sixth transistor M6 is turned on, the third node N3 is written with the low potential of the second power supply VEE, and the fourth transistor M4 and the seventh transistor M7 are turned on. Simultaneously, when the second timing control signal line CKE2 is high, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 are turned off, the second node N2 maintains the low potential of the previous moment, the second transistor M2 and the third transistor M3 are turned on, and the first node N1 is written with the high potential of the first power supply VDD due to the turn-on of the third transistor M3, and the first transistor M1 is turned off. Therefore, the first transistor M1 is turned off, and the second transistor M2 is turned on. Finally, the signal output terminal Enout outputs a low potential of the second power supply VEE.

[0143] In this embodiment, refer to Figure 16 and 18In Step 22, the signal input terminal IN is high, the first timing control signal line CKE1 is high, and the second timing control signal line CKE2 is low. At this time, the first transistor M1, the fourth transistor M4, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are turned on, while the second transistor M2, the third transistor M3, the fifth transistor M5, and the sixth transistor M6 are turned off. Specifically, the first timing control signal line CKE1 is high, the sixth transistor M6 is off, the third node N3 maintains the low potential of the previous moment, and the fourth transistor M4 and the seventh transistor M7 are on. Simultaneously, the second timing control signal line CKE2 is input at a low level, turning on the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12. Due to the turn-on of the seventh transistor M7, the eighth transistor M8, and the twelfth transistor M12, the second node N2 simultaneously writes a high potential to both the signal input terminal IN and the first power supply VDD, turning off the second transistor M2 and the third transistor M3. Conversely, due to the turn-on of the fourth transistor M4 and the eleventh transistor M11, the first node N1 writes a low potential to the second power supply VEE, turning on the first transistor M1. Thus, the first transistor M1 is turned on, and the second transistor M2 is turned off. Finally, the signal output terminal Enout outputs a high potential to the first power supply VDD.

[0144] In this embodiment, refer to Figure 16 and 19 In Step 23, the signal input terminal IN is high, the first timing control signal line CKE1 is low, and the second timing control signal line CKE2 is high. At this time, the first transistor M1, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, the ninth transistor M9, and the tenth transistor M10 are turned on, while the second transistor M2, the third transistor M3, the fifth transistor M5, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 are turned off. Specifically, when the first timing control signal line CKE1 is low, the sixth transistor M6 is turned on, the third node N3 is written with the low potential of the second power supply VEE, and the fourth transistor M4 and the seventh transistor M7 are turned on. Simultaneously, when the second timing control signal line CKE2 is high, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 are turned off, the first node N1 maintains the low potential of the previous moment, and the first transistor M1 is turned on. The second node N2 maintains the high potential of the previous moment, and the second transistor M2 and the third transistor M3 are turned off. Therefore, the first transistor M1 turns on, and the second transistor M2 turns off. Finally, the signal output terminal Enout outputs a high potential of the first power supply VDD.

[0145] In this embodiment, refer to Figure 16 and 20In Step 24, the signal input terminal IN is high, the first timing control signal line CKE1 is high, and the second timing control signal line CKE2 is low. At this time, the first transistor M1, the fourth transistor M4, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are turned on, while the second transistor M2, the third transistor M3, the fifth transistor M5, and the sixth transistor M6 are turned off. Specifically, the first timing control signal line CKE1 is high, the sixth transistor M6 is off, the third node N3 maintains the low potential of the previous moment, and the fourth transistor M4 and the seventh transistor M7 are on. Simultaneously, the second timing control signal line CKE2 is input at a low level, turning on the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12. Due to the turn-on of the seventh transistor M7, the eighth transistor M8, and the twelfth transistor M12, the second node N2 simultaneously writes a high potential to both the signal input terminal IN and the first power supply VDD, turning off the second transistor M2 and the third transistor M3. Conversely, due to the turn-on of the fourth transistor M4 and the eleventh transistor M11, the first node N1 writes a low potential to the second power supply VEE, turning on the first transistor M1. Thus, the first transistor M1 is turned on, and the second transistor M2 is turned off. Finally, the signal output terminal Enout outputs a high potential to the first power supply VDD.

[0146] In this embodiment, refer to Figure 16 and 21 In Step 25, the signal input terminal IN is low, the first timing control signal line CKE1 is low, and the second timing control signal line CKE2 is high. At this time, the first transistor M1, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the ninth transistor M9, and the tenth transistor M10 are turned on, while the second transistor M2, the third transistor M3, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 are turned off. Specifically, when the signal input terminal IN and the first timing control signal line CKE1 are low, the fifth transistor M5 and the sixth transistor M6 are turned on. Due to the turn-on of the fifth transistor M5 and the sixth transistor M6, the third node N3 simultaneously writes a low potential to the first timing control signal line CKE1 and the second power supply VEE, and the fourth transistor M4 and the seventh transistor M7 are turned on. Simultaneously, the second timing control signal line CKE2 is input at a high level, turning off the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12. The first node N1 maintains the low potential from the previous moment, and the first transistor M1 is turned on. The second node N2 maintains the high potential from the previous moment, and the second transistor M2 and the third transistor M3 are turned off. Therefore, the first transistor M1 is turned on, and the second transistor M2 is turned off. Finally, the signal output terminal Enout outputs the high potential of the first power supply VDD.

[0147] In this embodiment, refer to Figure 16 and 22 During Step 26, the signal input terminal IN is low, the first timing control signal line CKE1 is high, and the second timing control signal line CKE2 is low. At this time, the second transistor M2, the third transistor M3, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are turned on, while the first transistor M1, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are turned off. Specifically, when the first timing control signal line CKE1 is high, the sixth transistor M6 is off, and the fifth transistor M5 is turned on due to the low potential of the signal input terminal IN at the third node N3, thus writing a high potential into the first timing control signal line CKE1, while the fourth transistor M4 and the seventh transistor M7 are off. Simultaneously, the second timing control signal line CKE2 is input at a low level, turning on the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12. Due to the turn-on of the eighth transistor M8, the second node N2 receives a low potential from the signal input terminal IN, turning on the second transistor M2 and the third transistor M3. Due to the turn-on of the third transistor M3, the first node N1 receives a high potential from the first power supply VDD, turning off the first transistor M1. Thus, the first transistor M1 turns off, and the second transistor M2 turns on. Finally, the signal output terminal Enout outputs a low potential from the second power supply VEE.

[0148] In this embodiment, refer to Figure 16 and 23During Step 27, the signal input terminal IN is low, the first timing control signal line CKE1 is low, and the second timing control signal line CKE2 is high. At this time, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the ninth transistor M9, and the tenth transistor M10 are turned on, while the first transistor M1, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 are turned off. Specifically, when the signal input terminal IN and the first timing control signal line CKE1 are low, the fifth transistor M5 and the sixth transistor M6 are turned on. Due to the turn-on of the fifth transistor M5 and the sixth transistor M6, the third node N3 simultaneously writes a low potential to the first timing control signal line CKE1 and the second power supply VEE, thus turning on the fourth transistor M4 and the seventh transistor M7. Simultaneously, the second timing control signal line CKE2 inputs a high level, turning off the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12. The second node N2 maintains the low potential from the previous moment, while the second transistor M2 and the third transistor M3 turn on. The first node N1, due to the third transistor M3 being on, receives a high potential from the first power supply VDD, turning off the first transistor M1. Thus, the first transistor M1 turns off, and the second transistor M2 turns on. Finally, the signal output terminal Enout outputs a low potential from the second power supply VEE.

[0149] In this embodiment, the light-emitting driving unit repeats the process from Step 26 to Step 27 after Step 27 until the next frame of the image begins to be displayed. At this time, the starting pulse signal STE or the signal input terminal IN is input with a high potential, and the next round of the Step 21 process is restarted.

[0150] In this embodiment, the relationship between the input and output of the light-emitting driving unit is as follows: when the start pulse signal STE or the signal input terminal IN inputs a high-level signal at the beginning of a certain process, the signal output terminal Enout outputs a high-level signal at the start of the next process; when the start pulse signal STE or the signal input terminal IN inputs a low-level signal at a certain moment, the signal output terminal Enout outputs a low-level signal at the start of the second process following that moment. At other times, the signal output terminal Enout and the signal input to the start pulse signal STE or the signal input terminal IN are both low-level signals.

[0151] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel 10 described above in the embodiments of the present invention. This display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Implementation of this display device can refer to the embodiments of the display panel 10 described above; repeated details will not be repeated.

[0152] In summary, the light-emitting driving circuit and display panel of the present invention, by providing a new light-emitting driving unit circuit, enable the first node N1, the second node N2 and the third node N3 to be controlled independently, avoiding mutual interference among the three, thereby improving the output stability of the light-emitting driving unit, reducing display abnormalities of the display panel and extending the service life of the display panel; in addition, the present invention reduces the number of components in the light-emitting driving circuit by reducing the use of timing control signal lines, thereby reducing the bezel width of the display panel and adapting to the trend of narrow bezels in display panels.

[0153] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A light emitting drive circuit, characterized by, The light emitting driving unit comprises a control module, a reset module and an output set module; The control module comprises: a fourth transistor, a second electrode of the fourth transistor is connected to a first node; a fifth transistor, a first electrode of the fifth transistor is connected to a third node, a second electrode is connected to a first timing control end, and a gate electrode is connected to a signal input end; a sixth transistor, a first electrode of the sixth transistor is connected to the third node, a second electrode is connected to a second power supply, and a gate electrode is connected to the first timing control end; The reset module comprises: a third transistor, a first electrode of the third transistor is connected to a first power supply, a second electrode is connected to the first node, and a gate electrode is connected to a second node; a seventh transistor, a second electrode of the seventh transistor is connected to the second node; a twelfth transistor, a first electrode of the twelfth transistor is connected to the first power supply, and a second electrode is connected to a first electrode of the seventh transistor; The output set module comprises: a first transistor, a first electrode of the first transistor is connected to the first power supply, a second electrode is connected to a signal output end, and a gate electrode is connected to the first node; a second transistor, a first electrode of the second transistor is connected to the signal output end, a second electrode is connected to the second power supply, and a gate electrode is connected to a fourth node; an eighth transistor, a first electrode of the eighth transistor is connected to the signal input end, a second electrode is connected to the second node, and a gate electrode is connected to a second timing control end; a ninth transistor, a second electrode of the ninth transistor is connected to the fourth node, and a gate electrode is connected to the second power supply; an eleventh transistor, a first electrode of the eleventh transistor is connected to the second power supply, a second electrode is connected to a first electrode of the fourth transistor, and a gate electrode is connected to the second timing control end.

2. The light emitting driving circuit according to claim 1, wherein the output set module further comprises: a tenth transistor, a first electrode of the tenth transistor is connected to the second node, a second electrode is connected to a first electrode of the ninth transistor, and a gate electrode is connected to the second power supply.

3. The light emitting driving circuit according to claim 2, wherein a gate electrode of the fourth transistor is connected to the third node; a gate electrode of the seventh transistor is connected to the first node; a gate electrode of the twelfth transistor is connected to the first timing control end.

4. The light emitting driving circuit according to claim 1, wherein the control module further comprises: a tenth transistor, a first electrode of the tenth transistor is connected to a gate electrode of the fourth transistor, a second electrode is connected to the third node, and a gate electrode is connected to the second power supply.

5. The light emitting driving circuit according to claim 4, wherein a gate electrode of the seventh transistor is connected to the third node; a first electrode of the ninth transistor is connected to the second node; a gate electrode of the twelfth transistor is connected to the second timing control.

6. The light emitting drive circuit according to claim 3 or 5, wherein The light emitting driving unit further comprises: a first capacitor, a first electrode of the first capacitor is connected to the first timing control end, and a second electrode is connected to the fourth node; a second capacitor, a first pole of the second capacitor being connected to a first pole of the fourth transistor, and a second pole of the second capacitor being connected to a gate of the fourth transistor; a third capacitor, a first pole of the third capacitor being connected to the first power supply, and a second pole of the third capacitor being connected to the first node.

7. The light emitting drive circuit of claim 6, wherein, A timing controller is further included, and the timing controller includes a first timing control signal line and a second timing control signal line.

8. The light emitting drive circuit of claim 7, wherein, The first timing control signal line is used for outputting a first timing control signal, and the second timing control signal line is used for outputting a second timing control signal.

9. The light emitting drive circuit of claim 8, wherein, The first timing control signal and the second timing control signal are square wave signals with the same output frequency and a phase difference of 180°.

10. The light emitting drive circuit of claim 7, wherein, The light-emitting driving unit of a previous stage outputs a light-emitting driving signal to the light-emitting driving unit of a next stage, and the light-emitting driving unit of a last stage outputs a light-emitting driving signal.

11. The light emitting drive circuit of claim 10, wherein, In the light-emitting driving unit of an odd-numbered stage, the first timing control end is connected to the first timing control signal line, and the second timing control end is connected to the second timing control signal line.

12. The light emitting drive circuit of claim 11, wherein, In the light-emitting driving unit of an even-numbered stage, the first timing control end is connected to the second timing control signal line, and the second timing control end is connected to the first timing control signal line.

13. The light emitting drive circuit of claim 4, wherein, The first transistor to the eleventh transistor are all P-type MOS transistors.

14. A display panel, characterized by The light-emitting driving circuit according to any one of claims 1 to 13 is included.

Images