Fm0 decoding circuit and decoding method for etc

Abstract

The application discloses an FM0 decoding circuit and method for ETC, which comprises an edge detection unit, a narrowband filter unit, a rounding unit, a half frequency division unit, a non-gate processing unit, a shift delay unit, an exclusive or gate processing unit and a with gate processing unit. The application takes full advantage of the feature that FM0 coding is self-brought bit synchronization information, adopts a bit synchronization extraction mode, directly recovers a bit synchronization clock from an original coding sequence, avoids the synchronization problem of a transmission source clock and a local clock, has a simple and stable circuit structure, is low in cost, can adapt to various processors, and reduces the difficulty of processor selection and system design.

Description

Technical Field

[0001] This invention relates to the fields of intelligent transportation and electronic toll collection (ETC), and more specifically, to an FMO decoding circuit and decoding method for ETC. Background Technology

[0002] Electronic Toll Collection (ETC) uses Dedicated Short-Range Communication (DSRC) technology to achieve data exchange between Roadside Units (RSUs) and Onboard Units (OBUs). According to the national ETC standard and relevant technical requirements of the Ministry of Transport, the baseband front-end data is explicitly specified to use Bi-Phase Space (FM0) encoding. The FM0 encoding principle uses the level change in the middle of bits to represent logic 0 and 1. The middle level of the bit for data 1 remains unchanged, while the middle level of the bit for data 0 changes once, and there is a level change between bits.

[0003] Currently, there are five main methods for RSU and OBU devices to implement FM0 decoding in the ETC system: First, using a dedicated RF transceiver chip to complete the decoding output after demodulation; second, using a microcontroller software program for decoding; third, using an MCU with FM0 decoding capabilities, such as the STR710 series MCU; fourth, using FPGA or CPLD for hardware logic programming to implement decoding; and fifth, using hardware circuitry for decoding.

[0004] The most commonly used methods for OBU devices are the first and second methods. RSU devices use different methods depending on the manufacturer, and even different models from the same manufacturer use different methods, mainly focusing on the second, third, and fourth methods. The second method is relatively flexible, with less dependence on the MCU platform and a wide range of choices. Its disadvantage is that decoding requires a significant amount of processing time, making it difficult for ordinary MCUs to handle other real-time tasks during decoding. The third method has the simplest hardware and software design, directly calling the MCU's peripheral modules. Its disadvantage is that the choice of MCUs is very limited. The fourth method offers a wider range of choices and is relatively flexible, but its cost is higher. The fifth method is implemented in hardware, with relatively independent functionality, no impact on MCU selection, and lower cost. Its disadvantage is that it occupies PCB space. Summary of the Invention

[0005] This invention proposes an FMO decoding circuit and decoding method for ETC to solve the problem of how to perform FMO decoding efficiently.

[0006] To address the aforementioned problems, according to one aspect of the present invention, an FMO decoding circuit for ETC is provided, the FMO decoding circuit comprising: an edge detection unit, a narrowband filtering unit, a shaping unit, a frequency divider unit, a NOT gate processing unit, a shift delay unit, an XNOR gate processing unit, and an AND gate processing unit; wherein;

[0007] The edge detection unit is connected to the narrowband filtering unit and is used to detect the transition edge of the input signal in FM0 format and generate a transition edge pulse signal Ep.

[0008] The narrowband filtering unit is connected to the shaping unit and is used to filter the transition edge pulse signal Ep to extract the sinusoidal signal Sin, which is the second harmonic of the bit rate.

[0009] The shaping unit is connected to the frequency divider unit and the AND gate processing unit respectively, and is used to convert the sine signal Sin into a square wave clock signal Cx2;

[0010] The frequency divider unit is used to divide the square wave clock signal Cx2 to obtain the bit synchronization clock signal Clk output by FM0 decoding; wherein, the square wave clock signal Cx2 and the decoded data Data output by the XOR gate processing unit are ANDed by the AND gate processing unit to obtain the set control signal Set and send it to the frequency divider unit so that the frequency divider unit adjusts the phase of the bit synchronization clock signal Clk based on the set control signal Set;

[0011] The NOT gate processing unit is connected to the shift delay unit and is used to invert the square wave clock signal Cx2 to obtain a second-harmonic clock signal Cx2n with the opposite waveform to the square wave clock signal Cx2, so as to sample and delay the input signal based on the second-harmonic clock signal Cx2n;

[0012] The shift delay unit is connected to the XOR gate processing unit and is used to synchronously sample the input signal using the double frequency clock Cx2n to obtain the sampled signal D0 and the delayed output signal D1.

[0013] The XOR gate processing unit, connected to the AND gate processing unit, is used to perform XOR gate processing on the sampled signal D0 and the delayed output signal D1 to obtain decoded data Data; the AND gate processing unit, connected to the frequency divider unit, is used to perform AND logic on the square wave clock signal Cx2 and the decoded data Data output by the XOR gate processing unit to obtain a set control signal Set and send it to the frequency divider unit so that the frequency divider unit adjusts the phase of the bit synchronization clock signal Clk based on the set control signal Set.

[0014] Preferably, the center frequency of the narrowband filter unit is twice the FM0 coding bit rate frequency; the narrowband filter unit includes a passive RC filter and an LC circuit; or the narrowband filter unit includes an active filter.

[0015] Preferably, the FM0 decoding circuit further includes:

[0016] An amplifier, connected to the narrowband filter unit and the shaping unit respectively, is used to amplify the sinusoidal signal Sin.

[0017] Preferably, the shaping unit is a voltage comparator or a hysteresis comparator.

[0018] Preferably, the XOR gate processing unit is connected to the AND gate processing unit and is used to perform XOR gate processing on the sampled signal D0 and the delayed output signal D1 to obtain decoded data Data, including:

[0019] When the sampling signal D0 and the delayed output signal D1 are the same, a high level is output; when the sampling signal D0 and the delayed output signal D1 are different, a low level is output to obtain the decoded data Data.

[0020] According to another aspect of the present invention, an FMO decoding method based on the FMO decoding circuit for ETC as described above is provided, the method comprising:

[0021] The edge detection unit detects the rising edge of the FM0 format input signal and generates a rising edge pulse signal Ep;

[0022] The narrowband filtering unit filters the transition edge pulse signal Ep to extract the bit rate second harmonic sine signal Sin;

[0023] The shaping unit converts the sinusoidal signal Sin into a square wave clock signal Cx2;

[0024] The frequency divider unit divides the square wave clock signal Cx2 to obtain the bit synchronization clock signal Clk output by FM0 decoding; wherein, the AND gate processing unit performs AND logic on the square wave clock signal Cx2 and the decoded data Data output by the XOR gate processing unit to obtain a set control signal Set and send it to the frequency divider unit so that the frequency divider unit adjusts the phase of the bit synchronization clock signal Clk based on the set control signal Set;

[0025] The NOT gate processing unit inverts the square wave clock signal Cx2 to obtain a second harmonic clock signal Cx2n that is opposite to the waveform of the square wave clock signal Cx2, and then samples and delays the input signal based on the second harmonic clock signal Cx2n.

[0026] The shift delay unit uses the double frequency clock Cx2n to synchronously sample the input signal to obtain the sampled signal D0 and the delayed output signal D1.

[0027] The XOR gate processing unit performs XOR gate processing on the sampled signal D0 and the delayed output signal D1 to obtain the decoded data Data.

[0028] The AND gate processing unit performs an AND logic on the square wave clock signal Cx2 and the decoded data Data output by the XOR gate processing unit to obtain a set control signal Set and sends it to the frequency divider unit so that the frequency divider unit adjusts the phase of the bit synchronization clock signal Clk based on the set control signal Set.

[0029] Preferably, the center frequency of the narrowband filter unit is twice the FM0 coding bit rate frequency; the narrowband filter unit includes a passive RC filter and an LC circuit; or the narrowband filter unit includes an active filter.

[0030] Preferably, the method further includes:

[0031] Before the shaping unit converts the sinusoidal signal Sin into a square wave clock signal Cx2, the sinusoidal signal Sin is amplified by an amplifier.

[0032] Preferably, the shaping unit is a voltage comparator or a hysteresis comparator.

[0033] Preferably, when the decoded data Data is 1 and the square wave clock signal Cx2 is high, the bit synchronization clock signal Clk is controlled to be high; when the decoded data Data is low, the bit synchronization clock signal Clk is controlled to flip on the rising edge of Cx2.

[0034] Preferably, the XOR gate processing unit performs XOR gate processing on the sampled signal D0 and the delayed output signal D1 to obtain decoded data Data, including:

[0035] When the sampling signal D0 and the delayed output signal D1 are the same, a high level is output; when the sampling signal D0 and the delayed output signal D1 are different, a low level is output to obtain the decoded data Data.

[0036] This invention provides an FM0 decoding circuit and decoding method for ETC, comprising: an edge detection unit for detecting the transition edge of an FM0 format input signal and generating a transition edge pulse signal Ep; a narrowband filtering unit for filtering the transition edge pulse signal Ep to extract a sinusoidal signal Sin at twice the bit rate; a shaping unit for converting the sinusoidal signal Sin into a square wave clock signal Cx2; a frequency divider unit for dividing the square wave clock signal Cx2 to obtain a bit synchronization clock signal Clk output from the FM0 decoding; and a NOT gate processing unit for inverting the square wave clock signal Cx2 to obtain a clock signal Cx2n at twice the frequency, which is opposite to the waveform of the square wave clock signal Cx2. The system utilizes the bit synchronization clock signal Cx2n to sample and delay the input signal. A shift delay unit is used to synchronously sample the input signal using the doubled clock signal Cx2n to obtain a sampled signal D0 and a delayed output signal D1. An XOR gate processing unit processes the sampled signal D0 and the delayed output signal D1 using an XOR gate to obtain decoded data Data. An AND gate processing unit performs an AND logic operation on the square wave clock signal Cx2 and the decoded data Data output by the XOR gate processing unit to obtain a set control signal Set, which is then sent to the frequency divider unit so that the frequency divider unit adjusts the phase of the bit synchronization clock signal Clk based on the set control signal Set. This invention fully utilizes the inherent bit synchronization information of FM0 encoding, employing a bit synchronization extraction method to directly recover the bit synchronization clock from the original encoded sequence, avoiding the synchronization problem between the transmitter clock and the local clock. The circuit structure is simple and stable, with low cost, and can adapt to various processors, reducing the difficulty of processor selection and system design. Attached Figure Description

[0037] Exemplary embodiments of the present invention can be more fully understood by referring to the following figures:

[0038] Figure 1 This is a schematic diagram of the structure of an FMO decoding circuit 100 for ETC according to an embodiment of the present invention;

[0039] Figure 2 This is a connection diagram of the FMO decoding circuit for ETC according to an embodiment of the present invention;

[0040] Figure 3 This is a circuit diagram of an edge detection unit according to an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of the waveform of the edge detection circuit according to an embodiment of the present invention;

[0042] Figure 5This is a circuit diagram of a narrowband filter unit according to an embodiment of the present invention;

[0043] Figure 6 This is a schematic diagram of the shaping circuit according to an embodiment of the present invention;

[0044] Figure 7 This is a schematic diagram of the output waveform of the shaping circuit according to an embodiment of the present invention;

[0045] Figure 8 The circuit diagram is shown below for a frequency divider unit according to an embodiment of the present invention.

[0046] Figure 9 The circuit diagram is shown below for a shift delay unit according to an embodiment of the present invention.

[0047] Figure 10 This is a schematic diagram of the output waveforms of each unit in the FM0 decoding circuit according to an embodiment of the present invention;

[0048] Figure 11 This is a flowchart of an FMO decoding method 1100 for ETC according to an embodiment of the present invention. Detailed Implementation

[0049] Exemplary embodiments of the invention will now be described with reference to the accompanying drawings. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided to fully and completely disclose the invention and to fully convey its scope to those skilled in the art. The terminology used in the exemplary embodiments illustrated in the drawings is not intended to limit the invention. In the drawings, the same units / elements are referred to by the same reference numerals.

[0050] Unless otherwise stated, the terms used herein (including technical terms) have their common meaning as understood by one of ordinary skill in the art. Furthermore, it is understood that terms defined in commonly used dictionaries should be understood to have a meaning consistent with the context of their relevant field, and not to be interpreted as having an idealized or overly formal meaning.

[0051] Figure 1 This is a schematic diagram of the structure of an FMO decoding circuit 100 for ETC according to an embodiment of the present invention. Figure 1As shown, the FMO decoding circuit for ETC provided in this embodiment of the invention fully utilizes the characteristic of FMO encoding with built-in bit synchronization information. It employs a bit synchronization extraction method to directly recover the bit synchronization clock from the original encoded sequence, avoiding the synchronization problem between the transmitter clock and the local clock. The circuit structure is simple and stable, with low cost, and can adapt to various processors, reducing the difficulty of processor selection and system design. The FMO decoding circuit 100 for ETC provided in this embodiment of the invention includes: an edge detection unit 101, a narrowband filtering unit 102, a shaping unit 103, a frequency divider unit 104, a NOT gate processing unit 105, a shift delay unit 106, an XNOR gate processing unit 107, and an AND gate processing unit 108.

[0052] Preferably, the edge detection unit 101 is connected to the narrowband filter unit and is used to detect the transition edge of the input signal in FM0 format and generate a transition edge pulse signal Ep.

[0053] Combination Figure 2 As shown, in this invention, the decoding circuit includes: an edge detection unit, a narrowband filtering unit, a shaping unit, a frequency divider unit, a NOT gate processing unit, a shift delay unit, an XNOR gate processing unit, and an AND gate processing unit.

[0054] In this invention, the edge detection unit is used to detect the rising edge of the FM0 input signal and generate a rising edge pulse signal Ep. When the input waveform is a standard FM0 code, the Ep pulse must contain a double frequency component for synchronizing the encoded data bits. Extracting and processing this frequency component yields the synchronization clock for the FM0 code.

[0055] The edge detection circuit can employ the RC differential edge detection method. For example... Figure 3 As shown, in the edge detection circuit, C2 is a capacitor, R1 and R2 are resistors, and D1 and D2 are diodes. R1, C1, and D1 form a falling edge transition detection unit, R1 and C1 form a differentiating circuit, and D1 is used to quickly discharge the high pulse generated at Ein1 by the rising edge. R2, C2, and D2 form a rising edge transition detection unit, R2 and C2 form a differentiating circuit, and D2 is used to quickly discharge the low pulse generated at Ein2 by the falling edge.

[0056] The XOR gate here is used to perform an XOR logic operation on Ein1 and Ein2. When the logic levels of the two inputs are the same, the output is logic 1, and when the logic levels of the two inputs are different, the output is logic 0.

[0057] When the FM0 input remains unchanged, Ein1 is high, Ein2 is low, and the output Ep is logic 0.

[0058] When the rising edge arrives, Ein1 remains high, while Ein2 generates a high-level transition and quickly discharges back to low through R2. During the transition of Ein2 to high, there is a brief high-level logic 1. The XOR gate will output a brief high-level logic 1 and quickly return to logic 0.

[0059] When the falling edge arrives, Ein2 remains low, while Ein1 experiences a low-level transition and quickly returns to high level via R1. During the transition of Ein1 to low level, there is a brief low-level logic 0. The XOR gate will output a brief high-level logic 1 and quickly return to logic 0. The waveform of the edge detection circuit is as follows: Figure 4 As shown.

[0060] By changing the values ​​of the resistors and capacitors, the charging and discharging times can be adjusted, thereby adjusting the width of the XNOR gate output pulse. The XNOR gate can be replaced by an XOR gate; the resulting Ep pulse has the exact opposite logic and does not affect the subsequent extraction of the synchronization clock.

[0061] Preferably, the narrowband filtering unit 102 is connected to the shaping unit and is used to filter the transition edge pulse signal Ep to extract the sinusoidal signal Sin, which is the second harmonic of the bit rate.

[0062] Preferably, the narrowband filter unit 102 has a center frequency that is twice the FM0 coding bit rate frequency; the narrowband filter unit includes a passive RC filter and an LC circuit; or the narrowband filter unit includes an active filter.

[0063] In this invention, the narrowband filter unit is a bandpass filter with a very small bandwidth. Its center frequency is twice the FM0 encoding bit rate frequency. It is used to filter the pulse signal Ep and extract the sinusoidal signal Sin, which is twice the bit rate frequency. Adjusting the filter bandwidth allows the decoding circuit to adapt to changes in the FM0 encoding rate within a certain range. The narrowband filter unit can be composed of passive RC or LC circuits or active filters. The center frequency of the filter is determined by the FM0 bit rate; it is 1024kHz when decoding uplink OBU data and 512kHz when decoding downlink RSU data.

[0064] In this invention, the following methods can be used: Figure 5 The fifth-order LC bandpass filter shown is used as a narrowband filter unit.

[0065] Preferably, the shaping unit 103 is connected to the frequency divider unit and the AND gate processing unit respectively, and is used to convert the sine signal Sin into a square wave clock signal Cx2.

[0066] Preferably, the FM0 decoding circuit further includes:

[0067] An amplifier, connected to the narrowband filter unit and the shaping unit respectively, is used to amplify the sinusoidal signal Sin.

[0068] Preferably, the shaping unit 103 is a voltage comparator or a hysteresis comparator.

[0069] In this invention, the shaping unit converts the sinusoidal signal Sin into a square wave clock signal Cx2, which is used to control data decoding and generate a bit synchronization clock. Generally, the filtered Sin signal is relatively weak and needs to be amplified before shaping. The shaping circuit can use a common voltage comparator or a hysteresis comparator to eliminate noise.

[0070] like Figure 6 As shown, in this invention, the shaping circuit consists of an amplifier and a hysteresis comparator. The filtered small signal is amplified, and then the hysteresis comparator is used to shape the sinusoidal signal to obtain a square wave signal.

[0071] When there is no signal at the FM0 input or the input is random noise, the signal obtained by the narrowband filter is random noise with a very small amplitude. Even after amplification, the amplitude remains small, and the hysteresis comparator output remains unchanged. When there is a correct FM0 encoded input, the narrowband filter output is a small-amplitude sine wave. After amplification, a very strong signal is obtained, and after passing through the hysteresis comparator, the output is a square wave. The waveform is as follows: Figure 7 As shown, Sin is the output waveform of the narrowband filter, SinA is the output waveform of the amplifier, and Cx2 is the output waveform of the hysteresis comparator.

[0072] Preferably, the frequency divider unit 104 is used to divide the square wave clock signal Cx2 to obtain the bit synchronization clock signal Clk output by FM0 decoding.

[0073] Preferably, the AND gate processing unit 108 is connected to the frequency divider unit and is used to perform AND logic on the square wave clock signal Cx2 and the decoded data Data output by the XOR gate processing unit to obtain a set control signal Set and send it to the frequency divider unit so that the frequency divider unit adjusts the phase of the bit synchronization clock signal Clk based on the set control signal Set.

[0074] Preferably, when the decoded data Data is 1 and the square wave clock signal Cx2 is high, the bit synchronization clock signal Clk is controlled to be high; when the decoded data Data is low, the bit synchronization clock signal Clk is controlled to flip on the rising edge of Cx2.

[0075] In this invention, Cx2 is divided by a frequency divider unit to obtain the bit synchronization clock signal Clk output from the FM0 decoder. The phase of the clock is determined by the decoded data. In this invention, an AND gate processing unit is used to AND Cx2 and Data to obtain the set control signal Set of the frequency divider unit, which is used to adjust the phase of Clk. Specifically, when the decoded data Data is 1 and the square wave clock signal Cx2 is high, the bit synchronization clock signal Clk is controlled to be high; when the decoded data Data is low, the bit synchronization clock signal Clk is controlled to flip on the rising edge of Cx2.

[0076] In this invention, a D flip-flop is used to implement a frequency divider of two. The circuit of the frequency divider unit is as follows: Figure 8 As shown in the figure, the set input of the D flip-flop is active low. Therefore, the data Data and the clock Cx2 are ANDed together to adjust the phase of Clk and ensure that the clock and data are output synchronously.

[0077] Preferably, the NOT gate processing unit 105 is connected to the shift delay unit and is used to invert the square wave clock signal Cx2 to obtain a second-harmonic clock signal Cx2n that is opposite to the waveform of the square wave clock signal Cx2, so as to sample and delay the input signal based on the second-harmonic clock signal Cx2n.

[0078] In this invention, the NOT gate processing unit is used to invert Cx2 to obtain a double frequency clock Cx2n that is opposite to the waveform of Cx2. Using this clock to sample and delay the FM0 input can ensure that the rising edge of the data output is not at the same time as the rising edge of the clock Clk, that is, to ensure that the data Data corresponding to the rising edge of Clk is stable.

[0079] Preferably, the shift delay unit 106 is connected to the XNOR gate processing unit and is used to synchronously sample the input signal using the double frequency clock Cx2n to obtain the sampled signal D0 and the delayed output signal D1.

[0080] In this invention, the shift delay unit uses an inverted double frequency clock Cx2n to synchronously sample the input FM0 to obtain D0, and simultaneously obtains the delayed output D1 of D0.

[0081] In this invention, a D flip-flop is used to form a shift delay unit, and the circuit structure is as follows: Figure 9 As shown.

[0082] Preferably, the XOR gate processing unit 107 is connected to the AND gate processing unit and is used to perform XOR gate processing on the sampled signal D0 and the delayed output signal D1 to obtain decoded data Data.

[0083] Preferably, the XOR gate processing unit 107 is connected to the AND gate processing unit and is used to perform XOR gate processing on the sampled signal D0 and the delayed output signal D1 to obtain decoded data Data, including:

[0084] When the sampling signal D0 and the delayed output signal D1 are the same, a high level is output; when the sampling signal D0 and the delayed output signal D1 are different, a low level is output to obtain the decoded data Data.

[0085] In this invention, a XNOR gate processing unit is used to decode and generate data. Specifically, when D0 and D1 are the same, a high level (1) is output; when they are different, a low level (0) is output, resulting in the data output waveform Data.

[0086] Suppose the original data is a binary data stream of 10001101X101, where X represents the data at the waveform error point. Then the output waveforms of each unit of the FM0 decoding circuit are as follows: Figure 10 As shown. Among them,

[0087] The FM0 input is the encoded waveform of the original data stream 10001101X101. At point X, the FM0 waveform is abnormal. From the front, it appears as a data 0 plus a half-bit error waveform. From the back, it appears as a half-bit error waveform plus a data 1. After that, the waveform returns to normal.

[0088] Ep is the transition pulse waveform of the FM0 input, synchronized with the edge of the FM0 waveform, and its spectrum includes the frequency component of the bit synchronization double frequency.

[0089] Sin is a bit-synchronous double-frequency sine signal extracted from the Ep signal through narrowband filtering.

[0090] Cx2 is a square wave with the same frequency as Sin, which is obtained by amplifying and shaping Sin.

[0091] Cx2n, a square wave with the opposite logic to Cx2, is used for data decoding output control, ensuring that the rising edges of Data and Clk are not at the same time, thus ensuring that Data remains stable when sampled on the rising edge of Clk.

[0092] D0 is the waveform of the FM0 input after synchronous sampling by Cx2n.

[0093] D1 is the waveform of D0 after a Cx2n delay of one clock cycle.

[0094] Data is the decoded data output. A high level (1) is generated when D0 and D1 are the same, and a low level (0) is generated when they are different. Each data bit lasts for half a bit cycle; the Data output corresponds to the rising edge of Clk.

[0095] Set is the phase control signal for Clk. When Data is 1 and Cx2 is high, Clk is forced to be high. When Data is 0, Clk toggles on the rising edge of Cx2.

[0096] Clk is the decoding clock output; the rising edge corresponds to the data output.

[0097] The circuit of this invention adopts a bit synchronization extraction method, which directly recovers the bit synchronization clock from the original encoded sequence. It is composed of common basic electronic components and chips, does not require a local clock source, is functionally independent of other circuits, has a simple and stable circuit structure, low cost, and can be adapted to various processors, reducing the difficulty of processor selection and system design.

[0098] Figure 11 This is a flowchart of an FMO decoding method 1100 for ETC according to an embodiment of the present invention. Figure 11 As shown, the FMO decoding method 1100 based on the FMO decoding circuit for ETC provided by the embodiment of the present invention starts from step 1101. In step 1101, the edge detection unit detects the transition edge of the input signal in FMO format and generates a transition edge pulse signal Ep.

[0099] In step 1102, the narrowband filtering unit filters the transition edge pulse signal Ep to extract the sinusoidal signal Sin, which is the second harmonic of the bit rate.

[0100] Preferably, the center frequency of the narrowband filter unit is twice the FM0 coding bit rate frequency; the narrowband filter unit includes a passive RC filter and an LC circuit; or the narrowband filter unit includes an active filter.

[0101] In step 1103, the shaping unit converts the sinusoidal signal Sin into a square wave clock signal Cx2.

[0102] Preferably, the method further includes:

[0103] Before the shaping unit converts the sinusoidal signal Sin into a square wave clock signal Cx2, the sinusoidal signal Sin is amplified by an amplifier.

[0104] Preferably, the shaping unit is a voltage comparator or a hysteresis comparator.

[0105] In step 1104, the frequency divider unit divides the square wave clock signal Cx2 to obtain the bit synchronization clock signal Clk output by the FM0 decoder; wherein, the AND gate processing unit performs AND logic on the square wave clock signal Cx2 and the decoded data Data output by the XOR gate processing unit to obtain the set control signal Set and send it to the frequency divider unit so that the frequency divider unit adjusts the phase of the bit synchronization clock signal Clk based on the set control signal Set.

[0106] Preferably, when the decoded data Data is 1 and the square wave clock signal Cx2 is high, the bit synchronization clock signal Clk is controlled to be high; when the decoded data Data is low, the bit synchronization clock signal Clk is controlled to flip on the rising edge of Cx2.

[0107] In step 1105, the NOT gate processing unit inverts the square wave clock signal Cx2 to obtain a second-harmonic clock signal Cx2n that is opposite to the waveform of the square wave clock signal Cx2, so as to sample and delay the input signal based on the second-harmonic clock signal Cx2n.

[0108] In step 1106, the shift delay unit uses the double frequency clock Cx2n to synchronously sample the input signal to obtain the sampled signal D0 and the delayed output signal D1.

[0109] In step 1107, the XNOR gate processing unit performs XNOR gate processing on the sampled signal D0 and the delayed output signal D1 to obtain the decoded data Data.

[0110] Preferably, the XOR gate processing unit performs XOR gate processing on the sampled signal D0 and the delayed output signal D1 to obtain decoded data Data, including:

[0111] When the sampling signal D0 and the delayed output signal D1 are the same, a high level is output; when the sampling signal D0 and the delayed output signal D1 are different, a low level is output to obtain the decoded data Data.

[0112] The FMO decoding method 1100 for ETC in an embodiment of the present invention corresponds to the FMO decoding circuit 100 for ETC in another embodiment of the present invention, and will not be described again here.

[0113] The invention has been described with reference to a few embodiments. However, as will be known to those skilled in the art, and as defined in the appended claims, other embodiments besides those disclosed above fall equivalently within the scope of the invention.

[0114] Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the art, unless otherwise expressly defined herein. All references to “a / the / the [device, component, etc.]” ​​are openly interpreted as at least one instance of said device, component, etc., unless otherwise expressly stated. The steps of any method disclosed herein need not be performed in the exact order disclosed unless explicitly stated otherwise.

[0115] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0116] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0117] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0118] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. An FMO decoding circuit for ETC, characterized in that, The FM0 decoding circuit includes: an edge detection unit, a narrowband filtering unit, a shaping unit, a frequency divider unit, a NOT gate processing unit, a shift delay unit, an XNOR gate processing unit, and an AND gate processing unit; wherein... The edge detection unit is connected to the narrowband filtering unit and is used to detect the transition edge of the input signal in FM0 format and generate a transition edge pulse signal Ep. The narrowband filtering unit is connected to the shaping unit and is used to filter the transition edge pulse signal Ep to extract the sinusoidal signal Sin, which is the second harmonic of the bit rate. The shaping unit is connected to the frequency divider unit and the AND gate processing unit respectively, and is used to convert the sine signal Sin into a square wave clock signal Cx2; The frequency divider unit is used to divide the square wave clock signal Cx2 to obtain the bit synchronization clock signal Clk output by FM0 decoding; The NOT gate processing unit is connected to the shift delay unit and is used to invert the square wave clock signal Cx2 to obtain a second-harmonic clock signal Cx2n with the opposite waveform to the square wave clock signal Cx2, so as to sample and delay the input signal based on the second-harmonic clock signal Cx2n; The shift delay unit is connected to the XOR gate processing unit and is used to synchronously sample the input signal using the double frequency clock Cx2n to obtain the sampled signal D0 and the delayed output signal D1. The XOR gate processing unit is connected to the AND gate processing unit and is used to perform XOR gate processing on the sampled signal D0 and the delayed output signal D1 to obtain decoded data Data. The AND gate processing unit is connected to the frequency divider unit and is used to perform AND logic on the square wave clock signal Cx2 and the decoded data Data output by the XOR gate processing unit to obtain a set control signal Set and send it to the frequency divider unit so that the frequency divider unit adjusts the phase of the bit synchronization clock signal Clk based on the set control signal Set. The XOR gate processing unit, connected to the AND gate processing unit, is used to perform XOR gate processing on the sampled signal D0 and the delayed output signal D1 to obtain decoded data Data, including: When the sampling signal D0 and the delayed output signal D1 are the same, a high level is output; when the sampling signal D0 and the delayed output signal D1 are different, a low level is output to obtain the decoded data Data.

2. The FMO decoding circuit according to claim 1, characterized in that, The narrowband filtering unit has a center frequency that is twice the FM0 coding bit rate frequency; the narrowband filtering unit includes a passive RC filter and an LC circuit; or the narrowband filtering unit includes an active filter.

3. The FMO decoding circuit according to claim 1, characterized in that, The FMO decoding circuit also includes: An amplifier, connected to the narrowband filter unit and the shaping unit respectively, is used to amplify the sinusoidal signal Sin.

4. The FMO decoding circuit according to claim 1, characterized in that, The shaping unit is a voltage comparator or a hysteresis comparator.

5. The FMO decoding circuit according to claim 1, characterized in that, When the decoded data Data is 1 and the square wave clock signal Cx2 is high, the bit synchronization clock signal Clk is controlled to be high. When the decoded data Data is low, the bit synchronization clock signal Clk is controlled to flip on the rising edge of Cx2.

6. An FMO decoding method based on the FMO decoding circuit for ETC as described in any one of claims 1-5, characterized in that, The method includes: The edge detection unit detects the rising edge of the FM0 format input signal and generates a rising edge pulse signal Ep; The narrowband filtering unit filters the transition edge pulse signal Ep to extract the bit rate second harmonic sine signal Sin; The shaping unit converts the sinusoidal signal Sin into a square wave clock signal Cx2; The frequency divider unit divides the square wave clock signal Cx2 to obtain the bit synchronization clock signal Clk output by FM0 decoding; wherein, the AND gate processing unit performs AND logic on the square wave clock signal Cx2 and the decoded data Data output by the XOR gate processing unit to obtain a set control signal Set and send it to the frequency divider unit so that the frequency divider unit adjusts the phase of the bit synchronization clock signal Clk based on the set control signal Set; The NOT gate processing unit inverts the square wave clock signal Cx2 to obtain a second harmonic clock signal Cx2n that is opposite to the waveform of the square wave clock signal Cx2, and then samples and delays the input signal based on the second harmonic clock signal Cx2n. The shift delay unit uses the double frequency clock Cx2n to synchronously sample the input signal to obtain the sampled signal D0 and the delayed output signal D1. The XOR gate processing unit performs XOR gate processing on the sampled signal D0 and the delayed output signal D1 to obtain the decoded data Data. The XOR gate processing unit performs XOR gate processing on the sampled signal D0 and the delayed output signal D1 to obtain decoded data Data, including: When the sampling signal D0 and the delayed output signal D1 are the same, a high level is output; when the sampling signal D0 and the delayed output signal D1 are different, a low level is output to obtain the decoded data Data.

7. The method according to claim 6, characterized in that, The narrowband filtering unit has a center frequency that is twice the FM0 coding bit rate frequency; the narrowband filtering unit includes a passive RC filter and an LC circuit; or the narrowband filtering unit includes an active filter.

8. The method according to claim 6, characterized in that, The method further includes: Before the shaping unit converts the sinusoidal signal Sin into a square wave clock signal Cx2, the sinusoidal signal Sin is amplified by an amplifier.

9. The method according to claim 6, characterized in that, The shaping unit is a voltage comparator or a hysteresis comparator.

10. The method according to claim 6, characterized in that, When the decoded data Data is 1 and the square wave clock signal Cx2 is high, the bit synchronization clock signal Clk is controlled to be high. When the decoded data Data is low, the bit synchronization clock signal Clk is controlled to flip on the rising edge of Cx2.

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