A data encryption method, device and electronic equipment

Abstract

The application discloses a data encryption method, which comprises the following steps: obtaining a block cipher corresponding to multimedia data through a neural network processor, and recombining the block cipher to obtain a first sequence; wherein the block cipher is obtained by performing feature extraction on the multimedia data through a general-purpose processor and performing binary format conversion on the extraction result; performing multi-round confusion and diffusion on the first sequence through the general-purpose processor and the neural network processor to obtain a second sequence; and performing inverse combination on the second sequence through the neural network processor to obtain ciphertext data; wherein the recombination and the inverse combination are a pair of inverse operations. The application also discloses a data encryption device and an electronic equipment.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of information security technology, and in particular to a data encryption method, a data encryption device, and an electronic device. Background Technology

[0002] Currently, with the rapid development and widespread application of computer and information technology, the scale of application systems in various industries is expanding rapidly, resulting in an explosive growth in application data. While promoting industry development, the generation and transmission of large amounts of data undoubtedly exposes more application information to the network, leading to a heavy reliance on electronic cryptographic devices for sensitive information and assets. Under this trend, the methods for security analysis of electronic cryptographic devices are increasing, posing a significant challenge to the security of electronic devices. To ensure the security of generated and transmitted data, various industries are researching effective hardware and software implementations of encryption and decryption modules in their application systems. In existing technologies, the Data Encryption Standard (DES) algorithm is commonly used to protect the security of sensitive information and assets in electronic devices.

[0003] However, when running on a large amount of encrypted / decrypted data, it consumes valuable general-purpose processor (CPU) resources, resulting in slow business operations and impacting user experience. Summary of the Invention

[0004] This application provides a data encryption method, a data encryption device, and an electronic device that can fully utilize the parallel computing capabilities of the NPU and save CPU memory resources when encrypting and decrypting large amounts of data.

[0005] The technical solution of this application is implemented as follows:

[0006] A data encryption method, the method comprising:

[0007] The block ciphers corresponding to the multimedia data are obtained through a neural network processor, and the block ciphers are recombined to obtain a first sequence; wherein, the block ciphers are obtained by a general-purpose processor extracting features from the multimedia data and converting the extraction results into binary format;

[0008] The first sequence is obtained by performing multiple rounds of obfuscation and diffusion on the first sequence using the general-purpose processor and the neural network processor;

[0009] The neural network processor performs an inverse combination on the second sequence to obtain ciphertext data; wherein the recombination and the inverse combination are a pair of inverse operations.

[0010] A data encryption device, the device comprising:

[0011] The first processing module is used to obtain the block cipher corresponding to the multimedia data through a neural network processor, and to recombine the block cipher to obtain a first sequence; wherein the block cipher is obtained by a general-purpose processor extracting features from the multimedia data and converting the extraction results into binary format;

[0012] The first processing module and the second processing module are used to perform multiple rounds of confusion and diffusion on the first sequence through the general-purpose processor and the neural network processor to obtain the second sequence;

[0013] The first processing module is further configured to perform inverse combination on the second sequence through the neural network processor to obtain ciphertext data; wherein the recombination and the inverse combination are a pair of inverse operations.

[0014] An electronic device, comprising: a neural network processor, a general-purpose processor, a memory, and a communication bus;

[0015] The communication bus is used to realize communication connections between the neural network processor, the general-purpose processor, and the memory;

[0016] The neural network processor and the general-purpose processor are used to execute the data encryption program stored in the memory to implement the steps of the data encryption method as described above.

[0017] This application provides a data encryption method, data encryption device, and electronic device. The method includes: obtaining a block cipher corresponding to multimedia data through a neural network processor; recombining the block cipher to obtain a first sequence; wherein the block cipher is obtained by a general-purpose processor extracting features from the multimedia data and converting the extracted results into binary format; performing multiple rounds of obfuscation and diffusion on the first sequence through a general-purpose processor and a neural network processor to obtain a second sequence; and performing inverse combination on the second sequence through a neural network processor to obtain ciphertext data; wherein recombination and inverse combination are a pair of inverse operations. Thus, by first extracting features from the multimedia data to obtain the corresponding block cipher, and then recombinating the block cipher to obtain the first sequence, efficient feature extraction of the multimedia data can be achieved; then, by performing multiple rounds of obfuscation and diffusion on the first sequence to obtain the second sequence, parallel processing of large amounts of data can be achieved through the NPU, fully utilizing the hardware computing power of the NPU and improving execution efficiency; finally, performing inverse combination on the second sequence to obtain ciphertext data enables efficient encryption during the data encryption process, saving CPU memory resources, reducing CPU computational pressure, and improving business processing speed. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating a data encryption method in a related technology.

[0019] Figure 2 A flowchart illustrating an optional data encryption method provided for an embodiment of this application;

[0020] Figure 3 Example 1 of an optional data encryption method provided for embodiments of this application;

[0021] Figure 4 An example of an optional key generation provided for embodiments of this application;

[0022] Figure 5 Example 2 of an optional data encryption method provided for embodiments of this application;

[0023] Figure 6 This application provides a schematic diagram of the structure of an optional data encryption device according to an embodiment;

[0024] Figure 7 This is a schematic diagram of the structure of an electronic device provided as an embodiment of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0027] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in a sequence other than that illustrated or described herein.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0029] Currently in China, with the launch of the "Three Golden Projects," especially the Golden Card Project, the DES algorithm is widely used in point-of-sale (POS) terminals, automated teller machines (ATMs), magnetic stripe cards and integrated circuit (IC) cards, gas stations, highway toll booths, and other fields to ensure the confidentiality of critical data. This includes the encrypted transmission of credit card holders' personal identification numbers (PINs), two-way authentication between IC cards and POS terminals, and verification of message authentication codes (MACs) in financial transaction data packets. (See reference...) Figure 1 As shown, the DES algorithm in the prior art runs on the CPU.

[0030] The embodiments of this application provide a data encryption method, referring to... Figure 2 As shown, the method includes the following steps:

[0031] Step 201: Obtain the block cipher corresponding to the multimedia data through a neural network processor, and recombine the block cipher to obtain the first sequence.

[0032] Among them, block ciphers are obtained by a general-purpose processor extracting features from multimedia data and converting the extracted results into binary format.

[0033] In some embodiments, multimedia data may include text, images, photographs, sounds, animations and videos, as well as data generated by other computer-provided interactive functions.

[0034] In some embodiments, prior to step 201, multimedia data may also be obtained by: capturing raw images using a camera or webcam and sending the captured raw images to an Internet Service Provider (ISP) for image processing.

[0035] In an optional embodiment, feature extraction of multimedia data may include: after receiving the original image, the ISP performs image processing on the original image, and then the NPU performs binarization on the image processing result, and finally converts the image data into a binary vector, wherein the image processing result can also be understood as a feature map.

[0036] It should be noted that the NPU's performance in extracting features from multimedia data in this application is not limited to image scenarios; it can be applied to any scenario related to multimedia data.

[0037] In this embodiment of the application, the first sequence can be a 64-bit plaintext cipher. Here, 64 bits refers to the size of the plaintext cipher being 64 bits, and a 64-bit plaintext cipher can also be understood as a 64-bit vector.

[0038] It's important to note that in the DES algorithm, permutations can be understood as reordering the original 64-bit binary data. In different permutations, the movement of each bit is different. Furthermore, each permutation involved in the DES encryption algorithm corresponds to a permutation table; the values ​​in the table are not data, but rather indicate which bit each bit moves to after being swapped.

[0039] In some embodiments, the recombination of the block cipher in step 201 to obtain the first sequence can be achieved by the following steps: performing initial address IP permutation on the block cipher using a neural network processor to obtain the first sequence.

[0040] For example, the NPU uses the neural network gather operator IP permutation to recombine 64-bit data into two parts of 32 bits each. The function of IP permutation is to recombine the input 64-bit data block bit by bit, and its permutation rules are shown in the table below.

[0041] 58 50 42 34 26 18 10 2 60 52 44 36 28 20 12 4 62 54 46 38 30 22 14 6 64 56 48 40 32 24 16 8 57 49 41 33 25 17 9 1 59 51 43 35 27 19 11 3 61 53 45 37 29 21 13 5 63 55 47 39 31 23 15 7

[0042] IP Replacement Table

[0043] The numbers in the IP substitution table represent, for example, moving the 58th bit of the input to the first bit, the 50th bit to the second bit, and so on, with the last bit being the original 7th bit.

[0044] In this way, by first extracting features from the multimedia data to obtain the corresponding block ciphers, and then recombining the block ciphers to obtain the first sequence, the efficient extraction of features from the multimedia data can be achieved.

[0045] Step 202: The first sequence is subjected to multiple rounds of confusion and diffusion using a general-purpose processor and a neural network processor to obtain the second sequence.

[0046] In some embodiments, the methods for performing multi-round obfuscation and diffusion may include: S-box substitution and P-box permutation.

[0047] The S-box substitution function compresses 48 bits of data into 32 bits. This is achieved using eight different S-boxes, each with 6 bits of input and 4 bits of output. The 48-bit input is divided into eight 6-bit groups, each corresponding to one S-box. The corresponding S-box performs the substitution operation on each group. In other words, the input to the S-box is 6 bits of data, and the output is 4 bits of data. This compresses the 48-bit output into 32 bits. The S-box substitution table includes S1 to S8, as shown below.

[0048] 14 4 13 1 2 15 11 8 3 10 6 12 5 9 0 7 0 15 7 4 14 2 13 1 10 6 12 11 9 5 3 8 4 1 14 8 13 6 2 11 15 12 9 7 3 10 5 0 15 12 8 2 4 9 1 7 5 11 3 14 10 0 6 13

[0049] S1 Replacement Table

[0050] 15 1 8 14 6 11 3 4 9 7 2 13 12 0 5 10 3 13 4 7 15 2 8 14 12 0 1 10 6 9 11 5 0 14 7 11 10 4 13 1 5 8 12 6 9 3 2 15 13 8 10 1 3 15 4 2 11 6 7 12 0 5 14 9

[0051] S2 Replacement Table

[0052] 10 0 9 14 6 3 15 5 1 13 12 7 11 4 2 8 13 7 0 9 3 4 6 10 2 8 5 14 12 11 15 1 13 6 4 9 8 15 3 0 11 1 2 12 5 10 14 7 1 10 13 0 6 9 8 7 4 15 14 3 11 5 2 12

[0053] S3 Replacement Table

[0054] 7 13 14 3 0 6 9 10 1 2 8 5 11 12 4 15 13 8 11 5 6 15 0 3 4 7 2 12 1 10 14 9 10 6 9 0 12 11 7 13 15 1 3 14 5 2 8 4 3 15 0 6 10 1 13 8 9 4 5 11 12 7 2 14

[0055] S4 Replacement Table

[0056] 2 12 4 1 7 10 11 6 8 5 3 15 13 0 14 9 14 11 2 12 4 7 13 1 5 0 15 10 3 9 8 6 4 2 1 11 10 13 7 8 15 9 12 5 6 3 0 14 11 8 12 7 1 14 2 13 6 15 0 9 10 4 5 3

[0057] S5 Replacement Table

[0058]

[0059]

[0060] S6 Replacement Table

[0061] 4 11 2 14 15 0 8 13 3 12 9 7 5 10 6 1 13 0 11 7 4 9 1 10 14 3 5 12 2 15 8 6 1 4 11 13 12 3 7 14 10 15 6 8 0 5 9 2 6 11 13 8 1 4 10 7 9 5 0 15 14 2 3 12

[0062] S7 Replacement Table

[0063] 13 2 8 4 6 15 11 1 10 9 3 14 5 0 12 7 1 15 13 8 10 3 7 4 12 5 6 11 0 14 9 2 7 11 4 1 9 12 14 2 0 6 10 13 15 3 5 8 2 1 14 7 4 10 8 13 15 12 9 0 3 5 6 11

[0064] S8 Replacement Table

[0065] Taking the S8 box as an example, the input 110011, the first and sixth bits (most significant and least significant bits) combine to form 11 (binary), which is 3 in decimal. Therefore, the row number in the S8 box is 3. Correspondingly, the calculated column is: the second to fifth bits of the original data are 1001 (binary), which is 9 in decimal. Therefore, the column number in the S8 box is 9. Since the number in row 03, column 09 of S8 box is 12, which is 1100 in binary, we use binary 1100 to replace 110011. In this way, the S-box substitution achieves non-linear operation, improving the security of the password.

[0066] Similar to IP permutation, P-box permutation shuffles and rearranges 32-bit data. The rules for P-box permutation are as follows.

[0067] 16 7 20 21 29 12 28 17 1 15 23 26 5 18 31 10 2 8 24 14 32 27 3 9 19 13 30 6 22 11 4 25

[0068] P-box replacement table

[0069] Understandably, diffusion and confusion are two fundamental methods in cryptographic design, aimed at resisting statistical analysis of the cryptosystem. In block cipher design, fully utilizing diffusion and confusion can effectively prevent adversaries from deducing the plaintext or key from the statistical properties of the ciphertext. Diffusion and confusion are the foundation of modern block cipher design. Diffusion involves making each bit in the plaintext influence many bits in the ciphertext, or in other words, making each bit in the ciphertext influenced by many bits in the plaintext, thus concealing the statistical properties of the plaintext. Confusion involves making the statistical relationship between the ciphertext and the key as complex as possible, so that even if some statistical properties of the ciphertext are obtained, the key cannot be deduced. Using complex nonlinear substitution transformations can achieve a relatively good confusion effect.

[0070] In some embodiments, the multi-round confusion and diffusion can be performed through multiplication and iteration, or other nonlinear substitution transformations, which are not specifically limited here.

[0071] In this way, the computational burden in the step of obtaining the second sequence by performing multiple rounds of confusion and diffusion on the first sequence is transferred to the NPU, which can achieve parallel processing of big data, make full use of the hardware computing power of the NPU, and thus save CPU memory resources and reduce the computational burden on the CPU.

[0072] Step 203: The second sequence is reverse-combined using a neural network processor to obtain ciphertext data.

[0073] Recombination and inverse combination are a pair of inverse operations.

[0074] In some embodiments, in step 203, the second sequence can be subjected to inverse IP permutation by a neural network processor to obtain ciphertext data.

[0075] Inverse IP permutation is the inverse operation of IP permutation, and can also be written as IP permutation. -1 The rules for IP replacement and reverse IP replacement are as follows.

[0076] 40 8 48 16 56 24 64 32 39 7 47 15 55 23 63 31 38 6 46 14 54 22 62 30 37 5 45 13 53 21 61 29 36 4 44 12 52 20 60 28 35 3 43 11 51 19 59 27 34 2 42 10 50 18 58 26 33 1 41 9 49 17 57 25

[0077] Reverse IP Replacement Table

[0078] Embodiments of the present application provide a data encryption method, a data encryption apparatus, and an electronic device. The method includes: obtaining a block cipher corresponding to multimedia data via a neural network processor, and recombining the block cipher to obtain a first sequence; wherein the block cipher is obtained by a general-purpose processor performing feature extraction on the multimedia data and performing binary format conversion on the extraction result; performing multiple rounds of confusion and diffusion on the first sequence through the general-purpose processor and the neural network processor to obtain a second sequence; performing inverse combination on the second sequence via the neural network processor to obtain ciphertext data; wherein the recombination and the inverse combination are a pair of inverse operations. In this way, the feature extraction of the multimedia data is first performed to obtain the corresponding block cipher, and then the block cipher is recombined to obtain the first sequence, which can realize efficient extraction of the feature quantity of the multimedia data; then, multiple rounds of confusion and diffusion are performed on the first sequence to obtain the second sequence, which can implement parallel processing of large data through the NPU, fully utilize the hardware computing power of the NPU, and improve execution efficiency; finally, the second sequence is inversely combined to obtain ciphertext data, which can achieve efficient encryption in the data encryption process, save the memory resources of the CPU, reduce the computing pressure of the CPU, and improve the business processing speed.

[0079] In some embodiments, step 202 of performing multiple rounds of confusion and diffusion on the first sequence through the general-purpose processor and the neural network processor to obtain the second sequence includes:

[0080] Step A1: Dividing the first sequence into an R0 data block and an L0 data block via the neural network processor;

[0081] Step A2: Performing the n-th round of confusion and diffusion by the neural network processor based on the R0 data block and the L0 data block; wherein 1≤n≤N, n is a positive integer, and N is the total number of rounds of the multiple rounds of confusion and diffusion;

[0082] Step A3: Judging, by the neural network processor, the relationship between n and N, and obtaining the second sequence according to the result obtained from the first n rounds of confusion and diffusion in a case where the relationship satisfies a preset condition.

[0083] In the embodiments of the present application, the R0 data block, the L0 data block and the like are all composed of data, which can be understood as multi-byte binary data.

[0084] In an optional embodiment, in step A1, the NPU divides the 64-bit first sequence into a left part and a right part, the R0 data block represents the right part, the L0 represents the left part, and each part is 32 bits long.

[0085] In an optional embodiment, step A2 includes: if n=1 and n<N, performing the first round of confusion and diffusion on the R0 data block and the L0 data block; if 1<n<N, obtaining, by the neural network processor, Rn-1 Data blocks and L n-1 The data block undergoes the nth round of obfuscation and diffusion.

[0086] In an optional embodiment, step A3 includes: when n = N, processing R through a neural network processor. n Data blocks and L n The data blocks are combined to obtain the second sequence.

[0087] In this way, the execution of the DES algorithm is split into two parts: logical operations executed by the CPU and parallel operations executed by the NPU, thereby saving CPU memory resources and reducing the CPU's computational pressure.

[0088] In some embodiments, prior to step A2, the method further includes:

[0089] The initial key is subjected to a first selection permutation by a neural network processor to obtain a permutation sequence;

[0090] The permutation sequence is divided into C0 and D0 data blocks using a neural network processor;

[0091] The shift parameters corresponding to the nth round are obtained using a general-purpose processor;

[0092] The C0 data block is shifted according to the shift parameters by a general-purpose processor to obtain C. n Data block, D0 data block is shifted according to the shift parameter to obtain D n Data blocks;

[0093] C through neural network processor n Data blocks and D n The data blocks are combined, and the combined result is subjected to a second selection permutation to obtain the nth subkey.

[0094] In this embodiment of the application, the initial key can be obtained by converting the original 8-character hexadecimal key into a 64-bit binary key through the CPU.

[0095] For example, the hexadecimal key K is: K = 133457799BBCDFF1;

[0096] In binary form, K = 00010011 00110100 01010111 01111001 1001101110111100 11011111 11110001.

[0097] In an optional embodiment, the first selection permutation may include a PC1 permutation, which reduces the 64-bit initial key to a 56-bit key, and the permutation sequence can be a 56-bit key. This removes the 8-bit parity bit from the 64-bit initial key through the subtraction operation.

[0098] For example, the rules for PC1 permutation are as follows.

[0099] 57 49 41 33 25 17 9 1 58 50 42 34 26 18 10 2 59 51 43 35 27 19 11 3 60 52 44 36 63 55 47 39 31 23 15 7 62 54 46 38 30 22 14 6 61 53 45 37 29 21 13 5 28 20 12 4

[0100] PC1 Replacement Table

[0101] In an optional embodiment, dividing the permutation sequence into C0 and D0 data blocks by a neural network processor includes: after obtaining a 56-bit key, dividing it into two parts, each 28 bits.

[0102] In this embodiment, the shift parameter may include the number of bits to the left for each data element in the data block. That is, depending on the number of rounds, each data element in the C0 and D0 data blocks is cyclically shifted left by 1 or 2 bits, respectively. The number of bits shifted in each round can be obtained from the shift parameter table.

[0103] Number of rounds 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Number of digits 1 1 2 2 2 2 2 2 1 2 2 2 2 2 2 1

[0104] Shift parameter table

[0105] In an optional embodiment, the second alternative permutation may include the PC2 permutation.

[0106] The PC2 permutation works similarly to the PC1 permutation, reducing the 56-bit key to 48 bits. The rules for the PC2 permutation are as follows.

[0107] 14 17 11 24 1 5 3 28 15 6 21 10 23 19 12 4 26 8 16 7 27 20 13 2 41 52 31 37 47 55 30 40 51 45 33 48 44 49 39 56 34 53 46 42 50 36 29 32

[0108] PC2 Replacement Table

[0109] For example, before the first obfuscation and diffusion, the general processor obtains the corresponding shift parameter as 1 according to the shift parameter table. That is, the general processor cyclically shifts each bit of data in the C0 data block one bit to the left to obtain the C1 data block, and cyclically shifts each bit of data in the D0 data block one bit to the left to obtain the D1 data block. The neural network processor combines the C1 data block and the D1 data block, and performs a second selection permutation on the combination result to obtain the first subkey.

[0110] In this way, the subtraction operation in the key derivation process is transferred to the NPU for processing, making full use of the NPU's hardware computing power. The CPU is only responsible for shifting the data in the key, saving CPU memory resources and reducing the CPU's computational pressure.

[0111] In some embodiments, step A2 performs the n-th round of confusion and diffusion by the neural network processor based on the R0 data block and the L0 data block, including:

[0112] Step B1: performing expansion processing on R by the neural network processor n-1 the data block to obtain the n-th expanded data block;

[0113] Step B2: performing an XOR operation on the n-th expanded data block and the n-th subkey by the neural network processor to obtain the n-th operation result;

[0114] Step B3: performing confusion on the n-th operation result by the general-purpose processor, and performing diffusion on the compressed processed result by the neural network processor to obtain the (n+1)-th operation result;

[0115] Step B4: using R by the neural network processor n-1 the data block to assign a value to L n the data block;

[0116] Step B5: updating n to n+1 by the neural network processor, and returning to execute the judgment on the relationship between n and N.

[0117] In the embodiment of the present application, if n=1 and n<N, before step B1, the method includes: obtaining the R0 data block and the L0 data block obtained in step A1.

[0118] In the embodiment of the present application, if 1<n<N, before step B1, the method includes: obtaining R by the neural network processor n-1 the data block and L n-1 the data block. The R n-1 data block and the L n-1 data block are obtained by processing the R0 data block and the L0 data block.

[0119] In an optional embodiment, the expansion processing in step B1 may include: performing expansion processing through E permutation.

[0120] The function of the E permutation is to expand a 32-bit input into 48 bits, and the E permutation rule is shown as follows.

[0121] 32 1 2 3 4 5 4 5 6 7 8 9 8 9 10 11 12 13 12 13 14 15 16 17 16 17 18 19 20 21 20 21 22 23 24 25 24 25 26 27 28 29 28 29 30 31 32 1

[0122] E permutation table

[0123] In an optional embodiment, the confusion processing on the n-th operation result by the general-purpose processor in step B3 may be implemented through S-box substitution; the diffusion processing on the compressed processed result by the neural network processor may be implemented through P-box permutation.

[0124] For example, the nth round of obfuscation and diffusion based on R0 and L0 data blocks by the neural network processor can be achieved through the following steps:

[0125] During the 10th round of obfuscation and diffusion, the left 32 bits and right 32 bits of data from the 9th round were obtained;

[0126] The NPU uses the neural network gather operator E permutation to expand the right-hand 32-bit data to 48-bit data;

[0127] The NPU uses the neural network bitwise_xor operator to perform an XOR operation on 48-bit data and 48-bit derived key;

[0128] The CPU performs an S-box substitution operation on the 48-bit data to obtain 32-bit data.

[0129] The NPU uses the neural network gather operator to perform P-box permutation operations on 32-bit data.

[0130] The NPU uses the neural network bitwise_xor operator to perform a P-box permutation result XOR with the original left half of the 32-bit part, and then swaps the left and right halves.

[0131] The NPU updates the round number from 10 to 11 and returns to perform a judgment on the relationship between 11 and N.

[0132] In this way, operations requiring a large amount of computing power, such as expansion, XOR operations, and multiple permutations, are transferred to the NPU. Since the NPU has powerful parallel computing capabilities, it can make full use of the hardware computing power of the NPU, so that the DES algorithm has high execution efficiency and data throughput, thereby saving CPU memory resources and reducing the CPU's computing pressure.

[0133] In some embodiments, if the relationship between n and N satisfies a preset condition including n = N, then step A3, under the condition that the relationship satisfies the preset condition, obtains the second sequence based on the results of the first n rounds of confusion and diffusion, including:

[0134] R through a neural network processor n Data blocks and L n The data blocks are combined to obtain the second sequence.

[0135] The results obtained from the first n rounds of confusion and diffusion include R. n Data blocks and L n Data block.

[0136] In this embodiment of the application, after obtaining the output of the Nth round of obfuscation and diffusion, the left and right halves of the output are not swapped, but the two halves are merged to form a data block.

[0137] In this embodiment of the application, N can be 16.

[0138] Understandably, the DES algorithm requires multiple rounds of iterative computation, with each iteration generating a subkey, resulting in a total of 16 subkeys. After 16 rounds of identical computation, the input 64-bit plaintext string is converted into a 64-bit ciphertext string. During these 16 iterations, a 56-bit key is used to encrypt the 64-bit plaintext string 16 times, yielding the 64-bit ciphertext string. Of these, 64 bits are used as the key, 56 bits are actually used, and the remaining 8 bits are used for parity checking.

[0139] In this way, the ciphertext data is obtained by inversely combining the output results of multiple rounds of iterative operations. This enables efficient encryption during the data encryption process, saves CPU memory resources, reduces CPU computational pressure, and ensures the security of sensitive data.

[0140] In some embodiments, after step 203, the method further includes: outputting and displaying the encrypted data via a general-purpose processor.

[0141] For example, after obtaining the encrypted data, the encrypted data is sent to the neural network processor through a general-purpose processor. The general-purpose processor and the neural network processor decrypt the encrypted data to obtain a feature map, and then restore the feature map to obtain multimedia data.

[0142] It is understandable that decryption is the reverse process of encryption, using a subkey to perform the reverse process of the above steps, and performing 16 rounds of iteration, which will not be elaborated here.

[0143] In this way, given the derived key, decryption can be performed directly using the existing key, improving the ease of decryption.

[0144] In some embodiments, the scheme provided in this application can also be combined with the Triple DES (3DES) encryption algorithm. That is, the DES encryption algorithm is applied three times to each data block according to the method provided in the above embodiments, and three encryption and decryption operations are performed. The encryption process is encryption, decryption, encryption, and the decryption process is to perform decryption, encryption, decryption operations in the order of key 3, key 2, and key 1.

[0145] The following examples illustrate the data encryption methods in one or more of the above embodiments.

[0146] Figure 3 Example 1 of an optional data encryption method provided for embodiments of this application.

[0147] Step 301: The CPU converts the plaintext data into a 64-bit vector.

[0148] The size of the plaintext data can be 8 bytes.

[0149] Step 302: The NPU uses the neural network gather operator to perform IP permutation, recombining the 64-bit vector.

[0150] After obtaining the combined 64-bit vector, the 64-bit vector is divided into two parts, each with 32 bits.

[0151] Step 303: Repeat the iteration for 16 rounds.

[0152] Step 304: The NPU uses the neural network gather operator to perform IP... -1 The permutation yields a 64-bit vector containing the ciphertext data.

[0153] Step 305: The CPU outputs encrypted data.

[0154] It should be noted that the descriptions of the same steps and contents as in other embodiments in this embodiment can be found in the descriptions in other embodiments, and will not be repeated here.

[0155] Figure 4 An example of an optional key generation method provided for embodiments of this application.

[0156] Step 401: The CPU converts the initial key Key into a 64-bit vector.

[0157] The Key is 8 bytes in size.

[0158] Step 402: The NPU uses the neural network gather operator to perform PC1 permutation, reducing the DES key from 64 bits to 56 bits.

[0159] Step 403: The CPU performs vector shifting on the obtained 56-bit key in different rounds.

[0160] Step 404: The NPU uses the neural network gather operator to perform PC2 permutation, generating different 48-bit subkeys from the 56-bit key.

[0161] It should be noted that the descriptions of the same steps and contents as in other embodiments in this embodiment can be found in the descriptions in other embodiments, and will not be repeated here.

[0162] Figure 5 Example 2 of an optional data encryption method provided for embodiments of this application.

[0163] Step 501: The NPU uses the neural network gather operator to perform E permutation, expanding the 32-bit vector on the right to a 48-bit vector.

[0164] Step 502: The NPU uses the neural network bitwise_xor operator to perform an XOR operation on the 48-bit vector and the 48-bit derived key K.

[0165] Step 503: The CPU performs a substitution operation on the 48-bit data S-box to obtain 32-bit data.

[0166] Step 504: The NPU uses the neural network gather operator to perform P-box permutation on the 32-bit data.

[0167] Step 505: The NPU uses the neural network bitwise_xor operator to perform an XOR operation between the result of the P-box permutation and the original left half of the 32 bits.

[0168] In step 505, the left and right halves of the output of the XOR operation are swapped.

[0169] It should be noted that the descriptions of the same steps and contents as in other embodiments in this embodiment can be found in the descriptions in other embodiments, and will not be repeated here.

[0170] Embodiments of this application provide a data encryption device that can be applied to... Figure 1 In a corresponding embodiment of a data encryption method, refer to Figure 6 As shown, the data encryption device 6 includes:

[0171] The first processing module 601 is used to obtain the block cipher corresponding to the multimedia data through a neural network processor, and to recombine the block cipher to obtain a first sequence; wherein, the block cipher is obtained by a general-purpose processor extracting features from the multimedia data and converting the extracted results into binary format;

[0172] The first processing module 601 and the second processing module 602 are used to perform multiple rounds of confusion and diffusion on the first sequence through a general-purpose processor and a neural network processor to obtain the second sequence.

[0173] The first processing module 601 is also used to perform inverse combination of the second sequence through a neural network processor to obtain ciphertext data; wherein recombination and inverse combination are a pair of inverse operations.

[0174] In other embodiments of this application, the first processing module 601 is further configured to divide the first sequence into R0 data blocks and L0 data blocks using the neural network processor;

[0175] The first processing module 601 and the second processing module 602 are further configured to perform the nth round of obfuscation and diffusion based on the R0 data block and the L0 data block; where 1≤n≤N, and n is a positive integer, and N is the total number of rounds of obfuscation and diffusion.

[0176] The first processing module 601 is further configured to determine the relationship between n and N through the neural network processor, and, if the relationship satisfies a preset condition, obtain the second sequence based on the results obtained from the first n rounds of confusion and diffusion.

[0177] In other embodiments of this application, the first processing module 601 is further configured to perform expansion processing on the R0 data block through a neural network processor to obtain a first expanded data block; and to perform an XOR operation on the first expanded data block and the first subkey through the neural network processor to obtain a first operation result.

[0178] The second processing module 602 is also used to perform obfuscation processing on the first calculation result through a general-purpose processor;

[0179] The first processing module 601 is also used to diffuse the result of the obfuscation process through the neural network processor to obtain the second operation result; and to assign the value of the L1 data block to the R0 data block through the neural network processor.

[0180] The neural network processor updates n to 2 and returns the result, determining the relationship between n and N.

[0181] In other embodiments of this application, the first processing module 601 is further configured to: obtain R through a neural network processor n-1 Data blocks and L n-1 Data blocks; where R n-1 Data blocks and L n-1 The data block is obtained by processing the R0 data block and the L0 data block; the R0 data block is processed by a neural network processor. n-1 The data block is expanded to obtain the nth expanded data block; the nth expanded data block and the nth subkey are XORed by the neural network processor to obtain the nth operation result;

[0182] The second processing module 602 is also used to obfuscate the result of the nth operation.

[0183] The first processing module 601 is further configured to: diffuse the result of the compression process using a neural network processor to obtain the (n+1)th operation result; and combine the (n+1)th operation result with L using a neural network processor. n-1 Perform an XOR operation on the data block to obtain R. n Data blocks; processed by a neural network processor using R n-1 Data block given to L n The data block is assigned a value; the neural network processor updates n to n+1 and returns the result, determining the relationship between n and N.

[0184] In other embodiments of this application, the first processing module 601 is further configured to:

[0185] R through a neural network processor n Data blocks and L n The data blocks are combined to obtain the second sequence, where the results obtained from the first n rounds of confusion and diffusion include R. n Data blocks and L n Data block.

[0186] In other embodiments of this application, the first processing module 601 is further configured to: perform a first selection permutation on the initial key using a neural network processor to obtain a permutation sequence; and divide the permutation sequence into C0 data blocks and D0 data blocks using a neural network processor.

[0187] The second processing module 602 is further configured to obtain the shift parameters corresponding to the nth round through a general-purpose processor; and to shift the C0 data block according to the shift parameters using the general-purpose processor to obtain C. n Data block, D0 data block is shifted according to the shift parameter to obtain D n Data blocks;

[0188] The first processing module 601 is also used to process C through a neural network processor. n Data blocks and D n The data blocks are combined, and the combined result is subjected to a second selection permutation to obtain the nth subkey.

[0189] In other embodiments of this application, the first processing module 601 is further configured to perform initial address IP permutation on the block cipher using a neural network processor to obtain a first sequence.

[0190] In other embodiments of this application, the first processing module 601 is further configured to perform inverse IP permutation on the second sequence through a neural network processor to obtain ciphertext data; wherein, inverse IP permutation is the inverse operation of IP permutation.

[0191] Embodiments of this application provide an electronic device that can be applied to... Figure 1 The method provided in the corresponding embodiment is referred to Figure 7 As shown, the electronic device 7 ( Figure 7 Electronic devices 7 and Figure 6 The data encryption device 6 (corresponding to the one in the middle) includes: a neural network processor 701, a general-purpose processor 702, a memory 703, and a communication bus 704, wherein:

[0192] The communication bus 704 is used to realize the communication connection between the neural network processor 701, the general-purpose processor 702 and the memory 703.

[0193] The neural network processor 701 and the general-purpose processor 702 are used to execute the data encryption program stored in the memory 703 to perform the following steps:

[0194] The neural network processor 701 obtains the block cipher corresponding to the multimedia data and recombines the block cipher to obtain the first sequence; wherein, the block cipher is obtained by the general-purpose processor extracting features from the multimedia data and converting the extracted results into binary format;

[0195] The neural network processor 701 and the general-purpose processor 702 perform multiple rounds of confusion and diffusion on the first sequence to obtain the second sequence;

[0196] The neural network processor 701 performs inverse recombination on the second sequence to obtain ciphertext data; wherein recombination and inverse recombination are a pair of inverse operations.

[0197] In other embodiments of this application, the neural network processor 701 and the general-purpose processor 702 are used to execute a data encryption program stored in the memory 703 to perform the following steps:

[0198] The neural network processor 701 divides the first sequence into R0 data blocks and L0 data blocks;

[0199] The neural network processor 701 and the general-purpose processor 702 perform the nth round of obfuscation and diffusion based on the R0 data block and the L0 data block; where 1≤n≤N, and n is a positive integer, and N is the total number of rounds of obfuscation and diffusion.

[0200] The neural network processor 701 determines the relationship between n and N, and if the relationship satisfies a preset condition, obtains the second sequence based on the results obtained from the first n rounds of confusion and diffusion.

[0201] In other embodiments of this application, the neural network processor 701 and the general-purpose processor 702 are used to execute a data encryption program stored in the memory 703 to perform the following steps:

[0202] The neural network processor 701 expands the R0 data block to obtain a first expanded data block; the neural network processor then performs an XOR operation on the first expanded data block and the first subkey to obtain a first operation result.

[0203] The general-purpose processor 702 performs obfuscation processing on the first operation result;

[0204] The neural network processor 701 diffuses the result of the obfuscation process to obtain the second computation result;

[0205] The neural network processor 701 assigns values ​​to the L1 data block using the R0 data block;

[0206] The neural network processor 701 updates n to 2 and returns to perform the judgment on the relationship between n and N.

[0207] In other embodiments of this application, the neural network processor 701 and the general-purpose processor 702 are used to execute a data encryption program stored in the memory 703 to perform the following steps:

[0208] The neural network processor 701 obtains R n-1 Data blocks and L n-1 Data blocks; where R n-1 Data blocks and L n-1 The data block is obtained by processing the R0 data block and the L0 data block;

[0209] Neural Network Processor 701 for R n-1 The data block is expanded to obtain the nth expanded data block;

[0210] The neural network processor 701 performs an XOR operation on the nth extended data block and the nth subkey to obtain the nth operation result;

[0211] The general-purpose processor 702 obfuscates the result of the nth operation;

[0212] The neural network processor 701 diffuses the result of the compression process to obtain the (n+1)th operation result;

[0213] The neural network processor 701 combines the result of the (n+1)th operation with L n-1 Perform an XOR operation on the data block to obtain R. n Data blocks;

[0214] The 701 Neural Network Processor uses R n-1 Data block given to L n Assign values ​​to the data blocks;

[0215] The neural network processor 701 updates n to n+1 and returns to perform the judgment on the relationship between n and N.

[0216] In other embodiments of this application, the neural network processor 701 is used to execute a data encryption program stored in the memory 703 to perform the following steps:

[0217] R n Data blocks and L n The data blocks are combined to obtain the second sequence, where the results obtained from the first n rounds of confusion and diffusion include R. n Data blocks and L n Data block.

[0218] In other embodiments of this application, the neural network processor 701 and the general-purpose processor 702 are used to execute a data encryption program stored in the memory 703 to perform the following steps:

[0219] The neural network processor 701 performs a first selection permutation on the initial key to obtain a permutation sequence;

[0220] The neural network processor 701 divides the permutation sequence into C0 data blocks and D0 data blocks;

[0221] The general-purpose processor 702 obtains the shift parameters corresponding to the nth round;

[0222] The general-purpose processor 702 shifts the C0 data block according to the shift parameters to obtain C. n Data block, D0 data block is shifted according to the shift parameter to obtain D n Data blocks;

[0223] Neural Network Processor 701 vs C n Data blocks and D n The data blocks are combined, and a second selection permutation is performed on the combined result to obtain the nth subkey.

[0224] In other embodiments of this application, the neural network processor 701 is used to execute a data encryption program stored in the memory 703 to perform the following steps:

[0225] The first sequence is obtained by performing initial address IP substitution on the block cipher.

[0226] In other embodiments of this application, the neural network processor 701 is used to execute a data encryption program stored in the memory 703 to perform the following steps:

[0227] The second sequence is subjected to inverse IP permutation to obtain ciphertext data; where inverse IP permutation is the inverse operation of IP permutation.

[0228] As an example, a general-purpose processor can be an integrated circuit chip with signal processing capabilities, such as a central processing unit (CPU), a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The CPU can be a microprocessor or any conventional processor. As another example, a neural network processor can be an embedded neural network processor characterized by a "data-driven parallel computing" architecture, adept at processing massive amounts of multimedia data such as video and images.

[0229] It should be noted that the specific implementation process of the steps executed by the processor in this embodiment can be referred to Figure 1 The implementation process of the method provided in the corresponding embodiments will not be described in detail here.

[0230] The electronic device provided in this application embodiment can obtain the block cipher corresponding to multimedia data through a neural network processor, and recombine the block cipher to obtain a first sequence. The block cipher is obtained by a general-purpose processor extracting features from the multimedia data and converting the extracted results into binary format. The first sequence is then subjected to multiple rounds of obfuscation and diffusion by the general-purpose processor and the neural network processor to obtain a second sequence. Finally, the second sequence is inversely combined by the neural network processor to obtain ciphertext data. Recombination and inverse combination are inverse operations. This approach, by first extracting features from the multimedia data to obtain the corresponding block cipher, and then recombinating the block cipher to obtain the first sequence, achieves efficient feature extraction of the multimedia data. Next, by performing multiple rounds of obfuscation and diffusion on the first sequence to obtain the second sequence, parallel processing of large datasets can be achieved, fully utilizing the hardware computing power of the NPU and improving execution efficiency. Finally, the inverse combination of the second sequence to obtain ciphertext data enables efficient encryption during the data encryption process, saving CPU memory resources and reducing CPU computational pressure.

[0231] Embodiments of this application provide a computer-readable storage medium storing one or more programs that can be executed by one or more processors to perform, as follows: Figure 1 The implementation process of the data encryption method provided in the corresponding embodiments will not be described in detail here.

[0232] It should be noted that the descriptions of the storage medium and device embodiments above are similar to the descriptions of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0233] The aforementioned computer storage media / memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM), etc.; or it can be various terminals that include one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0234] It should be understood that the terms "an embodiment," "an embodiment," "an embodiment of this application," "the foregoing embodiment," "some embodiments," or "some implementations" mentioned throughout the specification mean that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, the phrases "an embodiment," "an embodiment," "an embodiment of this application," "the foregoing embodiment," "some embodiments," or "some implementations" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0235] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0236] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0237] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0238] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0239] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0240] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0241] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0242] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, or the parts that contribute to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0243] It is worth noting that the accompanying drawings in this application are only for illustrating the schematic positions of various devices on the terminal device and do not represent their actual positions in the terminal device. The actual positions of each device or area may be changed or shifted according to the actual situation (e.g., the structure of the terminal device). Furthermore, the proportions of different parts in the terminal device in the drawings do not represent the actual proportions.

[0244] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data encryption method, characterized in that, The method includes: The block ciphers corresponding to the multimedia data are obtained through a neural network processor, and the block ciphers are recombined to obtain a first sequence; wherein, the block ciphers are obtained by a general-purpose processor extracting features from the multimedia data and converting the extraction results into binary format; The first sequence is subjected to multiple rounds of obfuscation and diffusion by the general-purpose processor and the neural network processor to obtain the second sequence; wherein the general-purpose processor is used for obfuscation processing and the neural network processor is used for diffusion processing. The second sequence is inversely combined using a neural network processor to obtain ciphertext data; wherein, the recombination and the inverse combination are a pair of inverse operations. The process of performing multiple rounds of obfuscation and diffusion on the first sequence using the general-purpose processor and the neural network processor to obtain the second sequence includes: dividing the first sequence into an R0 data block and an L0 data block by the neural network processor; performing the n-th round of confusion and diffusion by the general-purpose processor and the neural network processor based on the R0 data block and the L0 data block; when 1≤n<N, obtaining R by the neural network processor n-1 data block and L n-1 data block; performing expansion permutation processing on the R by the neural network processor n-1 data block to obtain an n-th expanded data block; performing an XOR operation on the n-th expanded data block and an n-th subkey by the neural network processor to obtain an n-th operation result; performing confusion processing on the n-th operation result by the general-purpose processor, and performing diffusion on the confusion processed result by the neural network processor to obtain an n+1-th operation result; performing an XOR operation on the n+1-th operation result and the L by the neural network processor n-1 data block to obtain R n data block; assigning the R by the neural network processor n-1 data block to L n data block; updating n to n+1 by the neural network processor; when n=N, combining the R by the neural network processor n data block and the L n data block to obtain the second sequence; where 1≤n≤N, n is a positive integer, and N is the total number of rounds of the multi-round confusion and diffusion.

2. The method according to claim 1, characterized in that, Before performing n rounds of obfuscation and diffusion on the R0 data block and the L0 data block using the general-purpose processor and the neural network processor, the method further includes: The initial key is permuted using the neural network processor to obtain the permutation sequence; The neural network processor divides the permutation sequence into C0 data blocks and D0 data blocks; The shift parameters corresponding to the nth round are obtained through the general-purpose processor; The general-purpose processor shifts the C0 data block according to the shift parameters to obtain C. n The data block, D0, is shifted according to the shift parameter to obtain D. n Data blocks; The neural network processor processes the C n Data blocks and the D n The data blocks are combined, and the combined result is PC2 permuted to obtain the nth subkey.

3. The method according to any one of claims 1 to 2, characterized in that, The first sequence is obtained by recombining the block cipher using a neural network processor, including: The neural network processor performs initial address IP permutation on the block cipher to obtain the first sequence.

4. The method according to claim 3, characterized in that, The ciphertext data is obtained by inversely combining the second sequence using the neural network processor, including: The ciphertext data is obtained by performing an inverse IP permutation on the second sequence using the neural network processor; wherein the inverse IP permutation is the inverse operation of the IP permutation.

5. A data encryption device, characterized in that, The device includes: The first processing module is used to obtain the block cipher corresponding to the multimedia data through a neural network processor, and to recombine the block cipher to obtain a first sequence; wherein the block cipher is obtained by a general-purpose processor extracting features from the multimedia data and converting the extraction results into binary format; The first processing module and the second processing module are used to perform multiple rounds of obfuscation and diffusion on the first sequence through the general-purpose processor and the neural network processor to obtain the second sequence; wherein, the general-purpose processor is used to perform obfuscation processing and the neural network processor is used to perform diffusion processing; The first processing module is further configured to perform inverse combination on the second sequence through the neural network processor to obtain ciphertext data; wherein, the recombination and the inverse combination are a pair of inverse operations; Wherein, the first processing module and the second processing module are specifically configured to divide the first sequence into an R0 data block and an L0 data block via the neural network processor; perform the n-th round of confusion and diffusion based on the R0 data block and the L0 data block through the general-purpose processor and the neural network processor; when 1≤n<N, obtain R via the neural network processor n-1 data block and L n-1 data block; perform expansion permutation processing on the R via the neural network processor n-1 data block to obtain the n-th expanded data block; perform an XOR operation on the n-th expanded data block and the n-th sub-key via the neural network processor to obtain an n-th operation result; perform confusion processing on the n-th operation result via the general-purpose processor, and perform diffusion on the confusion-processed result via the neural network processor to obtain an (n+1)-th operation result; perform an XOR operation on the (n+1)-th operation result and the L via the neural network processor n-1 data block to obtain R n data block; assign the R via the neural network processor n-1 data block to L n data block via the neural network processor; update n to n+1 via the neural network processor; when n=N, combine the R via the neural network processor n data block and the L n data block to obtain the second sequence; wherein 1≤n≤N, n is a positive integer, and N is the total number of rounds of multi-round confusion and diffusion.

6. An electronic device, characterized in that, The electronic device includes: a neural network processor, a general-purpose processor, a memory, and a communication bus; The communication bus is used to realize communication connections between the neural network processor, the general-purpose processor, and the memory; The neural network processor and the general-purpose processor are used to execute the data encryption program stored in the memory to implement the data encryption method as described in any one of claims 1 to 4.

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