A circuit and method for extracting the quantization margin of a time-to-digital converter

Abstract

This invention belongs to the technical field of time-to-digital converters (TD-SCDs), specifically disclosing a circuit and method for extracting the quantization margin of a time-to-digital converter. This invention adds an XOR gate and a transmission gate unit to the existing time-to-digital converter to extract the time margin, and outputs it through a dynamic OR gate. The circuit provided by this invention can extract the time margin that the time-to-digital converter cannot quantize, accurately measure the quantization error, and thus allow for further measurement of the time margin, improving the overall measurement accuracy of the time-to-digital converter. The circuit and method provided by this invention can not only extract the time margin that the time-to-digital converter cannot quantize, but also accurately determine the position of the trigger signal in the delay chain.

Description

Technical Field

[0001] This invention belongs to the field of time-to-digital converter technology, specifically relating to a circuit and method for extracting the quantization margin of a time-to-digital converter. Background Technology

[0002] A time-to-digital converter (TDC) is an instrument used in electronic instruments or signal processing to convert continuous analog signals (time) into discrete digital signals. The TDC outputs the recorded time for each pulse compared to a set starting point. TDCs are generally used in applications measuring time intervals ranging from 1 nanosecond to picosecond.

[0003] like Figure 1 The diagram shows the circuit schematic of an existing TDC (Thermal Design DC), with input signals start and stop. When the rising edge of the start signal arrives, the signal begins to propagate in the delay chain. When the rising edge of the stop signal arrives, which is the effective clock edge of the D flip-flop, the flip-flop samples the start signal and outputs a set of thermometer codes. These thermometer codes are then converted into binary codes using a thermometer code converter. However, when the time interval between the input signals start and stop is less than the delay unit τ, the TDC cannot quantize the time interval, resulting in a large quantization error and poor performance. Summary of the Invention

[0004] The purpose of this invention is to provide a circuit for extracting the quantization margin of a time-to-digital converter, so as to improve the measurement accuracy of the entire time-to-digital converter.

[0005] Another objective of this invention is to provide a method for extracting the quantization margin of a time-to-digital converter.

[0006] To achieve the above objectives, the technical solution adopted by this invention is as follows:

[0007] A circuit for extracting the quantization margin of a time-to-digital converter includes n edge-triggered D flip-flops. A trigger signal is input to the data input terminals of each of the n edge-triggered D flip-flops via a delay chain, and a clock signal is input to the clock signal input terminals of each of the n edge-triggered D flip-flops. The delay chain includes a first to an nth delay unit connected in series. A trigger signal is input to the data input terminal of a first edge-triggered D flip-flop via the first delay unit, and a trigger signal is input to the data input terminal of an i-th edge-triggered D flip-flop via the first to i-th delay units connected in series, where i∈[2,n], n≥2.

[0008] The circuit for extracting the quantization margin of a time-to-digital converter further includes n-1 XOR gates, wherein the two inputs of the x-th XOR gate are respectively connected to the outputs of the x-th edge-triggered D flip-flop and the x+1-th edge-triggered D flip-flop; x∈[1,n-1];

[0009] The circuit for extracting the quantization margin of a time-to-digital converter further includes n transmission gate units. Each transmission gate unit includes a timer and a transmission gate connected in series. The data input terminal of the x-th edge-triggered D flip-flop is connected to the input terminal of the corresponding transmission gate through the timer in the x-th transmission gate unit. The output terminal of the x-th XOR gate is connected to the input terminal of the transmission gate in the x-th transmission gate unit. The output terminals of the transmission gates in the first to (n-1)-th transmission gate units are respectively connected to the n-1 input terminals of a dynamic OR gate. The output terminal of the dynamic OR gate serves as the first output terminal of the circuit for extracting the quantization margin of a time-to-digital converter.

[0010] The clock signal is connected to the input terminal of the corresponding transmission gate through the delay unit in the nth transmission gate unit, and the output terminal of the transmission gate in the nth transmission gate unit serves as the second output terminal of the circuit for extracting the quantization margin of the time-to-digital converter.

[0011] As a constraint, the delay time of the delay unit in the transmission gate unit is greater than or equal to the sum of the delay times of the edge-triggered D flip-flop and the XOR gate connected to it.

[0012] The method for extracting the quantization margin of a time-to-digital converter is implemented using the circuit described above. The method is performed in the following steps:

[0013] S1. Input a trigger signal into the delay chain, and the trigger signal is transmitted in the delay chain;

[0014] S2. Input a clock signal to the clock signal input terminal of the first to nth edge D flip-flops;

[0015] Both the trigger signal and the clock signal are rising edge signals;

[0016] S3. Obtain the arrival time of the rising edge signal at the first output terminal;

[0017] S4. Obtain the arrival time of the rising edge signal at the second output terminal;

[0018] S5. Calculate the time difference between the arrival time of the rising edge signal at the second output terminal and the arrival time of the rising edge signal at the first output terminal, which is the time margin that the time-to-digital converter cannot quantize.

[0019] The rising edge signal in step S5 is the rising edge signal that arrives after and is adjacent to the rising edge signal in step S4.

[0020] As a limitation, the binary code output of the first to the (n-1)th XOR gates is measured, and the transmission position of the trigger signal in the delay chain is determined based on the measured binary code. The determination step includes the following process: record the number m of the XOR gate whose output binary code is "1", then the trigger signal is transmitted in the delay chain to the delay units between the mth and (m+1)th delay units; where m∈[1, n-1].

[0021] As a second limitation, the output signals of n-1 XOR gates are used to control the conduction and disconnection of the transmission gates connected to them, one by one.

[0022] The present invention, by adopting the above-described technical solution, achieves the following technical advancements compared to existing technologies:

[0023] (1) The circuit provided by the present invention can extract the time margin that the time digital converter cannot quantize, accurately measure the quantization error, and thus further measure the time margin to improve the measurement accuracy of the entire time digital converter.

[0024] (2) Compared with other quantization margin measurement circuits, the circuit structure designed in this invention is simple and has higher accuracy. The circuit provided by this invention can extract the time margin in the range of 40ps to 80ps.

[0025] (3) Since the trigger has an output delay, the transmission gate has a delay, and the dynamic OR gate has a delay, the present invention adds a matching delay device before each transmission gate to ensure that the XOR gate output signal has already turned on the corresponding transmission gate before the trigger signal enters the transmission gate, thereby ensuring the accuracy of the measurement results.

[0026] (4) The circuit and method provided by the present invention can not only extract the time margin that the time-to-digital converter cannot quantize, but also accurately determine the position of the delay chain of the trigger signal.

[0027] This invention belongs to the field of time-to-digital converter technology and can extract time margins that cannot be quantized by time-to-digital converters. Attached Figure Description

[0028] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0029] In the attached diagram:

[0030] Figure 1 This is a time-to-digital converter in the prior art of this invention;

[0031] Figure 2This is a circuit schematic diagram of Embodiment 1 of the present invention;

[0032] Figure 3 The circuit diagrams are shown for the transmission gates in the first to thirty-first transmission gate units of Embodiment 1 of the present invention.

[0033] Figure 4 This is a circuit diagram of the dynamic OR gate in Embodiment 1 of the present invention;

[0034] Figure 5 This is a circuit schematic diagram of the edge-triggered D flip-flop in Embodiment 1 of the present invention;

[0035] Figure 6 The waveform diagram shows the test results in Embodiment 2 of the present invention. Detailed Implementation

[0036] The preferred embodiments of the present invention will now be described with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the scope of the invention.

[0037] Example 1: A circuit for extracting the quantization margin of a time-to-digital converter

[0038] This embodiment uses a time-to-digital converter containing thirty-two edge-triggered D flip-flops as an example for illustration. Figure 2 As shown, this embodiment adds thirty-two transmission gate units, thirty-one XOR gates D1 to D31, and one thirty-one-bit dynamic OR gate to the existing technology.

[0039] Specifically, such as Figure 2 As shown, the trigger signal `start` is input to the data input terminals of the thirty-two edge-triggered D flip-flops through a delay chain, and the clock signal `stop` is input to the clock signal input terminals of the thirty-two edge-triggered D flip-flops. The delay chain includes delay units numbered 1 to 32 connected in series. The trigger signal is input to the data input terminal of the first edge-triggered D flip-flop through the first delay unit, and the trigger signal is input to the data input terminal of the i-th edge-triggered D flip-flop through the first to i-th delay units connected in series. The delay parameters of the first to thirty-two delay units correspond one-to-one with τ1 to τ2. 32 , i∈[2,32].

[0040] For the thirty-one XOR gates D1 to D31, the two input terminals of the x-th XOR gate Dx are respectively connected to the output terminals of the x-th edge-triggered D flip-flop and the x+1-th edge-triggered D flip-flop; x∈[1,31].

[0041] For the thirty-two transmission gate units, each transmission gate unit consists of a series-connected delay and a transmission gate. The data input terminal of the x-th edge-triggered D flip-flop is connected to the input terminal of the corresponding transmission gate TGx through the delay in the x-th transmission gate unit. The output terminal of the x-th XOR gate Dx is connected to the input terminal of the transmission gate TGx in the x-th transmission gate unit. The transmission gates TG1 to TGx in the first to thirty-first transmission gate units are... 31 The output terminal is connected one-to-one with the 31 input terminals of the 31-bit dynamic OR gate; the output terminal of the dynamic OR gate serves as the first output terminal of the entire circuit, outputting the start_fine signal.

[0042] The clock signal stop is input to the corresponding transmission gate TG through the delay unit in the 32nd transmission gate unit. 32 The input terminal, the transmission gate TG in the thirty-second transmission gate unit. 32 The output terminal serves as the second output terminal of the entire circuit, outputting the stop_fine signal.

[0043] like Figure 3 As shown, these are transmission gates TG1 to TG2 in the first to thirty-first transmission gate units of this embodiment. 31 The circuit schematic is as follows; it has two input terminals, one receiving the output signal IN of the corresponding delay unit, and the other receiving the output signal D[x] of the corresponding XOR gate. The output signal D[x] of the XOR gate is input to one input terminal of the corresponding transmission gate, which turns on the transmission gate. The trigger signal start passes through the delay units in the delay chain and the corresponding transmission gate unit before reaching the other input terminal of the transmission gate, and is then output to the corresponding input terminal of the dynamic OR gate through that transmission gate. The transmission gate TG in the thirty-second transmission gate unit... 32 Hardware structure and Figure 3 The hardware structures shown are the same, with the transmission gate TG. 32 The transmission gate TG has two input terminals. One is directly connected to the clock / stop signal, and the other is connected to the clock / stop signal via a delay circuit. 32 The output terminal outputs the stop_fine signal.

[0044] Since edge-triggered D flip-flops and XOR gates both have delays, a matching delay is added before each transmission gate to ensure that the output signal of the corresponding XOR gate has already turned on the transmission gate before the trigger signal (start signal) enters each transmission gate. Thirty-one transmission gates TG1~TG 31The output is passed through a dynamic OR gate to generate a start_fine signal. Clearly, the delay time of the delay unit in the transmission gate unit should be greater than or equal to the sum of the delay times of the connected edge-triggered D flip-flops and XOR gates. In this embodiment, the delay time of the delay unit in the transmission gate unit is equal to the sum of the delay times of the connected edge-triggered D flip-flops and XOR gates.

[0045] like Figure 4 The diagram shown is a schematic of the dynamic OR gate in this embodiment; it has thirty-one input terminals in1 to in31 and outputs the start_fine signal.

[0046] like Figure 5 The diagram shown is a circuit schematic of an edge-triggered D flip-flop in this embodiment, which has a trigger signal input terminal IN. start The clock signal input terminal is CLK, and the output terminal is OUT and the output signal is Q, which includes Q[1] and Q[i].

[0047] When the rising edge of the start signal arrives, the start signal begins to propagate in the delay chain. When the rising edge of the stop signal arrives (i.e., the effective clock edge of the edge-triggered D flip-flop), the edge-triggered D flip-flop samples the start signal and outputs a set of temperature codes. In the delay chain, the corresponding edge-triggered D flip-flop outputs a temperature code 1 for delays where the start signal has completely passed, and a temperature code 0 for delays where the start signal has not completely passed. Therefore, by confirming the position of 0, the position of the start signal transmission can be determined, thereby judging the quantization time error.

[0048] The time interval between the start_fine and stop_fine signals is the time margin that cannot be digitally quantized in the coarse quantization TDC. The key point of this embodiment is to lock the nearest start signal when the stop signal arrives, and use this start signal as the start signal of the second-level fine quantization TDC, and the stop signal as the stop signal of the second-level TDC.

[0049] The working principle of the time margin extraction circuit: The start signal is transmitted in the delay chain. After the stop signal arrives, the edge-triggered D flip-flop outputs the corresponding thermometer code. An XOR gate is connected to the output of two adjacent edge-triggered D flip-flops to detect the thermometer codes "1" and "0". When the thermometer code output by the adjacent edge-triggered D flip-flops is "10", the corresponding XOR gate output is 1. During each quantization of the input time interval by the first-stage TDC, one XOR gate output must be 1. Assuming that the outputs of the edge-triggered D flip-flops Q[i] and Q[i+1] are 1 and 0 respectively during the time interval quantization process, it indicates that when the rising edge of the stop signal arrives, the start signal is transmitted in the delay chain between the i-th delay and the (i+1)-th delay. Therefore, the start signal through the i-th delay is used as the start_fine input of the second-stage fine quantization TDC, and the stop signal of the first-stage coarse quantization TDC is used as the stop_fine signal. At the same time, the output of the XOR gate is used as the switch of the corresponding transmission gate to turn the corresponding transmission gate on and off.

[0050] Example 2: A method for extracting quantization margin in a time-to-digital converter

[0051] This embodiment uses Embodiment 1 and is carried out in the following steps:

[0052] S1. Input a trigger signal start signal into the delay chain. The trigger signal is transmitted in the delay chain.

[0053] S2. Input the clock signal stop signal to the clock signal input terminal of the D flip-flops with the first to thirty-second edges;

[0054] Both the start and stop signals are rising edge signals.

[0055] S3. Obtain the time of the rising edge of the output signal start_fine at the first output terminal;

[0056] S4. Obtain the time of the rising edge of the output signal stop_fine at the second output terminal;

[0057] S5. Calculate the time difference between the rising edge of the output signal stop_fine at the second output terminal and the rising edge of the output signal start_fine at the first output terminal. This gives the time margin that the time-to-digital converter cannot quantize.

[0058] The rising edge signal in step S5 is the rising edge signal that arrives after and is adjacent to the rising edge signal in step S4.

[0059] In the above process, by measuring the binary code output by the first to the thirty-first XOR gates, the transmission position of the trigger signal start signal in the delay chain can be determined based on the measured binary code. Specifically: if the number m of the XOR gate whose output binary code is "1" is recorded, then the trigger signal is transmitted in the delay chain to the delay unit between the m-th to the (m+1)-th delay unit; where m∈[1, 31].

[0060] like Figure 6 The image shown is a waveform diagram of the test results in this embodiment. The time margin that the time-to-digital converter cannot quantize is set to T. res The entire circuit takes into account the output delay T of the edge-triggered D flip-flop. delay The delay T of the transmission gate D Delay T of dynamic OR gate sel This ultimately generates start_fine and stop-fine signals. The time difference between these two signals represents the time margin that the time-to-digital converter cannot quantize. Using the circuit and method provided in this embodiment, this margin can be extracted, allowing for precise measurement of the quantization error. This enables further measurement of the time margin, improving the overall measurement accuracy of the time-to-digital converter. For the sake of consistent numbering... Figure 6 In this circuit, the relevant subscripts are uniformly replaced with 'i'. Furthermore, since the delay of the XOR gate is much smaller than the delays of other components in the circuit, the effect of the XOR gate's delay on the overall circuit is ignored.

[0061] For ease of description, assume the delay parameters τ1 to τ2 of the first to thirty-second delay units are assumed to be... 32 All are the same, and the value is τ=80ps. Assuming the input interval is 200ps, that is, the rising edge of the clock signal stop arrives 200ps after the rising edge of the trigger signal start signal. With τ=80ps, the quantization margin is 40ps. At this time, the position of the start signal in the delay chain is between the second delay unit and the third delay unit. At this time, the second trigger unit samples a high level, and the third trigger unit samples a low level. Therefore, the output D2 of the second XOR gate is 1, which makes the transmission gate TG2 conduct. Finally, the result is sent to the dynamic OR gate as the start_fine signal.

Claims

1. A circuit for extracting the quantization margin of a time-to-digital converter, comprising n edge-triggered D flip-flops, wherein trigger signals are input to the data input terminals of the n edge-triggered D flip-flops respectively through a delay chain, and clock signals are input to the clock signal input terminals of the n edge-triggered D flip-flops respectively; characterized in that, The delay chain includes a first to nth delay unit connected in series. The trigger signal is input to the data input terminal of the first edge D flip-flop through the first delay unit. The trigger signal is input to the data input terminal of the i-th edge D flip-flop through the first to i-th delay units connected in series, i∈[2,n], n≥2; The circuit for extracting the quantization margin of a time-to-digital converter further includes n-1 XOR gates, wherein the two inputs of the x-th XOR gate are respectively connected to the outputs of the x-th edge-triggered D flip-flop and the x+1-th edge-triggered D flip-flop; x∈[1,n-1]; The circuit for extracting the quantization margin of a time-to-digital converter further includes n transmission gate units. Each transmission gate unit includes a timer and a transmission gate connected in series. The data input terminal of the x-th edge-triggered D flip-flop is connected to the input terminal of the corresponding transmission gate through the timer in the x-th transmission gate unit. The output terminal of the x-th XOR gate is connected to the input terminal of the transmission gate in the x-th transmission gate unit. The output terminals of the transmission gates in the first to (n-1)-th transmission gate units are respectively connected to the n-1 input terminals of a dynamic OR gate. The output terminal of the dynamic OR gate serves as the first output terminal of the circuit for extracting the quantization margin of a time-to-digital converter. The clock signal is input to the input terminal of the corresponding transmission gate through the delay unit in the nth transmission gate unit, and the output terminal of the transmission gate in the nth transmission gate unit serves as the second output terminal of the circuit for extracting the quantization margin of the time-to-digital converter.

2. The circuit for extracting the quantization margin of a time-to-digital converter according to claim 1, characterized in that, The delay time of the delay unit in the transmission gate unit is greater than or equal to the sum of the delay times of the edge-triggered D flip-flops and the XOR gate connected to it.

3. A method for extracting the quantization margin of a time-to-digital converter, implemented using a circuit for extracting the quantization margin of a time-to-digital converter as described in claim 1 or 2, characterized in that, This method is performed in the following steps in sequence: S1. Input a trigger signal into the delay chain, and the trigger signal is transmitted in the delay chain; S2. Input a clock signal to the clock signal input terminal of the first to nth edge D flip-flops; Both the trigger signal and the clock signal are rising edge signals; S3. Obtain the arrival time of the rising edge signal at the first output terminal; S4. Obtain the arrival time of the rising edge signal at the second output terminal; S5. Calculate the time difference between the arrival time of the rising edge signal at the second output terminal and the arrival time of the rising edge signal at the first output terminal, which is the time margin that the time-to-digital converter cannot quantize. The rising edge signal in step S5 is the rising edge signal that arrives after and is adjacent to the rising edge signal in step S4.

4. The method for extracting quantization margin of a time-to-digital converter according to claim 3, characterized in that, Measure the binary code output of the first to the (n-1)th XOR gates, and determine the transmission position of the trigger signal in the delay chain based on the measured binary code. The determination step includes the following process: record the number m of the XOR gate whose output binary code is "1", then the trigger signal is transmitted in the delay chain to the delay units between the mth and (m+1)th delay units; where m∈[1, n-1].

5. The method for extracting the quantization margin of a time-to-digital converter according to claim 3 or 4, wherein the delay time of the delay unit in the transmission gate unit is greater than or equal to the sum of the delay times of the edge-triggered D flip-flops and the XOR gate connected thereto, characterized in that, The output signals of n-1 XOR gates are used to control the conduction and disconnection of the transmission gates connected to them, one by one.

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