A method and related apparatus for data repair

Abstract

This application discloses a data repair method and related apparatus, applicable to high-performance computing and other scenarios, to promptly repair faulty bits and ensure the correctness of subsequent HBM data reading and writing. The method includes: obtaining first information including a first field, the first information indicating the repair operation identified by the first field to be performed on the faulty byte in the faulty Dword that needs to be repaired; after determining that the repair operation identified by the first field needs to be performed on the faulty byte in the faulty Dword according to the first information, obtaining the first bit of the faulty byte, the first bit being the faulty bit in the Dword; obtaining the bit width value of the second bit of the target byte, the target byte being either the faulty byte or a redundant byte in the HBM; updating the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte to repair the first bit.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to a data repair method and related apparatus. Background Technology

[0002] High-bandwidth memory (HBM), as a next-generation high-bandwidth memory, is suitable for applications requiring high memory bandwidth. HBM can achieve data transfer speeds of 2Gbps on 16nm processes, and even 3.2Gbps or 3.6Gbps on 7nm or 5nm processes. In chips using HBM, metal interconnects are typically used to connect various functional modules. With the development of modern processes, the linewidth between interconnect wires in HBM-configured chips is becoming increasingly narrow, leading to increased coupling effects and interference noise. Furthermore, according to HBM protocols, devices configured with third-generation high-bandwidth memory (HBM 2E) can achieve data read / write speeds up to 3.6GHz baud rates. Since HBM 2E transmits data on both the rising and falling edges of the clock, the actual communication clock frequency of HBM 2E is at most 1.8GHz. At such high operating frequencies, data transmission is susceptible to noise interference on the data communication link or crosstalk between data lines, which can easily lead to data read / write errors in high-speed operating mode. Furthermore, due to the complex manufacturing process of HBM DRAM and the use of 3D packaging technology, some bits in the data word (Dword) are prone to corruption during the manufacturing and packaging process, resulting in data read / write errors in high-speed operating mode.

[0003] If certain bits in a Dword fail or become corrupted, and are not repaired promptly, the accuracy of subsequent data reads and writes in the HBM cannot be guaranteed. Therefore, there is an urgent need to propose a technical solution capable of repairing faulty bits in a Dword. Summary of the Invention

[0004] This application provides a data repair method and related apparatus to promptly repair bits that have experienced operational failures, ensuring the correctness of subsequent HBM data reading and writing.

[0005] In a first aspect, embodiments of this application provide a data repair method. The method includes: obtaining first information, the first information including a first field, the first information indicating that a repair operation identified by the first field needs to be performed on a faulty byte in a Dword that has experienced a runtime failure in a High Bandwidth Memory (HBM), the Dword including at least two bytes, the faulty byte being one of the at least two bytes; after determining, based on the first information, that the repair operation identified by the first field needs to be performed on the faulty byte in the Dword that has experienced a runtime failure, obtaining a first bit of the faulty byte, the first bit being a bit in the Dword that experienced a runtime failure; obtaining the bit width value of a second bit of a target byte, the second bit being a bit in the HBM that did not experience a runtime failure, the target byte being either a faulty byte or a redundant byte in the HBM; updating the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte to repair the first bit. It should be noted that different values ​​in the first field can indicate different repair operations that need to be performed. For example, when the first value is used to indicate a hard repair operation, if the first field takes the first value, it can be known that a hard repair operation needs to be performed; similarly, when the second value is used to indicate a soft repair operation, if the first field takes the second value, it can be known that a soft repair operation needs to be performed, where the first value and the second value are different.

[0006] Secondly, embodiments of this application provide a data repair apparatus. This data repair apparatus includes, but is not limited to, terminal devices, servers, etc. The data repair apparatus includes an acquisition unit and a processing unit. The acquisition unit is configured to acquire first information, the first information including a first field, the first information indicating that a repair operation identified by the first field needs to be performed on a faulty byte in a Dword that has experienced a runtime failure in a High Bandwidth Memory (HBM). The Dword includes at least two bytes, and the faulty byte is one of the at least two bytes. The acquisition unit is configured to, after determining that a repair operation identified by the first field needs to be performed on the faulty byte in the Dword that has experienced a runtime failure based on the first information, acquire a first bit of the faulty byte, the first bit being the bit position in the Dword where a runtime failure has occurred. The acquisition unit is configured to acquire the bit width value of a second bit of a target byte, the second bit being a bit position in the HBM where a runtime failure has not occurred, and the target byte being either a faulty byte or a redundant byte in the HBM. The processing unit is configured to update the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte, in order to repair the first bit.

[0007] In some optional examples, the repair operation includes a hard repair operation. The acquisition unit is further configured to acquire hard repair confirmation information when the value of the first field is a first value, prior to updating the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte to repair the first bit. The hard repair confirmation information indicates at least one confirmation of whether a hard repair operation has been performed on the faulty byte in the Dword that has experienced a runtime failure, and the first value is used to indicate the hard repair operation. The processing unit is configured to determine, based on the hard repair confirmation information, to perform a hard repair operation on the faulty byte in the Dword that has experienced a runtime failure.

[0008] In some other optional examples, the fault byte consists of any one of at least two bytes.

[0009] In some alternative examples, the target byte is a redundant byte. The processing unit is configured to: change the bit width value of the DBI signal to the bit width value of any bit in the redundant byte when the first bit is the data bus toggle DBI signal.

[0010] In some alternative examples, the target byte is a fault byte. The processing unit is configured to: when the first bit is a data mask DM signal or a data queue DQ signal, change the bit width value of the DM signal or the bit width value of the DQ signal to the bit width value of the fault byte's DBI signal.

[0011] In some alternative examples, the fault byte consists of a first byte and a second byte, which are two consecutive bytes out of at least two bytes.

[0012] In some alternative examples, the target byte is a fault byte. The processing unit is configured to: if both the first bit of the first byte and the first bit of the second byte have operational faults, change the bit width value of the first bit of the first byte to the bit width value of the DBI signal in the first byte, and change the bit width value of the first bit of the second byte to the bit width value of the DBI signal in the second byte.

[0013] In some alternative examples, the target byte is a fault byte. The processing unit is configured to: if the first bit of either the first bit of the first byte or the first bit of the second byte experiences a malfunction, change the bit width value of the first bit of the malfunctioning byte to the bit width value of the DBI signal in the corresponding byte.

[0014] In some alternative examples, the target byte is a redundant byte. The processing unit is configured to: if the first bit of either the first bit of the first byte or the first bit of the second byte experiences a malfunction, change the bit width value of the first bit of the malfunctioning byte to the bit width value of any bit in the redundant byte.

[0015] In some other optional examples, the processing unit is also configured to: change the bit width value of the first bit of the byte that has not experienced a failure to a target value, the target value being used to indicate that the first bit of the byte that has not experienced a failure is disabled.

[0016] In some other optional examples, the acquisition unit is used to: acquire a first instruction, which includes the first bit of the fault byte.

[0017] In some other optional examples, the processing unit is also configured to: update the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte to repair the first bit, and then write data into the repaired first bit; or, read data from the repaired first bit.

[0018] A third aspect of this application provides a data repair apparatus, including: a memory, an input / output (I / O) interface, and a processor. The memory stores program instructions. The processor executes the program instructions in the memory to perform the data repair method corresponding to the implementation of the first aspect described above.

[0019] A fourth aspect of this application provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the method corresponding to the embodiments of the first aspect described above.

[0020] The fifth aspect of this application provides a computer program product containing instructions that, when run on a computer or processor, causes the computer or processor to execute the method described above for performing the implementation method of the first aspect.

[0021] As can be seen from the above technical solutions, the embodiments of this application have the following advantages:

[0022] In this embodiment, since the first information can be used to instruct the execution of the repair operation identified by the first field on the faulty byte in the Dword of the high-bandwidth memory (HBM) that has experienced a malfunction, and the Dword includes at least two bytes, with the faulty byte being one of those at least two bytes, after obtaining the first information and determining, based on the first information, that the faulty byte in the Dword has experienced a malfunction and that the repair operation identified by the first field has been executed, the first bit of the faulty byte can be obtained. This first bit is the bit in the Dword that has experienced a malfunction. Then, using the faulty byte as the target byte or a redundant byte in the HBM as the target byte, the bit width value of the second bit of the target byte can be obtained. This second bit is the bit in the Dword that has not experienced a malfunction. Thus, when the target byte is a faulty byte or a redundant byte in the HBM, the bit width value of the first bit of the faulty byte can be updated based on the bit width value of the second bit of the target byte, thereby completing the repair of the faulty bit in the Dword, i.e., completing the repair of the first bit. In other words, it can be understood that the bit width value of the bit that has experienced a runtime failure can be updated by using the bit width value of the bit that has not experienced a runtime failure in the fault byte of the Dword, or the bit width value of the bit that has experienced a runtime failure in the fault byte can be updated by using the bit width value of the bit in the redundant byte of the HBM, thereby completing the repair processing of the bit that has experienced a runtime failure in a timely manner and ensuring the correctness of subsequent HBM data reading and writing. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1A A schematic diagram of initiating a write operation to HBM is shown;

[0025] Figure 1B A schematic diagram illustrating the data format for writing data in HBM DRAM is shown.

[0026] Figure 1C This diagram illustrates a timing sequence for writing data into HBM DRAM.

[0027] Figure 1D This diagram illustrates another timing sequence when writing data into HBM DRAM.

[0028] Figure 2A A schematic diagram of initiating a read operation on HBM is shown;

[0029] Figure 2B A schematic diagram illustrating the data format for reading data in HBM DRAM is shown.

[0030] Figure 2C This diagram illustrates a timing sequence for reading data from HBM DRAM.

[0031] Figure 2D This diagram illustrates another timing sequence when reading data from HBM DRAM.

[0032] Figure 3 The diagram shows the operation waveforms of different types of interface signals in the IEEE 1500 interface;

[0033] Figure 4 A schematic diagram of the system architecture provided in the embodiments of this application is shown;

[0034] Figure 5 This paper illustrates a first flowchart of a data repair method provided in an embodiment of this application.

[0035] Figure 6 A second flowchart illustrating the data repair method provided in this application embodiment is shown.

[0036] Figure 7 A schematic diagram of one embodiment of the data repair apparatus provided in this application is shown;

[0037] Figure 8 A schematic diagram of the hardware structure of the data repair device provided in the embodiments of this application is shown. Detailed Implementation

[0038] This application provides a data repair method and related apparatus to promptly repair bits that have experienced operational failures, ensuring the correctness of subsequent HBM data reading and writing.

[0039] It is understood that in the specific embodiments of this application, data such as user information are involved. When the above embodiments of this application are applied to specific products or technologies, user permission or consent is required, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that implementations of the application described herein can be implemented, for example, in sequences other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0042] High-bandwidth memory (HBM), as a new generation of high-bandwidth memory, is suitable for applications requiring high memory bandwidth. The following is a brief description of the data writing and reading processes in HBM, with reference to the accompanying diagram.

[0043] HBM write operations are generally implemented in the form of bursts, and the initiation of a write operation is marked by the sending of a write command. Figure 1A This diagram illustrates a write operation initiated against HBM. For example... Figure 1A As shown, the burst pulse length of the HBM write instruction is 2. A write operation is initiated by sending a write instruction with a burst pulse length of 2. Indicatively, the burst pulse length of the HBM write instruction can also be 4, etc., but this application embodiment does not impose specific limitations.

[0044] When the host needs to write data into the HBM DRAM, it sends a write command to the HBM DRAM. After receiving the write command from the host, the host writes the data queue (DQ), data mask (DM), data bus inversion (DBI), and the associated wideband digital sampling signal (WDQS) to the HBM DRAM. This allows the HBM DRAM to use the WDQS signal to sample DQ, DM, and DBI. Figure 1B This diagram illustrates the data format for writing data in HBM DRAM. For example... Figure 1BAs shown, with a burst pulse length of 4, after receiving a write instruction, four data entries can be continuously written into the HBM DRAM, such as Da, Da+1, Da+2, and Da+3, etc. This embodiment does not impose further limitations. Additionally, Figure 1B The tDQSS(min / max) in the table can represent the minimum and maximum time range between the rising edge of WDQS_c and the rising edge of CK_c; or, it can represent the minimum and maximum time range between the falling edge of WDQS_t and the falling edge of CK_t. Figure 1B In the diagram, tDQSS describes the time delay between the rising edge of WDQS and the rising edge of CK, tDQSH describes the time delay during which the WDQS signal remains high, and tDQSL describes the time delay during which the WDQS signal remains low. Additionally, tDSS describes the setup time between the falling edge of the WDQS signal and the rising edge of CK, tDSH describes the hold time between the falling edge of the WDQS signal and the rising edge of CK, tDS describes the setup time between writing data and the associated rising or falling edge of WDQS, and tDH describes the hold time between writing data and the associated rising or falling edge of WDQS.

[0045] Indicatively, Figure 1C This diagram illustrates a timing sequence for writing data into HBM DRAM. Figure 1C As shown, in HBM DRAM, when writing data using a burst length (BL) of 2, two data entries can be written consecutively, such as Da and Da+1. Similarly, Figure 1D This diagram illustrates another timing sequence for writing data into HBM DRAM. When writing data into HBM DRAM using a burst length (BL) of 4, four data entries can be written consecutively, such as Da, Da+1, Da+2, and Da+3. It should be noted that the above description only uses burst lengths of 2 and 4 as examples to illustrate the data writing process in HBM DRAM. In practical applications, the burst length can be other lengths, such as 6 or 8, etc., which are not specifically limited in this embodiment.

[0046] Similarly, HBM read operations are generally implemented in the form of bursts, with the initiation of a read operation marked by the sending of a read command. Figure 2A This diagram illustrates the initiation of a read operation on HBM. For example... Figure 2AAs shown, the burst pulse length of HBM's read command is 2. A read operation is initiated by sending a read command with a burst pulse length of 2. Indicatively, the burst pulse length of HBM's read command can also be 4, etc., but this application does not impose specific limitations on this embodiment.

[0047] When HBM DRAM receives a read command from the host, it returns read data DQ, DM, and DBI to the host. Figure 2B This diagram illustrates the data format for reading data in HBM DRAM. (For example...) Figure 2B As shown, after receiving the read instruction, four data entries can be read continuously from the HBM DRAM, such as Da, Da+1, Da+2, and Da+3, etc. This application embodiment does not provide a specific description.

[0048] Indicatively, Figure 2C This diagram illustrates a timing sequence for reading data from HBM DRAM. Figure 2C As shown, when reading data from HBM DRAM using a pulse length of 2, two data entries, such as Da and Da+1, can be read consecutively from the HBM DRAM. Similarly, Figure 2D This diagram illustrates another timing sequence when reading data from HBM DRAM. Figure 2D It can be seen that when reading data from HBM DRAM using a pulse length of 4, four data entries can be continuously read from the HBM DRAM, such as Da, Da+1, Da+2, and Da+3. It should be noted that the above description only uses pulse lengths of 2 and 4 as examples to illustrate the process of reading data from HBM DRAM. In practical applications, the pulse length may also be other lengths, such as 6 or 8, etc., which are not specifically limited in this embodiment.

[0049] From the above Figures 1A to 2D It can be seen that high-speed data read and write operations in HBM DRAM use DQ as the data read and write transmission channel. It should be noted that the above... Figures 1A to 2D The text uses DQ as an example to describe the data read / write behavior in HBM DRAM. This is illustrative; the transmission behavior for DM and DBI is similar to that of DQ. Please refer to the above for details. Figures 1A to 2D The diagram shown is for reference only and will not be elaborated upon here.

[0050] The IEEE 1500 interface is a set of interfaces provided by HBM to the host for performing tests, boundary scans, and repairs. Its interface signals are shown in Table 1 below:

[0051] Table 1

[0052]

[0053]

[0054] For details regarding the operation waveforms of different types of interface signals of the IEEE 1500 interface shown in Table 1 above, please refer to Table 1. Figure 3 Please refer to the diagram shown for clarification.

[0055] Furthermore, in HBM DRAM, the DQ, DM, and DBI signals in the Dword are primarily used as the transmission channels for data read and write operations. This HBM DRAM also provides redundant channels for remapping the Dword. Table 2 below shows the Dword and redundant channel interfaces in a single-channel HBM DRAM.

[0056] Table 2

[0057] Function Data bit width Function Description DQ 128-bit HBM DRAM write data bus DM 16-bit Data Mask, write data mask signal DBI 16-bit Data Bus Inversion RD 8-bit Redundant Data

[0058] As shown in Table 2, Dword includes DQ, DM, and DBI. The maximum data width for the DQ signal is 128 bits, for the DM signal it is 16 bits, and for the DBI signal it is 16 bits. Furthermore, RD, as a redundant channel in HBM DRAM provided for Dword remapping, has a maximum data width of 8 bits.

[0059] However, in chips using HBM DRAM, the increasingly narrow interconnect wire widths lead to increased coupling effects and interference noise. Furthermore, since HBM data is transmitted on both the rising and falling edges of the clock, at higher operating frequencies, noise interference on the data communication link or crosstalk between data lines can easily cause errors in high-speed operation. Additionally, the complex manufacturing process of HBM DRAM, including 3D packaging, makes it susceptible to damage to certain bits within the data word during production and packaging, leading to errors in high-speed operation. When certain bits in a Dword, such as the first bit of the DQ signal, malfunction or become damaged, failure to repair them promptly will compromise the accuracy of subsequent HBM data reads and writes.

[0060] Therefore, in order to solve the aforementioned technical problems, this application provides a data repair method. This method can be applied to... Figure 4 The system architecture diagram shown is as follows. Figure 4 As shown, the system architecture includes a host and an HBM. When the host determines that certain bytes in the HBM's Dword have experienced operational failures, it can obtain a repair instruction and, based on the first information carried in the repair instruction, indicate the need to perform a repair operation identified by the first field on the faulty byte in the faulty Dword. Different values ​​in the first field indicate different repair operations. For example, if the first value indicates a hard repair operation, and the first field is set to the first value, a hard repair operation is required; similarly, if the second value indicates a soft repair operation, and the first field is set to the second value, a soft repair operation is required, where the first and second values ​​are different. Thus, after determining that the faulty byte in the faulty Dword needs to be repaired based on the first information, the host can further obtain the first bit of the faulty byte and the bit width value of the second bit of the target byte. In this way, when the target byte is a faulty byte or a redundant byte in HBM, the bit width value of the first bit of the faulty byte can be updated according to the bit width value of the second bit of the target byte, thereby completing the fault repair of the bit in the Dword that has run into fault, that is, completing the fault repair of the first bit, and ensuring the correctness of subsequent HBM data reading and writing.

[0061] It should be noted that the data repair methods mentioned above can also be applied to application scenarios such as cloud computing, artificial intelligence, data centers, and high-performance computing. Specifically, they can also be applied to application scenarios such as storage, but this application does not limit their application. Furthermore, the host mentioned can be a terminal device or a server, etc., and this application does not specifically limit its application. Terminal devices can include, but are not limited to, smartphones, desktop computers, laptops, tablets, smart speakers, in-vehicle devices, smartwatches, wearable smart devices, smart voice interaction devices, smart home appliances, and aircraft. Servers can be independent physical servers, server clusters or distributed systems composed of multiple physical servers, or cloud servers providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDNs), and big data and artificial intelligence platforms, etc., and this application does not specifically limit their application. Additionally, the terminal devices and servers mentioned can be directly or indirectly connected through wired or wireless communication, and this application does not specifically limit their connection.

[0062] Furthermore, the described repair operations can include both soft repair and hard repair operations. Soft repair operations do not permanently write the repair mapping table inside the HBM DRAM, and the data is not lost after power failure. Hard repair operations, on the other hand, are an in-circuit programming repair method that can permanently write the hard repair mapping table inside the HBM DRAM. The data is lost after power failure; therefore, the HBM DRAM only has one opportunity to perform a hard repair operation during use. Subsequent embodiments will describe the data repair methods provided in this application from the perspectives of soft repair and hard repair operations, respectively.

[0063] (a) Performing a hard repair operation

[0064] Figure 5 A first flowchart of a data repair method provided in an embodiment of this application is shown. Figure 5 As shown, the data repair method may include the following steps:

[0065] 501. Obtain first information, the first information including a first field, the first information being used to indicate that a hard repair operation identified by the first field needs to be performed on the fault byte in the Dword in the HBM that has experienced a runtime failure, the Dword including at least two bytes, the fault byte being a byte from the at least two bytes.

[0066] In this example, before writing or reading data from the HBM, the host can detect whether a byte in the Dword of the HBM is malfunctioning by sending commands or other means; alternatively, the host can detect malfunctions by using flags. For instance, a flag value of "1" indicates that the corresponding byte is still functioning normally; a flag value of "0" indicates that the corresponding byte has malfunctioned, thus identifying the faulty byte in the Dword. Upon determining that a byte in the Dword has malfunctioned, the host can further obtain first information and, based on the indication of this first information, determine whether to perform the repair operation identified by the first field in the faulty byte of the Dword in the HBM.

[0067] For example, since repair instructions such as HARD_LANE_REPAIR include first information, the host can execute repair instructions such as HARD_LANE_REPAIR through configuration instructions. Thus, after parsing the repair instruction, the first information carried in the repair instruction can be obtained, and this first information includes a first field that identifies the corresponding repair operation. Taking the HARD_LANE_REPAIR instruction as an example, the first information described can be understood with reference to the content described in Table 3 below, namely:

[0068] Table 3

[0069]

[0070]

[0071]

[0072] The IEEE 1500 interface described in Table 3 can be understood by referring to the content of Table 1 above, and will not be repeated here.

[0073] Furthermore, HBM DRAM internally comprises 8 channels, each of which can contain Dwords. Moreover, the WIR[11:8] described in Table 3 above can be used to control channel selection. The specific content of this WIR[11:8] can be understood by referring to Table 4, namely:

[0074] Table 4

[0075] WIR[11:8] Channel selection Xh neglect 0h channel 0 1h channel 1 2h channel 2 3h channel 3 4h channel 4 5h channel 5 6h channel 6 7h channel 7 Eh~8h Reserved words Fh All channels

[0076] As can be seen from Table 4 above, in WIR[11:8], the identifier 0h can be used to identify channel 0 in the HBM DRAM, and after obtaining the identifier 0h, the corresponding channel 0 can be selected. Similarly, the identifier 1h can be used to identify channel 1 in the HBM DRAM, and after obtaining the identifier 1h, the corresponding channel 1 can be selected. The identifiers 2h, 3h, 4h, 5h, 6h, 7h, etc., can also be understood with reference to the contents described by the identifiers 0h and 1h above, and will not be repeated here. In addition, the identifier Fh can be used to identify all channels in the HBM DRAM, so that all channels can be selected through the identifier Fh. Identifiers Eh to 8h are reserved fields in this WIR instruction for the subsequent addition of other identifiers. Based on this, the host can obtain WIR instructions, etc., to determine which channel's bits need to be repaired.

[0077] Furthermore, WIR[7:0] in Table 3 can be understood as the first field. The value of the first field is the first value, such as 13h, which can be used to indicate a hard repair operation. In other words, when the first field is the first value, it can be determined through this first value that a hard repair operation needs to be performed. For example, performing a hard repair operation can also be understood as executing hard repair instructions such as HARD_LANE_REPAIR. Combining with Table 4 above, it can be seen from Table 3 that under the identifier 0h in WIR[11:8], since this identifier 0h can be used to identify channel 0 in the HBM DRAM, after obtaining the first information, identifier 0h is determined from the first information, thus indicating that the HARD_LANE_REPAIR instruction needs to be executed on channel 0 identified by 0h. Then, under the instruction of the HARD_LANE_REPAIR instruction, the hard repair operation on HBM DRAM channel 0 is completed through the IEEE1500 interface. Similarly, the identifier 1h can be used to identify channel 1 in the HBM DRAM. After obtaining the first information, identifier 1h is determined from the first information, and it is then known that the HARD_LANE_REPAIR instruction needs to be executed on channel 1 identified by 1h. Under the instruction of HARD_LANE_REPAIR, the hard repair operation on HBM DRAM channel 1 is completed through the IEEE1500 interface. Similarly, the hard repair operation is performed on the channels corresponding to the other identifiers in Table 2 above. The specific implementation can be understood by referring to the hard repair operation performed on the channels corresponding to identifiers 0h and 1h, which will not be repeated here. It should be noted that the value of the first field in Table 3 is the first value, and the first value is 13h. This is only an exemplary description. In actual applications, other values ​​are possible, and this application embodiment does not limit the value.

[0078] Furthermore, since computers use both instructions and data, computer words can represent either. If certain computer words represent data to be processed, they are called data words (Dwords). Moreover, as described in Table 2 above, each of the eight channels provided by HBM DRAM includes Dwords. Taking any channel as an example, a Dword includes DQ, DM, and DBI signals, totaling 160 bits. When at most eight of these 160 bits experience operational failures, hard repair can be achieved through remapping. This hard repair is an online programming repair method; the repaired data will be lost after power loss. Illustratively, as an example, according to the HBM implementation, these 160 bits can be divided into four independent Dwords, and each Dword can be further divided into four bytes. For details, please refer to Table 5 below:

[0079] Table 5

[0080]

[0081] As shown in Table 5 above, each Dword can include 4 bytes, and each byte can include 8 bits of the DQ signal, 1 bit of the DM signal, and 1 bit of the DBI signal. For example, these 160 bits can be divided into 4 Dwords, namely Dword0 to Dword3. Dword0 can include 4 bytes, namely Byte0 to Byte3. Furthermore, Byte0 can include DQ0 to DQ7, DBI0, and DM0; Byte1 can include DQ8 to DQ15, DBI1, and DM1; Byte2 can include DQ16 to DQ23, DBI2, and DM2; and Byte3 can include DQ24 to DQ31, DBI3, and DM3. Similarly, the contents of Dword1, Dword2, and Dword3 can be understood by referring to the contents of Dword0 above, and will not be elaborated further here.

[0082] It should be noted that the division of the Dword field into 4 Dwords in Table 5 above is merely an illustrative description. In practical applications, with the reduction of the data bus, the Dword field can also be divided into 2 Dwords, etc. The specific steps in the embodiments of this application are limited accordingly. In addition, the number of bytes in each Dword can also be determined according to the actual situation. This application does not impose any limitations. It is sufficient that each byte includes 8 DQ, 1 DM, and 1 DBI signal, and the bit order of these 8 DQs is not specifically limited.

[0083] 502. After determining, based on the first information, that a hard repair operation identified by the first field needs to be performed on the faulty byte in the Dword that has experienced a running failure, the first bit of the faulty byte is obtained. The first bit is the bit in the Dword that experienced a running failure.

[0084] In this example, after receiving the first information and determining, based on the indication of the value of the first field in the first information, that a hard repair operation needs to be performed on the faulty byte in the Dword that has experienced a runtime failure, the host can then further obtain the first bit of the faulty byte.

[0085] For example, if the flag bit of Byte1 in Dword0 is "0", then Byte1 is a faulty byte. If, using a similar method, it is determined that the flag bits of some bits in Byte1 are also "0", then the bits with flag bits of "0" can also be considered to have experienced a malfunction. In this case, the first bit can be identified from Byte1; that is, the first bit is the faulty bit in the Dword. For example, if the flag bit of DQ8 in Byte1 is "0", then DQ8 can be identified as the first faulty bit. It should be noted that this description only uses the flag bit method to illustrate the process of identifying faulty bytes. The specific process for identifying faulty bytes can be understood by referring to step 501 above, and will not be elaborated upon here.

[0086] 503. Obtain the bit width value of the second bit of the target byte. The second bit is the bit in HBM that has not experienced a running fault. The target byte is either a faulty byte or a redundant byte in HBM.

[0087] In this example, if the first bit of a faulty byte experiences a malfunction, the bit width of the first bit can be updated using the bit width values ​​of other non-malfunctioning bits in the faulty byte, thus repairing the fault in the first bit. Alternatively, since HBM provides a redundant channel, i.e., the redundant data (RD) bits in Table 2 above, the bit width of the first bit in the faulty byte can also be updated using the bit width values ​​of the redundant bytes corresponding to the redundant channel, thus repairing the fault in the first bit. Therefore, regardless of the method used to repair the fault in the first bit, the bit width value of the second bit of the target byte needs to be obtained. The described bit width value can be understood as the data width. The described target byte can be a faulty byte, or it can be the redundant byte corresponding to RD in HBM.

[0088] For example, the host can obtain target configuration information, and use this target configuration information to obtain the bit width value of the second bit of the target byte. The target configuration information described herein can be understood with reference to the content shown in Table 6 below, namely:

[0089] Table 6

[0090]

[0091]

[0092] As shown in Table 6 above, taking DM0 as the bit where the operational failure occurred as an example, the faulty DM0 will be configured as "0000". During the repair process, the original DQ0 signal replaces the original QD1, the original DQ1 signal replaces the original DQ2, and so on. The original DQ7 signal occupies the bit position where the DBI signal is located. If mode 2, mentioned in Table 7, is used for repair, the bit width value of the redundant byte can be obtained, i.e., the bit width value of RD can be used to repair DM0. If mode 1, mentioned in Table 7, is used for repair, the bit width value of DBI in the corresponding byte can be obtained for repair. For details, please refer to step 504 below; it will not be elaborated here.

[0093] It should be noted that the execution order of steps 502 and 503 is not specifically limited in this embodiment. For example, step 503 can be executed first, followed by step 502; or steps 502 and 503 can be executed simultaneously.

[0094] 504. When the value of the first field is the first value, obtain the hard repair confirmation information. The hard repair confirmation information indicates the confirmation status of whether a hard repair operation has been performed on the faulty byte in the Dword that has experienced a running failure at least once. The first value is used to indicate the hard repair operation.

[0095] 505. Based on the hard repair confirmation information, determine to perform a hard repair operation on the faulty bytes in the Dword that has experienced a runtime failure.

[0096] Since hard repair permanently writes to the hard repair mapping table inside the HBM DRAM, the HBM DRAM only has one opportunity to perform a hard repair operation during use. Therefore, to ensure that this hard repair is not a misconfiguration of the object, a secondary confirmation is required before performing hard repair on the first bit. For example, before updating the bit width of the first bit of the faulty byte according to the bit width value of the second bit of the target byte to repair the first bit, it can be determined whether the value of the first field is the first value, and this first value is used to indicate the hard repair operation. When the first field is the first value, it can be known that a hard repair operation needs to be performed. Therefore, when the first field is the first value, hard repair confirmation information is obtained, which indicates at least one confirmation of whether a hard repair operation has been performed on the faulty byte in the Dword that has experienced a runtime failure. Then, based on the hard repair confirmation information, it is determined whether the hard repair operation will be performed on the faulty byte in the Dword that has experienced a runtime failure. Through the above method, the hard repair operation can be performed without errors. It should be noted that the "at least one confirmation" described above can be understood as reconfirmation or multiple confirmations, etc., and this application does not limit the description. In addition, "multiple confirmations" can be understood as three or more confirmations, etc., and this application does not limit the description.

[0097] 506. Update the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte to repair the first bit.

[0098] In this example, after confirming or confirming multiple times based on the hard repair confirmation information that a hard repair operation will be performed on the faulty byte in the Dword that has experienced a runtime failure, the obtained bit width value of the second bit can be used to perform a hard repair operation on the bit that has experienced a runtime failure in the faulty byte, that is, to update the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte.

[0099] When a faulty byte consists of any one of at least two bytes in a Dword, or consists of two consecutive bytes, different repair modes can be used to update the bit width value of the first bit in the faulty byte. Based on this, the host can obtain the corresponding hard repair configuration information for the Dword, and through the indications in this hard repair configuration information, use different repair modes to perform hard repair on the bit in the faulty byte that has experienced a runtime failure. For example, the configuration of different repair modes in each Dword can be understood by referring to the content described in Table 7 below:

[0100] Table 7

[0101]

[0102]

[0103] As can be seen from Table 7 above, taking Byte0 in Dword0 as an example, its corresponding hard repair configuration table describes the value of each bit in Byte0. Among them, "h9" indicates that when the DBI signal in Byte0 has a failure, mode 2 needs to be used for repair. The specific description of mode 2 can be understood by referring to the contents shown in case ① in mode (1) and case ① in mode (2) below, which will not be elaborated here. In addition, "hE" indicates that when a bit in any of two consecutive bytes has a failure, the bit width value of the bit that has not had a failure needs to be set to a disabled state. "hF" indicates that it is not necessary to perform hard repair on other bits that have not had a failure, and the original bit width value is still used. It should be noted that the identifiers "hE" and others shown in Table 7 above are only illustrative descriptions. Other identifiers may be used in actual applications, and this application embodiment does not limit them.

[0104] In addition, the hard repair configuration tables for other bytes in Dword0, other Dword1, Dword2, and each byte in Dword3 can be understood by referring to the hard repair configuration table for Byte0 in Dword0, which will not be elaborated here.

[0105] Based on the information shown in Tables 6 and 7 above, the following section provides a detailed description of how to hard-repair the first bit for faulty bytes composed of different bytes.

[0106] (1) The fault byte consists of any one of at least two bytes.

[0107] In this example, when the faulty byte consists of only one arbitrary byte, different repair modes can be used to update the bit width value of the first bit in the faulty byte, depending on whether the target byte belongs to a different type of byte. For example, if the target byte is a faulty byte, the bit width value of the first bit can be updated using the bit width value of the bits within the faulty byte that have not experienced operational failures. Alternatively, if the target byte is a redundant byte in HBM, the bit width value of the first bit can be updated using the bit width value of the redundant byte. The following section describes in detail how to hard-repair the first bit for different types of target bytes.

[0108] ① The target byte is a redundant byte.

[0109] For example, updating the bit width of the first bit of the faulty byte based on the bit width of the second bit of the target byte can be achieved by changing the bit width of the DBI signal to the bit width of any bit in the redundant byte when the first bit is a DBI signal.

[0110] In this example, since the redundant byte has a total data width of 8 bits, and the faulty byte consists of only one byte, the redundant byte is sufficient to be allocated to the faulty byte for hard repair. Therefore, when the first bit that caused the operational failure is determined to be the DBI signal in the faulty byte, the bit width of the DBI signal can be directly changed to the bit width of any bit in the redundant byte. Alternatively, the bit width of the DBI signal can be modified to the bit width of any bit in the redundant byte.

[0111] ② The target byte is a faulty byte.

[0112] For example, updating the bit width of the first bit of the faulty byte based on the bit width of the second bit of the target byte can be achieved as follows: when the first bit is a data mask (DM) signal or a data queue (DQ) signal, the bit width of the DM signal or the bit width of the DQ signal is changed to the bit width of the DBI signal of the faulty byte.

[0113] In this example, if the target byte is a fault byte, and the DM or DQ signal in the fault byte has a malfunction but the DBI signal has not, then the bit width value of the DBI signal in the current fault byte can be used directly to change the bit width value of the first bit that has already had a malfunction, that is, to change the bit width value of the DM or DQ signal in the fault byte.

[0114] It should be noted that after the first bit is repaired by the repair method ① or ② in the above method (1), the original DBI function in the fault byte corresponding to the first bit will no longer be used, while the DBI function in other bytes that have not undergone hard repair operation can still continue to be used normally.

[0115] (2) The fault byte consists of two consecutive bytes from at least two bytes.

[0116] In this example, when the faulty byte consists of a first byte and a second byte, different repair modes can be used to update the bit width value of the first bit in the faulty byte if the target byte belongs to a different byte type. For example, if the target byte is a faulty byte, the bit width value of the first bit can be updated by the bit width value of the bits within the faulty byte that have not experienced operational failures. Alternatively, if the target byte is a redundant byte in HBM, the bit width value of the first bit can be updated by the bit width value of the redundant byte's bits. It should be noted that the first byte and the second byte described are two consecutive bytes out of at least two bytes. Below, we will describe in detail how to hard repair the first bit for different types of target bytes.

[0117] ① The target byte is a redundant byte.

[0118] For example, updating the bit width of the first bit of the faulty byte based on the bit width of the second bit of the target byte can be achieved in the following way: if the first bit of either the first bit of the first byte or the first bit of the second byte experiences a failure, the bit width of the first bit of the byte experiencing the failure is changed to the bit width of any bit in the redundant byte.

[0119] In this example, since the redundant byte has a total data width of 8 bits, and the four Dwords shown in Table 5 have a total of 16 independent bytes, it is insufficient to allocate an independent redundant byte for hard repair for each of these 16 independent bytes. Therefore, consecutive bytes can be grouped together, and hard repair can be performed on consecutive bytes within the same group. For example, consecutive Byte0 and Byte1 in Dword0 in Table 5 can be grouped together and repaired simultaneously; similarly, consecutive Byte2 and Byte3 in Dword0 can be grouped together and repaired simultaneously. Likewise, for Dword1, Byte0 and Byte1 can be grouped together, and Byte2 and Byte3 can be grouped together. For Dword2, Byte0 and Byte1 can be grouped together, and Byte2 and Byte3 can be grouped together. For Dword3, Byte0 and Byte1 can be grouped together, and Byte2 and Byte3 can be grouped together.

[0120] In the case of a faulty byte consisting of two consecutive bytes, since the two consecutive bytes are allocated in the same group, and each group is allocated only one redundant byte for hard repair, and one redundant byte can only repair one byte, if the first bit of either the first bit of the first byte or the second bit of the second byte fails, the allocated redundant byte is sufficient for hard repair. Therefore, the bit width of the first bit of the byte with the failure can be changed to the bit width of any bit in the redundant byte. For example, if the first bit of the first byte fails, but the first bit of the second byte does not, the allocated redundant byte is sufficient to repair the first byte, and the bit width of the first bit of the first byte needs to be changed to the bit width of any bit in the redundant byte. Similarly, if the first bit of the second byte fails, but the first bit of the first byte does not, the bit width of the first bit of the second byte can also be changed to the bit width of any bit in the redundant byte. By using redundant bytes to repair the byte with the failure, the complete function of the DBI signal in the faulty byte can be preserved.

[0121] Furthermore, since redundant bytes can only be allocated to one byte for repair, for bytes within the same group that have not experienced operational failures, the bit width of the first bit of that byte is changed to a target value. This target value indicates that the first bit of the byte that has not experienced operational failures is disabled. The described target value may include, but is not limited to, "hE", where "E" can be understood as a hexadecimal value, i.e., "1110". It should be noted that in some examples, the target value may also be other numerical values, which are not limited in the embodiments of this application.

[0122] For example, if the faulty byte is determined to consist of Byte0 and Byte1 from Dword0 in Table 5, and DQ12 in Byte1 is the first bit of the operational fault, then the corresponding configuration information can be understood by referring to Table 8, that is:

[0123] Table 8

[0124]

[0125]

[0126] Based on Table 5 above, it can be determined that the DQ12 experiencing the operational failure is the 5th bit of Byte 1 in Dword 0. In this case, mode 2 can be used to change the bit width of DQ12 to the bit width of any bit in the redundant byte, such as configuring the value to "4'h5". Furthermore, since Byte 0 and Byte 1 are two consecutive bits in the same group, the bit width of the bits in Byte 0 of Dword 0 also needs to be configured to "4'hE", effectively disabling each bit in Byte 0. Additionally, for the bits in other bytes that did not experience operational failures, such as Dword 3, Dword 2, and Dword 1, as well as Byte 3 and Byte 2 in Dword 0, the configuration value of the corresponding bits can be set to "hF", meaning there is no need to change the bit width of the corresponding bits.

[0127] Alternatively, if it is determined that the faulty byte is composed of Byte3 in Dword2 of Table 5, and DBI11 in Byte3 is the first bit of the operational fault, then the corresponding configuration information can be understood by referring to Table 9, that is:

[0128] Table 9

[0129] Bit domain Configuration value 71:56 DWORD3[15:0] 16'hFFFF 55:40 DWORD2[15:0] 16'h9EFF 39:32 Reserved 16'hFF 31:16 DWORD1[15:0] 16'hFFFF 15:0 DWORD0[15:0] 16'hFFFF

[0130] Based on Table 5 above, we can see that the DBI11 that experienced the operational failure is the 9th bit of Byte 3 in Dword 2. In this case, mode 2 can be used to change the bit width of DBI11 to the bit width of any bit in the redundant byte, such as configuring the value to "h9". Furthermore, since Byte 2 and Byte 3 are two consecutive bits in the same group, the bit width of the bits in Byte 2 of Dword 2 also needs to be configured to "hE", that is, each bit in Byte 2 is disabled. Additionally, for the bits in other bytes that did not experience operational failures, such as Dword 3, Dword 0, and Dword 1, and Byte 0 and Byte 1 in Dword 2, the configuration value of the corresponding bits can be set to "hF", meaning that the bit width of the corresponding bits does not need to be changed.

[0131] ② The target byte is a faulty byte.

[0132] In some examples, updating the bit width of the first bit of the faulty byte based on the bit width of the second bit of the target byte includes: if both the first bit of the first byte and the first bit of the second byte have operational faults, then changing the bit width of the first bit of the first byte to the bit width of the DBI signal in the first byte, and changing the bit width of the first bit of the second byte to the bit width of the DBI signal in the second byte.

[0133] In this example, since the redundant byte has a total data width of 8 bits, and the faulty byte consists of two consecutive bytes (i.e., the first byte and the second byte), and both the first and second bytes have byte faults, the allocated redundant bytes are insufficient to repair the faulty byte. Therefore, for each byte that has experienced a runtime fault, the DBI signal within that byte can be used for repair. For example, when the first bit of the first byte experiences a runtime fault, the bit width value of the first bit of the first byte can be changed using the bit width value of the DBI signal within that first byte. Specifically, if the first bit is the DQ signal or DM signal in the first byte, the bit width value of the DQ signal or DM signal in the first byte can be updated using the bit width value of the DBI signal. Similarly, when the second bit of the second byte also experiences a runtime fault, the bit width value of the first bit of the second byte can also be changed using the bit width value of the DBI signal within the second byte. Specifically, when the first bit is the DQ signal or DM signal in the second byte, the bit width value of the DBI signal in the second byte can be used to update the bit width value of the DQ signal or DM signal in the second byte.

[0134] For example, if the faulty bytes are determined to consist of Byte2 and Byte3 in Dword0 of Table 5, and both DM2 in Byte2 and DQ25 in Byte3 of Dword0 have experienced operational failures, then the corresponding configuration information can be understood by referring to Table 10, namely:

[0135] Table 10

[0136] Bit domain Configuration value 71:56 DWORD3[15:0] 16'hFFFF 55:40 DWORD2[15:0] 16'h9EFF 39:32 Reserved 16'hFF 31:16 DWORD1[15:0] 16'hFFFF 15:0 DWORD0[15:0] 16'h20FF

[0137] Referring to Table 5 above, we can see that the faulty DM2 is the 9th bit in Byte 2 of Dword 0, and DQ25 is the 2nd bit in Byte 3. In this case, mode 1 can be used to modify the bit width of DM2 to match the bit width of the DBI signal in Byte 2. Similarly, for DQ25 in Byte 3, mode 1 can also be used to modify the bit width of DQ25 to match the bit width of the DBI signal in Byte 3. Furthermore, for bits in other bytes that did not experience faults, such as Dword 3, Dword 2, and Dword 1, as well as Byte 0 and Byte 1 in Dword 0, the configuration value of the corresponding bits can be set to "hF", meaning that the bit width value of the corresponding bits does not need to be changed.

[0138] In other examples, updating the bit width of the first bit of the faulty byte based on the bit width of the second bit of the target byte can also be implemented as follows: if the first bit of either the first bit of the first byte or the first bit of the second byte experiences a malfunction, then the bit width of the first bit of the malfunctioning byte is changed to the bit width of the DBI signal in the corresponding byte. It should be noted that how to change the bit width of the first bit of the malfunctioning byte to the bit width of the DBI signal in the corresponding byte in this example can be understood by referring to the section above regarding the malfunction of bits in both bytes; it will not be elaborated here.

[0139] In other examples, after repairing the first bit through step 506 above, data can be written to the repaired first bit; or data can be read from the repaired first bit. It should be noted that the specific implementation process of writing data into the repaired first bit can be referred to the aforementioned... Figures 1A to 1D The content will be understood in detail here, and will not be repeated here. Additionally, the specific implementation process of reading data from the repaired first bit can also be referred to the aforementioned... Figures 2A to 2D The content will be understood in detail here, and will not be elaborated upon further.

[0140] (II) Performing a soft repair operation

[0141] Figure 6A second flowchart of the data repair method provided in an embodiment of this application is shown. Figure 6 As shown, the data repair method may include the following steps:

[0142] 601. Obtain first information, the first information including a first field, the first information being used to indicate that a soft repair operation identified by the first field needs to be performed on the fault byte in the Dword in the HBM where an operational failure has occurred, the Dword including at least two bytes, the fault byte being a byte from the at least two bytes.

[0143] In this example, before writing or reading data from the HBM, the host can detect whether any bytes in the Dword within the HBM are malfunctioning by sending commands or other means; alternatively, the host can detect malfunctions by using flags or other methods. For instance, a flag value of "1" indicates that the corresponding byte is functioning normally; a flag value of "0" indicates that the corresponding byte has malfunctioned, thus identifying the faulty byte in the Dword. For an example, how the host determines the faulty byte in the Dword can be referred to the aforementioned explanation. Figure 5 The content of step 501 in the previous section will be understood and will not be elaborated here.

[0144] When the host determines that a byte in the Dword has a runtime failure, it can further obtain first information and then, based on the value of the first field in that first information, determine whether a soft repair operation, identified by the first field, needs to be performed on the faulty byte in the Dword that has experienced a runtime failure in the HBM. Different values ​​of the first field indicate different repair operations. For example, when the first value indicates a hard repair operation, if the first field is set to the first value, it can be determined that a hard repair operation is required, as detailed above. Figure 5 The embodiments shown are for illustrative purposes only and will not be elaborated upon here. Similarly, when the second value is used to indicate a soft repair operation, if the first field takes the second value, the need for a soft repair operation can be determined through that second value. The first and second values ​​are not the same.

[0145] For example, since repair instructions such as SOFT_LANE_REPAIR include first information, the host can execute SOFT_LANE_REPAIR and other repair instructions through configuration instructions. Thus, after parsing the repair instruction, the first information carried in the repair instruction is obtained, and this first information includes a first field that identifies the corresponding repair operation. Taking SOFT_LANE_REPAIR as an example of a repair instruction, the first information described can be understood with reference to the content described in Table 11 below, namely:

[0146] Table 11

[0147]

[0148]

[0149] Furthermore, WIR[7:0] in Table 11 can be understood as the first field. The value of the first field is the second value, such as 12h, which can be used to indicate a soft repair operation. In other words, when the first field is the second value, it can be determined through this second value that a hard repair operation needs to be performed. For example, performing a soft repair operation can also be understood as executing soft repair instructions such as SOFT_LANE_REPAIR. Combining with Table 4 above, it can be seen from Table 11 that under the identifier 0h in WIR[11:8], since this identifier 0h can be used to identify channel 0 in the HBM DRAM, after obtaining the first information, the identifier 0h is determined from the first information, thus indicating that the SOFT_LANE_REPAIR instruction needs to be executed on channel 0 identified by 0h. Then, under the instruction of the SOFT_LANE_REPAIR instruction, the soft repair operation on HBM DRAM channel 0 is completed through the IEEE1500 interface. Similarly, the identifier 1h can be used to identify channel 1 in the HBM DRAM. After obtaining the first information, identifier 1h is determined from the first information, and it is then known that the SOFT_LANE_REPAIR instruction needs to be executed on channel 1 identified by 1h. Under the instruction of SOFT_LANE_REPAIR, the soft repair operation on HBM DRAM channel 1 is completed through the IEEE1500 interface. Similarly, the soft repair operation is performed on the channels corresponding to the other identifiers in Table 2 above. The specific implementation can be understood by referring to the soft repair operation performed on the channels corresponding to identifiers 0h and 1h, which will not be repeated here. It should be noted that the value of the first field in Table 11 is the second value, and the second value is 12h. This is only an exemplary description. In actual applications, other values ​​are possible, and this application embodiment does not limit the specific values.

[0150] Furthermore, as described in Table 2 above, each of the eight channels provided by HBM DRAM includes a Dword. Taking any channel as an example, the Dword includes the DQ, DM, and DBI signals, totaling 160 bits. Therefore, when at most eight of these 160 bits experience operational failures, soft repair can be achieved through remapping.

[0151] In addition, the Dword is divided in this example. For details, please refer to the content described in Table 5 above. It will not be repeated here.

[0152] 602. After determining, based on the first information, that a soft repair operation identified by the first field needs to be performed on the faulty byte in the Dword that has experienced a running failure, the first bit of the faulty byte is obtained. The first bit is the bit in the Dword that experienced a running failure.

[0153] In this example, after receiving the first information and determining, based on the indication of the value of the first field in the first information, that a soft repair operation needs to be performed on the faulty byte in the Dword that has experienced a runtime failure, the host can then further obtain the first bit of the faulty byte.

[0154] For example, if the flag bit of Byte1 in Dword0 is "0", then Byte1 is a faulty byte. If, using a similar method, we determine that the flag bits of certain bits in Byte1 are also "0", then we can also consider that the bits with flag bits of "0" have experienced a malfunction. In this case, the first bit can be identified from Byte1; that is, the first bit is the faulty bit in the Dword. For example, if the flag bit of DQ8 in Byte1 is "0", then DQ8 can be identified as the first faulty bit. It should be noted that this description only uses the flag bit method to illustrate the process of identifying faulty bytes; for a more detailed explanation of how to identify faulty bytes, please refer to the aforementioned explanation. Figure 5 The content of step 501 in the previous section will be understood and will not be elaborated here.

[0155] 603. Obtain the bit width value of the second bit of the target byte. The second bit is the bit in HBM that has not experienced a running fault. The target byte is either a faulty byte or a redundant byte in HBM.

[0156] In this example, if the first bit of a faulty byte experiences a malfunction, the bit width of the first bit can be updated using the bit width values ​​of other non-malfunctioning bits in the faulty byte, thus repairing the fault in the first bit. Alternatively, since HBM provides a redundant channel, i.e., the redundant data (RD) bits in Table 2 above, the bit width of the first bit in the faulty byte can also be updated using the bit width values ​​of the redundant bytes corresponding to the redundant channel, thus repairing the fault in the first bit. Therefore, regardless of the method used to repair the fault in the first bit, the bit width value of the second bit of the target byte needs to be obtained. The described bit width value can be understood as the data width. The described target byte can be a faulty byte, or it can be the redundant byte corresponding to RD in HBM.

[0157] For example, the host can obtain target configuration information, and use this target configuration information to obtain the bit width value of the second bit of the target byte. The target configuration information described herein can be understood with reference to the content shown in Table 6 above, and will not be repeated here.

[0158] It should be noted that the execution order of steps 602 and 603 is not specifically limited in this embodiment. For example, step 603 can be executed first, followed by step 602; or steps 602 and 603 can be executed simultaneously.

[0159] 604. Update the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte to repair the first bit.

[0160] In this example, after determining, based on the first information, to perform the soft repair operation identified by the first field on the faulty byte in the Dword that has experienced a runtime failure, the obtained bit width value of the second bit can be used to perform the soft repair operation on the bit in the faulty byte that has experienced a runtime failure, that is, to update the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte.

[0161] When a faulty byte consists of any one of at least two bytes in a Dword, or consists of two consecutive bytes, different repair modes can be used to update the bit width value of the first bit in the faulty byte. Based on this, the host can obtain the corresponding soft repair configuration information for the Dword, and through the indications in this soft repair configuration information, use different repair modes to perform soft repair on the bit in the faulty byte that has experienced a runtime failure. For example, the configuration of different repair modes in each Dword can be understood by referring to the content described in Table 7 below, namely:

[0162] Table 12

[0163]

[0164]

[0165] As can be seen from Table 12 above, taking Byte0 in Dword0 as an example, its corresponding soft repair configuration table describes the value of each bit in Byte0. Among them, "h9" indicates that when the DBI signal in Byte0 has a failure, mode 2 needs to be used for repair. The specific description of mode 2 can be understood by referring to the contents shown in case ① in mode (3) and case ① in mode (4) later, which will not be elaborated here. In addition, "hE" indicates that when a bit in any of two consecutive bytes has a failure, the bit width value of the bit that has not had a failure needs to be set to a disabled state. "hF" indicates that it is not necessary to perform soft repair on other bits that have not had a failure, and the original bit width value is still used. It should be noted that the identifiers "hE" and others shown in Table 7 above are only illustrative descriptions. Other identifiers may be used in actual applications, and this application embodiment does not limit them.

[0166] In addition, the soft repair configuration tables for other bytes in Dword0, other Dword1, Dword2, and each byte in Dword3 can be understood by referring to the soft repair configuration table for Byte0 in Dword0, which will not be elaborated here.

[0167] Based on the information shown in Tables 6 and 12 above, the following section provides a detailed description of how to soft-repair the first bit for faulty bytes composed of different bytes.

[0168] (3) The fault byte consists of any one of at least two bytes.

[0169] In this example, when the faulty byte consists of only one arbitrary byte, different repair modes can be used to update the bit width value of the first bit in the faulty byte, depending on whether the target byte belongs to a different type of byte. For example, if the target byte is a faulty byte, the bit width value of the first bit can be updated using the bit width value of the bits within the faulty byte that have not experienced operational failures. Alternatively, if the target byte is a redundant byte in HBM, the bit width value of the first bit can be updated using the bit width value of the redundant byte. The following section describes in detail how to soft-repair the first bit for different types of target bytes.

[0170] ① The target byte is a redundant byte.

[0171] For example, updating the bit width of the first bit of the faulty byte based on the bit width of the second bit of the target byte can be achieved by changing the bit width of the DBI signal to the bit width of any bit in the redundant byte when the first bit is a DBI signal.

[0172] In this example, since the redundant byte has a total data width of 8 bits, and the faulty byte consists of only one byte, the redundant byte is sufficient to be allocated to the faulty byte for soft repair. Therefore, when the first bit that caused the operational failure is determined to be the DBI signal in the faulty byte, the bit width of the DBI signal can be directly changed to the bit width of any bit in the redundant byte. Alternatively, the bit width of the DBI signal can be modified to the bit width of any bit in the redundant byte.

[0173] ② The target byte is a faulty byte.

[0174] For example, updating the bit width of the first bit of the faulty byte based on the bit width of the second bit of the target byte can be achieved as follows: when the first bit is a data mask (DM) signal or a data queue (DQ) signal, the bit width of the DM signal or the bit width of the DQ signal is changed to the bit width of the DBI signal of the faulty byte.

[0175] In this example, if the target byte is a fault byte, and the DM or DQ signal in the fault byte has a malfunction but the DBI signal has not, then the bit width value of the DBI signal in the current fault byte can be used directly to change the bit width value of the first bit that has already had a malfunction, that is, to change the bit width value of the DM or DQ signal in the fault byte.

[0176] It should be noted that after the first bit is repaired by the repair method ① or ② in the above method (3), the original DBI function in the fault byte corresponding to the first bit will no longer be used, while the DBI function in other bytes that have not undergone the soft repair operation can still continue to be used normally.

[0177] (4) The fault byte consists of two consecutive bytes from at least two bytes.

[0178] In this example, when the faulty byte consists of a first byte and a second byte, different repair modes can be used to update the bit width value of the first bit in the faulty byte if the target byte belongs to a different byte type. For example, if the target byte is a faulty byte, the bit width value of the first bit can be updated by the bit width value of the bits within the faulty byte that have not experienced operational failures. Alternatively, if the target byte is a redundant byte in HBM, the bit width value of the first bit can be updated by the bit width value of the redundant byte's bits. It should be noted that the first byte and the second byte described are two consecutive bytes out of at least two bytes. Below, we will describe in detail how to soft-repair the first bit for different types of target bytes.

[0179] ① The target byte is a redundant byte.

[0180] For example, updating the bit width of the first bit of the faulty byte based on the bit width of the second bit of the target byte can be achieved in the following way: if the first bit of either the first bit of the first byte or the first bit of the second byte experiences a failure, the bit width of the first bit of the byte experiencing the failure is changed to the bit width of any bit in the redundant byte.

[0181] In this example, since the redundant byte has a total data width of 8 bits, and the four Dwords shown in Table 5 have a total of 16 independent bytes, it is insufficient to allocate an independent redundant byte for soft repair for each of these 16 independent bytes. Therefore, consecutive bytes can be grouped together, and soft repair can be performed on consecutive bytes within the same group. For example, consecutive Byte0 and Byte1 in Dword0 in Table 5 can be grouped together and repaired simultaneously; similarly, consecutive Byte2 and Byte3 in Dword0 can be grouped together and repaired simultaneously. Likewise, for Dword1, Byte0 and Byte1 can be grouped together, and Byte2 and Byte3 can be grouped together. For Dword2, Byte0 and Byte1 can be grouped together, and Byte2 and Byte3 can be grouped together. For Dword3, Byte0 and Byte1 can be grouped together, and Byte2 and Byte3 can be grouped together.

[0182] In the case of a faulty byte consisting of two consecutive bytes, since the two consecutive bytes are allocated in the same group, and each group is allocated only one redundant byte for soft repair, and one redundant byte can only repair one byte, if the first bit of either the first bit of the first byte or the second bit of the second byte fails, the allocated redundant byte is sufficient for soft repair. Therefore, the bit width of the first bit of the byte with the failure can be changed to the bit width of any bit in the redundant byte. For example, if the first bit of the first byte fails, but the first bit of the second byte does not, the allocated redundant byte is sufficient to repair the first byte, and the bit width of the first bit of the first byte needs to be changed to the bit width of any bit in the redundant byte. Similarly, if the first bit of the second byte fails, but the first bit of the first byte does not, the bit width of the first bit of the second byte can also be changed to the bit width of any bit in the redundant byte. By using redundant bytes to repair the byte with the failure, the complete function of the DBI signal in the faulty byte can be preserved.

[0183] Furthermore, since redundant bytes can only be allocated to one byte for repair, for bytes within the same group that have not experienced operational failures, the bit width of the first bit of that byte is changed to a target value. This target value indicates that the first bit of the byte that has not experienced operational failures is disabled. The described target value may include, but is not limited to, "hE", where "E" can be understood as a hexadecimal value, i.e., "1110". It should be noted that in some examples, the target value may also be other numerical values, which are not limited in the embodiments of this application.

[0184] For example, if it is determined that the faulty byte consists of Byte0 and Byte1 in Dword0 of Table 5 above, and DQ12 in Byte1 is the first bit of the operational fault, then the corresponding configuration information can be understood by referring to the contents of Table 8 above, which will not be elaborated here.

[0185] Alternatively, if it is determined that the faulty byte is composed of Byte3 in Dword2 of Table 5, and DBI11 in Byte3 is the first bit of the operational fault, then the corresponding configuration information can be understood by referring to Table 13, that is:

[0186] Table 13

[0187] Bit domain Configuration value 71:56 DWORD3[15:0] 16'hFFFF 55:40 DWORD2[15:0] 16'h9EFF 39:32 Reserved 16'hFF 31:16 DWORD1[15:0] 16'hFFFF 15:0 DWORD0[15:0] 16'hFFFF

[0188] Based on Table 5 above, we can see that the DBI11 that experienced the operational failure is the 9th bit of Byte 3 in Dword 2. Table 13 shows that we can use Mode 2 to change the bit width of DBI11 to the bit width of any bit in the redundant byte, such as configuring the value to "h9". Furthermore, since Byte 2 and Byte 3 are two consecutive bits in the same group, we also need to configure the bit width of the bits in Byte 2 of Dword 2 to "hE", that is, disable each bit in Byte 2. Additionally, for the bits in other bytes that did not experience operational failures, such as Dword 3, Dword 0, and Dword 1, and Byte 0 and Byte 1 in Dword 2, the configuration value of the corresponding bits can be set to "hF", meaning we do not need to change the bit width of the corresponding bits.

[0189] ② The target byte is a faulty byte.

[0190] In some examples, updating the bit width of the first bit of the faulty byte based on the bit width of the second bit of the target byte includes: if both the first bit of the first byte and the first bit of the second byte have operational faults, then changing the bit width of the first bit of the first byte to the bit width of the DBI signal in the first byte, and changing the bit width of the first bit of the second byte to the bit width of the DBI signal in the second byte.

[0191] In this example, since the redundant byte has a total data width of 8 bits, and the faulty byte consists of two consecutive bytes (i.e., the first byte and the second byte), and both the first and second bytes have byte faults, the allocated redundant bytes are insufficient to repair the faulty byte. Therefore, for each byte that has experienced a runtime fault, the DBI signal within that byte can be used for repair. For example, when the first bit of the first byte experiences a runtime fault, the bit width value of the first bit of the first byte can be changed using the bit width value of the DBI signal within that first byte. Specifically, if the first bit is the DQ signal or DM signal in the first byte, the bit width value of the DQ signal or DM signal in the first byte can be updated using the bit width value of the DBI signal. Similarly, when the second bit of the second byte also experiences a runtime fault, the bit width value of the first bit of the second byte can also be changed using the bit width value of the DBI signal within the second byte. Specifically, when the first bit is the DQ signal or DM signal in the second byte, the bit width value of the DBI signal in the second byte can be used to update the bit width value of the DQ signal or DM signal in the second byte.

[0192] For example, if the faulty byte is determined to consist of Byte2 and Byte3 in Dword0 of Table 5, and both DM2 in Byte2 and DQ25 in Byte3 of Dword0 are experiencing operational failures, the corresponding configuration information can be understood by referring to the content of Table 10 above, and will not be elaborated here. In some other examples, updating the bit width of the first bit of the faulty byte based on the bit width of the second bit of the target byte can also be implemented as follows: if the first bit of either the first bit of the first byte or the first bit of the second byte is experiencing an operational failure, then the bit width of the first bit of the byte experiencing the operational failure is changed to the bit width of the DBI signal in the corresponding byte. It should be noted that how to change the bit width of the first bit of the byte experiencing the operational failure to the bit width of the DBI signal in the corresponding byte in this example can be understood by referring to the content above where bits in both bytes are experiencing operational failures, and will not be elaborated here.

[0193] In other examples, after repairing the first bit through step 604 above, data can be written to the repaired first bit; or data can be read from the repaired first bit. It should be noted that the specific implementation process of writing data into the repaired first bit can be referred to the aforementioned... Figures 1A to 1D The content will be understood in detail here, and will not be repeated here. Additionally, the specific implementation process of reading data from the repaired first bit can also be referred to the aforementioned... Figures 2A to 2D The content will be understood in detail here, and will not be elaborated upon further.

[0194] In this embodiment, since the first information can be used to indicate that the repair operation identified by the first field needs to be performed on the faulty byte in the Dword of the high-bandwidth memory (HBM) that has experienced a malfunction, and the Dword includes at least two bytes, with the faulty byte being one of those at least two bytes, after obtaining the first information and determining, based on the first information, that the repair operation identified by the first field needs to be performed on the faulty byte in the Dword that has experienced a malfunction, the first bit of the faulty byte can be obtained. This first bit is the bit in the Dword that has experienced a malfunction. Then, using the faulty byte as the target byte or a redundant byte in the HBM as the target byte, the bit width value of the second bit of the target byte can be obtained. This second bit is the bit in the Dword that has not experienced a malfunction. Thus, when the target byte is a faulty byte or a redundant byte in the HBM, the bit width value of the first bit of the faulty byte can be updated based on the bit width value of the second bit of the target byte, thereby completing the repair of the faulty bit in the Dword, i.e., completing the repair of the first bit. In other words, it can be understood that the bit width value of the bit that has experienced a runtime failure can be updated by using the bit width value of the bit that has not experienced a runtime failure in the fault byte of the Dword, or the bit width value of the bit that has experienced a runtime failure in the fault byte can be updated by using the bit width value of the bit in the redundant byte of the HBM, thereby completing the repair processing of the bit that has experienced a runtime failure in a timely manner and ensuring the correctness of subsequent HBM data reading and writing.

[0195] The foregoing primarily describes the solutions provided by the embodiments of this application from a methodological perspective. It is understood that to achieve the above functions, corresponding hardware structures and / or software modules are included to execute each function. Those skilled in the art should readily recognize that, based on the modules and algorithm steps described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0196] This application embodiment can divide the device into functional modules according to the above method example. For example, each function can be divided into its own functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0197] The data repair apparatus in the embodiments of this application will be described in detail below. Figure 7 This is a schematic diagram of one embodiment of the data repair apparatus provided in this application. The described data repair apparatus may include, but is not limited to, servers, terminal devices, etc., and this application does not limit it. Figure 7 As shown, the data repair device includes an acquisition unit 701 and a processing unit 702.

[0198] The acquisition unit 701 is used to acquire first information, which includes a first field. The first information indicates that a repair operation identified by the first field needs to be performed on the faulty byte in the Dword of the high-bandwidth memory (HBM) that has experienced a malfunction. The Dword includes at least two bytes, and the faulty byte is one of those at least two bytes. It should be noted that different values ​​in the first field can indicate different repair operations. For example, when the first value indicates a hard repair operation, the first value indicates that a hard repair operation needs to be performed; similarly, when the second value indicates a soft repair operation, the second value indicates that a soft repair operation needs to be performed, where the first and second values ​​are different. See the foregoing for details. Figure 5 Step 501 or the aforementioned Figure 6 The content described in step 601 is for your understanding and will not be repeated here.

[0199] The acquisition unit 701 is used to acquire the first bit of the faulty byte after determining, based on the first information, that a repair operation identified by the first field needs to be performed on the faulty byte in the Dword that has experienced a runtime failure. The first bit is the bit in the Dword where the runtime failure occurred. For details, please refer to the foregoing. Figure 5 Step 502 or the aforementioned Figure 6 The content described in step 602 is for your understanding and will not be repeated here.

[0200] Acquisition unit 701 is used to acquire the bit width value of the second bit of the target byte. The second bit is a bit in the HBM that has not experienced a running fault, and the target byte is either a faulty byte or a redundant byte in the HBM. For details, please refer to the foregoing. Figure 5 Step 503 or the aforementioned Figure 6 The content described in step 603 is for your understanding and will not be repeated here.

[0201] Processing unit 702 is used to update the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte, so as to repair the first bit. See the foregoing for details. Figure 5 Step 506 or the aforementioned Figure 6 The content described in step 604 is for your understanding and will not be repeated here.

[0202] In some optional examples, the repair operation includes a hard repair operation; the acquisition unit 701 is further configured to acquire hard repair confirmation information when the value of the first field is a first value before updating the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte to repair the first bit. The hard repair confirmation information indicates at least one confirmation of whether a hard repair operation has been performed on the faulty byte in the Dword that has experienced a runtime failure, and the first value is used to indicate the hard repair operation. The processing unit 702 is configured to determine, based on the hard repair confirmation information, to perform a hard repair operation on the faulty byte in the Dword that has experienced a runtime failure. See the foregoing for details. Figure 5 The content described in steps 504 to 505 is for your understanding and will not be repeated here.

[0203] In some other optional examples, the fault byte consists of any one of at least two bytes.

[0204] In some alternative examples, the target byte is a redundant byte. Processing unit 702 is configured to: when the first bit is the data bus toggle DBI signal, change the bit width value of the DBI signal to the bit width value of any bit in the redundant byte. See the foregoing for details. Figure 5 Step 506 or the aforementioned Figure 6 The content described in step 604 is for your understanding and will not be repeated here.

[0205] In some alternative examples, the target byte is a fault byte. Processing unit 702 is configured to: when the first bit is a data mask (DM) signal or a data queue (DQ) signal, change the bit width value of the DM signal or the bit width value of the DQ signal to the bit width value of the fault byte's DBI signal. See the foregoing for details. Figure 5 Step 506 or the aforementioned Figure 6The content described in step 604 is for your understanding and will not be repeated here.

[0206] In some alternative examples, the fault byte consists of a first byte and a second byte, which are two consecutive bytes out of at least two bytes.

[0207] In some alternative examples, the target byte is a fault byte. Processing unit 702 is configured to: if both the first bit of the first byte and the first bit of the second byte experience operational faults, change the bit width value of the first bit of the first byte to the bit width value of the DBI signal in the first byte, and change the bit width value of the first bit of the second byte to the bit width value of the DBI signal in the second byte. See the foregoing for details. Figure 5 Step 506 or the aforementioned Figure 6 The content described in step 604 is for your understanding and will not be repeated here.

[0208] In some alternative examples, the target byte is a fault byte. Processing unit 702 is configured to: if the first bit of either the first bit of the first byte or the first bit of the second byte experiences a malfunction, change the bit width value of the first bit of the malfunctioning byte to the bit width value of the DBI signal in the corresponding byte. See the foregoing for details. Figure 5 Step 506 or the aforementioned Figure 6 The content described in step 604 is for your understanding and will not be repeated here.

[0209] In some alternative examples, the target byte is a redundant byte. Processing unit 702 is configured to: if the first bit of either the first bit of the first byte or the first bit of the second byte experiences a malfunction, change the bit width value of the first bit of the malfunctioning byte to the bit width value of any bit in the redundant byte. See the foregoing for details. Figure 5 Step 506 or the aforementioned Figure 6 The content described in step 604 is for your understanding and will not be repeated here.

[0210] In some alternative examples, processing unit 702 is further configured to: change the bit width value of the first bit of the byte that has not experienced a runtime failure to a target value, the target value being used to indicate that the first bit of the byte that has not experienced a runtime failure is disabled. See the foregoing for details. Figure 5 Step 506 or the aforementioned Figure 6 The content described in step 604 is for your understanding and will not be repeated here.

[0211] In some alternative examples, the acquisition unit 701 is used to: acquire a first instruction, the first instruction including the first bit of a fault byte. See the foregoing for details. Figure 5Step 502 or the aforementioned Figure 6 The content described in step 602 is for your understanding and will not be repeated here.

[0212] In some alternative examples, the processing unit 702 is also configured to: update the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte to repair the first bit, and then write data into the repaired first bit; or, read data from the repaired first bit.

[0213] The data repair device in this application embodiment has been described above from the perspective of modular functional entities. The data repair device in this application embodiment is now described below from the perspective of hardware processing. The described data repair device may include, but is not limited to, servers, terminal devices, etc., and this application does not impose any limitations on it. Figure 8 This is a schematic diagram of the data repair device provided in an embodiment of this application. The data repair device can vary considerably due to differences in configuration or performance. The data repair device may include at least one processor 801, a communication line 807, a memory 803, and at least one communication interface 804.

[0214] The processor 801 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (server IC), or one or more integrated circuits used to control the execution of the program of the present application.

[0215] Communication line 807 may include a path for transmitting information between the aforementioned components.

[0216] The communication interface 804 uses any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area networks (WLAN), etc.

[0217] The memory 803 can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions. The memory can exist independently and be connected to the processor via communication line 807. The memory can also be integrated with the processor.

[0218] The memory 803 stores computer execution instructions for implementing the scheme of this application, and its execution is controlled by the processor 801. The processor 801 executes the computer execution instructions stored in the memory 803, thereby implementing the data repair method provided in the above embodiments of this application.

[0219] Optionally, the computer execution instructions in the embodiments of this application may also be referred to as application code, and the embodiments of this application do not specifically limit this.

[0220] In a specific implementation, as one example, the data repair device may include multiple processors, such as... Figure 8 Processors 801 and 802 are described herein. Each of these processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. A processor here may refer to one or more devices, circuits, and / or processing cores used to process data (e.g., computer program instructions).

[0221] In a specific implementation, as one embodiment, the data repair device may further include an output device 805 and an input device 806. The output device 805 communicates with the processor 801 and can display information in various ways. The input device 806 communicates with the processor 801 and can receive input from the target object in various ways. For example, the input device 806 may be a mouse, a touch screen device, or a sensing device, etc.

[0222] The aforementioned data repair device can be a general-purpose device or a dedicated device. In specific implementations, the data repair device can be a server, a terminal, or something similar. Figure 8 A device with a similar structure. The embodiments of this application do not limit the type of data repair device.

[0223] It should be noted that Figure 8 The processor 801 can invoke computer execution instructions stored in the memory 803 to cause the data repair device to perform actions such as... Figure 5 or Figure 6 The data repair method in the corresponding method embodiment.

[0224] Specifically, Figure 7 The function / implementation process of the processing unit 702 can be achieved through... Figure 8 The processor 801 in the memory calls computer execution instructions stored in the memory 803 to implement the function. Figure 7 The function / implementation process of the acquisition unit 701 can be achieved through... Figure 8 It is implemented using the 804 communication interface.

[0225] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0226] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0227] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0228] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0229] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0230] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0231] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, they can be implemented in whole or in part in the form of a computer program product.

[0232] A computer program product includes one or more computer instructions. When these computer instructions are loaded and executed on a computer, they generate, in whole or in part, the processes or functions according to embodiments of this application. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions may be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., SSDs), etc.

[0233] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for data repair, characterized in that, include: Obtain first information, the first information including a first field, the first information being used to indicate that a repair operation identified by the first field needs to be performed on the faulty byte in the Dword of the high bandwidth memory HBM that has experienced a running failure, the Dword including at least two bytes, the faulty byte being a byte among the at least two bytes; After determining, based on the first information, that the repair operation identified by the first field needs to be performed on the faulty byte in the Dword that has experienced a running failure, the first bit of the faulty byte is obtained, where the first bit is the bit in the Dword where the running failure occurred; Obtain the bit width value of the second bit of the target byte, where the second bit is the bit in the HBM where the operational fault has not occurred, and the target byte is either the fault byte or a redundant byte in the HBM; The bit width value of the first bit of the faulty byte is updated based on the bit width value of the second bit of the target byte to repair the first bit.

2. The method according to claim 1, characterized in that, The repair operation includes a hard repair operation. Before repairing the first bit by updating the bit width value of the faulty byte based on the bit width value of the second bit of the target byte, the method further includes: When the value of the first field is the first value, hard repair confirmation information is obtained. The hard repair confirmation information indicates at least one confirmation of whether the hard repair operation has been performed on the faulty byte in the Dword that has experienced a running failure. The first value is used to indicate the hard repair operation. Based on the hard repair confirmation information, it is determined that the hard repair operation will be performed on the faulty bytes in the Dword that has experienced a runtime failure.

3. The method according to claim 1 or 2, characterized in that, The fault byte is composed of any one of the at least two bytes.

4. The method according to claim 3, characterized in that, The target byte is the redundant byte; updating the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte includes: When the first bit is the data bus toggle DBI signal, the bit width value of the DBI signal is changed to the bit width value of any bit in the redundant byte.

5. The method according to claim 3, characterized in that, The target byte is the faulty byte; updating the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte includes: When the first bit is a data mask DM signal or a data queue DQ signal, the bit width value of the DM signal or the bit width value of the DQ signal is changed to the bit width value of the fault byte's DBI signal.

6. The method according to claim 1 or 2, characterized in that, The fault byte consists of a first byte and a second byte, wherein the first byte and the second byte are two consecutive bytes among the at least two bytes.

7. The method according to claim 6, characterized in that, The target byte is the faulty byte; updating the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte includes: If both the first bit of the first byte and the first bit of the second byte experience a malfunction, then the bit width value of the first bit of the first byte is changed to the bit width value of the DBI signal in the first byte, and the bit width value of the first bit of the second byte is changed to the bit width value of the DBI signal in the second byte.

8. The method according to claim 6, characterized in that, The target byte is a faulty byte; updating the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte includes: If the first bit of either the first bit of the first byte or the first bit of the second byte experiences a malfunction, the bit width value of the first bit of the malfunctioning byte will be changed to the bit width value of the DBI signal in the corresponding byte.

9. The method according to claim 6, characterized in that, The target byte is the redundant byte; updating the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte includes: If the first bit of either the first bit of the first byte or the first bit of the second byte experiences a malfunction, the bit width value of the first bit of the malfunctioning byte is changed to the bit width value of any bit in the redundant byte.

10. The method according to claim 8 or 9, characterized in that, The method further includes: The bit width value of the first bit of the byte that did not experience the operational failure is changed to a target value, which is used to indicate that the first bit of the byte that did not experience the operational failure is disabled.

11. The method according to claim 1 or 2, characterized in that, Obtaining the first bit of the fault byte includes: Obtain a first instruction, the first instruction including the first bit of the fault byte.

12. The method according to claim 1 or 2, characterized in that, After updating the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte to repair the first bit, the method further includes: Write the data into the repaired first bit; or, Read the data from the repaired first bit.

13. A data repair device, characterized in that, include: The acquisition unit is used to acquire first information, the first information including a first field, the first information being used to indicate that a repair operation identified by the first field needs to be performed on the faulty byte in the Dword of the high bandwidth memory HBM that has experienced a running failure, the Dword including at least two bytes, and the faulty byte being a byte among the at least two bytes; The acquisition unit is configured to acquire the first bit of the faulty byte after determining, based on the first information, that a repair operation identified by the first field needs to be performed on the faulty byte in the Dword that has experienced a running failure. The first bit is the bit in the Dword where the running failure occurred. The acquisition unit is used to acquire the bit width value of the second bit of the target byte, wherein the second bit is a bit in the HBM where the operational fault has not occurred, and the target byte is the fault byte or a redundant byte in the HBM; The processing unit is configured to update the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte, so as to repair the first bit.

14. A data repair device, characterized in that, include: Input / output (I / O) interface, processor, and memory, wherein program instructions are stored in the memory; The processor is configured to execute program instructions stored in the memory to perform the method as described in any one of claims 1 to 12.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes instructions that, when executed on a computer device, cause the computer device to perform the method as described in any one of claims 1 to 12.

16. A computer program product, characterized in that, The computer program product includes instructions that, when executed on a computer device, cause the computer device to perform the method as described in any one of claims 1 to 12.

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