Display panel and display device

Abstract

The application provides a display panel and a display device, wherein M0 signal lines are arranged to be overlapped with a first driving circuit, and N0 signal lines are arranged to be overlapped with a second driving circuit, so that the area occupied by the signal lines can be reduced, and the frame width of the display device can be reduced. Furthermore, the width W1 of the first driving circuit, the width W2 of the second driving circuit, the total width D1 of the M0 signal lines and the total width D2 of the N0 signal lines are arranged to satisfy the relationship W2>W1, D2>D1 and D2 / W2>D1 / W1, so that the overlap of the shift register with a larger width and the shift register with a smaller width and the total width of the corresponding signal lines is optimized, the area occupied by the driving circuit and the signal lines is reduced, and the frame width of the display device is further reduced.

Description

[0001] This application is a divisional application of a patent with the application date of September 10, 2021, the application number of 202111063932.7, and the invention name of display panel and display device. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, more specifically, to a display panel and a display device. BACKGROUND

[0003] The existing display device frame area includes a peripheral driving circuit for providing a driving signal for a display area pixel unit. In the display device, a plurality of pixel units are arranged in the display area, and each pixel unit includes a pixel circuit. Each pixel circuit is electrically connected with the peripheral driving circuit at the frame area, and the peripheral driving circuit provides a scanning control signal and a light emitting control signal for the pixel circuit to control the pixel circuit to provide a driving current for the light emitting element. However, the existing driving circuit occupies a large space, which makes it difficult to reduce the frame width of the display device. SUMMARY

[0004] Therefore, the present application provides a display panel and a display device, which effectively solve the technical problems existing in the prior art and ensure that the frame width of the display device is small.

[0005] To achieve the above-mentioned purpose, the technical scheme provided by the present application is as follows:

[0006] A display panel comprises:

[0007] a driving circuit and a pixel circuit, the driving circuit provides a control signal for the pixel circuit, and the pixel circuit provides a driving current for a light emitting element of the display panel;

[0008] The driving circuit comprises a first driving circuit and a second driving circuit;

[0009] a signal line group, the signal line group comprises a first signal line group and a second signal line group, the first signal line group comprises M signal lines for providing signals for the first driving circuit, and the second signal line group comprises N signal lines for providing signals for the second driving circuit, M≥1, N≥1;

[0010] In the direction perpendicular to the surface of the display panel, M0 signal lines in the first signal line group intersect and overlap with the first driving circuit, and N0 signal lines in the second signal line group intersect and overlap with the second driving circuit, 1≤M0≤M, 1≤N0≤N;

[0011] The first driving circuit comprises a S1-stage shift register extending along a first direction, and the second driving circuit comprises a S2-stage shift register extending along the first direction, a second direction being parallel to a plane in which the display panel surface is located and perpendicular to the first direction, S1>=2, and S2>=2; wherein,

[0012] In the second direction, a width of the first driving circuit is W1, a width of the second driving circuit is W2, a total width of the M0 signal lines in the first signal line group is D1, and a total width of the N0 signal lines in the second signal line group is D2.

[0013] W2>W1, D2>D1, and D2 / W2>D1 / W1.

[0014] Correspondingly, the application also provides a display device comprising the display panel.

[0015] Compared with the prior art, the technical solution provided by the application has at least the following advantages:

[0016] The application provides a display panel and a display device, wherein the M0 signal lines and the first driving circuit are arranged to intersect and overlap each other, and the N0 signal lines and the second driving circuit are arranged to intersect and overlap each other, so that the area occupied by part of the signal lines can be reduced, and the frame width of the display device can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only provide the embodiments of the application, and for those skilled in the art, other drawings can be obtained based on the drawings provided without any creative effort.

[0018] Figure 1 A structural schematic diagram of a display panel provided by the embodiment of the application is shown in the figure.

[0019] Figure 2 A structural schematic diagram of another display panel provided by the embodiment of the application is shown in the figure.

[0020] Figure 3A structure schematic diagram of still another display panel provided by the embodiment of the present application is shown in FIG. 6;

[0021] Figure 4 A structure schematic diagram of still another display panel provided by the embodiment of the present application is shown in FIG. 6;

[0022] Figure 5 A structure schematic diagram of still another display panel provided by the embodiment of the present application is shown in FIG. 6;

[0023] Figure 6 A structure schematic diagram of still another display panel provided by the embodiment of the present application is shown in FIG. 6;

[0024] Figure 7 A structure schematic diagram of still another display panel provided by the embodiment of the present application is shown in FIG. 6;

[0025] Figure 8 A structure schematic diagram of a shift register provided by the embodiment of the present application is shown in FIG. 7;

[0026] Figure 9 A structure schematic diagram of a shift register provided by the embodiment of the present application is shown in FIG. 7; Figure 8 A structure layout of the shift register shown in FIG. 7 is shown in FIG. 8;

[0027] Figure 10 A structure schematic diagram of a shift register provided by the embodiment of the present application is shown in FIG. 7;

[0028] Figure 11 A structure schematic diagram of a shift register provided by the embodiment of the present application is shown in FIG. 7; Figure 10 A structure layout of the shift register shown in FIG. 7 is shown in FIG. 8;

[0029] Figure 12 A structure schematic diagram of a shift register provided by the embodiment of the present application is shown in FIG. 7;

[0030] Figure 13 A structure schematic diagram of a shift register provided by the embodiment of the present application is shown in FIG. 7; Figure 12 A structure layout of the shift register shown in FIG. 7 is shown in FIG. 8;

[0031] Figure 14 A structure schematic diagram of a shift register of a first driving circuit provided by the embodiment of the present application is shown in FIG. 9;

[0032] Figure 15 A structure schematic diagram of a shift register of a second driving circuit provided by the embodiment of the present application is shown in FIG. 10;

[0033] Figure 16 A structure schematic diagram of a signal line provided by the embodiment of the present application is shown in FIG. 11;

[0034] Figure 17 A structure schematic diagram of a signal line provided by the embodiment of the present application is shown in FIG. 11;

[0035] Figure 18 A structure schematic diagram of still another display panel provided by the embodiment of the present application is shown in FIG. 6;

[0036] Figure 19 FIG. 1 shows a structural schematic diagram of a display panel according to an embodiment of the present application;

[0037] Figure 20 FIG. 1 shows a structural schematic diagram of a display panel according to an embodiment of the present application;

[0038] Figure 21 FIG. 1 shows a structural schematic diagram of a display panel according to an embodiment of the present application; DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0040] As described in the background, the existing display device frame area includes a peripheral driving circuit for providing a driving signal for a pixel unit of a display area. In the display device, a plurality of pixel units are arranged in the display area, and each pixel unit includes a pixel circuit. Each pixel circuit is electrically connected to the peripheral driving circuit at the frame area, and the peripheral driving circuit provides a scanning control signal and a light emitting control signal for the pixel circuit to control the pixel circuit to provide a driving current for a light emitting element. However, the existing driving circuit occupies a large space, which makes it difficult to reduce the frame width of the display device.

[0041] Therefore, the embodiments of the present application provide a display panel and a display device, which effectively solve the technical problems in the prior art and ensure that the frame width of the display device is small.

[0042] To achieve the above object, the technical solutions provided by the embodiments of the present application are as follows, which will be specifically described in combination with Figures 1 to 21 The technical solutions provided by the embodiments of the present application will be described in detail.

[0043] Reference Figure 1 FIG. 1 shows a structural schematic diagram of a display panel according to an embodiment of the present application, wherein the display panel includes a driving circuit and a pixel circuit 20, the driving circuit provides a control signal for the pixel circuit 20, and the pixel circuit 20 provides a driving current for a light emitting element 30 of the display panel.

[0044] The display panel includes a display area AA and a frame area NA, the pixel circuit 20 and the light emitting element 30 can be arranged in the display area AA, and the driving circuit is arranged in the frame area NA. The driving circuit includes a first driving circuit 11 and a second driving circuit 12.

[0045] The display panel includes a signal line group at the frame area NA, the signal line group includes a first signal line group and a second signal line group, the first signal line group includes M signal lines for providing signals to the first driving circuit 11, the second signal line group includes N signal lines for providing signals to the second driving circuit 12, M≥1, N≥1. In addition, in the direction perpendicular to the surface of the display panel (i.e. in the direction perpendicular to the light-emitting direction of the display panel), M0 signal lines 110 in the first signal line group intersect and overlap with the first driving circuit 11, N0 signal lines 120 in the second signal line group intersect and overlap with the second driving circuit 12, 1≤M0≤M, 1≤N0≤N.

[0046] The first driving circuit 11 includes a S1-stage shift register extending along the first direction Y, the second driving circuit 12 includes a S2-stage shift register extending along the first direction Y, and the first driving circuit 11 and the second driving circuit 12 can be arranged along the second direction X. Wherein, the second direction X is parallel to the plane where the surface of the display panel is located, and perpendicular to the first direction Y, S1≥2, S2≥2; wherein,

[0047] Along the second direction X, the width of the first driving circuit 11 is W1, the width of the second driving circuit 12 is W2, the total width of the M0 signal lines 110 in the first signal line group is D1, and the total width of the N0 signal lines 120 in the second signal line group is D2; W2>W1, D2>D1, and D2 / W2>D1 / W1.

[0048] It can be understood that by arranging the intersection and overlap between the M0 signal lines and the first driving circuit, and the intersection and overlap between the N0 signal lines and the second driving circuit, wherein the extension direction of the M0 signal lines and the extension direction of the N0 signal lines are the first direction, the occupied area of part of the signal lines can be reduced, and the frame width of the display device can be reduced.

[0049] In the second direction, when the width of the driving circuit is wider and the width of the signal line is wider, the bezel of the display panel is larger. In order to reduce the bezel, the signal line and the driving circuit can generally be set to overlap with each other to reduce the bezel. However, when there is more than one set of driving circuits in the bezel, how to set it to fully reduce the bezel is a problem. Based on this problem, the inventors of this application found that when W2>W1 and D2>D1, by setting D2 / W2>D1 / W1, the width of the signal line overlapped by the driving circuit with a larger width is also larger, thereby fully reducing the width occupied by the driving circuit with a larger width and the signal line connected to it on the display panel, so that the driving circuit with a larger width and the driving circuit with a smaller width both achieve a good overlapping relationship with their respective signal lines, thereby fully reducing the bezel. Therefore, the embodiment of the present application further optimizes the overlapping setting of the shift register with a larger width and the shift register with a smaller width and the total width of their respective corresponding signal lines by setting the relationship between the width W1 of the first driving circuit, the width W2 of the second driving circuit, the total width D1 of the M0 signal lines and the total width D2 of the N0 signal lines to W2>W1, D2>D1, and D2 / W2>D1 / W1, thereby fully reducing the occupied area of ​​the driving circuit and the signal lines, and further reducing the border width of the display device.

[0050] In one embodiment of the present invention, the display panel provided by the present invention may be a unilaterally driven panel structure, such as Figure 1 As described above, the first driving circuit 11 and the second driving circuit 12 of the driving circuit are located on one side of the display area AA, and the pixel circuit 20 is driven by the unilateral driving circuit. Alternatively, the display panel provided by the present invention can also be a panel structure with bilateral driving, such as Figure 2 As shown, the driving circuit includes a first driving circuit 11 located on both sides of the display area AA, and the driving circuit includes a second driving circuit 12 located on both sides of the display area AA, thereby driving the pixel circuit 20 through the bilateral driving circuit.

[0051] like Figure 2 As shown, in the double-sided driven panel structure provided by an embodiment of the present invention, the pixel circuits 20 in the same row can be driven simultaneously by two first driving circuits 11 located on different sides of the display area AA, and the pixel circuits 20 in the same row can be driven simultaneously by two second driving circuits 12 located on different sides of the display area AA.

[0052] It can be understood that the first driving circuit on different sides of the display area (defined as the first side first driving circuit and the second side first driving circuit) each includes a plurality of cascaded shift registers, the first stage shift register of the first side first driving circuit and the first stage shift register of the second side first driving circuit are electrically connected with the pixel circuit of the first row, the second stage shift register of the first side first driving circuit and the second stage shift register of the second side first driving circuit are electrically connected with the pixel circuit of the second row, and so on, the last stage shift register of the first side first driving circuit and the last stage shift register of the second side first driving circuit are electrically connected with the pixel circuit of the last row. Similarly, the second driving circuit on different sides of the display area (defined as the first side second driving circuit and the second side second driving circuit) each includes a plurality of cascaded shift registers, the first stage shift register of the first side second driving circuit and the first stage shift register of the second side second driving circuit are electrically connected with the pixel circuit of the first row, the second stage shift register of the first side second driving circuit and the second stage shift register of the second side second driving circuit are electrically connected with the pixel circuit of the second row, and so on, the last stage shift register of the first side second driving circuit and the last stage shift register of the second side second driving circuit are electrically connected with the pixel circuit of the last row.

[0053] Alternatively, as shown in FIG. 2, the panel structure provided by the embodiment of the present application is driven by two first driving circuits 11 on different sides of the display area AA, and the pixel circuit 20 of different rows is driven by two second driving circuits 12 on different sides of the display area AA. Figure 3

[0054] It can be understood that the odd stage first driving circuit in the first driving circuit is located on the first side of the display area, and the even stage first driving circuit in the first driving circuit is located on the second side of the display area, wherein the odd stage first driving circuit is electrically connected with the pixel circuit of the odd row, and the even stage first driving circuit is electrically connected with the pixel circuit of the even row. Similarly, the odd stage second driving circuit in the second driving circuit is located on the first side of the display area, and the even stage second driving circuit in the second driving circuit is located on the second side of the display area, wherein the odd stage second driving circuit is electrically connected with the pixel circuit of the odd row, and the even stage second driving circuit is electrically connected with the pixel circuit of the even row.

[0055] ​In one embodiment of the present invention, the display panel provided by the present invention includes a base substrate, the driving circuit and the pixel circuit are located on the base substrate; the M0 signal lines are located on the side of the first driving circuit away from the base substrate, the N0 signal lines are located on the side of the second driving circuit away from the base substrate, and the M0 signal lines are located on the same layer, and / or the N0 signal lines are located on the same layer. Figure 4 , which is a schematic structural diagram of another display panel provided by an embodiment of the present invention, wherein the display panel includes a substrate 100. A transistor array layer located on the substrate 100 includes a semiconductor layer 210 located on the substrate 100, the semiconductor layer 210 including a plurality of active regions; a gate insulating layer 220 located on a side of the semiconductor layer 210 facing away from the substrate 100; a gate metal layer 230 located on a side of the gate insulating layer 220 facing away from the substrate 100, the gate metal layer 230 including a plurality of gate electrodes and a plurality of first capacitor plates; an interlayer insulating layer 240 located on a side of the gate metal layer 230 facing away from the substrate 100; and an interlayer insulating layer 250 located on a side of the gate metal layer 230 facing away from the substrate 100. The insulating layer 240 is located on the side of the capacitor metal layer 250 facing away from the substrate 100, and the capacitor metal layer 250 includes a second capacitor plate arranged to overlap with the first capacitor plate; the isolation layer 260 is located on the side of the capacitor metal layer 250 facing away from the substrate 100; the source-drain metal layer 270 is located on the side of the isolation layer 260 facing away from the substrate 100, and the source-drain metal layer 270 includes multiple source electrodes and drain electrodes, and the source electrodes and drain electrodes are connected to the active area through their respective corresponding vias; wherein the transistor array layer includes a driving circuit and a pixel circuit. The first insulating layer 310 is located on the side of the source-drain metal layer 270 facing away from the substrate 100. The M0 signal lines 110 are located on the side of the first insulating layer 310 facing away from the substrate 100, wherein the M0 signal lines 110 can be prepared from the same conductive layer. Furthermore, the display panel further includes N0 signal lines 120 located on a side of the first insulating layer 310 facing away from the base substrate 100 , wherein the N0 signal lines 120 can be made of the same conductive layer.

[0056] like Figure 4 As shown, the M0 signal lines 110 and N0 signal lines 120 provided in the embodiment of the present invention can be prepared from the same conductive layer, that is, the M0 signal lines 110 and N0 signal lines 120 are located in the same layer. Figure 5As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present invention, wherein the M0 signal lines 110 and N0 signal lines 120 provided by the embodiment of the present invention can be prepared by different conductive layers, that is, there is a second insulating layer 320 between the M0 signal lines 110 and the N0 signal lines 120, wherein the M0 signal lines 110 or the N0 signal lines 120 can be located on the side of the second insulating layer 320 close to the first insulating layer 310, and the present invention does not make specific restrictions on this.

[0057] In one embodiment of the present invention, the widths of the signal lines and driver circuits can be further optimized to optimize the width of the display panel's border area, achieving a narrow border trend. In the second direction, the total width of the M signal lines is D11, and the total width of the N signal lines is D22; where [(W1-D11)-(W2-D22)]×[(D11-D1)-(D22-D2)]≤0.

[0058] It can be understood that, among the width W1 of the first driving circuit, the width W2 of the second driving circuit, the total width D11 of the M signal lines, the total width D1 of the M0 signal lines, the total width D22 of the N signal lines, and the total width D2 of the N0 signal lines provided in the embodiment of the present invention, the larger one of (W1-D11) and (W2-D22) indicates that the difference between the total width of the signal line and the width of the corresponding driving circuit is large, and the total width of the signal line is smaller than the width of the corresponding driving circuit. At this time, the area where the driving circuit is located has more space to set the signal line that overlaps with the driving circuit. Furthermore, since the area where the corresponding driving circuit (the first driving circuit or the second driving circuit) is located can overlap more signal lines, the driving circuit corresponds to the smaller one of (D11-D1) and (D22-D2). Such a setting can fully save the border area of ​​the display panel, avoid unnecessary space waste, and comply with the narrow border design. Optionally, an embodiment of the present invention provides that (D11-D1)=(D22-D2)=0, that is, M signal lines all overlap with the first driving circuit, and N signal lines all overlap with the second driving circuit, thereby minimizing the width of the border area of ​​the display panel and ensuring that the border of the display panel is narrower.

[0059] like Figure 6 , which is a structural diagram of another display panel provided by an embodiment of the present invention, wherein the relationship between the number of N0 signal lines 120 and the number of M0 signal lines 110 provided by the embodiment of the present invention can be: N0-M0≥1.

[0060] It can be understood that the relationship between the width W1 of the first driving circuit, the width W2 of the second driving circuit, the total width D1 of the M0 signal lines and the total width D2 of the N0 signal lines provided in the embodiment of the present invention is W2>W1, D2>D1, and D2 / W2>D1 / W1. Therefore, by setting the number of N0 signal lines and the number of M0 signal lines to N0-M0≥1, the number of N0 signal lines overlapping with the second driving circuit is greater, thereby achieving the purpose of reducing the width of the border area.

[0061] like Figure 7 FIG. 1 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention, wherein the i signal line 11i among the M0 signal lines 120 and the j signal line 12j among the N0 signal lines are signal lines that transmit signals of the same function; along the second direction X, the width of the i signal line 11i is Di, and the width of the j signal line 12j is Dj; wherein Dj>Di. The i signal line is any signal line among the M0 signal lines, and the j signal line is any signal line among the N0 signal lines.

[0062] It should be noted that the i signal line and the j signal line provided in the embodiments of the present invention can be a single signal line or a combination of multiple signal lines, and the present invention does not impose any specific limitations on this. Specifically, when the i signal line and the j signal line are a combination of multiple signal lines, the width of the i signal line and the j signal line is the total width of each signal line.

[0063] It is understandable that the width W2 of the second drive circuit is greater than the width W1 of the first drive circuit. Compared with the transistors in the shift register of the first drive circuit, the transistors in the shift register of the second drive circuit occupy a larger area, and in many cases, the output requirements of the shift register in the second drive circuit may be higher. Therefore, in order to ensure the accuracy and stability of the signal transmission and output of the second drive circuit, the second drive circuit needs to be connected to a wider signal line to reduce the voltage drop on the signal line and avoid large fluctuations in the signal transmitted on the signal line. Therefore, the technical solution provided by the embodiment of the present invention has a larger width W2 of the second drive circuit, and at the same time, the j signal line with a larger width is designed to overlap with the second drive circuit in the light output direction of the display panel. This can avoid the j signal line affecting the width of the border area of ​​the display panel while ensuring the normal output of the second drive circuit, thereby ensuring that the width of the display panel is small.

[0064] In one embodiment of the present invention, the i signal line 11i and the j signal line 12j provided by the present invention can both be clock signal lines; the first driving circuit 11 provides a light-emitting control signal for the light-emitting control transistor of the pixel circuit 20, and the second driving circuit 12 provides a control signal for the PMOS transistor in the pixel circuit 20; wherein, Dj / W2>Di / W1.

[0065] Specifically combined Figure 8 and Figure 9 as shown, Figure 8 is a structure diagram of a shift register provided by an embodiment of the present application, Figure 9 is Figure 8 a structure layout of the shift register shown. Figure 8 The structure diagram of the shift register in the first drive circuit can be provided, wherein the shift register in the first drive circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a first capacitor C11, a second capacitor C12, and a third capacitor C13. The first signal line group includes a start signal line STV1 (the start signal line STV1 provides an enable signal for a shift register at the end of a cascade shift register in the first drive circuit), a clock signal line CK1, a clock signal line XCK1 (the clock signal line CK1 and the clock signal line XCK1 transmit pulse signals with opposite phases), a low-voltage signal line VGL, and a high-voltage signal line VGH. The first signal line group provides signals for the shift register in the first drive circuit, and then the first transistor M1 to the thirteenth transistor M13 and the first capacitor C11 to the third capacitor C13 cooperate to finally make the shift register output a light-emitting control signal for controlling the operation of a light-emitting control transistor in the pixel circuit 20. The start signal line STV1, the clock signal line CK1, the clock signal line XCK1, the low-voltage signal line VGL, and the high-voltage signal line VGH provided by the embodiment of the present application can be overlapped with the first drive circuit, that is, the M0 signal lines include the start signal line STV1, the clock signal line CK1, the clock signal line XCK1, the low-voltage signal line VGL, and the high-voltage signal line VGH, so as to ensure that the width of the frame region of the display panel is small.

[0066] and combined Figure 10 and Figure 11 as shown, Figure 10 is another structure diagram of a shift register provided by an embodiment of the present application, Figure 11 is Figure 10 a structure layout of the shift register shown. Figure 10A structure diagram of a shift register in a second driving circuit can be provided, wherein the second driving circuit is configured to control PMOS transistors in a pixel circuit, the shift register in the second driving circuit includes a first transistor P1, a second transistor P2, a third transistor P3, a fourth transistor P4, a fifth transistor P5, a sixth transistor P6, a seventh transistor P7, an eighth transistor P8, a first capacitor C21, and a second capacitor C22, wherein a second signal line group includes a start signal line STV2 (the start signal line STV2 is configured to provide an enable signal for a shift register at an end of a cascade shift register in the second driving circuit), a clock signal line CK2, a clock signal line XCK2, a low voltage signal line VGL, and a high voltage signal line VGH. The shift register in the second driving circuit is configured to receive signals from the second signal line group, and then the first transistor P1 to the eighth transistor P8, the first capacitor C21, and the second capacitor C22 are configured to cooperate to finally output a control signal for controlling the PMOS transistors in the pixel circuit 20. The start signal line STV2, the clock signal line CK2, the clock signal line XCK2 (the clock signal line CK2 and the clock signal line XCK2 transmit pulse signals with opposite phases), the low voltage signal line VGL, and the high voltage signal line VGH provided by the embodiment of the present application can be overlapped with the second driving circuit, that is, N0 signal lines include the start signal line STV2, the clock signal line CK2, the clock signal line XCK2, the low voltage signal line VGL, and the high voltage signal line VGH, so as to ensure that the width of the frame region of the display panel is small.

[0067] In combination Figure 11 As shown in the figure, the j signal lines include a j1 signal line CK2 and a j2 signal line XCK2, along the second direction X, the j2 signal line XCK2 is located on one side of the j1 signal line CK2 towards the display area AA of the display panel, the width of the j1 signal line CK2 is Dj1, the width of the j2 signal line XCK2 is Dj2, Dj2>Dj1; wherein Dj1≥Di, and / or Dj2≥Di, wherein optionally, Dj=Dj1+Dj2.

[0068] It can be understood that the output control of the j signal line and the second driving circuit and other related control processes are all related, so the j signal line can be essentially set as a combination of the j1 signal line and the j2 signal line, and the j2 signal line can be arranged on the side of the j1 signal line facing the display area. In addition, the output end of the driving circuit is generally arranged on the side facing the display area, so as to be electrically connected with the pixel circuit in the display area, and the j2 signal line can be connected with the output module of the shift register. In this case, the width of the j2 signal line is designed to be larger, so as to ensure the transmission stability of the signal input by the output module, so that Dj2 is designed to be greater than Dj1. On this basis, the width relationship can be set as Dj1≥Di, and / or Dj2≥Di, so as to meet the high transmission stability of the signal input by the shift register of the second driving circuit with a larger width. At the same time, the width W2 of the second driving circuit provided by the embodiment of the present application is larger, so that a wider j signal line can be arranged to overlap with the second driving circuit, so as to realize the design of narrow frame.

[0069] In an embodiment of the present application, the i signal line and the j signal line can also be other types of signal lines. That is, the i signal line 11i and the j signal line provided by the present application can also be high-level voltage signal lines or low-level voltage signal lines; the first driving circuit 11 provides a light-emitting control signal for the light-emitting control transistor of the pixel circuit 20, and the second driving circuit 12 provides a control signal for the NMOS transistor in the pixel circuit 20, and the NMOS transistor is connected with the gate of the driving transistor; wherein Dj / W2>Di / W1. The driving transistor is a transistor for providing a driving current in the pixel circuit 20, and the light-emitting element in the pixel circuit 20 emits light in response to the driving current.

[0070] The shift register of the first driving circuit provided by the embodiment of the present application can be a shift register circuit structure as shown in Figure 8 and Figure 9 . In combination with Figure 12 and Figure 13 , Figure 12 is another structure diagram of the shift register provided by the embodiment of the present application, Figure 13 is a layout of the shift register as shown in Figure 12 . Figure 12A structure diagram of a shift register in a second driving circuit can be provided, wherein the second driving circuit is used to control an NMOS transistor in a pixel circuit, and the shift register in the second driving circuit comprises a first transistor N1, a second transistor N2, a third transistor N3, a fourth transistor N4, a fifth transistor N5, a sixth transistor N6, a seventh transistor N7, an eighth transistor N8, a ninth transistor N9, a tenth transistor N10, an eleventh transistor N11, a twelfth transistor N12, a thirteenth transistor N13, a first capacitor C31, a second capacitor C32 and a third capacitor C33. A second signal line group comprises a start signal line STV3 (the start signal line STV3 provides an enabling signal for a shift register at an end of a cascade shift register in the second driving circuit), a clock signal line CK3, a clock signal line XCK3 (the clock signal line CK3 and the clock signal line XCK3 transmit pulse signals in opposite phases), a low voltage signal line VGL and a high voltage signal line VGH. The shift register in the second driving circuit is provided with signals through the second signal line group, and then the first transistor N1 to the thirteenth transistor N13 and the first capacitor C31 to the third capacitor C33 are cooperated to finally make the shift register output a control signal for controlling the NMOS transistor in the pixel circuit 20 to work. The start signal line STV3, the clock signal line CK3, the clock signal line XCK3, the low voltage signal line VGL and the high voltage signal line VGH provided by the embodiment of the present application can be overlapped with the second driving circuit, that is, N0 signal lines comprise the start signal line STV3, the clock signal line CK3, the clock signal line XCK3, the low voltage signal line VGL and the high voltage signal line VGH, so that the width of the frame area of the display panel is ensured to be small.

[0071] In combination Figure 8 and Figure 12As shown, when the i signal line and the j signal line are both the high voltage signal line VGH or the low voltage signal line VGL, the output transistors (the ninth transistor M9 and the tenth transistor M10) of the shift register of the first driving circuit and the output transistors (the ninth transistor N9 and the tenth transistor N10) of the shift register of the second driving circuit are connected to the high voltage signal line VGH and the low voltage signal line VGL. Since the gate potential of the driving transistor in the pixel circuit is closely related to the size of the driving current, the NMOS transistor connected to the gate of the driving transistor has higher requirements for the stability and the leakage current of the NMOS transistor, so as to ensure the high stability of the potential of the gate of the driving transistor. Therefore, by designing the width W2 of the second driving circuit to be larger, the embodiment of the present application can make the output stability of the shift register in the second driving circuit higher. Since the width W2 of the second driving circuit is designed to be larger, the Dj parameter with a larger width can be designed, and finally the purpose of reducing the signal pressure drop and ensuring the stability of the transmission signal is achieved, and the narrow frame design can also be realized, and the width relationship is further optimized as Dj / W2>Di / W1.

[0072] As shown in the figure, Figure 13 The j signal line includes a j1 signal line VGL and a j2 signal line VGH, and along the second direction X, the j2 signal line VGH is located on the side of the j1 signal line VGL facing the display area AA of the display panel, the width of the j1 signal line VGL is Dj1, the width of the j2 signal line VGH is Dj2, and Dj2>Dj1; wherein Dj1≥Di, and / or Dj2≥Di, and optionally Dj=Dj1+Dj2.

[0073] It can be understood that the j signal line provided by the embodiment of the present application is related to the output of the second driving circuit and other related control processes of other circuits, so the j signal line can be essentially set as the combination of the j1 signal line and the j2 signal line, and the j2 signal line can be arranged on the side of the j1 signal line facing the display area. Moreover, the output end of the driving circuit is on the side facing the display area, so as to be electrically connected with the pixel circuit at the display area, and the j2 signal line is connected with the output module of the shift register. In this way, the width of the j2 signal line is designed to be larger, so as to ensure the transmission stability of the signal connected by the output module, and thus Dj2 can be designed to be larger than Dj1. On this basis, the width relationship can be set as Dj1≥Di, and / or Dj2≥Di, so as to meet the high transmission stability of the signal connected by the shift register of the second driving circuit with a larger width. Meanwhile, the width W2 of the second driving circuit provided by the embodiment of the present application is larger, so a wider j signal line can be arranged to intersect with the second driving circuit, so as to realize the design of narrow frame.

[0074] In an embodiment of the present application, the first driving circuit comprises x1 transistors and y1 capacitors in a shift register, x1≥1, y1≥1; the second driving circuit comprises x2 transistors and y2 capacitors in a shift register, x1≥1, y2≥1; at least one of the M0 signal lines and at least one of the x1 transistors overlap each other, and none of the y1 capacitors overlap with the at least one of the M0 signal lines; and / or, at least one of the N0 signal lines and at least one of the x2 transistors overlap each other, and none of the y2 capacitors overlap with the at least one of the N0 signal lines.

[0075] It can be understood that the signal line is used for transmitting signals, and when the signal line overlaps with the capacitor, it is equivalent to that the original capacitor is connected with a new capacitor, thereby causing the change of the capacitance value, which not only affects the capacitor, but also affects the stability of the signal transmission on the signal line. Therefore, the shift register in the first driving circuit and the shift register in the second driving circuit provided by the embodiment of the present application both comprise a plurality of transistors and at least one capacitor, and at least one of the signal lines overlapping with the driving circuit (the first driving circuit and / or the second driving circuit) only overlaps with the transistor, and does not overlap with the capacitor, thereby ensuring the stability of the signal transmission on the signal line and the reliability of the capacitor in the driving circuit.

[0076] Specifically as shown in Figure 14 and Figure 15 , the structure diagram of the shift register of the first driving circuit provided by the embodiment of the present application is shown in Figure 14 , the structure diagram of the shift register of the second driving circuit provided by the embodiment of the present application is shown in Figure 15 . The M0 signal lines in the shift register of the first driving circuit comprise a start signal line STV1, a clock signal line CK1, a clock signal line XCK1, a low-level voltage signal line VGL and a high-level voltage signal line VGH, wherein the start signal line STV1, the clock signal line CK1, the clock signal line XCK1, the low-level voltage signal line VGL and the high-level voltage signal line VGH overlap with the transistors included in the shift register, and the start signal line STV1, the clock signal line CK1 and the clock signal line XCK1 do not overlap with the capacitors included in the shift register, thereby improving the change of the capacitance value of the capacitor in the shift register, and ensuring the high stability of the signal transmission on the signal line.

[0077] And, the N0 signal lines in the shift register of the second driving circuit include a start signal line STV2, a clock signal line CK2, a clock signal line XCK2, a low voltage signal line VGL and a high voltage signal line VGH, wherein the start signal line STV2, the clock signal line CK2, the clock signal line XCK2, the low voltage signal line VGL and the high voltage signal line VGH all overlap with the transistors included in the shift register, and the start signal line STV2, the clock signal line CK2, the low voltage signal line VGL and the clock signal line XCK2 do not overlap with the capacitors included in the shift register, thereby improving the situation that the capacitance value of the capacitor in the shift register changes, and ensuring the stability of the signal transmitted on the signal line.

[0078] Further, at least one clock signal line in the M0 signal lines does not overlap with any one of the y1 capacitors, and / or at least one clock signal line in the N0 signal lines does not overlap with any one of the y2 capacitors. It can be understood that, since the clock signal line transmits a pulse signal, the pulse signal is not only easily affected by the capacitor, but also can affect the charging and discharging process of the capacitor. The non-overlapping design of the clock signal line and the capacitor can effectively ensure the stability of the pulse signal transmission on the clock signal line and the reliability of the capacitor. Specifically, as shown in Figure 14 and Figure 15 The clock signal line CK1 and the clock signal line XCK1 do not overlap with the capacitors of the corresponding shift register, and the clock signal line CK2 and the clock signal line XCK2 do not overlap with the capacitors of the corresponding shift register.

[0079] In an embodiment of the present application, the M0 signal lines include a signal line with the maximum width along the second direction, and the signal line with the maximum width along the second direction does not overlap with any one of the y1 capacitors, and / or the N0 signal lines include a signal line with the maximum width along the second direction, and the signal line with the maximum width along the second direction does not overlap with any one of the y2 capacitors. Since the size of the capacitor is proportional to the relative area of the plate, the signal line with a larger width is designed to be non-overlapping with the capacitor, so as to avoid the capacitance value of the capacitor in the driving circuit from changing greatly, ensure the stability of the signal transmitted on the signal line, and ensure the reliability of the capacitor.

[0080] As shown in Figure 16FIG. 1 is a schematic diagram of the structure of a signal line provided in an embodiment of the present invention, wherein the M0 signal lines or the N0 signal lines provided in an embodiment of the present invention include a first clock signal line CKL for transmitting a first clock signal and a second clock signal line XCKL for transmitting a second clock signal (the pulse signals transmitted by the clock signal line CKL and the clock signal line XCKL are in phase with each other), and a first voltage signal line VG1 for transmitting a constant first voltage signal; the first clock signal line CKL and the first voltage signal line VG1 are respectively located on both sides of the second clock signal line XCKL; wherein the spacing L1 between the first clock signal line CKL and the second clock signal line XCKL is greater than the spacing L2 between the first voltage signal line VG1 and the second clock signal line XCKL. The first voltage signal line VG1 can be a low-level voltage signal line or a high-level voltage signal line.

[0081] It is understandable that the clock signal lines CKL and XCKL provided in the embodiments of the present invention transmit pulse signals with opposite phases. Therefore, the spacing between the clock signal lines CKL and XCKL needs to be larger to prevent the electric field generated between them from significantly affecting the respective pulse signals when the signals on the clock signal lines CKL and XCKL transition. The first voltage signal line VG1 transmits a constant voltage signal without rising or falling edges, so a smaller spacing between it and the clock signal lines will have less impact. Therefore, the spacing L2 between it and the second clock signal line XCKL can be set to be smaller than the spacing L1 between the first clock signal line CKL and the second clock signal line XCKL, thereby optimizing the circuit layout space.

[0082] like Figure 17 As shown, it is a structural schematic diagram of another signal line provided in an embodiment of the present invention, wherein the M0 signal lines or the N0 signal lines include a first voltage signal line VG1 for transmitting a constant first voltage signal and a second voltage signal line VG2 for transmitting a constant second voltage signal, and a first clock signal line CK for transmitting a first clock signal; the first voltage signal line VG1 and the first clock signal line CK are respectively located on both sides of the second voltage signal line VG2; wherein the spacing L3 between the first voltage signal line VG1 and the second voltage signal line VG2 is greater than the spacing L4 between the first clock signal line CK and the second voltage signal line VG2.

[0083] It can be understood that the first voltage signal line VG1 and the second voltage signal line VG2 provided in the embodiment of the present invention transmit voltage signals of different levels, that is, when the first voltage signal line VG1 is a high-level voltage signal line, the second voltage signal line VG2 is a low-level voltage signal line; and when the first voltage signal line VG1 is a low-level voltage signal line, the second voltage signal line VG2 is a high-level voltage signal line; therefore, the voltage signal line VG1 and the second voltage signal line VG2 are required to have high stability in transmitting signals. The present invention sets a larger distance between the first voltage signal line VG1 and the second voltage signal line VG2 to avoid mutual influence between the two, which makes the stability of the signals transmitted by each of them poor, resulting in unstable output signals of the driving circuit.

[0084] like Figure 18 As shown, it is a structural schematic diagram of another display panel provided by an embodiment of the present invention, wherein the driving circuit further includes a third driving circuit 13, and the signal line group further includes a third signal line group, and the third signal line group includes P signal lines providing signals to the third driving circuit 13, P≥1; in a direction perpendicular to the surface of the display panel, P0 signal lines 130 in the third signal line group overlap with the third driving circuit 13, 1≤P0≤P; the third driving circuit 13 includes an S3-stage shift register extending along the first direction Y, S3≥2; wherein, in the second direction X, the width of the third driving circuit 13 is W3, and the total width of the P0 signal lines 130 in the third signal line group is D3; W2>W3, and D3 / W3>D2 / W2>D1 / W1.

[0085] It is understood that the drive circuit provided in the embodiment of the present invention may include a first drive circuit, a second drive circuit, and a third drive circuit. The width W2 of the second drive circuit is greater than the width W3 of the third drive circuit. Moreover, the width W3 of the third drive circuit provided in the embodiment of the present invention may be between the width W1 of the first drive circuit and the width W2 of the second drive circuit. In particular, the total width D3 of the P0 signal lines 130 provided in the embodiment of the present invention is relatively large, such that D3 / W3>D2 / W2>D1 / W1.

[0086] When the width W3 of the third drive circuit is smaller than the width of the second drive circuit W2, but the output requirements are higher, on the one hand, the widths of some of the P signal lines corresponding to it are relatively wide. In order not to affect the frame space, they need to be arranged to overlap with the third drive circuit as much as possible. In this case, a situation may occur where W3 is not too large, but D3 is large, resulting in a situation where D3 / W3>D2 / W2>D1 / W1. In this case, because D3 is large, the wider signal line P0 among the P signal lines is arranged to overlap with the third drive circuit, thereby avoiding additional increase in the frame area.

[0087] As Figure 18 shown, the technical scheme provided by the embodiment of the present application can be selected, and the first driving circuit 11, the third driving circuit 13 and the second driving circuit 12 can be arranged side by side along the second direction X, so as to facilitate the provision of different driving signals for each row of pixel circuits. Further, along the second direction X, the first driving circuit 11, the third driving circuit 13 and the second driving circuit 12 are arranged in sequence from the frame N1 of the display panel towards the display area AA of the display panel; the first driving circuit 11 provides a light-emitting control signal for the light-emitting control transistor of the pixel circuit 20; the second driving circuit 12 provides a control signal for the PMOS transistor in the pixel circuit 20; and the third driving circuit 13 provides a control signal for the NMOS transistor in the pixel circuit 20, which is connected with the gate of the driving transistor.

[0088] It should be noted that the pixel circuit provided by the embodiment of the present application can include a driving transistor, a light-emitting control transistor and the remaining NMOS transistor and PMOS transistor, wherein the driving transistor is used to generate a driving current, and the light-emitting element in the pixel circuit emits light in response to the driving circuit; and the light-emitting control transistor is used to transmit the driving current to the light-emitting element according to the control of the light-emitting control signal. The remaining NMOS transistor and PMOS transistor are used for reset, threshold value capture and other control of the pixel circuit, which is the same as the prior art, and the present application does not make redundant description.

[0089] In an embodiment of the present application, the display panel provided by the present application can be a single-side driving panel structure, as Figure 18 shown, the first driving circuit 11, the second driving circuit 12 and the third driving circuit of the driving circuit are located on one side of the display area AA, and the pixel circuit 20 is driven by the single-side driving circuit. Alternatively, the display panel provided by the present application can also be a double-side driving panel structure, as Figure 18 shown, the driving circuit includes the first driving circuit 11 located on the two sides of the display area AA, the driving circuit includes the second driving circuit 12 located on the two sides of the display area AA, and the driving circuit includes the third driving circuit 13 located on the two sides of the display area AA, and the pixel circuit 20 is driven by the double-side driving circuit.

[0090] As Figure 19As shown, in the double-sided driven panel structure provided by an embodiment of the present invention, the pixel circuits 20 in the same row can be simultaneously driven by two first driving circuits 11 located on different sides of the display area AA, the pixel circuits 20 in the same row can be simultaneously driven by two second driving circuits 12 located on different sides of the display area AA, and the pixel circuits 20 in the same row can be simultaneously driven by two third driving circuits 13 located on different sides of the display area AA.

[0091] Or, as Figure 20 As shown, in the double-sided driven panel structure provided by an embodiment of the present invention, pixel circuits 20 in different rows can be respectively driven by two first driving circuits 11 located on different sides of the display area AA, pixel circuits 20 in different rows can be respectively driven by two second driving circuits 12 located on different sides of the display area AA, and pixel circuits 20 in different rows can be respectively driven by two third driving circuits 13 located on different sides of the display area AA.

[0092] In one embodiment of the present invention, along the second direction X, the width of the output transistor of the first driving circuit 11 is smaller than the width of the output transistor of the third driving circuit 13, and the width of the output transistor of the third driving circuit 13 is smaller than the width of the output transistor of the second driving circuit 12. The output transistor is a transistor connected to the output end of the shift register, and is used to output the relevant control signal to the output end of the shift register. Figures 8 to 13 As shown, Figure 8 and Figure 9 The shift register of the first driving circuit 11 is shown, wherein the output transistors of the shift register of the first driving circuit are the ninth transistor M9 and the tenth transistor M10, the ninth transistor M9 is used to transmit the output signal of the high-level voltage signal line VGH to the output end OUT1 of the shift register, and the tenth transistor M10 is used to transmit the output signal of the low-level voltage signal line VGL to the output end OUT1 of the shift register. Figure 10 and Figure 11 The shift register of the second driving circuit 12 is shown, wherein the output transistors of the shift register of the second driving circuit are the seventh transistor P7 and the eighth transistor P8. The seventh transistor P7 is used to transmit the output signal of the high-level voltage signal line VGH to the output end OUT2 of the shift register, and the eighth transistor P8 is used to transmit the output pulse signal of the clock signal line XCK2 to the output end OUT2 of the shift register. Figure 12 and Figure 13It can be the shift register of the third driving circuit 13, and the output transistors of the shift register of the third driving circuit are the ninth transistor N9 and the tenth transistor N10. The ninth transistor N9 is used to transmit the output signal of the high-level voltage signal line VGH to the output end OUT3 of the shift register, and the tenth transistor N10 is used to transmit the output signal of the low-level voltage signal line VGL to the output end OUT3 of the shift register.

[0093] It should be noted that the shift registers shown in the first drive circuit, the second drive circuit and the third drive circuit provided in the embodiment of the present invention are not limited to Figures 8 to 13 The shift register shown may also be other types of shift register structures, to which the present invention does not impose any specific limitation.

[0094] In one embodiment of the present invention, the relationship among the width W1 of the first drive circuit, the width W2 of the second drive circuit, the width W3 of the third drive circuit, the total width D1 of the M0 signal lines, the total width D2 of the N0 signal lines, and the total width D3 of the P0 signal lines provided by the present invention can be D3 / W3-D2 / W2<D2 / W2-D1 / W1. The shift registers in the second and third drive circuits have higher output signal requirements, while the shift register in the first drive circuit has lower output signal requirements. Therefore, the present invention can design the values ​​of D3 / W3 and D2 / W2 to be relatively close to each other to fully avoid the problem of increased border area caused by the wider width of the corresponding signal lines. The values ​​of the aforementioned two values ​​are designed to be relatively different from the values ​​of D1 / W1.

[0095] In one embodiment of the present invention, the relationship between the number of M0 signal lines, the number of N0 signal lines, and the number of P0 signal lines provided by the present invention can be set to M0 < P0 < N0. The width of the second driving circuit provided in the embodiment of the present invention is greater than the width of the third driving circuit, and the width of the third driving circuit is greater than the width of the first driving circuit. By setting the number of signal lines to M0 < P0 < N0, because the second driving circuit corresponds to a larger number of signal lines or the width of the signal lines corresponding to the second driving circuit is wider, setting N0 to be larger can fully prevent the second driving circuit and its corresponding signal lines from occupying too much border area; the width of the third driving circuit is smaller than the width of the second driving circuit. If the output requirements of the third driving circuit are higher, the number of signal lines corresponding to it may also be larger, or the width of the signal lines may be larger. Therefore, setting P0 to be larger can fully prevent the second driving circuit and its corresponding signal lines from occupying too much border area; the first driving circuit itself is smaller in width and may not have much space to overlap the corresponding signal lines. Therefore, M0 can be set to a relatively small value. Such a setting can ensure the optimization of the overlap between the signal lines and the driving circuit, thereby reducing the border width of the display panel.

[0096] In one embodiment of the present invention, the M0 signal lines provided by the present invention include a third clock signal line for transmitting a third clock signal; the N0 signal lines include a fourth clock signal line for transmitting a fourth clock signal; and the P0 signal lines include a fifth clock signal line for transmitting a fifth clock signal; wherein the width of the third clock signal line is smaller than the width of the fifth clock signal line, and the width of the fifth clock signal line is smaller than the width of the fourth clock signal line. The width of the second driving circuit provided by the embodiment of the present invention is larger than the width of the third driving circuit, and the width of the third driving circuit is larger than the width of the first driving circuit. Furthermore, by designing the width of the third clock signal line to be smaller than the width of the fifth clock signal line, and designing the width of the fifth clock signal line to be smaller than the width of the fourth clock signal line, it is ensured that the clock signal lines corresponding to different driving circuits match each other, thereby improving the stability and reliability of signal transmission by different clock signal lines.

[0097] In one embodiment of the present invention, the M0 signal lines provided by the present invention include a third voltage signal line for transmitting a third voltage signal; the N0 signal lines include a fourth voltage signal line for transmitting a fourth voltage signal; and the P0 signal lines include a fifth voltage signal line for transmitting a fifth voltage signal; wherein the width of the third voltage signal line is smaller than the width of the fourth voltage signal line, and the width of the fourth voltage signal line is smaller than the width of the fifth voltage signal line. The width of the second driving circuit provided by the embodiment of the present invention is greater than the width of the third driving circuit, and the width of the third driving circuit is greater than the width of the first driving circuit. Furthermore, by designing the width of the third voltage signal line to be smaller than the width of the fourth voltage signal line, and designing the width of the fourth voltage signal line to be smaller than the width of the fifth voltage signal line, it is ensured that the voltage signal lines corresponding to different driving circuits match each other, thereby improving the stability and reliability of signal transmission by different voltage signal lines.

[0098] Correspondingly, an embodiment of the present invention further provides a display device, comprising the display panel provided by any one of the above embodiments.

[0099] like Figure 21 , which is a schematic structural diagram of a display device provided by an embodiment of the present invention, wherein the display device 1000 provided by an embodiment of the present invention may be a mobile terminal device.

[0100] In other embodiments of the present invention, the display device provided by the present invention may also be an electronic display device such as a mobile phone, a computer, or a vehicle-mounted terminal, and the present invention does not impose any specific limitation on this.

[0101] The display panel and the display device provided by the embodiments of the present application can reduce the area occupied by part of the signal lines and the frame width of the display device by arranging the M0 signal lines and the first driving circuit to be overlapped and arranging the N0 signal lines and the second driving circuit to be overlapped. In addition, the embodiments of the present application set the relationship between the width W1 of the first driving circuit, the width W2 of the second driving circuit, the total width D1 of the M0 signal lines and the total width D2 of the N0 signal lines as W2>W1, D2>D1 and D2 / W2>D1 / W1, further optimize the overlap arrangement between the shift register with larger width, the shift register with smaller width and the total width of the respective corresponding signal lines, sufficiently reduce the area occupied by the driving circuit and the signal lines, and further reduce the frame width of the display device.

[0102] The above description of disclosed embodiments enables one of ordinary skill in the art to make or use the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized by, Comprising: a substrate substrate; a driving circuit and a pixel circuit, the driving circuit and the pixel circuit being located on the substrate substrate; the driving circuit comprises a first driving circuit and a second driving circuit; a signal line group, the signal line group comprises a first signal line group and a second signal line group, the first signal line group comprises M signal lines for providing signals for the first driving circuit, the second signal line group comprises N signal lines for providing signals for the second driving circuit, M≥1, N≥1; in the direction perpendicular to the surface of the display panel, M0 signal lines in the first signal line group are overlapped with the first driving circuit and are located on the side of the first driving circuit away from the substrate substrate, N0 signal lines in the second signal line group are overlapped with the second driving circuit and are located on the side of the second driving circuit away from the substrate substrate, 1≤M0≤M, 1≤N0≤N; the first driving circuit comprises a S1 stage shift register extending along a first direction, and / or the second driving circuit comprises a S2 stage shift register extending along the first direction, the second direction is parallel to the plane where the surface of the display panel is located and perpendicular to the first direction, S1≥2, S2≥2; the first driving circuit provides a light emitting control signal for a light emitting control transistor in the pixel circuit; the second driving circuit provides a control signal for a PMOS type transistor in the pixel circuit, or the second driving circuit provides a control signal for an NMOS type transistor in the pixel circuit; the M0 signal lines or the N0 signal lines comprise a first clock signal line transmitting a first clock signal and a second clock signal line transmitting a second clock signal, and a first voltage signal line transmitting a first voltage signal; in the second direction, the interval between the first clock signal line and the second clock signal line is greater than the interval between the first voltage signal line and the second clock signal line; or, the M0 signal lines or the N0 signal lines comprise a first voltage signal line transmitting a first voltage signal and a second voltage signal line transmitting a second voltage signal, and a first clock signal line transmitting a first clock signal; in the second direction, the interval between the first voltage signal line and the second voltage signal line is greater than the interval between the first clock signal line and the second voltage signal line.

2. The display panel of claim 1, wherein: the M0 signal lines or the N0 signal lines comprise a first clock signal line transmitting a first clock signal and a second clock signal line transmitting a second clock signal, and a first voltage signal line transmitting a first voltage signal; and the first clock signal line and the first voltage signal line are respectively located on both sides of the second clock signal line.

3. The display panel of claim 1, wherein: the M0 signal lines or the N0 signal lines comprise a first voltage signal line transmitting a first voltage signal and a second voltage signal line transmitting a second voltage signal, and a first clock signal line transmitting a first clock signal. The first voltage signal line and the first clock signal line are respectively located on two sides of the second voltage signal line.

4. The display panel of claim 1, wherein, The first clock signal line and the second clock signal line transmit pulse signals with opposite phases. The first voltage signal line is a low-level voltage signal line or a high-level voltage signal line.

5. The display panel of claim 1, wherein, The first voltage signal line is a high-level voltage signal line, and the second voltage signal line is a low-level voltage signal line; or, The first voltage signal line is a low-level voltage signal line, and the second voltage signal line is a high-level voltage signal line.

6. The display panel of claim 1, wherein, The display panel comprises a transistor array layer, and the transistor array layer comprises the drive circuit and / or the pixel circuit. The transistor array layer comprises: a semiconductor layer comprising an active region; a gate metal layer comprising a plurality of gates; a source-drain metal layer comprising a plurality of sources and a plurality of drains; wherein, The M0 signal lines are located on a side of the source-drain metal layer away from the substrate, and the N0 signal lines are located on a side of the source-drain metal layer away from the substrate.

7. The display panel of claim 1 or 6, wherein, The M0 signal lines are located on the same layer, and / or the N0 signal lines are located on the same layer.

8. The display panel of claim 1 or 6, wherein, The M0 signal lines and the N0 signal lines are located on the same layer; or, The M0 signal lines and the N0 signal lines are located on different layers.

9. The display panel of claim 6, wherein, The source-drain metal layer and the film layer in which the M0 signal lines are located comprise a first insulating layer, or the source-drain metal layer and the film layer in which the N0 signal lines are located comprise a first insulating layer; The film layer in which the M0 signal lines are located and the film layer in which the N0 signal lines are located comprise a second insulating layer.

10. A display panel, characterized by, comprises: a substrate; a drive circuit located on the substrate, the drive circuit comprising a first drive circuit and a second drive circuit; a signal line group comprising a first signal line group and a second signal line group, the first signal line group comprising M signal lines for providing signals to the first drive circuit, and the second signal line group comprising N signal lines for providing signals to the second drive circuit, M≥1, N≥1; In a direction perpendicular to the surface of the display panel, M0 signal lines in the first signal line group intersect and overlap the first drive circuit and are located on a side of the first drive circuit away from the substrate, and N0 signal lines in the second signal line group intersect and overlap the second drive circuit and are located on a side of the second drive circuit away from the substrate, 1≤M0≤M, 1≤N0≤N; The first driving circuit comprises a S1-stage shift register extending along a first direction, and / or the second driving circuit comprises a S2-stage shift register extending along the first direction, a second direction being parallel to a plane in which the display panel surface lies and perpendicular to the first direction, S1≥2, S2≥2; The M0 signal lines or the N0 signal lines comprise a first clock signal line transmitting a first clock signal and a second clock signal line transmitting a second clock signal, and a first voltage signal line transmitting a first voltage signal; In the second direction, a spacing between the first clock signal line and the second clock signal line is greater than a spacing between the first voltage signal line and the second clock signal line; Or, The M0 signal lines or the N0 signal lines comprise a first voltage signal line transmitting a first voltage signal and a second voltage signal line transmitting a second voltage signal, and a first clock signal line transmitting a first clock signal; In the second direction, a spacing between the first voltage signal line and the second voltage signal line is greater than a spacing between the first clock signal line and the second voltage signal line.

11. The display panel of claim 10, wherein The M0 signal lines or the N0 signal lines comprise a first clock signal line transmitting a first clock signal and a second clock signal line transmitting a second clock signal, and a first voltage signal line transmitting a first voltage signal; wherein The first clock signal line and the first voltage signal line are respectively located on two sides of the second clock signal line.

12. The display panel of claim 10, wherein The M0 signal lines or the N0 signal lines comprise a first voltage signal line transmitting a first voltage signal and a second voltage signal line transmitting a second voltage signal, and a first clock signal line transmitting a first clock signal; The first voltage signal line and the first clock signal line are respectively located on two sides of the second voltage signal line.

13. The display panel of claim 10, wherein The first clock signal line and the second clock signal line transmit pulse signals with opposite phases; The first voltage signal line is a low voltage signal line or a high voltage signal line.

14. The display panel of claim 10, wherein The first voltage signal line is a high voltage signal line, and the second voltage signal line is a low voltage signal line; or The first voltage signal line is a low voltage signal line, and the second voltage signal line is a high voltage signal line.

15. The display panel of claim 10, wherein The display panel comprises a transistor array layer, and the transistor array layer comprises the driving circuit; The transistor array layer comprises: a semiconductor layer comprising an active region; a gate metal layer comprising a plurality of gates; a source-drain metal layer comprising a plurality of sources and a plurality of drains; wherein The M0 signal lines are located on the side of the source-drain metal layer away from the substrate, and the N0 signal lines are located on the side of the source-drain metal layer away from the substrate.

16. The display panel of claim 10 or 15, wherein, The M0 signal lines are located on the same layer, and / or the N0 signal lines are located on the same layer.

17. The display panel of claim 10 or 15, wherein, The M0 signal lines are located on the same layer as the N0 signal lines; or The M0 signal lines are located on different layers from the N0 signal lines.

18. The display panel of claim 15, wherein, The source-drain metal layer and the film layer in which the M0 signal lines are located include a first insulating layer, or the source-drain metal layer and the film layer in which the N0 signal lines are located include a first insulating layer; The film layer in which the M0 signal lines are located and the film layer in which the N0 signal lines are located include a second insulating layer.

19. A display device comprising: A display panel as claimed in any one of claims 1-18.

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