A battery management system and MOS tube gate drive circuit thereof

Abstract

The present invention relates to a battery management system and a MOS transistor gate drive circuit thereof. The first drive unit of the MOS transistor gate drive circuit includes a first charge pump, a fifth switch tube, a sixth switch tube, and a first inverter. The first charge pump includes a first switch tube, a second switch tube, a third switch tube, and a fourth switch tube, and a first capacitor. The first switch tube is connected to the third switch tube and the fifth switch tube respectively, the second switch tube is connected to the fifth switch tube and the first capacitor respectively, the other end of the first capacitor is connected to the third switch tube, the second switch tube is also connected to the fourth switch tube, and the fourth switch tube is connected to the control terminal of the first MOS transistor. The control terminals of the first switch tube and the fourth switch tube are both used to receive a first PWM signal, and the control terminals of the second switch tube and the third switch tube are both used to receive a second PWM signal. Therefore, the driving capability of the MOS transistor can be improved by the first charge pump of the MOS transistor gate drive circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS tubes, and in particular to a battery management system and a MOS tube gate drive circuit thereof. Background Art

[0002] As the most widely used power device, MOS transistors are increasingly being developed in specialized fields, particularly high-power applications, as market applications evolve. MOS transistors are commonly used in lithium-ion battery protection systems, often directly driven by integrated circuit chips. However, most commercially available integrated circuit chips suffer from insufficient supply voltage and are affected by other internal chip parameters, making them unable to provide sufficient voltage to turn the MOS transistors on and off in real time. This is a major factor in the loss of control of current lithium-ion battery protection board systems, which directly poses a safety hazard to lithium-ion batteries and endangers personal safety. Summary of the Invention

[0003] The purpose of the present invention is to overcome the shortcomings of the existing technology and provide a battery management system and a MOS tube gate drive circuit thereof, which can improve the driving capability of the MOS tube through the MOS tube gate drive circuit, thereby reducing the risk of the lithium battery protection system and improving the reliability of the lithium battery protection system, thereby reducing the cost of the lithium battery protection system.

[0004] In order to solve at least one of the above technical problems, an embodiment of the present invention provides a MOS transistor gate drive circuit for a battery management system, wherein the battery management system includes a first MOS transistor and a second MOS transistor, the first MOS transistor and the second MOS transistor are connected in series, the other end of the second MOS transistor is grounded, the other end of the first MOS transistor is a negative voltage output, and the first voltage input end is used as a positive voltage output;

[0005] The MOS transistor gate drive circuit includes a first drive unit, the first drive unit includes a first charge pump, a fifth switch tube, a sixth switch tube, and a first inverter, the first charge pump includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube and a first capacitor;

[0006] An input terminal of the fifth switch tube is connected to the first voltage input terminal, a control terminal of the fifth switch tube is connected to the output terminal of the first inverter, and the input terminal of the first inverter is used to receive the first latch signal; an output terminal of the fifth switch tube is connected to the input terminal of the sixth switch tube, an output terminal of the sixth switch tube is grounded, and a control terminal of the sixth switch tube is connected to the input terminal of the first inverter;

[0007] The input end of the first switching tube is connected to the output end of the fifth switching tube, the output end of the first switching tube is connected to the input end of the third switching tube, the input end of the second switching tube is connected to the output end of the fifth switching tube, the output end of the second switching tube is connected to one end of the first capacitor, the other end of the first capacitor is connected to the input end of the third switching tube, the output end of the second switching tube is also connected to the input end of the fourth switching tube, the output end of the fourth switching tube is connected to the control end of the first MOS tube, the control end of the first switching tube and the control end of the fourth switching tube are both used to receive the first PWM signal, and the control end of the second switching tube and the control end of the third switching tube are both used to receive the second PWM signal.

[0008] Preferably, the MOS transistor gate drive circuit includes a second drive unit, the second drive unit includes a second charge pump, an eleventh switch tube, a twelfth switch tube, and a second inverter, the second charge pump includes a seventh switch tube, an eighth switch tube, a ninth switch tube, a tenth switch tube, and a second capacitor;

[0009] The input end of the eleventh switch tube is connected to the second voltage input end, the control end of the eleventh switch tube is connected to the output end of the second inverter, and the input end of the second inverter is used to receive the second latch signal; the output end of the eleventh switch tube is connected to the input end of the twelfth switch tube, the output end of the twelfth switch tube is grounded, and the control end of the twelfth switch tube is connected to the input end of the second inverter;

[0010] The input end of the seventh switching tube is connected to the output end of the eleventh switching tube, the output end of the seventh switching tube is connected to the input end of the ninth switching tube, the input end of the eighth switching tube is connected to the output end of the eleventh switching tube, the output end of the eighth switching tube is connected to one end of the second capacitor, the other end of the second capacitor is connected to the input end of the ninth switching tube, the output end of the eighth switching tube is also connected to the input end of the tenth switching tube, the output end of the tenth switching tube is connected to the control end of the second MOS tube, the control ends of the seventh switching tube and the tenth switching tube are both used to receive the third PWM signal, and the control ends of the eighth switching tube and the ninth switching tube are both used to receive the fourth PWM signal.

[0011] Preferably, the battery management system has a built-in battery management chip, and the first driving unit and the second driving unit are built into the battery management chip.

[0012] A battery management system, comprising the MOS transistor gate drive circuit according to claim 3, and a first MOS transistor and a second MOS transistor, wherein one end of the first MOS transistor and one end of the second MOS transistor are connected in series, the other end of the second MOS transistor is grounded, the other end of the first MOS transistor is a negative voltage output, and the first voltage input end is a positive voltage output.

[0013] Preferably, the battery management system further includes a sampling resistor, one end of the sampling resistor is connected to the other end of the second MOS tube, and one end of the sampling resistor is connected to the current sampling signal pin of the battery management chip, and the other end of the sampling resistor is grounded.

[0014] Preferably, when the battery management chip detects through the current sampling signal pin that the sampling voltage is greater than a threshold, it controls the second PWM signal and the fourth PWM signal to be high-level signals and controls the first PWM signal and the third PWM signal to be low-level signals.

[0015] Preferably, after the battery management chip controls the second PWM signal and the fourth PWM signal to be high-level signals and controls the first PWM signal and the third PWM signal to be low-level signals for a set period of time, it controls the second PWM signal and the fourth PWM signal to be low-level signals and controls the first PWM signal and the third PWM signal to be high-level signals.

[0016] Preferably, the set time period is determined based on the output current of the battery management system and the ratio of twice the voltage of the first voltage input terminal to the capacitance value of the first capacitor.

[0017] Preferably, the battery management system further includes a battery cell, a positive electrode of the battery cell is connected to the first voltage input terminal, and a negative electrode of the battery cell is grounded.

[0018] Preferably, the voltage of the battery cell is greater than or equal to 2V and less than or equal to 5V.

[0019] In an embodiment of the present invention, a battery management system and a MOS tube gate drive circuit thereof are provided. The battery management system includes a first MOS tube and a second MOS tube, the first MOS tube and the second MOS tube are connected in series, the other end of the second MOS tube is grounded, the other end of the first MOS tube is a negative voltage output, and the first voltage input end is used as a positive voltage output; the MOS tube gate drive circuit includes a first drive unit, the first drive unit includes a first charge pump, a fifth switch tube and a sixth switch tube, and a first inverter, the first charge pump includes a first switch tube, a second switch tube, a third switch tube and a fourth switch tube and a first capacitor; the input end of the fifth switch tube is connected to the first voltage input end, the control end of the fifth switch tube is connected to the output end of the first inverter, and the input end of the first inverter is used to receive a first latch signal; the fifth switch tube The output end of the gate transistor is connected to the input end of the sixth switching transistor, the output end of the sixth switching transistor is grounded, and the control end of the sixth switching transistor is connected to the input end of the first inverter; the input end of the first switching transistor is connected to the output end of the fifth switching transistor, the output end of the first switching transistor is connected to the input end of the third switching transistor, the input end of the second switching transistor is connected to the output end of the fifth switching transistor, the output end of the second switching transistor is connected to one end of the first capacitor, the other end of the first capacitor is connected to the input end of the third switching transistor, the output end of the second switching transistor is also connected to the input end of the fourth switching transistor, the output end of the fourth switching transistor is connected to the control end of the first MOS transistor, the control ends of the first switching transistor and the fourth switching transistor are both used to receive the first PWM signal, and the control ends of the second switching transistor and the third switching transistor are both used to receive the second PWM signal. Therefore, the driving capability of the MOS transistor can be improved by the MOS transistor gate drive circuit, thereby reducing the risk of the lithium battery protection system and improving the reliability of the lithium battery protection system, thereby reducing the cost of the lithium battery protection system. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a circuit diagram of a partial structure of a battery management system according to an embodiment of the present invention;

[0021] Figure 2 4 is a timing diagram of the PWM signal and the enable signal of the charge pump in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0023] The present invention provides a MOS tube gate drive circuit for a battery management system. The battery management system includes a first MOS tube and a second MOS tube, the first MOS tube and the second MOS tube are connected in series, the other end of the second MOS tube is grounded, the other end of the first MOS tube is a negative voltage output, and the first voltage input end is a positive voltage output; the MOS tube gate drive circuit includes a first drive unit, the first drive unit includes a first charge pump, a fifth switch tube and a sixth switch tube, a first inverter, the first charge pump includes a first switch tube, a second switch tube, a third switch tube and a fourth switch tube and a first capacitor; the input end of the fifth switch tube is connected to the first voltage input end, the control end of the fifth switch tube is connected to the output end of the first inverter, and the input end of the first inverter is used to receive a first latch signal; the output end of the fifth switch tube is connected to the input end of the sixth switch tube. The input end of the first switching tube is connected to the output end of the fifth switching tube, the output end of the first switching tube is connected to the input end of the third switching tube, the input end of the second switching tube is connected to the output end of the fifth switching tube, the output end of the second switching tube is connected to one end of the first capacitor, the other end of the first capacitor is connected to the input end of the third switching tube, the output end of the second switching tube is further connected to the input end of the fourth switching tube, the output end of the fourth switching tube is connected to the control end of the first MOS tube, the control ends of the first switching tube and the fourth switching tube are both used to receive the first PWM signal, and the control ends of the second switching tube and the third switching tube are both used to receive the second PWM signal.

[0024] Furthermore, the MOS tube gate drive circuit includes a second drive unit, the second drive unit includes a second charge pump, an eleventh switch tube, a twelfth switch tube, and a second inverter, the second charge pump includes a seventh switch tube, an eighth switch tube, a ninth switch tube, a tenth switch tube, and a second capacitor; the input end of the eleventh switch tube is connected to the second voltage input end, the control end of the eleventh switch tube is connected to the output end of the second inverter, and the input end of the second inverter is used to receive the second latch signal; the output end of the eleventh switch tube is connected to the input end of the twelfth switch tube, the output end of the twelfth switch tube is grounded, and the control end of the twelfth switch tube is connected to the input end of the second inverter The input end of the seventh switching tube is connected to the output end of the eleventh switching tube, the output end of the seventh switching tube is connected to the input end of the ninth switching tube, the input end of the eighth switching tube is connected to the output end of the eleventh switching tube, the output end of the eighth switching tube is connected to one end of the second capacitor, the other end of the second capacitor is connected to the input end of the ninth switching tube, the output end of the eighth switching tube is also connected to the input end of the tenth switching tube, the output end of the tenth switching tube is connected to the control end of the second MOS tube, the control ends of the seventh switching tube and the tenth switching tube are both used to receive the third PWM signal, and the control ends of the eighth switching tube and the ninth switching tube are both used to receive the fourth PWM signal.

[0025] Specifically, if Figure 1 As shown, the first MOS transistor and the second MOS transistor are M1 and M2, respectively. The first voltage input terminal is VCC. The positive voltage output is output+, and the negative voltage output is output-. The first switching transistor, the second switching transistor, the third switching transistor, the fourth switching transistor, the fifth switching transistor, and the sixth switching transistor are J1, J2, J3, J4, J5, and J6, respectively. The first capacitor is capacitor C1. The first inverter is inverter UI. The DSG1 signal is the first latch signal input to inverter U1. The first PWM signal is PWMB1. The second PWM signal is PWMA1.

[0026] The seventh, eighth, ninth, tenth, eleventh, and twelfth switching transistors are J7, J8, J9, J10, J11, and J12, respectively. The second capacitor is capacitor C2. The second inverter is U2. The DHG1 signal is the second latch signal input to inverter U2. The third PWM signal is PWMB2. The fourth PWM signal is PWMA2.

[0027] Preferably, the battery management system has a built-in battery management chip, and the first driving unit and the second driving unit are built into the battery management chip.

[0028] Specifically, if Figure 1 As shown, the battery management chip is a BMS chip, and the first charge pump and the second charge pump are integrated into the battery management chip IC of the battery management system, that is, the BMS chip, to achieve the purpose of reducing MOS power consumption and improving battery cell energy conversion efficiency.

[0029] The present invention also provides a battery management system. The battery management system includes the MOS transistor gate drive circuit described in the above embodiment, as well as a first MOS transistor and a second MOS transistor, wherein one end of the first MOS transistor is connected in series with one end of the second MOS transistor, the other end of the second MOS transistor is grounded, the other end of the first MOS transistor serves as a negative voltage output, and the first voltage input serves as a positive voltage output.

[0030] Preferably, the battery management system further includes a sampling resistor, one end of the sampling resistor is connected to the other end of the second MOS tube, and one end of the sampling resistor is connected to the current sampling signal pin of the battery management chip, and the other end of the sampling resistor is grounded.

[0031] Specifically, if Figure 1As shown, resistor R1 is a sampling resistor. One end of resistor R1 is grounded, and the other end is connected to the output end of tube M2. The connection point between resistor R1 and tube M2 is connected to the current sampling signal pin of the battery management chip. Figure 1 The current sampling signal pin of the BMS chip is not shown.

[0032] Preferably, when the battery management chip detects that the sampled voltage is greater than a threshold value through the current sampling signal pin, it controls the second and fourth PWM signals to be high-level signals and the first and third PWM signals to be low-level signals. Furthermore, after the battery management chip controls the second and fourth PWM signals to be high-level signals and the first and third PWM signals to be low-level signals for a set period of time, it controls the second and fourth PWM signals to be low-level signals and the first and third PWM signals to be high-level signals. The set period of time is determined based on the output current of the battery management system and the ratio of the voltage at twice the first voltage input terminal to the capacitance value of the first capacitor.

[0033] Specifically, if Figure 1 As shown, the first latch signal DGS1 and the second latch signal CHG1 are set low, the PWMA1 and PWMA2 signals are set low, the PWMB1 and PWMB2 signals are set low, and MOS transistors M1 and M2 are turned on. When the voltage detected by the current sampling signal pin is greater than the threshold, it is determined that charging / discharging is in progress, the PWMA1 and PWMA2 signals are set high, and the PWMB1 and PWMB2 signals are set low. At this time, for the first charge pump, transistors J5, J2, and J3 are turned on, and transistors J1, J4, and J6 are turned off. VCC charges capacitor C1 through transistors J5 and J2. After a set period of time, T, the PWMA1 and PWMA2 signals are set low, while the PWMB1 and PWMB2 signals are set high. At this point, in the first charge pump, transistors J1, J4, and J5 are turned on, while transistors J2, J3, and J6 are turned off. Since the potential difference across capacitor C1 remains unchanged, the voltage at the DSG2 pin is raised, and the maximum voltage reaches 2 times VCC. In other words, the gate voltage of transistor M1 is increased to 2 times VCC.

[0034] In the second charge pump, transistors J11, J8, and J9 are turned on, while transistors J7, J10, and J12 are turned off. VCC charges capacitor C2 through transistors J11 and J8. After a set time period T, the PWMA1 and PWMA2 signals are set low, while the PWMB1 and PWMB2 signals are set high. At this point, in the second charge pump, transistors J7, J10, and J11 are turned on, while transistors J8, J9, and J12 are turned off. Since the potential difference across capacitor C2 remains unchanged, the voltage on the DHG2 pin is raised, and the maximum voltage reaches 2 times VCC. This means that the gate voltage of transistor M2 is increased to 2 times VCC.

[0035] Specifically, the time period T is set by F=I out / (VCC+V PWM )*C is calculated. Where F represents the frequency corresponding to the set time period T. out Indicates the output current, VCC indicates the first input voltage, V PWM The voltage of the PWM signal is also VCC. The PWM signal inputted by the present invention is the same, with a voltage of VCC. C represents the capacitance of capacitors C1 and C2. Therefore, when capacitor C1 is charged by VCC, the voltage between the positive and negative terminals of capacitor C1 reaches a maximum of VCC. When the negative terminal of capacitor C1 is connected to VCC, the potential difference between capacitor C1 and ground is twice VCC. The same description applies to capacitor C2.

[0036] Among them, the timing diagram of the PWMA1 signal and the PWMA2 signal, the PWMB1 signal and the PWMB2 signal, and the enable signal in the first charge pump and the second charge pump can be seen in FIG. Figure 2 shown.

[0037] Therefore, by driving the gate of the MOS transistor with a voltage close to 2 times VCC, the RDS(ON) of the MOS transistor is reduced, thereby reducing the power consumption of the MOS transistor and improving working efficiency. When there is no current flowing, the output of the PWM signal can be turned off through the current detection signal, thereby reducing the static power consumption.

[0038] In one embodiment, the battery management system further comprises a battery cell, wherein a positive electrode of the battery cell is connected to the first voltage input terminal and a negative electrode of the battery cell is grounded, wherein a voltage of the battery cell is greater than or equal to 2V and less than or equal to 5V.

[0039] Specifically, if Figure 1 As shown, the positive electrode of the battery cell E1 is connected to VCC, and the negative electrode of the battery cell E1 is grounded. The voltage range of the battery cell E1 is [2, 5]V.

[0040] In summary, the mainstream lithium battery protection chips currently on the market drive charging and discharging MOS tubes with a maximum driving voltage equal to the power supply voltage VCC. The VCC voltage is provided by the battery, such as the voltage of a lithium iron phosphate battery is 2V to 3.6V, and the voltage of a ternary lithium battery is 3V to 4.2V. When driving some MOS tubes, the Vgs is barely higher than the Vgs(th), and the RDS(ON) is high. When a large current passes through the MOS tube, the heat will be higher, and its energy loss will also be higher. Especially in the lithium battery protection system, the MOS tube is a switching power device. The instantaneous startup capability and shutdown efficiency directly affect the efficiency and safety of the lithium battery protection system. The present invention can improve the driving capability of the MOS tube through the MOS tube gate drive circuit, thereby reducing the risk of the lithium battery protection system and improving the reliability of the lithium battery protection system. At the same time, it redefines the high requirement standards of the MOS tube to a certain extent, thereby reducing the cost of the lithium battery protection system.

[0041] In addition, the above describes in detail a battery management system and a MOS tube gate drive circuit thereof provided in an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A MOS tube gate drive circuit for a battery management system, characterized in that: The battery management system includes a first MOS transistor and a second MOS transistor, the first MOS transistor and the second MOS transistor are connected in series, the other end of the second MOS transistor is grounded, the other end of the first MOS transistor is a negative voltage output, and the first voltage input end is used as a positive voltage output; the battery management system also includes a battery cell, the positive electrode of the battery cell is connected to the first voltage input end, and the negative electrode of the battery cell is grounded; the battery management system also includes a sampling resistor; The MOS transistor gate drive circuit includes a first drive unit, the first drive unit includes a first charge pump, a fifth switch tube, a sixth switch tube, and a first inverter, the first charge pump includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube and a first capacitor; The input end of the fifth switch tube is connected to the first voltage input end, the control end of the fifth switch tube is connected to the output end of the first inverter, and the input end of the first inverter is used to receive the first latch signal; The output end of the fifth switch tube is connected to the input end of the sixth switch tube, the output end of the sixth switch tube is grounded, and the control end of the sixth switch tube is connected to the input end of the first inverter; The input end of the first switching tube is connected to the output end of the fifth switching tube, the output end of the first switching tube is connected to the input end of the third switching tube, the input end of the second switching tube is connected to the output end of the fifth switching tube, the output end of the second switching tube is connected to one end of the first capacitor, the other end of the first capacitor is connected to the input end of the third switching tube, the output end of the second switching tube is also connected to the input end of the fourth switching tube, the output end of the fourth switching tube is connected to the control end of the first MOS tube, the control end of the first switching tube and the control end of the fourth switching tube are both used to receive the first PWM signal, and the control end of the second switching tube and the control end of the third switching tube are both used to receive the second PWM signal; The MOS transistor gate drive circuit includes a second drive unit, the second drive unit includes a second charge pump, an eleventh switch tube, a twelfth switch tube, and a second inverter, the second charge pump includes a seventh switch tube, an eighth switch tube, a ninth switch tube, a tenth switch tube, and a second capacitor; The input end of the eleventh switch tube is connected to the second voltage input end, the control end of the eleventh switch tube is connected to the output end of the second inverter, and the input end of the second inverter is used to receive the second latch signal; the output end of the eleventh switch tube is connected to the input end of the twelfth switch tube, the output end of the twelfth switch tube is grounded, and the control end of the twelfth switch tube is connected to the input end of the second inverter; The input end of the seventh switching tube is connected to the output end of the eleventh switching tube, the output end of the seventh switching tube is connected to the input end of the ninth switching tube, the input end of the eighth switching tube is connected to the output end of the eleventh switching tube, the output end of the eighth switching tube is connected to one end of the second capacitor, the other end of the second capacitor is connected to the input end of the ninth switching tube, the output end of the eighth switching tube is also connected to the input end of the tenth switching tube, the output end of the tenth switching tube is connected to the control end of the second MOS tube, the control ends of the seventh switching tube and the tenth switching tube are both used to receive the third PWM signal, and the control ends of the eighth switching tube and the ninth switching tube are both used to receive the fourth PWM signal.

2. The MOS transistor gate drive circuit according to claim 1, characterized in that: The battery management system has a built-in battery management chip, and the first driving unit and the second driving unit are built-in the battery management chip.

3. A battery management system, characterized in that: The battery management system includes the MOS transistor gate drive circuit according to claim 2, and a first MOS transistor and a second MOS transistor, one end of the first MOS transistor and one end of the second MOS transistor are connected in series, the other end of the second MOS transistor is grounded, the other end of the first MOS transistor is a negative voltage output, and the first voltage input end is used as a positive voltage output.

4. The battery management system according to claim 3, characterized in that: One end of the sampling resistor is connected to the other end of the second MOS tube, and one end of the sampling resistor is connected to the current sampling signal pin of the battery management chip, and the other end of the sampling resistor is grounded.

5. The battery management system according to claim 4, characterized in that: When the battery management chip detects that the sampling voltage is greater than a threshold through the current sampling signal pin, it controls the second PWM signal and the fourth PWM signal to be high level signals and controls the first PWM signal and the third PWM signal to be low level signals.

6. The battery management system according to claim 5, characterized in that: After the battery management chip controls the second PWM signal and the fourth PWM signal to be high-level signals and controls the first PWM signal and the third PWM signal to be low-level signals for a set period of time, it controls the second PWM signal and the fourth PWM signal to be low-level signals and controls the first PWM signal and the third PWM signal to be high-level signals.

7. The battery management system according to claim 6, characterized in that: The set time period is determined based on an output current of the battery management system and a ratio of a voltage at twice the first voltage input terminal to a capacitance value of the first capacitor.

8. The battery management system according to claim 3, characterized in that: The voltage of the battery cell is greater than or equal to 2V and less than or equal to 5V.

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