Cache access apparatus and method

Abstract

The embodiment of the application provides a cache access device and method, at least applied to the cache field and the AI processor field, for accessing data in the cache, the cache comprising a plurality of memory block sets, each memory block set comprising a plurality of memory blocks; the device comprises: a memory block allocation module for determining a target memory block set pointed to by each to-be-accessed request in the cache and a target memory block pointed to in the target memory block set; a PBP module for generating priority information for each to-be-accessed request; based on the priority information, determining a processing time of the target memory block corresponding to the to-be-accessed request, and when the processing time arrives, performing data access on the stored data in the target memory block to obtain a plurality of data access results; and a data integration module for performing data integration processing on the plurality of data access results to obtain a data integration result and output. Through the application, parallel access can be realized, and the access efficiency and flexibility are greatly improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and to, but is not limited to, a cache access device and method. Background Technology

[0002] Currently, in mainstream artificial intelligence (AI) processors, the bandwidth of on-chip cache access is typically very high to match the high computing power of AI processors. Multiple sources of on-chip cache access can occur simultaneously, and the performance of these concurrent accesses significantly impacts the overall performance of the AI ​​processor. Furthermore, on-chip cache access methods are divided into vector data access and scalar data access.

[0003] However, accessing on-chip caches in related technologies has at least the following problems: it does not support discrete vector access; if multiple discrete vectors need to be accessed, multiple ordinary vector access instructions need to be initiated, and these multiple access data are read into the processor's internal registers and then concatenated together using data concatenation instructions; furthermore, the parallelism between different types of access sources is low or does not support parallel access. Therefore, the cache access methods in related technologies are inefficient and lack flexibility. Summary of the Invention

[0004] This application provides a cache access device and method, which are applied to at least the fields of caching and AI processors. It can realize parallel access to multiple types and multiple access sources, and can ensure that no memory block access conflicts occur when multiple access sources access the cache, which greatly improves access efficiency and access flexibility.

[0005] The technical solution of this application embodiment is implemented as follows: This application provides a cache access device for accessing data in a cache. The cache includes multiple sets of memory blocks, each set of memory blocks including multiple memory blocks. The device includes: a memory block allocation module, used to determine a target memory block set pointed to by each of the multiple requests to be accessed and a target memory block pointed to by each request in the cache, based on the request type and access address of each request to be accessed; wherein each target memory block corresponds to a PBP module; the PBP module is used to generate priority information for each request to be accessed; based on the priority information of each request to be accessed, determine the processing time of the target memory block corresponding to the request to be accessed, and when the processing time arrives, access the stored data in the target memory block to obtain multiple data access results; and a data integration module, used to perform data integration processing on the multiple data access results to obtain and output a data integration result.

[0006] In some embodiments, the request to be accessed includes a discrete vector read request; the memory block allocation module includes an IBP unit; the IBP unit is configured to: when there are multiple discrete vector read requests, determine the set identifier of the target memory block set pointed to by each discrete vector read request in the cache according to the access address of each discrete vector read request; and, if at least two discrete vector read requests have the same set identifier of the target memory block set, select one discrete vector read request from the at least two discrete vector read requests as the discrete vector read request accessing the target memory block set at the current time; and determine the target memory block accessed by the selected discrete vector read request from the target memory block set.

[0007] In some embodiments, the IBP unit is further configured to: if at least two discrete vector read requests have the same set identifier for the target memory block set, and discrete vector read requests that access the target memory block set at the current time have been filtered out, after the filtered discrete vector read requests have completed cache access, continue to filter the discrete vector read requests that access the target memory block set at the next time for the other discrete vector read requests among the at least two discrete vector read requests besides the filtered discrete vector read requests.

[0008] In some embodiments, the IBP unit includes a plurality of chained multiplexers; the plurality of chained multiplexers are used to: when there are multiple discrete vector read requests, perform chained selection based on the access address of each discrete vector read request to determine the set identifier of the target memory block set pointed to by each discrete vector read request in the cache.

[0009] In some embodiments, the request to be accessed includes a discrete vector write request; the memory block allocation module includes an IBP unit; the IBP unit is configured to: when there are multiple discrete vector write requests, determine the set identifier of the target memory block set pointed to by each discrete vector write request in the cache according to the access address of each discrete vector write request; and, if at least two discrete vector write requests have the same set identifier of the target memory block set, select one discrete vector write request from the at least two discrete vector write requests as the discrete vector write request accessing the target memory block set at the current time; and determine the target memory block accessed by the selected discrete vector write request from the target memory block set.

[0010] In some embodiments, the request to be accessed includes a continuous vector access request; the memory block allocation module includes an element shifting unit; the element shifting unit is configured to: determine the starting address accessed by the continuous vector access request, and determine a set identifier of at least one set of target memory blocks continuously accessed by the continuous vector access request based on the starting address; and determine the target memory block accessed by the continuous vector access request from the at least one set of target memory blocks corresponding to the set identifier.

[0011] In some embodiments, the request to be accessed includes a scalar access request; the memory block allocation module includes a splitting unit; the splitting unit is configured to: determine the access address corresponding to the scalar access request, and determine the set identifier of the target memory block set to be accessed based on the access address; and determine the target memory block accessed by the scalar access request from the target memory block set corresponding to the set identifier.

[0012] In some embodiments, each set of memory blocks corresponds to a PBP module; the apparatus further includes: a signal crossing module, used to perform signal crossing routing on multiple access requests after the memory block allocation module allocates target memory blocks, so as to integrate at least one access request corresponding to the same target memory block set into a signal set, and input the access requests in the same signal set to the PBP module of the corresponding target memory block set.

[0013] In some embodiments, the PBP module includes a priority generation unit, a sorting unit, and a data selector; the priority generation unit is used to generate priority information for each of the requests to be accessed; the sorting unit is used to sort the plurality of requests to be accessed based on the priority information to form a sequence of requests to be accessed; the data selector is used to select the request to be accessed from the sequence of requests to be accessed that has the current processing time, and send the selected request to be accessed to the data access module to realize data access to the stored data in the target memory block and obtain the data access result.

[0014] In some embodiments, the priority generation unit includes: a register corresponding to each access request, an initialization subunit, and an assignment subunit; the initialization subunit is used to initialize the count value in each register with a pre-designed value; the assignment subunit is used to assign a value to the count value in the register corresponding to the access request when an access request is received, and when any access request completes access, the register with a count value less than the count value in the register corresponding to the access request is determined as the target register, and the count value in the target register is incremented by one; wherein, the priority information of the access request is determined based on the count value in the corresponding register.

[0015] In some embodiments, the request to be accessed includes a discrete vector read request; the data integration module includes a rearrangement unit; the rearrangement unit is used to rearrange the discrete vector read data in the plurality of data access results according to the access address of each request to be accessed, to obtain rearranged data; the rearranged data constitutes the data integration result.

[0016] In some embodiments, the request to be accessed includes a continuous vector read request; the data integration module includes an element shifting unit; the element shifting unit is used to perform element shifting processing on the continuous vector read data in the plurality of data access results based on the starting address accessed by the continuous vector read request, to obtain element shifted data; the element shifted data constitutes the data integration result.

[0017] In some embodiments, the request to be accessed includes a scalar read request; the data integration module includes a multiplexer unit; the multiplexer unit is used to select data from scalar read data in multiple data access results to obtain read-selected data; the read-selected data constitutes the data integration result.

[0018] This application provides a cache access method applied to the aforementioned cache access device for accessing data in a cache. The method includes: receiving multiple requests to be accessed; determining, based on the request type and access address of each request to be accessed, a set of target memory blocks pointed to by the request to be accessed in the cache and a target memory block pointed to in the set of target memory blocks; generating priority information for each request to be accessed; determining, based on the priority information of each request to be accessed, a processing time for the target memory block corresponding to the request to be accessed, and when the processing time arrives, accessing the stored data in the target memory block to obtain multiple data access results; performing data integration processing on the multiple data access results to obtain a data integration result and outputting it.

[0019] The embodiments of this application have the following beneficial effects: By dividing the cache into multiple different sets of memory blocks, each set of memory blocks includes multiple memory blocks, multiple access sources can access different sets of memory blocks and different memory blocks within the sets of memory blocks in parallel. Furthermore, since the memory block allocation module can determine the target set of memory blocks pointed to by the request in the cache and the target memory block pointed to in the target set of memory blocks based on the request type and access address of the request to be accessed, and by generating priority information for each request to be accessed in conjunction with the PBP module, the access timing of different requests to the same memory block in the same set of memory blocks is coordinated, thus realizing the orderly access of multiple requests to be accessed from different access sources, ensuring that no memory block access conflict occurs when multiple access sources access the cache, thereby greatly improving access efficiency and access flexibility. Attached Figure Description

[0020] Figure 1 This is a schematic diagram illustrating the implementation process of discrete access in related technologies; Figure 2 This is a schematic diagram of the structure of the cache access device provided in the embodiments of this application. Figure 1 ; Figure 3 This is a schematic diagram of the structure of the cache access device provided in the embodiments of this application. Figure 2 ; Figure 4 This is a schematic diagram of the structure of the cache access device provided in the embodiments of this application. Figure 3 ; Figure 5 This is a schematic diagram of the structure of the cache access device provided in the embodiments of this application. Figure 4 ; Figure 6 This is a schematic diagram of the structure of the cache access device provided in the embodiments of this application. Figure 5 ; Figure 7 This is a schematic diagram of the structure of the cache access device provided in the embodiments of this application. Figure 6 ; Figure 8 This is a schematic diagram of the structure of the cache access device provided in the embodiments of this application. Figure 7 ; Figure 9 This is a schematic diagram of the structure of the cache access device provided in the embodiments of this application. Figure 8 ; Figure 10 This is a flowchart illustrating the cache access method provided in an embodiment of this application; Figure 11 This is a schematic diagram of scalar access provided in an embodiment of this application; Figure 12 This is a schematic diagram of continuous vector access provided in an embodiment of this application; Figure 13 This is a schematic diagram of discrete vector access provided in an embodiment of this application; Figure 14 This is a schematic diagram of the overall structure of the cache access device provided in the embodiments of this application; Figure 15 This is a schematic diagram of the structure of the IBP unit provided in the embodiments of this application; Figure 16 This is a schematic diagram of the structure of the PBP module provided in the embodiments of this application; Figure 17 This is a schematic diagram of the priority generation unit provided in an embodiment of this application; Figure 18 This is a schematic diagram illustrating the relationship between the memory block set and memory blocks provided in the embodiments of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] In the following description, references to "some embodiments" refer to a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same or different subsets of all possible embodiments and may be combined with each other without conflict. Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of this application pertain. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit the application.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0024] Before explaining the cache access apparatus and method of the embodiments of this application, the on-chip cache access method in the related art will be described first.

[0025] In related technologies, access to on-chip caches is typically subject to the following limitations: 1) It does not support discrete vector access. To achieve discrete access, multiple sequential vector access instructions and several concatenation instructions need to be used together, which is inefficient and lacks flexibility. In applications with many discrete vector access scenarios, the AI ​​processor performs poorly. Figure 1 This is a schematic diagram illustrating the implementation process of discrete access in related technologies. If you want to access... Figure 1 The four vectors D0, D1, D2, and D3 shown require four ordinary vector access instructions to read the four access data into the processor's internal registers, and then concatenate them together using a data concatenation instruction.

[0026] 2) The parallelism between multiple access sources is low, or parallel access is not supported, or the performance is poor when different access sources access the on-chip cache at the same time.

[0027] 3) The conflict issue of multiple access sources accessing the on-chip cache is resolved by software. Specifically, the software guarantees that no memory bank conflicts will occur when multiple sources access the on-chip cache, which significantly reduces the software's flexibility. Furthermore, bank conflicts are not allowed when multiple access sources access the on-chip cache, making the software highly restrictive and lacking in flexibility.

[0028] To address at least one of the aforementioned problems in related technologies, this application provides a cache access apparatus and method. This apparatus and method divide the cache into different sets of memory blocks to support discrete vector access, and sets up an IBP unit to detect and resolve bank conflicts between discrete vector accesses. Data is read from the on-chip cache and rearranged using a shuffle unit. Discrete vector access can be achieved with a single instruction, significantly improving the performance of discrete access in AI processors. Furthermore, dividing the cache into different sets of memory blocks, each set further divided into multiple memory blocks, supports parallel access from multiple sources, greatly improving performance. Additionally, this application provides a PBP module to handle bank conflicts when multiple access sources access the same memory block. Hardware resolves bank conflicts, eliminating the need for software restrictions on multiple access sources, significantly enhancing processor flexibility.

[0029] The cache access device provided in this application embodiment is used to access data in a cache. The cache includes multiple sets of memory blocks, and each set of memory blocks includes multiple memory blocks. The cache access device includes a memory block allocation module, a PBP module, and a data integration module. Since the cache is divided into multiple different sets of memory blocks, each set of memory blocks includes multiple memory blocks, it supports multiple access sources to access different sets of memory blocks and to access different memory blocks within the sets of memory blocks in parallel. Furthermore, the memory block allocation module can determine the target set of memory blocks pointed to by the request in the cache and the target memory block pointed to by the request in the target set based on the request type and access address of the request to be accessed. Combined with the priority information generated for each request to be accessed by the PBP module, it coordinates the access timing of different requests to the same memory block in the same set of memory blocks, achieving ordered access of multiple requests from different access sources. This ensures that no memory block access conflicts occur when multiple access sources access the cache, thereby greatly improving access efficiency and flexibility.

[0030] The cache access apparatus of this application embodiment will be described below.

[0031] Figure 2 This is a schematic diagram of the structure of the cache access device provided in the embodiments of this application. Figure 1 ,like Figure 2 As shown, the cache access device 20 includes: a memory block allocation module 21, a priority bank-conflict processor (PBP) module 22, and a data integration module 23.

[0032] Here, the memory block allocation module 21 is used to determine the target memory block set pointed to by each request in the cache and the target memory block pointed to in the target memory block set according to the request type and access address of each request in the multiple requests to be accessed; wherein, each target memory block corresponds to a PBP module.

[0033] In this embodiment of the application, for a pending access request input to the cache access device, the cache access device can parse the pending access request to obtain the request type and access address of the pending access request. The pending access request includes a read request and a write request, wherein a read request is used to request a data read operation on the data at the access address, and a write request is used to request a data write operation on the data at the access address.

[0034] In this embodiment, the cache access device may include multiple memory block allocation modules, each of which is used to perform memory block allocation processing on a type of request to be accessed. After parsing the request type and access address of the request to be accessed, the request to be accessed is input to the memory block allocation module corresponding to the request type, so that the memory block allocation module determines the target memory block set pointed to by the request to be accessed in the cache and the target memory block pointed to in the target memory block set based on the access address.

[0035] It should be noted that multiple different requests to be accessed may point to the same or different sets of target memory blocks in the cache; multiple different requests to be accessed may point to the same or different target memory blocks in the set of target memory blocks.

[0036] In this embodiment, the cache can be divided into multiple memory block sets, each containing multiple memory blocks. When dividing the memory block sets, the smallest unit of division can be a memory block (bank). Here, "bank" is a division method. In the CPU, data access involves accessing a specific address to obtain the data at that address. However, here, it involves accessing the addresses of multiple memory blocks (i.e., banks) at once to obtain all the data at those addresses and logically mapping it to different memory blocks. After dividing the memory blocks, they are grouped according to their corresponding addresses, with each group forming a memory block set. Grouping can be done according to a preset number of groups. For example, the multiple memory blocks in the cache can be divided into 4 or 7 groups, corresponding to 4 or 7 memory block sets.

[0037] In some embodiments, the number of groups can be determined based on the CPU's business scenario. For example, it can be determined based on the maximum parallelism of the business being processed by the processor, where parallelism refers to the number of access requests when performing parallel access in that business scenario. In this embodiment, the number of groups can be determined based on the parallelism of the CPU's parallel access in a typical or regular business scenario of the target application. For caches that have already been grouped, the number of memory block sets cannot be changed.

[0038] In the cache access mechanism, each target memory block corresponds to a PBP module. That is, each memory block has its own PBP module, and the requests to access that memory block are handled through the corresponding PBP module for subsequent conflict resolution. Therefore, once the target memory block is identified, the access request can be input to the PBP module corresponding to that target memory block.

[0039] PBP module 22 is used to generate priority information for each request to be accessed; based on the priority information of each request to be accessed, the processing time of the target memory block corresponding to the request to be accessed is determined, and when the processing time arrives, the stored data in the target memory block is accessed to obtain multiple data access results.

[0040] Here, for multiple pending requests received by the cache access device, each pending request has priority information for different request types. The priority information for different pending requests can be the same or different. The priority information reflects the current waiting time of the corresponding pending request; that is, the longer the current waiting time, the higher the priority. The priority information can be generated by a priority generation unit, the structure of which and the process of generating priority information will be explained below.

[0041] In this embodiment of the application, the PBP module generates priority information, determines the processing time, and performs data access when the processing time arrives. This series of processes enables priority memory block conflict handling for multiple pending access requests. In other words, the PBP module avoids memory block conflict between multiple pending access requests.

[0042] The data integration module 23 is used to integrate and process multiple data access results, obtain the data integration result, and output it.

[0043] Since the multiple input requests have different request types and access addresses, after data access is completed, different sets of memory blocks and access data under different memory blocks will be obtained, resulting in multiple different data access results. To achieve a unified output of access data for different request types, a data integration module can be used to integrate the multiple data access results.

[0044] Here, data integration processing refers to the process of classifying multiple data access results according to the request type of the corresponding request to be accessed. In the obtained data integration results, data access results of the same request type constitute a data set, and the data set under each request type is output separately to realize the access response to multiple input requests to be accessed.

[0045] The cache access device provided in this application divides the cache into multiple different sets of memory blocks, each set containing multiple memory blocks. This allows multiple access sources to access different sets of memory blocks and different memory blocks within those sets in parallel. Furthermore, the memory block allocation module can determine the target set of memory blocks in the cache and the target memory block in the target set based on the request type and access address of the request to be accessed. In addition, by combining the PBP module to generate priority information for each request to be accessed, the timing of access to the same memory block in the same set by different requests to be accessed is coordinated. This enables ordered access to multiple requests from different access sources, ensuring that no memory block access conflicts occur when multiple access sources access the cache, thereby greatly improving access efficiency and flexibility.

[0046] Figure 3 This is a schematic diagram of the structure of the cache access device provided in the embodiments of this application. Figure 2 ,like Figure 3 As shown, the cache access device 20 includes: an IBP unit 31, a PBP module 22, and a data integration module 23.

[0047] IBP unit 31 is used to determine the set identifier of the target memory block set pointed to by each discrete vector read request in the cache according to the access address of each discrete vector read request when there are multiple discrete vector read requests; and, if at least two discrete vector read requests have the same set identifier of the target memory block set, select one discrete vector read request from the at least two discrete vector read requests as the discrete vector read request that accesses the target memory block set at the current time; and determine the target memory block accessed by the selected discrete vector read request from the target memory block set.

[0048] Here, when the IBP unit determines that at least two discrete vector read requests have the same set identifier for their target memory block sets, it indicates that multiple discrete vector read requests are accessing the same memory block set. To avoid memory block conflicts caused by multiple discrete vector read requests accessing the same memory block set simultaneously, the IBP unit can select one discrete vector read request from the at least two discrete vector read requests as the discrete vector read request accessing the target memory block set at the current moment. Then, it determines the target memory block accessed by the selected discrete vector read request from the target memory block set. In this way, at the current moment, only one discrete vector read request accesses the target memory block in the target memory block set, thereby avoiding memory block conflicts.

[0049] In other embodiments, when the IBP unit determines that at least two discrete vector read requests correspond to target memory block sets with the same set identifier, it indicates that multiple discrete vector read requests are accessing the same memory block set. The IBP unit can further determine whether the target memory blocks accessed by these multiple discrete vector read requests are the same. If they are the same, it indicates that multiple discrete vector read requests are currently accessing the same memory block. In this case, to avoid memory block conflicts, the IBP unit can select one discrete vector read request as the discrete vector read request accessing the target memory block in the target memory block set at the current moment.

[0050] In some embodiments, the IBP unit is further configured to, if there are at least two discrete vector read requests whose target memory block sets have the same set identifier, and discrete vector read requests that access the target memory block set at the current time have been filtered out, after the filtered discrete vector read requests have completed cache access, continue to filter the other discrete vector read requests among the at least two discrete vector read requests besides the filtered discrete vector read requests to access the target memory block set at the next time.

[0051] Here, after the discrete vector read request accessing the target memory block set at the current moment completes the cache access, there are no other discrete vector read requests accessing the target memory block set. Therefore, one discrete vector read request can be selected from the remaining discrete vector read requests accessing the target memory block set to perform cache access and data access on the target memory block set. In this way, for at least two discrete vector read requests accessing the target memory block set, one discrete vector read request is selected for cache access each time, and access is performed in order, avoiding memory block conflicts.

[0052] In other embodiments, if at least two discrete vector read requests correspond to the same target memory block identifier, it indicates that multiple discrete vector read requests are performing discrete accesses on the same memory block in the same memory block set. In this case, if the discrete vector read requests accessing the target memory block at the current moment have already been selected, after the selected discrete vector read requests complete their cache access, the remaining discrete vector read requests (excluding the selected ones) from the at least two discrete vector read requests are further filtered to select the discrete vector read requests accessing the target memory block at the next moment.

[0053] PBP module 22 is used to generate priority information for each discrete vector read request; based on the priority information of each discrete vector read request, it determines the processing time of the target memory block corresponding to the discrete vector read request, and when the processing time arrives, it accesses the stored data in the target memory block to obtain multiple data access results.

[0054] The data integration module 23 is used to integrate and process multiple data access results, obtain the data integration result, and output it.

[0055] The cache access device provided in this application allocates memory blocks for multiple discrete vector read requests that access the same set of memory blocks or the same memory block through the IBP unit. This enables multiple discrete vector read requests to access the same set of memory blocks or the same memory block sequentially, thereby avoiding memory block conflicts and improving the efficiency and accuracy of cache access.

[0056] Figure 4 This is a schematic diagram of the structure of the cache access device provided in the embodiments of this application. Figure 3 ,like Figure 4 As shown, the cache access device 20 includes: a chain of multiple two-to-one selectors 41, a PBP module 22, and a data integration module 23.

[0057] Multiple 2-to-1 selectors 41 are linked together to perform chained selection based on the access address of each discrete vector read request when there are multiple discrete vector read requests, so as to determine the set identifier of the target memory block set pointed to by each discrete vector read request in the cache.

[0058] In other embodiments, the chained multiple two-to-one selectors 41 are further configured to, among multiple discrete vector read requests, if at least two discrete vector read requests have the same set identifier for their target memory block sets, select one discrete vector read request from the at least two discrete vector read requests as the discrete vector read request accessing the target memory block set at the current moment; and determine the target memory block accessed by the selected discrete vector read request from the target memory block set. Furthermore, if at least two discrete vector read requests have the same set identifier for their target memory block sets, and the discrete vector read request accessing the target memory block set at the current moment has already been selected, after the selected discrete vector read request completes its cache access, continue to select the discrete vector read request accessing the target memory block set at the next moment from the other discrete vector read requests among the at least two discrete vector read requests besides the selected discrete vector read request.

[0059] PBP module 22 is used to generate priority information for each discrete vector read request; based on the priority information of each discrete vector read request, it determines the processing time of the target memory block corresponding to the discrete vector read request, and when the processing time arrives, it accesses the stored data in the target memory block to obtain multiple data access results.

[0060] The data integration module 23 is used to integrate and process multiple data access results, obtain the data integration result, and output it.

[0061] The cache access device provided in this application embodiment sequentially selects multiple discrete vector read requests through a chained multiple two-to-one selector to determine the set identifier of the target memory block set pointed to by each discrete vector read request in the cache. It can allocate memory blocks for multiple discrete vector read requests that access the same memory block set or the same memory block, thereby realizing the sequential access of multiple discrete vector read requests to the same memory block set or the same memory block, avoiding memory block conflicts, and improving the efficiency and accuracy of cache access.

[0062] In some embodiments, the request to be accessed includes a discrete vector write request, and the cache access device can be used to respond to the discrete vector write request, thereby enabling access to the target memory block set and the target memory block in the cache. Figure 5 This is a schematic diagram of the structure of the cache access device provided in the embodiments of this application. Figure 4 ,like Figure 5 As shown, the cache access device 20 includes: an IBP unit 31, a PBP module 22, and a data integration module 23.

[0063] IBP unit 31 is configured to, when there are multiple discrete vector write requests, determine the set identifier of the target memory block set pointed to by each discrete vector write request in the cache according to the access address of each discrete vector write request; and, if at least two discrete vector write requests have the same set identifier of the target memory block set, select one discrete vector write request from the at least two discrete vector write requests as the discrete vector write request accessing the target memory block set at the current time; and determine the target memory block accessed by the selected discrete vector write request from the target memory block set.

[0064] PBP module 22 is used to generate priority information for each discrete vector write request; based on the priority information of each discrete vector write request, it determines the processing time of the target memory block corresponding to the discrete vector write request, and when the processing time arrives, it accesses the stored data in the target memory block to obtain multiple data access results.

[0065] The data integration module 23 is used to integrate and process multiple data access results, obtain the data integration result, and output it.

[0066] The cache access device provided in this application allocates memory blocks for multiple discrete vector write requests that access the same set of memory blocks or the same memory block through the IBP unit. This enables multiple discrete vector write requests to access the same set of memory blocks or the same memory block sequentially, thereby avoiding memory block conflicts and improving the efficiency and accuracy of cache access.

[0067] In some embodiments, the request to be accessed includes a continuous vector access request, and the cache access device can be used to respond to the continuous vector access request, thereby enabling access to the target memory block set and the target memory block in the cache. Figure 6 This is a schematic diagram of the structure of the cache access device provided in the embodiments of this application. Figure 5 ,like Figure 6 As shown, the cache access device 20 includes: an element shifting unit 61, a PBP module 22, and a data integration module 23.

[0068] The element shifting unit 61 is used to determine the starting address accessed by the continuous vector access request, and to determine the set identifier of the set of at least one target memory blocks continuously accessed by the continuous vector access request based on the starting address; and to determine the target memory blocks accessed by the continuous vector access request from the set of at least one target memory blocks corresponding to the set identifier.

[0069] In this embodiment of the application, the continuous vector access request includes a continuous vector read request and a continuous vector write request.

[0070] PBP module 22 is used to generate priority information for each consecutive vector access request; based on the priority information of each consecutive vector access request, it determines the processing time of the target memory block corresponding to the consecutive vector access request, and when the processing time arrives, it performs data access on the stored data in the target memory block to obtain multiple data access results.

[0071] The data integration module 23 is used to integrate and process multiple data access results, obtain the data integration result, and output it.

[0072] The cache access device provided in this application determines multiple consecutive target memory blocks pointed to by the continuous vector access request through the element shifting unit, thereby realizing cache access to the continuous vector data in these multiple target memory blocks and realizing accurate response to the continuous vector access request.

[0073] In some embodiments, the request to be accessed includes a scalar access request, and the cache access device can be used to respond to the scalar access request, thereby enabling access to the target memory block set and the target memory block in the cache. Figure 7 This is a schematic diagram of the structure of the cache access device provided in the embodiments of this application. Figure 6 ,like Figure 7 As shown, the cache access device 20 includes: a splitting unit 71, a PBP module 22, and a data integration module 23.

[0074] The splitting unit 71 is used to determine the access address corresponding to the scalar access request, and to determine the set identifier of the target memory block set based on the access address; and to determine the target memory block accessed by the scalar access request from the target memory block set corresponding to the set identifier.

[0075] In this embodiment of the application, scalar access requests include scalar read requests and scalar write requests.

[0076] PBP module 22 is used to generate priority information for each scalar access request; based on the priority information of each scalar access request, it determines the processing time of the target memory block corresponding to the scalar access request, and when the processing time arrives, it performs data access on the stored data in the target memory block to obtain multiple data access results.

[0077] The data integration module 23 is used to integrate and process multiple data access results, obtain the data integration result, and output it.

[0078] The cache access device provided in this application determines the target memory block pointed to by the scalar access request through the splitting unit, thereby realizing cache access to the scalar data in the target memory block and achieving accurate response to the scalar access request.

[0079] In some embodiments, Figure 8 This is a schematic diagram of the structure of the cache access device provided in the embodiments of this application. Figure 7 ,like Figure 8 As shown, the cache access device 20 includes: a memory block allocation module 21, a signal crossover module 81, a PBP module 22, and a data integration module 23.

[0080] The memory block allocation module 21 is used to determine the target memory block set pointed to by each request in the cache and the target memory block pointed to in the target memory block set according to the request type and access address of each request in the multiple requests to be accessed; wherein, each target memory block corresponds to a PBP module.

[0081] The signal crossover module 81 is used to perform signal crossover routing on multiple access requests after the memory block allocation module allocates the target memory block, so as to integrate at least one access request corresponding to the same target memory block set into a signal set, and input the access requests in the same signal set into the PBP module 22 of the corresponding target memory block.

[0082] In this embodiment, the input requests to be accessed may include multiple requests, and these requests may have different request types. The cache access device includes a memory block allocation module that allocates memory blocks for each request type. Therefore, different memory block allocation modules can output multiple requests to be accessed after allocating target memory blocks. Since requests of different types may point to the same set of memory blocks or the same memory block, an information cross-connection module can cross-connect the multiple requests to be accessed to obtain a signal set pointing to each target memory block set. In other words, the function of the signal cross-connection module is to cross-connect the multiple requests to be accessed to multiple target memory block sets, that is, to divide the multiple requests to be accessed into sets according to the set identifier of the target memory block set, so that multiple requests to be accessed corresponding to the same target memory block set constitute a signal set.

[0083] PBP module 22 is used to generate priority information for each request to be accessed; based on the priority information of each request to be accessed, the processing time of the target memory block corresponding to the request to be accessed is determined, and when the processing time arrives, the stored data in the target memory block is accessed to obtain multiple data access results.

[0084] The data integration module 23 is used to integrate and process multiple data access results, obtain the data integration result, and output it.

[0085] The cache access device provided in this application embodiment uses a signal crossover module to perform signal crossover routing on multiple requests to be accessed after the allocation of a target memory block, resulting in multiple signal sets. This allows the requests to be accessed in each signal set to be input into the PBP module of the same target memory block set, thus dividing requests to access the same target memory block set into the same signal set. In this way, requests to be accessed from the same target memory block set can be simultaneously input into the PBP module of that target memory block set, achieving accurate segmentation of requests of different request types at the target memory block set level. This ensures that subsequent cache access processes for multiple requests can proceed smoothly and orderly.

[0086] Figure 9 This is a schematic diagram of the structure of the cache access device provided in the embodiments of this application. Figure 8 ,like Figure 9 As shown, the cache access device 20 includes: a memory block allocation module 21, a priority generation unit 91, a sorting unit 92, a data selector 93, and a data integration module 23.

[0087] The memory block allocation module 21 is used to determine the target memory block set pointed to by each of the multiple pending requests and the target memory block pointed to by each pending request in the cache, based on the request type and access address of each pending request; wherein each target memory block corresponds to a PBP module. In this embodiment of the application, the PBP module includes a priority generation unit 91, a sorting unit 92, and a data selector 93.

[0088] Priority generation unit 91 is used to generate priority information for each request to be accessed.

[0089] In some embodiments, the priority generation unit 91 includes: a register corresponding to each access request, an initialization subunit, and an assignment subunit (not shown in the figure).

[0090] In this embodiment, an initialization subunit is used to initialize the count value in each of the registers using a pre-designed value. An assignment subunit is used to assign a value to the count value in the register corresponding to the access request when an access request is received, and to determine the register with a count value less than the count value in the register corresponding to the access request as the target register when any access request completes access, and to increment the count value in the target register by one. Here, the priority information of the access request is determined based on the count value in the corresponding register. The access request with the largest count value has the highest priority.

[0091] The sorting unit 92 is used to sort multiple requests to be accessed based on priority information to form a sequence of requests to be accessed.

[0092] The data selector 93 is used to select the request to be accessed from the sequence of requests to be accessed that is being processed at the current moment, and send the selected request to be accessed to the data access module to realize data access to the stored data in the target memory block and obtain the data access result.

[0093] Here, the request with the highest priority can be identified as the request to be processed at the current moment. Alternatively, in the sequence of requests to be accessed, the request that is first in the sequence can be identified as the request to be processed at the current moment. Or, in the sequence of requests to be accessed, the request that is N positions above the sequence can be identified as the request to be processed at the current moment, where N is an integer greater than 1.

[0094] The data integration module 23 is used to integrate and process multiple data access results, obtain the data integration result, and output it.

[0095] The cache access device provided in this application embodiment sequentially uses a priority generation unit, a sorting unit, and a data selector to handle priority conflicts of multiple requests to be accessed. This allows multiple requests to be accessed to be processed in sequence according to the priority of each request, thereby ensuring that the cache access process can proceed smoothly and orderly.

[0096] In some embodiments, the request to be accessed includes a discrete vector read request; the data integration module includes a rearrangement unit; wherein the rearrangement unit is used to rearrange the discrete vector read data in multiple data access results according to the access address of each request to be accessed, to obtain rearranged data; here, the rearranged data constitutes the data integration result.

[0097] In some embodiments, the request to be accessed includes a continuous vector read request; the data integration module includes an element shifting unit; wherein, the element shifting unit is used to perform element shifting processing on the continuous vector read data in multiple data access results based on the starting address accessed by the continuous vector read request, to obtain element-shifted data; here, the element-shifted data constitutes the data integration result.

[0098] In some embodiments, the request to be accessed includes a scalar read request; the data integration module includes a multiplexer unit; wherein the multiplexer unit is used to select scalar read data from multiple data access results to obtain read-selected data; here, the read-selected data constitutes the data integration result.

[0099] Based on the above embodiments of the cache access device, this application provides a cache access method for accessing data in the cache, and the cache access method is applied to the cache access device provided in any of the above embodiments. Figure 10 This is a flowchart illustrating the cache access method provided in an embodiment of this application, as shown below. Figure 10 As shown, the method includes the following steps: Step S11: Receive multiple requests to be accessed.

[0100] Step S12: Based on the request type and access address of each request to be accessed, determine the set of target memory blocks that the request to be accessed points to in the cache and the target memory block that it points to in the set of target memory blocks.

[0101] In some embodiments, the request to be accessed includes a discrete vector read request; step S12 can be implemented in the following ways: When there are multiple discrete vector read requests, the set identifier of the target memory block set pointed to by each discrete vector read request in the cache is determined according to the access address of each discrete vector read request. In some embodiments, when there are multiple discrete vector read requests, a chained selection can be performed according to the access address of each discrete vector read request to determine the set identifier of the target memory block set pointed to by each discrete vector read request in the cache.

[0102] Then, among multiple discrete vector read requests, if at least two discrete vector read requests have the same set identifier for the target memory block set, one discrete vector read request is selected from the at least two discrete vector read requests as the discrete vector read request that accesses the target memory block set at the current moment; and the target memory block accessed by the selected discrete vector read request is determined from the target memory block set.

[0103] In some embodiments, if at least two discrete vector read requests have the same set identifier for the target memory block set, and discrete vector read requests that access the target memory block set at the current time have been filtered out, after the filtered discrete vector read requests have completed cache access, for the other discrete vector read requests among the at least two discrete vector read requests besides the filtered discrete vector read requests, the discrete vector read requests that access the target memory block set at the next time are further filtered out.

[0104] In some embodiments, the request to be accessed includes a discrete vector write request; step S12 can also be implemented in the following way: when there are multiple discrete vector write requests, the set identifier of the target memory block set pointed to by each discrete vector write request in the cache is determined according to the access address of each discrete vector write request; and, among the multiple discrete vector write requests, if there are at least two discrete vector write requests whose target memory block set set identifiers are the same, a discrete vector write request is selected from the at least two discrete vector write requests as the discrete vector write request that accesses the target memory block set at the current time; and the target memory block accessed by the selected discrete vector write request is determined from the target memory block set.

[0105] In some embodiments, the request to be accessed includes a continuous vector access request; step S12 can also be implemented by: determining the starting address accessed by the continuous vector access request, and determining a set identifier of the set of at least one target memory blocks continuously accessed by the continuous vector access request based on the starting address. Then, the target memory blocks accessed by the continuous vector access request are determined from the set of at least one target memory blocks corresponding to the set identifier.

[0106] In some embodiments, the request to be accessed includes a scalar access request; step S12 can also be implemented by: determining the access address corresponding to the scalar access request, and determining the set identifier of the set of target memory blocks to be accessed based on the access address, and then determining the target memory block accessed by the scalar access request from the set of target memory blocks corresponding to the set identifier.

[0107] In some embodiments, after determining the target memory block set pointed to by the access request in the cache and the target memory block pointed to in the target memory block set in step S12, the method may further include: performing signal cross-winding on multiple access requests after the memory block allocation module allocates the target memory blocks, so as to integrate at least one access request corresponding to the same target memory block set into a signal set, and inputting the access requests in the same signal set into the PBP module of the corresponding target memory block set.

[0108] Step S13: Generate priority information for each request to be accessed.

[0109] Here, priority information can be generated as follows: The count value in the register corresponding to each access request is initialized using a pre-designed value; then, when an access request is received, the count value in the register corresponding to that access request is assigned a value; and when any access request completes access, the register with a count value less than the count value in the register corresponding to that access request is identified as the target register, and the count value in the target register is incremented. Here, the priority information of the access request is determined based on the count value in the corresponding register.

[0110] Step S14: Based on the priority information of each request to be accessed, determine the processing time of the target memory block corresponding to the request to be accessed, and when the processing time arrives, perform data access on the stored data in the target memory block to obtain multiple data access results.

[0111] Here, multiple requests to be accessed can be sorted based on priority information to form a sequence of requests to be accessed; then, the request to be accessed with the current processing time is selected from the sequence of requests to be accessed, and the selected request to be accessed is sent to the data access module to realize data access to the stored data in the target memory block and obtain the data access result.

[0112] Step S15: Perform data integration processing on multiple data access results to obtain and output the data integration result.

[0113] In some embodiments, the request to be accessed includes a discrete vector read request; the discrete vector read data in multiple data access results can be rearranged according to the access address of each of the requests to be accessed to obtain rearranged data; wherein, the rearranged data constitutes the data integration result.

[0114] In some embodiments, the request to be accessed includes a continuous vector read request; based on the starting address accessed by the continuous vector read request, the continuous vector read data in multiple data access results can be element-shifted to obtain element-shifted data; wherein, the element-shifted data constitutes the data integration result.

[0115] In some embodiments, the request to be accessed includes a scalar read request; data selection can be performed on the scalar read data from multiple data access results to obtain read selection data; wherein, the read selection data constitutes the data integration result.

[0116] The cache access method provided in this application divides the cache into multiple different sets of memory blocks, each set containing multiple memory blocks. This allows multiple access sources to access different sets of memory blocks and different memory blocks within those sets in parallel. Furthermore, by determining the target set of memory blocks in the cache and the target memory block in the target set based on the request type and access address of the request to be accessed, and by generating priority information for each request to be accessed, the method coordinates the access timing of different requests to the same memory block in the same set. This ensures orderly access by multiple requests from different access sources, preventing memory block access conflicts when multiple access sources access the cache, thereby greatly improving access efficiency and flexibility.

[0117] The following will describe an exemplary application of the embodiments of this application in a real-world application scenario.

[0118] In mainstream AI processors, on-chip cache access bandwidth is typically high to match the high computing power of the AI ​​processor. Multiple sources can access the on-chip cache simultaneously, and the performance of these simultaneous accesses significantly impacts the overall performance of the AI ​​processor. On-chip cache access methods are divided into vector data access and scalar data access. The main protection points of this application embodiment are: dividing the on-chip cache into multiple memory block sets (i.e., bank groups), each containing several memory blocks (i.e., banks), allowing parallel access to different memory blocks, thus improving the performance of multiple access sources accessing the on-chip cache simultaneously; supporting discrete vector access, this application embodiment uses an internal memory block conflict handling unit (IBP) to resolve memory block conflicts within discrete vector access; when multiple access sources point to the same memory block, this application embodiment implements a priority memory block conflict handling unit (PBP) to resolve memory block conflicts between multiple access sources; discrete vector access can access the entire on-chip cache area, offering high flexibility.

[0119] In the field of AI processors, the access performance of on-chip cache has a significant impact on the performance of AI processors. This application proposes a device (i.e., a cache access device) that supports discrete vector, continuous vector and scalar access, which greatly improves the access capability of on-chip cache and effectively enhances the competitiveness of products.

[0120] The following section introduces different types of on-chip cache access methods.

[0121] 1) Scalar access, such as Figure 11 The diagram shown is a scalar access schematic provided in an embodiment of this application. When performing scalar access, only one scalar data 111 in the on-chip cache is read.

[0122] 2) Continuous vector access, such as Figure 12 The diagram shown is a schematic diagram of continuous vector access provided in an embodiment of this application. When performing continuous vector access, a continuous data space 121 in the on-chip cache is accessed.

[0123] 3) Discrete vector access, such as Figure 13 The diagram shown is a schematic diagram of discrete vector access provided in an embodiment of this application. When performing discrete vector access, several discrete vectors 131 are accessed.

[0124] Figure 14 This is a schematic diagram of the overall structure of the cache access device provided in the embodiments of this application, as shown below. Figure 14 As shown, embodiments of this application support parallel access from multiple access sources, with different access sources from... Figure 14 Enter from the left side of the middle. Figure 14The document lists several types of access: Discrete vector read (disc_v_r0 / 1), Discrete vector write (disc_v_w), Continuous vector read (cont_v_r), Continuous vector write (cont_v_w), Scalar read (scalar_r), and Scalar write (scalar_w).

[0125] In this embodiment, different access methods are used for different types of access. For discrete vector read / write, the data needs to be sent to the IBP unit 141 for processing. The structure of the IBP unit 141 is as follows: Figure 15 As shown, where, Figure 15 In the memory block set, req_s0~7 represent 8 discrete vector access addresses. IBP unit 141 uses a chained two-to-one selector 151 to select the access to bg0~15. If multiple discrete accesses point to the same memory block set, only one discrete vector access will be selected to access the memory block set, and other discrete vector accesses will be performed subsequently. This solves the problem of bank conflicts caused by multiple discrete vector access sources. Finally, the output is a request for 16 memory block sets.

[0126] Please continue to refer to Figure 14 For ordinary continuous vector access, the element shift unit (ESFT, elementshift) 142 is fed into the array to obtain the set of continuous memory blocks that need to be accessed based on the starting address of the continuous access.

[0127] For scalar access, the data is sent to the split unit (SPLIT) 143 for splitting. Scalar access will only access one set of memory blocks, and the access address determines which set of memory blocks is being accessed.

[0128] After the processing of the various access sources of the above types is completed, the output is a normalized set of memory block access request signals. These memory block set request signals are sent to the PBP modules 145 in different memory block sets after passing through the cross-wrap 144.

[0129] It should be noted that, Figure 14 In the text, dg0, dg3, etc., represent different data groups (dg, datagroup) in the output.

[0130] Figure 16 This is a schematic diagram of the structure of the PBP module provided in the embodiments of this application, as shown below. Figure 16As shown, in the PBP module, the priority generation unit (time_pri_gen) 161 first generates time priority information. Then, the sorting unit 162 and the data selector 163 sort different requests according to the time priority information, obtain the request with the longest waiting time, and send the request to the subsequent module for data access. Here, each memory block corresponds to one PBP module.

[0131] Figure 17 This is a schematic diagram of the priority generation unit provided in an embodiment of this application, as shown below. Figure 17 The diagram illustrates four possible access sources. First, the counter register 171 is initialized to 7. When requests s1 and s2 arrive, the value of counter register 171 is assigned to s1 and s2, and counter register 171 is decremented by 2. Then, request s0 arrives, and the current value of counter register 171 (5) is assigned to s0. After s1 completes its request, requests with values ​​less than s1 are incremented by 1. This mechanism ensures that requests with larger values ​​among s0 to s3 have higher priority and should be processed first, as they have waited longer.

[0132] In this embodiment of the application, memory block conflicts between multiple request sources can be resolved through arbitration by the PBP module, and the software can send on-chip cache requests at will.

[0133] Figure 18 This is a schematic diagram illustrating the relationship between the memory block set and memory blocks provided in the embodiments of this application, such as... Figure 18 As shown in the embodiments of this application, each memory block set (BG, bank group) 181 contains several memory blocks, such as... Figure 18 The diagram shows memory blocks 0, 1, 2, and 3. For multiple access sources, if they access different sets of memory blocks, they can access them in parallel; if different access sources access the same set of memory blocks but different memory blocks, they can also access them in parallel. Thus, by using this configuration of multiple memory block sets and multiple memory blocks, along with memory block conflict arbitration, the parallelism of multiple access sources accessing the on-chip cache can be greatly increased, thereby significantly improving the overall performance of accessing the on-chip cache.

[0134] In some embodiments, after reading a memory block, for discrete vector access, the data needs to be shuffled to rearrange the read data. For continuous vector access, the data can be shifted using an element-wise shifting (ESFT) unit. For scalar access, the data is selected by a multiplexer unit.

[0135] The cache access apparatus and method provided in this application greatly increase the parallelism of multiple access sources and improve the performance of processor accessing on-chip cache by setting multiple memory block sets and multiple memory block modes; by setting IBP / PBP conflict handling modules, hardware detects memory block conflicts without software restrictions, greatly improving flexibility; and by processing through IBP, shuffle and other modules, discrete vector access function is realized without the need for multiple continuous vectors and splicing instructions for data integration, greatly improving the performance of discrete vector access.

[0136] It is understood that in the embodiments of this application, if the content involves user information, such as the set of memory blocks and the way the memory blocks are divided, the information stored in the memory blocks, etc., and if it involves data related to user information or enterprise information, when the embodiments of this application are applied to specific products or technologies, user permission or consent is required, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0137] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A cache access device for accessing data in a cache, characterized in that, The cache includes multiple sets of memory blocks, and each set of memory blocks includes multiple memory blocks; the device includes: The memory block allocation module is used to determine the target memory block set pointed to by each of the multiple requests to be accessed and the target memory block pointed to in the target memory block set, based on the request type and access address of each of the multiple requests to be accessed; wherein, each target memory block corresponds to a priority memory block conflict handling module. The priority memory block conflict handling module is used to generate priority information for each of the requests to be accessed; based on the priority information of each request to be accessed, determine the processing time of the target memory block corresponding to the request to be accessed, and when the processing time arrives, perform data access on the stored data in the target memory block to obtain multiple data access results. The data integration module is used to integrate the multiple data access results, obtain the data integration result, and output it.

2. The cache access device according to claim 1, characterized in that, The access request includes a discrete vector read request; the memory block allocation module includes an internal memory block conflict handling unit; the internal memory block conflict handling unit is used for: When there are multiple discrete vector read requests, the set identifier of the target memory block set pointed to by each discrete vector read request in the cache is determined according to the access address of each discrete vector read request; and, If at least two discrete vector read requests have the same set identifier for the target memory block set, then one discrete vector read request is selected from the at least two discrete vector read requests as the discrete vector read request that accesses the target memory block set at the current time; and the target memory block accessed by the selected discrete vector read request is determined from the target memory block set.

3. The cache access device according to claim 2, characterized in that, The internal memory block conflict handling unit is also used for: If at least two discrete vector read requests correspond to target memory block sets with the same set identifier, and discrete vector read requests accessing the target memory block set at the current time have been filtered out, After the selected discrete vector read requests complete cache access, for the other discrete vector read requests among the at least two discrete vector read requests besides the selected discrete vector read requests, continue to select discrete vector read requests that will access the target memory block set at the next moment.

4. The cache access device according to claim 2, characterized in that, The internal memory block conflict handling unit includes a chain-connected plurality of binary multiplexers; the chain-connected plurality of binary multiplexers are used for: When there are multiple discrete vector read requests, a chained selection is performed based on the access address of each discrete vector read request to determine the set identifier of the target memory block set pointed to by each discrete vector read request in the cache.

5. The cache access device according to claim 1, characterized in that, The access request includes a discrete vector write request; the memory block allocation module includes an internal memory block conflict handling unit; the internal memory block conflict handling unit is used for: When there are multiple discrete vector write requests, the set identifier of the target memory block set pointed to by each discrete vector write request in the cache is determined according to the access address of each discrete vector write request; and, If at least two discrete vector write requests have the same set identifier for the target memory block set, then one discrete vector write request is selected from the at least two discrete vector write requests as the discrete vector write request that accesses the target memory block set at the current time; and the target memory block accessed by the selected discrete vector write request is determined from the target memory block set.

6. The cache access device according to claim 1, characterized in that, The access request includes a continuous vector access request; the memory block allocation module includes an element shifting unit; the element shifting unit is used for: Determine the starting address accessed by the consecutive vector access request, and based on the starting address, determine the set identifier of at least one set of target memory blocks consecutively accessed by the consecutive vector access request; and, The target memory block accessed by the continuous vector access request is determined from at least one set of target memory blocks corresponding to the set identifier.

7. The cache access device according to claim 1, characterized in that, The access request includes a scalar access request; the memory block allocation module includes a splitting unit; the splitting unit is used for: Determine the access address corresponding to the scalar access request, and determine the set identifier of the target memory block set based on the access address; and, The target memory block accessed by the scalar access request is determined from the set of target memory blocks corresponding to the set identifier.

8. The cache access device according to claim 1, characterized in that, The device further includes: The signal crossover module is used to crossover multiple access requests after the memory block allocation module allocates the target memory block, so as to integrate at least one access request corresponding to the same target memory block set into a signal set, and input the access requests in the same signal set into the priority memory block conflict handling module of the corresponding target memory block.

9. The cache access device according to claim 1, characterized in that, The priority memory block conflict handling module includes a priority generation unit, a sorting unit, and a data selector. The priority generation unit is used to generate priority information for each of the requests to be accessed; The sorting unit is used to sort the plurality of requests to be accessed based on the priority information to form a sequence of requests to be accessed. The data selector is used to select the request to be accessed from the sequence of requests to be accessed that is being processed at the current time, and send the selected request to be accessed to the data access module to access the stored data in the target memory block and obtain the data access result.

10. The cache access device according to claim 9, characterized in that, The priority generation unit includes: a register corresponding to each access request, an initialization subunit, and an assignment subunit; The initialization subunit is used to initialize the count value in each of the registers using a pre-designed value; The assignment subunit is used to assign a value to the count value in the register corresponding to the access request when an access request is received, and... When any pending access request completes the access, the register whose count value is less than the count value in the register corresponding to the pending access request is determined as the target register, and the count value in the target register is incremented by one; The priority information of the access request is determined based on the count value in the corresponding register.

11. The cache access device according to any one of claims 1 to 10, characterized in that, The access request includes a discrete vector read request; the data integration module includes a rearrangement unit. The rearrangement unit is used to rearrange the discrete vector read data in the plurality of data access results according to the access address of each of the access requests to obtain rearranged data; the rearranged data constitutes the data integration result.

12. The cache access device according to any one of claims 1 to 10, characterized in that, The access request includes a continuous vector read request; the data integration module includes an element shifting unit; The element shifting unit is used to perform element shifting processing on the continuous vector read data in the multiple data access results based on the starting address accessed by the continuous vector read request, to obtain element shifted data; the element shifted data constitutes the data integration result.

13. The cache access device according to any one of claims 1 to 10, characterized in that, The request to be accessed includes a scalar read request; the data integration module includes a multiplexer unit. The multiplexer unit is used to select scalar read data from multiple data access results to obtain read selected data; the read selected data constitutes the data integration result.

14. A cache access method, applied to the cache access apparatus of any one of claims 1 to 13, for accessing data in a cache, characterized in that, The method includes: Receive multiple pending access requests; Based on the request type and access address of each request to be accessed, determine the set of target memory blocks that the request to be accessed points to in the cache and the target memory block that the set of target memory blocks points to. Generate priority information for each of the aforementioned requests to be accessed; Based on the priority information of each request to be accessed, the processing timing of the target memory block corresponding to the request to be accessed is determined, and when the processing timing arrives, the stored data in the target memory block is accessed to obtain multiple data access results. The multiple data access results are integrated to obtain the integrated data result, which is then output.

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