Display device and driving circuit structure

Abstract

A display device and a driving circuit structure. The display device has a display area and a peripheral area surrounding the display area. The display device includes a driving circuit substrate, a thin film transistor array substrate, a front panel stack, and a plurality of conductive lines. The driving circuit substrate includes a first conductive pad. The thin film transistor array substrate includes a second conductive pad. The thin film transistor array substrate is disposed on the driving circuit substrate. The thin film transistor array substrate is disposed between the driving circuit substrate and the front panel stack. The conductive lines electrically connect the first and second conductive pads distributed in the peripheral area. The present disclosure evenly distributes the first and second conductive pads in the peripheral area by stacking the thin film transistor array substrate and the driving circuit substrate, thereby avoiding the need to provide a bonding area that protrudes significantly from the peripheral area. Such a design allows the profile of the display panel to be unaffected by the protruding bonding area. In addition, selecting different second conductive pads to which the signal lines are electrically connected according to the extension direction of the signal lines can reduce the length of the lines and reduce the probability of line crossing.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a display device and a driving circuit structure. BACKGROUND

[0002] In a display panel, signal lines (e.g., data lines and selection lines) are concentrated to the same side of the panel, i.e., to the bonding area of the peripheral area, and then electrically connected to the driving integrated circuit (IC) on the flexible substrate by a chip on film (COF) method. The design of the bonding driving integrated circuit and the signal lines will have a bonding area protruding from the peripheral area, which will limit the outline of the display device to the design of the protruding bonding area.

[0003] Therefore, how to provide a display device to solve the above problems is still the goal of the field. SUMMARY

[0004] A technical aspect of the present disclosure is a display device.

[0005] In an embodiment of the present disclosure, a display device has a display area and a peripheral area surrounding the display area. The display device includes a driving circuit substrate, a thin film transistor array substrate, a front panel stack, and a plurality of conductive lines. The driving circuit substrate includes a plurality of first conductive pads. The thin film transistor array substrate includes a plurality of second conductive pads. The thin film transistor array substrate is located on the driving circuit substrate. The thin film transistor array substrate is located between the driving circuit substrate and the front panel stack. The plurality of conductive lines are electrically connected to the first conductive pads and the second conductive pads, respectively, wherein the first conductive pads and the second conductive pads are distributed in the peripheral area.

[0006] In an embodiment of the present disclosure, the vertical projection of the thin film transistor array substrate on the driving circuit substrate does not overlap the first conductive pads.

[0007] In an embodiment of the present disclosure, the area of the driving circuit substrate is greater than the area of the thin film transistor array substrate.

[0008] In an embodiment of the present disclosure, the first conductive pads surround the thin film transistor array substrate.

[0009] In an embodiment of the present disclosure, the first conductive pads are located on the surface of the driving circuit substrate facing the thin film transistor array substrate.

[0010] In an embodiment of the present disclosure, the second conductive pads surround the front panel stack.

[0011] In an embodiment of the present disclosure, the driving circuit substrate, the thin film transistor array substrate, and the front panel stack are circular arc-shaped.

[0012] In an embodiment of the present disclosure, the thin film transistor array substrate further includes a plurality of data lines extending in the first direction, the data lines are electrically connected to a portion of the second conductive pads, and the portion of the second conductive pads are located at opposite sides of the display device in the first direction.

[0013] In an embodiment of the present disclosure, the thin film transistor array substrate further includes a plurality of scan lines extending in the second direction, the scan lines are electrically connected to a portion of the second conductive pads, and the portion of the second conductive pads are located at opposite sides of the display device in the second direction.

[0014] In an embodiment of the present disclosure, the thin film transistor array substrate further includes a plurality of select lines extending in the second direction, the select lines are electrically connected to a portion of the second conductive pads, and the portion of the second conductive pads are located at opposite sides of the display device in the second direction.

[0015] In an embodiment of the present disclosure, the driving circuit substrate further includes a first pattern, and the thin film transistor array substrate further includes a second pattern matched with the first pattern.

[0016] Another technical aspect of the present disclosure is a display device.

[0017] In an embodiment of the present disclosure, the display device has a display area and a peripheral area surrounding the display area. The display device includes a driving circuit substrate, a thin film transistor array substrate, a front panel stack, and a plurality of conductive lines. The driving circuit substrate includes a plurality of first conductive pads and a driver connection area, wherein the driver connection area is located at a side edge of the driving circuit substrate. The thin film transistor array substrate includes a plurality of second conductive pads, wherein the thin film transistor array substrate is located on the driving circuit substrate. The thin film transistor array substrate is located between the driving circuit substrate and the front panel stack. The conductive lines are electrically connected to the first conductive pads and the second conductive pads, respectively. From a top view, the side edge of the driving circuit substrate is located within an edge formed by the driving circuit substrate and the thin film transistor array substrate.

[0018] In an embodiment of the present disclosure, the driving circuit substrate further includes a plurality of first driving lines, opposite ends of each first driving line are electrically connected to one of the first conductive pads and the driver connection area, respectively.

[0019] In an embodiment of the present disclosure, the driving circuit substrate further includes a plurality of second driving lines, opposite ends of each second driving line are electrically connected to one of the first conductive pads and the driver connection area, respectively.

[0020] In an embodiment of the present disclosure, the driving circuit substrate further includes a plurality of third driving lines, opposite ends of each third driving line are electrically connected to one of the first conductive pads and the driver connection area, respectively.

[0021] In an embodiment of the present disclosure, the driving circuit substrate further includes a plurality of common voltage lines, and each of the common voltage lines is electrically connected to the driver connection region and at least one of the first conductive pads.

[0022] In an embodiment of the present disclosure, one of the first conductive pads is electrically connected to more than one of the common voltage lines.

[0023] In an embodiment of the present disclosure, the first conductive pads and the second conductive pads are distributed in the peripheral region.

[0024] In an embodiment of the present disclosure, the driving circuit substrate, the thin film transistor array substrate, and the front panel are stacked together to form an edge in a circular arc shape.

[0025] Another technical aspect of the present disclosure is a driving circuit structure.

[0026] In an embodiment of the present disclosure, the driving circuit structure includes a driving circuit substrate and a thin film transistor array substrate. The driving circuit substrate includes a driver connection region, and the driver connection region is located at a side edge of the driving circuit substrate. The thin film transistor array substrate is located on the driving circuit substrate, and from a top view of the driving circuit structure, the side edge of the driving circuit substrate is located within an edge formed by the driving circuit substrate and the thin film transistor array substrate.

[0027] In the above embodiment, the display device of the present disclosure can avoid the use of the bonding region that protrudes from the peripheral region by stacking the thin film transistor array substrate and the driving circuit substrate and distributing the first conductive pads and the second conductive pads evenly in the peripheral region (i.e., the first bonding region and the second bonding region surround the display region). In this embodiment, the design can prevent the display panel from being affected by the protruding bonding region. In addition, the selection of the extension direction of the signal line to electrically connect the signal line to different second conductive pads can reduce the length of the wire and the probability of wire crossing. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 FIG. 1 is a top view of a display device according to an embodiment of the present disclosure;

[0029] Figure 2 FIG. 3 is a cross-sectional view along the line 2-2 of FIG. 1; Figure 1

[0030] Figure 3 FIG. 6 is an enlarged view of the frame selected region A of FIG. 5; Figure 1

[0031] Figure 4 FIG. 8 is a schematic view of the bonding region of the display device of FIG. 7; Figure 1

[0032] Figure 5 ​​​FIG. 1 is a schematic diagram of a portion of signal lines of a thin film transistor array substrate according to an embodiment of the present disclosure;

[0033] Figure 6 FIG. 2 is a schematic diagram of another portion of signal lines of the thin film transistor array substrate of FIG. 1; Figure 5

[0034] Figure 7 FIG. 3 is a schematic diagram of another portion of signal lines of the thin film transistor array substrate of FIG. 1; Figure 5

[0035] Figure 8 FIG. 4 is a schematic diagram of a portion of signal lines of a drive circuit substrate according to an embodiment of the present disclosure;

[0036] Figure 9 FIG. 5 is a schematic diagram of another portion of signal lines of the drive circuit substrate of FIG. 4; Figure 8

[0037] Figure 10 FIG. 6 is a schematic diagram of another portion of signal lines of the drive circuit substrate of FIG. 4; Figure 8

[0038] Figure 11 FIG. 7 is a schematic diagram of another portion of signal lines of the drive circuit substrate of FIG. 4; Figure 8

[0039] Figure 12A FIG. 8 is a schematic diagram of an alignment mark according to an embodiment of the present disclosure;

[0040] Figure 12B FIG. 9 is a schematic diagram of an alignment mark according to another embodiment of the present disclosure;

[0041] Figures 13A to 13C FIG. 10 is a schematic diagram of an alignment mark according to another embodiment of the present disclosure.

[0042]

Symbol Explanation

[0043] 100: display device

[0044] 1002: edge

[0045] 110: drive circuit substrate

[0046] 1102: driver connection area

[0047] 1104: side

[0048] 112: first conductive pad

[0049] 112’: dummy first conductive pad

[0050] 114: surface

[0051] ​​​​​116: first bonding region

[0052] 118A: first drive line

[0053] 118B: second drive line

[0054] 118C: third drive line

[0055] 118D: common voltage line

[0056] 120: thin film transistor array substrate

[0057] 122: second conductive pad

[0058] 122': dummy second conductive pad

[0059] 124: surface

[0060] 126: second bonding region

[0061] 128A: data line

[0062] 128B: scan line

[0063] 128C: select line

[0064] 130: front panel structure

[0065] 140: conductive line

[0066] 150, 150a: alignment mark

[0067] 152, 152a: first pattern

[0068] 154, 154a: second pattern

[0069] AA: display region

[0070] PA: peripheral region

[0071] 2-2: line segment

[0072] A: frame region

[0073] C: central region

[0074] D1: first direction

[0075] D2: second direction

[0076] B1, B9, B12, B13, B24: block

[0077] S1-S10: region DETAILED DESCRIPTION

[0078] Embodiments of the present disclosure will be described below with reference to the accompanying drawings. For the purpose of explanation, numerous specific details will be set forth in the description below. It should be appreciated that these specific details are not intended to limit the present disclosure in any manner. Rather, the present disclosure is to cover all modifications, alternatives, and equivalents falling within the scope of the claims. Further, for the purpose of simplicity and clarity, some of the conventional and well-known structures and devices are not described in detail or are illustrated using simple block diagrams. Also, the thicknesses of layers and regions in the drawings can be exaggerated, and like reference numerals can be used to denote like elements throughout the specification.

[0079] Figure 1 A top view of a display device 100 according to an embodiment of the present disclosure. Figure 2 A cross-sectional view taken along line 2-2 of Figure 1 Figure 1 Figure 2 The display device 100 has a display area AA and a peripheral area PA surrounding the display area AA. The display device 100 includes a drive circuit substrate 110, a thin film transistor (TFT) array substrate 120, and a front panel laminate (FPL) 130. The thin film transistor array substrate 120 is located on the drive circuit substrate 110, and the front panel laminate 130 is located on the thin film transistor array substrate 120. The thin film transistor array substrate 120 is located between the drive circuit substrate 110 and the front panel laminate 130.

[0080] For example, the display device 100 is a watch, and the drive circuit substrate 110 integrates an integrated circuit driver (IC Driver) and system components applied to the watch, such as a motor, a battery, and the like. The thin film transistor array substrate 120 includes a glass substrate, and structures (not shown) such as a gate, a drain / source, an insulating layer, and a pixel electrode formed on the glass substrate. The front panel laminate 130 includes, for example, a display medium layer, a transparent conductive film, or an adhesive layer (not shown), but the present disclosure is not limited thereto. For example, the display medium layer can be a liquid crystal display layer or an electronic ink layer.

[0081] Figure 1 Figure 2 The outline of the combination of the drive circuit substrate 110 and the thin film transistor array substrate 120 after the stacking is substantially circular. In Figure 1 ​​​​The driving circuit substrate 110 and the thin film transistor array substrate 120 jointly form an edge 1002 in the top view. The driving circuit substrate 110, the thin film transistor array substrate 120 and the front panel stack 130 are all circular arc-shaped, but the present disclosure is not limited thereto. In other embodiments, the display device 100 can be rectangular. The area of the driving circuit substrate 110 is greater than the area of the thin film transistor array substrate 120, and the area of the thin film transistor array substrate 120 is greater than the area of the front panel stack 130.

[0082] Figure 3 To Figure 1 , the enlarged view of the area A of the middle frame. Please refer to Figure 2 and Figure 3 . The driving circuit substrate 110 includes a plurality of first conductive pads 112, and the thin film transistor array substrate 120 includes a plurality of second conductive pads 122. The first conductive pads 112 and the second conductive pads 122 are evenly distributed in the peripheral area PA. In other words, the first conductive pads 112 and the second conductive pads 122 surround the display area AA. The conductive wires 140 are respectively electrically connected to the first conductive pads 112 and the second conductive pads 122. The connection mode of the conductive wires 140 is not limited to Figure 2 . In another embodiment of the present disclosure, a conductive via is formed in the thin film transistor array substrate 120 at a position corresponding to the second conductive pad 122, and a conductive wire 140 is formed in the conductive via to be connected to the first conductive pad 112, so as to electrically connect the first conductive pad 112 and the second conductive pad 122.

[0083] Please refer to Figure 3 . The display device 100 further includes a plurality of conductive wires 140. For the sake of clarity, the conductive wires 140 are omitted in Figure 1 . The conductive wires 140 are respectively electrically connected to the first conductive pads 112 and the second conductive pads 122. The signal lines in the thin film transistor array substrate 120 are connected to the second conductive pads 122, and a part of the second conductive pads 122 can be selectively not connected to the signal lines. In other words, a part of the first conductive pads 112 are dummy first conductive pads 112', and a part of the second conductive pads 122 are dummy second conductive pads 122'. The dummy first conductive pads 112' and the dummy second conductive pads 122' are not configured for signal transmission. Through such a design, the distances between the first conductive pads 112 and the dummy first conductive pads 112' are more uniform, and the distances between the second conductive pads 122 and the dummy second conductive pads 122' are more uniform.

[0084] Please refer to Figure 2 and Figure 3The vertical projection of the thin-film transistor array substrate 120 onto the driving circuit substrate 110 does not overlap with the first conductive pad 112. In other words, the first conductive pad 112 surrounds the thin-film transistor array substrate 120. The vertical projection of the front panel stack 130 onto the thin-film transistor array substrate 120 does not overlap with the second conductive pad 122, that is, the second conductive pad 122 surrounds the front panel stack 130. The first conductive pad 112 is located on the surface 114 of the driving circuit substrate 110 facing the thin-film transistor array substrate, and the second conductive pad 122 is located on the surface 124 of the thin-film transistor array substrate 120 facing the front panel stack 130.

[0085] The display device 100 disclosed herein avoids the presence of a bonding area that protrudes significantly from the peripheral region PA by stacking a thin-film transistor array substrate 120 and a driving circuit substrate 110, and by evenly distributing the first conductive pad 112 and the second conductive pad 122 in the peripheral region PA. Figure 1 For example, in the embodiment, such a design allows the shape of the thin-film transistor array substrate 120 to be closer to a circle, so that the outline of the display device 100 is not affected by the protruding bonding area.

[0086] Figure 4 for Figure 1 A schematic diagram of the bonding area of ​​the display device 100. For clarity, the conductive line 140 is... Figure 4 The text is omitted. See also: Figure 1 and Figure 4 The driving circuit substrate 110 includes a first bonding region 116, and first conductive pads 112 are evenly distributed in the first bonding region 116. The thin-film transistor array substrate 120 includes a second bonding region 126, and second conductive pads 122 are evenly distributed in the second bonding region 126. In other words, the design of the first conductive pads 112 and the second conductive pads 122 being evenly distributed in the peripheral region PA can also be regarded as setting the first bonding region 116 and the second bonding region 126 in the peripheral region PA of the display device 100, and making the first bonding region 116 and the second bonding region 126 surround the display region AA. Figure 4 The outline of the thin-film transistor array substrate 120 in the figure is only another embodiment of the present invention, and the present invention is not limited thereto.

[0087] like Figure 4As shown, the vertical projection of the second bonding area 126 on the driving circuit substrate 110 is located between the first bonding area 116 and the display area AA. The vertical projection of the front panel stack 130 on the thin film transistor array substrate 120 is surrounded by the second bonding area 126. In other words, the vertical projection of the front panel stack 130 on the thin film transistor array substrate 120 is located within the range surrounded by the second bonding area 126. In the present embodiment, the first bonding area 116 and the second bonding area 126 are annular. In other embodiments, the shapes of the first bonding area 116 and the second bonding area 126 are determined according to the overall profile of the display device 100.

[0088] According to the above, the display device 100 of the present disclosure can avoid setting a bonding area that protrudes obviously from the peripheral area PA by stacking the thin film transistor array substrate 120 and the driving circuit substrate 110, so that the first bonding area 116 and the second bonding area 126 surround the display area AA. Such a design can make the profile of the display device 100 not affected by the protruding bonding area.

[0089] Figure 5 A schematic diagram of a part of the signal lines of the thin film transistor array substrate 120 according to an embodiment of the present disclosure is shown. The signal lines of the thin film transistor array substrate 120 include a plurality of data lines 128A extending in the first direction D1. In the present embodiment, the thin film transistor array substrate 120 has 240 data lines 128A, and the plurality of data lines 128A extend to a part of the corresponding second conductive pads 122 in the four regions S1-S4. Figure 5 Only a part of the data lines 128A and the four corresponding second conductive pads 122 in the regions S1-S4 are shown by way of example. The regions S1-S4 are located on the opposite sides of the second bonding area 126 in the first direction D1. In other words, the distribution positions of the regions S1-S4 in the second bonding area 126 are determined according to the extension direction of the data lines 128A. In this way, the length of the data lines 128A electrically connected to the second conductive pads 122 can be reduced, and the bonding area that protrudes obviously from the peripheral area PA can be avoided by concentrating all the signal lines in the same place.

[0090] Figure 6 A schematic diagram of another part of the signal lines of the thin film transistor array substrate 120 is shown. Figure 5 In the present embodiment, the thin film transistor array substrate 120 is divided into 24 blocks. Figure 6 Only the blocks B1, B9, B12, B13, and B24 are shown by way of example. Each block includes 20 scan lines 128B extending in the second direction D2. Figure 6The diagram only shows a portion of the scan lines 128B in block B9; scan lines 128B in other blocks are omitted. The scan lines 128B in each block are electrically connected to each other and then collectively electrically connected to a portion of the second conductive pads 122 in the four regions S5 to S8. (See diagram for reference.) Figure 6 As shown, regions S5 and S6 each contain 10 second conductive pads 122, and regions S7 and S8 each contain 2 second conductive pads 122. Regions S5 to S8 are located on opposite sides of the second bonding area 126 in the second direction D2. In this way, the trace length of the scan line 128B electrically connected to the second conductive pads 122 can be reduced, and the bonding area that would protrude significantly from the surrounding region PA can be avoided by concentrating all signal lines in the same place.

[0091] Figure 7 for Figure 5 This is a schematic diagram of another portion of the signal lines of the thin-film transistor array substrate 120. The thin-film transistor array substrate 120 includes multiple select lines 128C extending in the second direction D2. In this embodiment, each select line 128C is electrically connected to the aforementioned 24 blocks. The multiple select lines 128C extend to a portion of a second conductive pad 122 in two different regions S9 to S10. Figure 7 The diagram only illustrates two select lines 128C and two second conductive pads 122 located in regions S9 to S10. Regions S9 to S10 are the opposite sides of the second junction area 126 in the second direction D2. In this way, the trace length of the select line 128C electrically connecting to the second conductive pad 122 can be reduced, and the junction area that would be obviously protruding from the surrounding area PA can be avoided by concentrating all signal lines in one place.

[0092] Simultaneously refer to Figures 5 to 7 As can be seen, the aforementioned regions S1 to S10 are distributed in the peripheral area PA of the display device 100, and regions S1 to S10 are staggered. This allows the signal lines of the display device 100 to be distributedly connected to the second conductive pads 122 evenly distributed in the peripheral area PA. Furthermore, by selecting different second conductive pads 122 to electrically connect the signal lines according to their extension direction, the trace length and the probability of trace crossing can be reduced. In the above embodiment, the relative positions of regions S1 to S10 can be varied, as long as the technical effect of reducing trace length and reducing trace crossing is achieved.

[0093] Figure 8 This is a schematic diagram of a portion of the signal lines of a drive circuit board 110 according to an embodiment of the present disclosure. The drive circuit board 110 has a driver connection area 1102, and the driver connection area 1102 is located on a side edge 1104 of the drive circuit board 110. In this embodiment, the side edge 1104 is flush. In other words, inFigure 8 From a top-down view, the side 1104 of the driving circuit substrate 110 is located within the edge 1002 formed by the driving circuit substrate 110 and the thin-film transistor array substrate 120. That is, the projection of the side 1104 onto the thin-film transistor array substrate 120 is located inside the projection of the edge 1002 onto the thin-film transistor array substrate 120. This design allows the shape of the thin-film transistor array substrate 120 to be closer to a circle, thus ensuring that the outline of the display device 100 is not affected by the protruding bonding area. The driving integrated circuit of the driving circuit substrate 110 can be disposed within the driver connection area 1102, or it can be electrically connected to the driving integrated circuit disposed on the flexible substrate via flip-chip bonding.

[0094] The signal lines of the drive circuit board 110 include multiple first drive lines 118A. Figure 8 Four first drive lines 118A are illustrated only as an example. The opposite ends of the first drive lines 118A are electrically connected to the driver connection area 1102 and a portion of the first conductive pad 112, respectively. In this embodiment, the first drive lines 118A of the drive circuit board 110 are connected to... Figure 5 This corresponds to the data line 128A of the thin-film transistor array substrate 120 shown. In other words, Figure 8 The four first drive lines 118A are electrically connected to the second conductive pad 122 and the data line 128A located in regions S1 to S4 via the first conductive pad 112.

[0095] For another embodiment of the driving circuit structure of the present invention, please refer to... Figure 8 and Figure 1 As shown, the driving circuit structure is composed of a driving circuit substrate 110 and a thin film transistor array substrate 120. The driving circuit substrate 110 includes a driver connection area 1102, and the driver connection area 1102 is located on the side 1104 of the driving circuit substrate 110. The thin film transistor array substrate 120 is located on the driving circuit substrate 110. From a top view of the driving circuit structure, the side 1104 of the driving circuit substrate 110 is located within an edge 1002 jointly formed by the driving circuit substrate 110 and the thin film transistor array substrate 120.

[0096] Figure 9 for Figure 8 A schematic diagram of another portion of the signal lines on the drive circuit board 110. The signal lines on the drive circuit board 110 include multiple second drive lines 118B. Figure 9 Two second drive lines 118B are illustrated only as examples. The opposite ends of the second drive lines 118B are electrically connected to the driver connection area 1102 and a portion of the first conductive pad 112, respectively. In this embodiment, the second drive lines 118B of the drive circuit board 110 are connected to...Figure 6 This corresponds to scan line 128B of the thin-film transistor array substrate 120 shown. Figure 9 The two second drive lines 118B are electrically connected to the second conductive pad 122 and the scan line 128B located in regions S5 to S6 via the first conductive pad 112.

[0097] Figure 10 for Figure 8 A schematic diagram of another portion of the signal lines on the drive circuit board 110. The signal lines on the drive circuit board 110 include multiple third drive lines 118C. Figure 10 Two third drive lines 118C are illustrated only as examples. The opposite ends of the third drive lines 118C are electrically connected to the driver connection area 1102 and a portion of the first conductive pad 112, respectively. In this embodiment, the third drive lines 118C of the drive circuit board 110 are connected to... Figure 7 The selection line 128C corresponds to the thin-film transistor array substrate 120 shown. Figure 10 The two third drive lines 118C are electrically connected to the second conductive pad 122 and the selection line 128C located in regions S9 to S10 via the first conductive pad 112.

[0098] Figure 11 for Figure 8 This is a schematic diagram of another portion of the signal lines on the drive circuit board 110. The signal lines of the drive circuit board 110 include multiple common voltage lines 118D. The opposite ends of the common voltage lines 118D are electrically connected to the driver connection area 1102 and a portion of the first conductive pads 112, respectively. In this embodiment, each common voltage line 118D is electrically connected to at least one first conductive pad 112. The first conductive pad 112 may be electrically connected to more than one of the common voltage lines 118D. In other words, the electrical connection between the first conductive pad 112 and the common voltage line 118D is not limited to a one-to-one connection. For example, such as... Figures 8 to 11 As shown, loop lines with different voltage values ​​can extend and connect to the same first conductive pad 112.

[0099] Simultaneously refer to Figures 5 to 7 It can be seen that the first drive line 118A, the second drive line 118B, and the third drive line 118C correspond to the aforementioned Figure 12A The multiple regions S1 to S10 are distributed in the peripheral area PA of the display device 100, and the regions S1 to S10 are staggered from each other. In this way, the signal lines of the display device 100 can be distributed to the first conductive pad 112 and the second conductive pad 122, which are evenly distributed in the peripheral area PA. Figure 1 This is a schematic diagram of an alignment mark 150 according to an embodiment of the present disclosure. See also... Figure 12A and Figure 12BThe display device 100 includes a central region C, and the alignment mark 150 is disposed in the central region C. The alignment mark 150 is composed of a first pattern 152 and a second pattern 154, and the second pattern 154 is configured to pair with the first pattern 152. The first pattern 152 and the second pattern 154 can be formed on the driving circuit substrate 110 and the thin film transistor array substrate 120, respectively, at positions corresponding to the central region C. When the driving circuit substrate 110 and the thin film transistor array substrate 120 are stacked, alignment can be performed by means of the alignment mark 150. The first pattern 152 is a rectangular frame and the second pattern 154 is a cross in the above embodiment, but the present disclosure is not limited thereto.

[0100] Figure 1 A schematic view of the alignment mark 150 according to another embodiment of the present disclosure is shown. In this embodiment, the alignment mark 150 can also be disposed near the first conductive pads 112 and the second conductive pads 122, such as the boxed region A in Figures 13A to 13C In other embodiments, the display device 100 includes a plurality of alignment marks 150 to achieve alignment in the first direction D1 and the second direction D2. In other embodiments, the alignment mark can be composed of two sets of ruler marks, and the ruler marks can be arranged along the first direction D1 or the second direction D2 to achieve alignment in the first direction D1 and the second direction D2.

[0101] Figures 13A to 13C A schematic view of the alignment mark 150a according to another embodiment of the present disclosure is shown. The alignment mark 150a includes a first pattern 152a and a second pattern 154a. The first pattern 152a and the second pattern 154a are formed on the driving circuit substrate 110 and the thin film transistor array substrate 120, respectively. In this embodiment, the first pattern 152a and the first conductive pads 112 are arranged together in a ring shape, and the second pattern 154a and the second conductive pads 122 are arranged together in a ring shape. In other words, the first pattern 152a can be disposed in the first bonding area 116, and the second pattern 154a can be disposed in the second bonding area 126.

[0102] Figure 1 The alignment marks 150a in ​ correspond to the upper right, right, and lower right of the display device 100 (see ), respectively. Similarly, the alignment marks 150a can also be disposed in the upper left, left, and lower left of the display device 100. In other words, the display device 100 can include a plurality of first patterns 152a evenly distributed in the first bonding area 116 and a plurality of second patterns 154a evenly distributed in the second bonding area 126 to achieve alignment in the first direction D1 and the second direction D2.

[0103] In summary, the display device of the present disclosure can avoid the setting of the bonding area which protrudes obviously from the peripheral area by stacking the thin film transistor array substrate and the driving circuit substrate and evenly distributing the first conductive pads and the second conductive pads in the peripheral area (equivalent to making the first bonding area and the second bonding area surround the display area). Such a design can make the profile of the display panel not affected by the protruding bonding area. In addition, the signal lines can be electrically connected to different second conductive pads according to the extension direction of the signal lines, which can reduce the length of the wires and reduce the probability of wire crossing.

[0104] Although the present application has been disclosed with the implementation as above, it is not intended to limit the present application, and any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present application, and therefore the protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A display device comprising a display area and a peripheral area surrounding the display area, characterized in that, The display device includes: A driving circuit substrate, comprising multiple first conductive pads; A thin-film transistor array substrate includes a plurality of second conductive pads and a plurality of data lines extending in a first direction, wherein the thin-film transistor array substrate is located on a driving circuit substrate, the data lines are electrically connected to a portion of the second conductive pads, and the portion of the second conductive pads is located on opposite sides of the display device in the first direction. A front panel stack, wherein the thin-film transistor array substrate is located between the driving circuit substrate and the front panel stack; and Multiple conductive lines electrically connect the first conductive pads and the second conductive pads, wherein the first conductive pads and the second conductive pads are distributed in the peripheral area.

2. The display device as claimed in claim 1, characterized in that, The vertical projection of the thin-film transistor array substrate onto the driving circuit substrate does not overlap with the first conductive pads.

3. The display device as claimed in claim 1, characterized in that, The area of ​​the driving circuit substrate is larger than the area of ​​the thin-film transistor array substrate.

4. The display device as claimed in claim 1, characterized in that, The first conductive pads are evenly distributed around the thin-film transistor array substrate.

5. The display device as claimed in claim 1, characterized in that, The first conductive pads are located on the surface of the driving circuit substrate facing the thin-film transistor array substrate.

6. The display device as claimed in claim 1, characterized in that, The second conductive pads are stacked evenly around the front panel.

7. The display device as claimed in claim 1, characterized in that, The driving circuit substrate, the thin-film transistor array substrate, and the front panel are stacked in an arc shape.

8. The display device as claimed in claim 1, characterized in that, The thin-film transistor array substrate further includes a plurality of scan lines extending in a second direction, the scan lines being electrically connected to a portion of the second conductive pads, and the portion of the second conductive pads being located on opposite sides of the display device in the second direction.

9. The display device as claimed in claim 1, characterized in that, The thin-film transistor array substrate further includes a plurality of select lines extending in a second direction, the select lines being electrically connected to a portion of the second conductive pads, and the portion of the second conductive pads being located on opposite sides of the display device in the second direction.

10. The display device as claimed in claim 1, characterized in that, The driving circuit substrate further includes a first pattern, and the thin-film transistor array substrate further includes a second pattern that is paired with the first pattern.

11. A display device having a display area and a peripheral area surrounding the display area, characterized in that, The display device includes: A driving circuit board includes a plurality of first conductive pads, a plurality of first driving lines and a driver connection area, wherein the driver connection area is located on one side of the driving circuit board, and the opposite ends of each of the first driving lines are electrically connected to one of the first conductive pads and the driver connection area. A thin-film transistor array substrate includes a plurality of second conductive pads, wherein the thin-film transistor array substrate is located on the driving circuit substrate; A front panel stack, wherein the thin-film transistor array substrate is located between the driving circuit substrate and the front panel stack; as well as Multiple conductive lines are electrically connected to the first conductive pads and the second conductive pads, respectively; Viewed from a top angle, the side of the driving circuit substrate is located within an edge formed by the driving circuit substrate and the thin film transistor array substrate.

12. The display device as claimed in claim 11, characterized in that, The driving circuit board also includes multiple common voltage lines, and the two ends of each of the common voltage lines are electrically connected to the driver connection area and electrically connected to at least one of the first conductive pads.

13. The display device as claimed in claim 12, characterized in that, One of the first conductive pads is electrically connected to one of the plurality of common voltage lines.

14. The display device as claimed in claim 11, characterized in that, The edge formed by the driving circuit substrate, the thin film transistor array substrate, and the front panel stack is arc-shaped.

15. A driving circuit structure, characterized in that, Include: A driving circuit board includes a driver connection area, wherein the driver connection area is located on one side of the driving circuit board; and A thin-film transistor array substrate is located on the driving circuit substrate. The thin-film transistor array substrate also includes a plurality of second conductive pads and a plurality of scan lines extending in a second direction. The scan lines are electrically connected to a portion of the second conductive pads, and the portion of the second conductive pads is located on opposite sides of the display device in the second direction. Viewed from a top angle, the side of the driving circuit substrate is located within an edge formed by the driving circuit substrate and the thin-film transistor array substrate.

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