Pixel driving circuit and control method thereof, pixel driving assembly and display panel

Abstract

The application relates to the technical field of display, and discloses a pixel driving circuit and a control method thereof, a pixel driving assembly and a display panel. The pixel driving circuit comprises a data input module, a first input module, a second input module and a pixel electrode. The pixel electrode comprises a first capacitor and a second capacitor. The data input module is connected with the first input module and the second input module respectively. The first input module is connected with the first capacitor, the second input module is connected with the second capacitor, the first capacitor is connected with the second capacitor, and the connection end of the first capacitor and the second capacitor is connected with a common voltage end. Therefore, the application can solve the problem of uneven picture display caused by low charging rate due to insufficient pixel charging time at high refresh frequency.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a pixel driving circuit and its control method, a pixel driving component and a display panel. Background Technology

[0002] With the rapid development of the chip industry, smartphones have become increasingly popular, and mobile applications are emerging in an endless stream. As a result, mobile phone users have higher and higher requirements for their phones, and high refresh rate phones have been produced in response to market demand.

[0003] However, a higher refresh rate means a shorter line cycle in the display panel, which affects the input time of the data voltage. Insufficient input time of the data voltage will cause incomplete charging of the pixel circuit, thus affecting the display effect of the display panel.

[0004] In summary, in traditional technologies, insufficient pixel charging time at high refresh rates leads to a low charging rate, resulting in uneven image display.

[0005] Application content

[0006] The main purpose of this application is to propose a pixel driving circuit and its control method, a pixel driving component and a display panel, which aims to solve the problem that insufficient pixel charging time at high refresh rates leads to low charging rates and thus uneven screen display.

[0007] To achieve the above objectives, this application provides a pixel driving circuit, which includes: a data input module, a first input module, a second input module, and a pixel electrode, wherein the pixel electrode includes: a first capacitor and a second capacitor;

[0008] The data input module is connected to the first input module and the second input module respectively. The first input module is connected to the first capacitor, the second input module is connected to the second capacitor, the first capacitor is connected to the second capacitor, and the connection terminals of the first capacitor and the second capacitor are connected to a common voltage terminal.

[0009] Optionally, the data input module includes: a first data signal input terminal;

[0010] The first data signal input terminal is connected to the first input module and the second input module respectively.

[0011] Optionally, the pixel driving circuit further includes: a control signal terminal, the first input module including: a first transistor, a third capacitor and a fourth capacitor, and the second input module including: a second transistor, a fifth capacitor and a sixth capacitor;

[0012] The control signal terminal is connected to the control terminal of the first transistor, the first terminal of the third capacitor, and the first terminal of the fourth capacitor, respectively. The first terminal of the first transistor is connected to the second terminal of the third capacitor and the first data signal input terminal, respectively. The second terminal of the first transistor is connected to the second terminal of the fourth capacitor and the first capacitor, respectively.

[0013] The control signal terminal is connected to the control terminal of the second transistor, the first terminal of the fifth capacitor, and the first terminal of the sixth capacitor, respectively. The first terminal of the second transistor is connected to the second terminal of the fifth capacitor and the first data signal input terminal, respectively. The second terminal of the second transistor is connected to the second terminal of the sixth capacitor and the second capacitor, respectively.

[0014] Optionally, the data input module includes: a second data signal input terminal and a third data signal input terminal;

[0015] The second data signal input terminal is connected to the first input module, and the third data signal input terminal is connected to the second input module.

[0016] Optionally, the pixel driving circuit further includes: a control signal terminal, the first input module including: a first transistor, a third capacitor and a fourth capacitor, and the second input module including: a second transistor, a fifth capacitor and a sixth capacitor;

[0017] The control signal terminal is connected to the control terminal of the first transistor, the first terminal of the third capacitor, and the first terminal of the fourth capacitor, respectively. The first terminal of the first transistor is connected to the second terminal of the third capacitor and the second data signal input terminal, respectively. The second terminal of the first transistor is connected to the second terminal of the fourth capacitor and the first capacitor, respectively.

[0018] The control signal terminal is connected to the control terminal of the second transistor, the first terminal of the fifth capacitor, and the first terminal of the sixth capacitor, respectively. The first terminal of the second transistor is connected to the second terminal of the fifth capacitor and the third data signal input terminal, respectively. The second terminal of the second transistor is connected to the second terminal of the sixth capacitor and the second capacitor, respectively.

[0019] Furthermore, to achieve the above objectives, this application provides a control method for a pixel driving circuit, wherein the control method is applied to the pixel driving circuit described above, and the control method for the pixel driving circuit includes:

[0020] The data input module charges the first capacitor through the first input module, and the data input module charges the second capacitor.

[0021] The electrical energy of the first capacitor and the second capacitor is output together to the common voltage terminal.

[0022] Optionally, the data input module includes: a first data signal input terminal, the control method of the pixel driving circuit is applied to the pixel driving circuit as described in claim 1, and the step of charging the first capacitor through the data input module via the first input module and charging the second capacitor through the second input module includes:

[0023] Increase the voltage value at the first data signal input terminal;

[0024] The increased voltage value charges the first capacitor through the first input module and the second capacitor through the second input module.

[0025] Optionally, the data input module includes a second data signal input terminal and a third data signal input terminal. The step of charging the first capacitor through the data input module via the first input module and charging the second capacitor through the second input module includes:

[0026] The first capacitor is charged through the second data signal input terminal via the first input module, and the second capacitor is charged through the third data signal input terminal via the second input module.

[0027] In addition, to achieve the above objectives, this application provides a pixel driving component, which includes the pixel driving circuit described above.

[0028] In addition, to achieve the above objectives, this application provides a display panel, which includes the pixel driving components described above.

[0029] This application provides a pixel driving circuit, comprising: a data input module, a first input module, a second input module, and pixel electrodes. Each pixel electrode includes a first capacitor and a second capacitor. The data input module is connected to both the first and second input modules. The first input module is connected to the first capacitor, the second input module is connected to the second capacitor, and the first and second capacitors are connected together. The connection terminals of the first and second capacitors are connected to a common voltage terminal. This application solves the problem of uneven display on the display panel caused by insufficient charging time by simultaneously opening two paths through the first and second input modules to charge the first and second capacitors within the same charging time, thereby improving the display effect. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the frame structure of an embodiment of the pixel driving circuit of this application;

[0031] Figure 2 This is a schematic diagram of the framework of an embodiment of the data input module of the pixel driving circuit of this application;

[0032] Figure 3 This is a circuit structure diagram of one embodiment of the pixel driving circuit of this application;

[0033] Figure 4 This is a charging timing diagram of one embodiment of the pixel driving circuit of this application;

[0034] Figure 5 This is a schematic diagram of the framework of another embodiment of the data input module of the pixel driving circuit of this application;

[0035] Figure 6 This is a circuit structure diagram of another embodiment of the pixel driving circuit of this application;

[0036] Figure 7 This is a charging timing diagram of another embodiment of the pixel driving circuit of this application;

[0037] Figure 8 This is a circuit wiring diagram illustrating an application scenario of one embodiment of the pixel driving circuit of this application.

[0038] Figure 9 The circuit wiring diagram is for another application scenario of the pixel driving circuit of this application;

[0039] Figure 10 A timing diagram showing the data signal input comparison for each embodiment of the pixel driving circuit of this application;

[0040] Figure 11 This is a flowchart of an embodiment of the control method for the pixel driving circuit of this application.

[0041] Explanation of icon numbers:

[0042]

[0043] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0044] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0046] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0047] In this application, unless otherwise expressly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0048] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0049] This application provides a pixel driving circuit.

[0050] In one embodiment of this application, reference is made to Figure 1 , Figure 1 This is a schematic diagram of the framework structure of an embodiment of the pixel driving circuit of this application. The pixel driving circuit includes: a data input module 10, a first input module 20, a second input module 30, and a pixel electrode 40. The pixel electrode 40 includes: a first capacitor C1 and a second capacitor C2.

[0051] The data input module 10 is connected to the first input module 20 and the second input module 40 respectively. The first input module 20 is connected to the first capacitor C1, the second input module 40 is connected to the second capacitor C2, the first capacitor C1 is connected to the second capacitor C2, and the connection end of the first capacitor C1 and the second capacitor C2 is connected to the common voltage terminal Vcom.

[0052] In this embodiment, the pixel electrode 40 is a PXL ITO (Pixel Electrode), divided into two equal parts, namely PXL ITO1 and PXL ITO2. PXL ITO1 is the first capacitor C1, and PXL ITO2 is the second capacitor. The storage capacity Cst1 of the first capacitor C1 and the storage capacity Cst2 of the second capacitor C2 are the same, that is, the size and shape of the equally divided pixel units are consistent, and the storage capacity is also consistent, Cst1 = Cst2 = 1 / 2Cst, where Cst is the storage capacity of a pixel electrode in conventional technology or a conventional pixel electrode. It should be noted that the first capacitor C1 and the second capacitor C2 are polarized capacitors, with the horizontal bar of the capacitor being the positive terminal and the curved arc being the negative terminal.

[0053] Based on the traditional method of charging pixel units via a single voltage input path, a new input path is added, namely a first input module 20 and a second input module 30. The pixel electrode is divided into two pixel units with the same storage capacity, namely a first capacitor C1 and a second capacitor C2. The voltage signal input from the data input module 10 charges the first capacitor C1 and the second capacitor C2 through the first input module 20 and the second input module 30 respectively. The electrical energy stored in the first capacitor C1 and the second capacitor C2 is output through a common voltage terminal Vcom. Thus, within the same charging time, two paths are simultaneously activated, charging the first capacitor C1 and the second capacitor C2 through the first input module 20 and the second input module 30 respectively. This improves charging efficiency, solves the problem of uneven display on the display panel caused by insufficient charging time, and helps improve the display effect.

[0054] Optionally, in some feasible embodiments, reference is made to... Figure 2 , Figure 2 This is a schematic diagram of the framework of a data input module of the pixel driving circuit of this application. The data input module includes: a first data signal input terminal DATA1;

[0055] The first data signal input terminal DATA1 is connected to the first input module 20 and the second input module 30 respectively.

[0056] In this embodiment, the first data signal input terminal DATA1 charges the first capacitor C1 and the second capacitor C2 through the first input module 20 and the second input module 30 respectively. It should be noted that the first data signal input terminal DATA1 is a data line. Since the first capacitor C1 and the second capacitor C2 are powered by the first input module 20 and the second input module 30 simultaneously through a single data line, it is necessary to increase the voltage of the first data signal input terminal DATA1. The increased voltage of the first data signal input terminal DATA1 simultaneously powers the first capacitor C1 and the second capacitor C2 through the first input module 20 and the second input module 30 respectively. Thus, it is possible to simultaneously open two paths to charge the first capacitor C1 and the second capacitor C2 through the first input module 20 and the second input module 30 within the same charging time. This improves the charging efficiency, solves the problem of uneven display on the display panel caused by insufficient charging time, and helps to improve the display effect.

[0057] For example, in this embodiment, the voltage of the conventional first data signal input terminal DATA1 is 5V. In conventional technology, the pixel electrode is powered only through a 5V data line via one input path. In this application, the voltage of the first data signal input terminal DATA1 can be increased to 7V. The 7V input voltage is used to charge the first capacitor C1 and the second capacitor C2 through the first input module 20 and the second input module 30 respectively, thereby improving the charging efficiency, solving the problem of uneven display on the display panel caused by insufficient charging time, and improving the display effect.

[0058] Optionally, in some feasible embodiments, reference is made to Figure 3 , Figure 3 This is a circuit structure diagram of an embodiment of the pixel driving circuit of this application. The pixel driving circuit further includes: a control signal terminal GATE; the first input module 20 includes: a first transistor T1, a third capacitor C3 and a fourth capacitor C4; and the second input module 30 includes: a second transistor T2, a fifth capacitor C5 and a sixth capacitor C6.

[0059] The control signal terminal GATE is connected to the control terminal of the first transistor T1, the first terminal of the third capacitor C3, and the first terminal of the fourth capacitor C4, respectively. The first terminal of the first transistor T1 is connected to the second terminal of the third capacitor C3 and the first data signal input terminal DATA1, respectively. The second terminal of the first transistor T1 is connected to the second terminal of the fourth capacitor C4 and the first capacitor C1, respectively.

[0060] The control signal terminal GATE is connected to the control terminal of the second transistor T2, the first terminal of the fifth capacitor C5, and the first terminal of the sixth capacitor C6, respectively. The first terminal of the second transistor T2 is connected to the second terminal of the fifth capacitor C5 and the first data signal input terminal DATA1, respectively. The second terminal of the second transistor T2 is connected to the second terminal of the sixth capacitor C6 and the second capacitor C2, respectively.

[0061] It should be noted that the control terminal of the first transistor T1 is the gate, the first terminal of the first transistor T1 is the source, and the second terminal of the first transistor T1 is the drain. The control terminal of the second transistor T2 is the gate, the first terminal of the second transistor T2 is the source, and the second terminal of the second transistor T2 is the drain. The third capacitor C3 and the fifth capacitor C5 are the storage capacitors for the control signal terminal GATE and the first data signal input terminal DATA1, respectively. The fourth capacitor C4 and the sixth capacitor C6 are the storage capacitors for the SOURCE (source signal terminal). The SOURCE DRIVER provides drive signals to the sources of the first transistor T1 and the second transistor T2 through the SOURCE (source signal terminal). The GATE DRIVER provides drive signals to the gates of the first transistor T1 and the second transistor T2 through the control signal terminal GATE.

[0062] In this embodiment, the control signal terminal GATE controls the gates of the first transistor T1 and the second transistor T2 respectively, thereby controlling the conduction and shutdown of the second transistor T2 of the first transistor T1, so as to store the voltage signal input by the first data signal input terminal DATA1 into the first capacitor C1 and the second capacitor C2 respectively. Thus, the second transistor T2 of the first transistor T1 is turned on simultaneously within the same charging time, charging the first capacitor C1 and the second capacitor C2 respectively, thereby improving the charging efficiency, solving the problem of uneven display on the display panel caused by insufficient charging time, and improving the display effect.

[0063] refer to Figure 3 , Figure 3 The drains of the first transistor T1 and the second transistor T2 are connected and connected to the test terminal Cr. The test terminal Cr is used to test the input waveforms of DATA and GATE. (Refer to...) Figure 4 , Figure 4 This is a charging timing diagram of one embodiment of the pixel driving circuit of this application. Figure 4The dashed line represents the GATE signal waveform. VGH (Vgatehigh) refers to the high potential of the gate level, i.e., the voltage to turn on the gate level. VGL (Vgatelow) refers to the low potential of the gate level, i.e., the voltage to turn off the gate level. The solid line represents the DATA1 signal waveform. VDH is the high potential of the first data signal input terminal DATA1, and VDL is the low potential of the first data signal input terminal DATA1. The input voltage of the first data signal input terminal DATA1 is set to 7V. In this case, T1 in the figure is the pixel charging time. T1 is the pixel charging time between the rising edge and the falling edge of the first data signal input terminal DATA1. The rising edge is the instant when the signal changes from low level to high level, and the falling edge is the instant when the signal changes from high level to low level. The pixel charging time T1 is longer than the traditional pixel charging time during high refresh rates, thereby improving charging efficiency and solving the problem of uneven display on the display panel caused by insufficient charging time, which is beneficial to improving the display effect.

[0064] In practical applications, refer to Figure 8 , Figure 8 This is a circuit wiring diagram illustrating an application scenario of one embodiment of the pixel driving circuit of this application. Figure 8 In the diagram, C1 is the first capacitor, i.e., PXL ITO1, and C2 is the second capacitor, i.e., PXL ITO2. The electrical energy of C1 and C2 is output to Com ITO, which is the common voltage terminal Vcom. The first transistor T1 and the second transistor T2 are soldered onto the substrate. The first data signal input terminal DATA1 is connected to the first transistor T1 and the second transistor T2 respectively. The first transistor T1 is controlled to charge the first capacitor C1 and the second transistor T2 is controlled to charge the second capacitor C2 through the control signal terminal GATE.

[0065] In addition, the pixel driving circuit also includes a control module, which includes a main controller connected to the first data signal input terminal DATA1. The main controller adjusts the input voltage of the first data signal input terminal DATA1 to achieve the required high refresh rate for the actual terminal device, such as a mobile phone, thus ensuring uniform image display. Furthermore, the main controller is connected to the terminal device, allowing the user to adjust the input voltage of the first data signal input terminal DATA1 via the main controller.

[0066] Optionally, in some feasible embodiments, reference is made to... Figure 5 , Figure 5 This is a schematic diagram of another embodiment of the data input module of the pixel driving circuit of this application. The data input module 10 includes: a second data signal input terminal DATA2 and a third data signal input terminal DATA3.

[0067] The second data signal input terminal DATA2 is connected to the first input module 20, and the third data signal input terminal DATA3 is connected to the second input module 30.

[0068] In this embodiment, the first capacitor C1 is charged via the second data signal input terminal DATA2 through the first input module 20, and the second capacitor C2 is charged via the third data signal input terminal DATA3 through the second input module 30. In addition to the traditional single data line (i.e., the second data signal input terminal DATA2), an extra IC (two-way two-wire synchronous serial bus) interface is added. Since the first capacitor C1 and the second capacitor C2 are charged via two data lines (the second data signal input terminal DATA2 and the third data signal input terminal DATA3, respectively) through the first input module 20 and the second data module 30, the input voltages of the second data signal input terminal DATA2 and the third data signal input terminal DATA3 are the same as those in the conventional technology. Therefore, it is possible to simultaneously open two paths to charge the first capacitor C1 and the second capacitor C2 via the first input module 20 and the second input module 30 within the same charging time, thereby improving charging efficiency, solving the problem of uneven display on the display panel caused by insufficient charging time, and improving the display effect.

[0069] For example, in this embodiment, the voltage of the conventional data signal input terminal DATA is 5V. In conventional technology, the pixel electrode is powered through an input path via a 5V data line. In this embodiment, the first capacitor C1 and the second capacitor C2 are charged through the first input module 20 and the second input module 30, respectively, via the 5V second data signal input terminal DATA2 and the 5V third data signal input terminal DATA3. This improves the charging efficiency, solves the problem of uneven display on the display panel caused by insufficient charging time, and helps to improve the display effect.

[0070] Optional, see reference Figure 6 , Figure 6 The following is a circuit diagram of another embodiment of the pixel driving circuit of this application. The pixel driving circuit further includes: a control signal terminal GATE; the first input module 10 includes: a first transistor T1, a third capacitor C3 and a fourth capacitor C4; and the second input module 20 includes: a second transistor T2, a fifth capacitor C5 and a sixth capacitor C6.

[0071] The control signal terminal GATE is connected to the control terminal of the first transistor T1, the first terminal of the third capacitor C3, and the first terminal of the fourth capacitor C4, respectively. The first terminal of the first transistor T1 is connected to the second terminal of the third capacitor C3 and the second data signal input terminal DATA2, respectively. The second terminal of the first transistor T1 is connected to the second terminal of the fourth capacitor C4 and the first capacitor C1, respectively.

[0072] The control signal terminal GATE is connected to the control terminal of the second transistor T2, the first terminal of the fifth capacitor C5, and the first terminal of the sixth capacitor C6, respectively. The first terminal of the second transistor T2 is connected to the second terminal of the fifth capacitor C5 and the third data signal input terminal DATA3, respectively. The second terminal of the second transistor T1 is connected to the second terminal of the sixth capacitor C6 and the second capacitor C2, respectively.

[0073] It should be noted that the control terminal of the first transistor T1 is the gate, the first terminal of the first transistor T1 is the source, and the second terminal of the first transistor T1 is the drain. The control terminal of the second transistor T2 is the gate, the first terminal of the second transistor T2 is the source, and the second terminal of the second transistor T2 is the drain. The third capacitor C3 and the fifth capacitor C5 are the storage capacitors for the control signal terminal GATE and the second data signal input terminal DATA2, respectively. The fourth capacitor C4 and the sixth capacitor C6 are the storage capacitors for the SOURCE (source signal terminal), respectively. The SOURCE DRIVER is connected to the SOURCE (source signal terminal), and the GATE DRIVER is connected to the control signal terminal GATE.

[0074] In this embodiment, the control signal terminal GATE controls the gates of the first transistor T1 and the second transistor T2, thereby controlling the on and off states of the second transistor T2. By controlling the first transistor T1, the voltage signal input from the second data signal input terminal DATA2 is stored in the first capacitor C1. By controlling the second transistor T2, the voltage signal input from the third data signal input terminal DATA3 is stored in the second capacitor C2. Thus, the second transistor T2 of the first transistor T1 is simultaneously turned on within the same charging time, charging the first capacitor C1 and the second capacitor C2 respectively. This improves charging efficiency, solves the problem of uneven display on the display panel caused by insufficient charging time, and helps improve the display effect.

[0075] refer to Figure 6 , Figure 6 The drains of the first transistor T1 and the second transistor T2 are connected and connected to the test terminal Cr. The test terminal Cr is used to test the input waveforms of DATA and GATE. (Refer to...) Figure 7 , Figure 7 This is a charging timing diagram of another embodiment of the pixel driving circuit of this application. Figure 7 The dashed line represents the GATE signal waveform. VGH (Vgatehigh) refers to the high potential of the gate stage, i.e., the voltage to turn on the gate stage. VGL (Vgatelow) refers to the low potential of the gate stage, i.e., the voltage to turn off the gate stage. The upper solid line represents the DATA2 signal waveform, and the lower solid line represents the DATA3 signal waveform. VDH represents the high potential of the second data signal input terminal DATA2 and the third data signal input terminal DATA3, respectively. VDL represents the low potential of the second data signal input terminal DATA2 and the third data signal input terminal DATA3, respectively. The input voltage of ATA3 is set to 5V. In this case, t1 in the diagram represents the rising edge of the second data signal input terminal DATA2 and the third data signal input terminal DATA3, and t2 represents the falling edge of the second data signal input terminal DATA2 and the third data signal input terminal DATA3. The rising edge is the instant when the signal changes from low level to high level, and the falling edge is the instant when the signal changes from high level to low level. The time between t1 and t2 is the pixel charging time. The pixel charging time is longer than the traditional pixel charging time during high refresh rates, thereby improving charging efficiency and solving the problem of uneven display on the display panel caused by insufficient charging time, which is beneficial to improving the display effect.

[0076] It should be noted that the reference Figure 10 , Figure 10 The following is a timing diagram showing the data signal input comparison for various embodiments of the pixel driving circuit of this application. Figure 10 In this context, A represents the input voltage of the first data signal input terminal DATA1 being 7V when the data input module 10 only includes the first data signal input terminal DATA1. Figure 10 In the figure, B means that when the data input module 10 includes a second data signal input terminal DATA2 and a third data signal input terminal DATA3, the input voltage of each of the second data signal input terminal DATA2 and the third data signal input terminal DATA3 is 7V.

[0077] In practical applications, refer to Figure 9 , Figure 9 This is a circuit wiring diagram illustrating an application scenario of another embodiment of the pixel driving circuit of this application. Figure 8In this circuit, C1 is the first capacitor, i.e., PXL ITO1, and C2 is the second capacitor, i.e., PXL ITO2. The electrical energy of C1 and C2 is output to Com ITO, which is the common voltage terminal Vcom. The first transistor T1 and the second transistor T2 are soldered onto the substrate. The second data signal input terminal DATA2 is connected to the first transistor T1, and the third data signal input terminal DATA3 is connected to the second transistor T2. The drain of the first transistor T1 is connected to the first capacitor C1, and the drain of the second transistor T2 is connected to the second capacitor C2. The first transistor T1 is controlled to charge the first capacitor C1, and the second transistor T2 is controlled to charge the second capacitor C2, through the control signal terminal GATE.

[0078] This application provides a pixel driving circuit, comprising: a data input module, a first input module, a second input module, and pixel electrodes. Each pixel electrode includes a first capacitor and a second capacitor. The data input module is connected to both the first and second input modules. The first input module is connected to the first capacitor, the second input module is connected to the second capacitor, and the first and second capacitors are connected together. The connection terminals of the first and second capacitors are connected to a common voltage terminal. This application solves the problem of uneven display on the display panel caused by insufficient charging time by simultaneously opening two paths through the first and second input modules to charge the first and second capacitors within the same charging time, thereby improving the display effect.

[0079] Based on various embodiments of the pixel driving circuit of this application, various embodiments of the control method of the pixel driving circuit of this application are proposed, with reference to Figure 1 , Figure 1 This is a schematic diagram of the framework structure of a pixel driving circuit according to an embodiment of the present application. In one embodiment of the control method for the pixel driving circuit, refer to... Figure 11 , Figure 11 This is a flowchart of an embodiment of the control method for the pixel driving circuit of this application. The control method for the pixel driving circuit includes:

[0080] Step S10: Charge the first capacitor through the data input module via the first input module, and charge the second capacitor through the second input module;

[0081] In this embodiment, Figure 1The middle pixel electrode 40 is a PXL ITO (Pixel Electrode), which is divided into two equal parts, namely PXL ITO1 and PXL ITO2. PXL ITO1 is the first capacitor C1, and PXL ITO2 is the second capacitor. The storage capacity Cst1 of the first capacitor C1 is the same as the storage capacity Cst2 of the second capacitor C2. That is, the size and shape of the equally divided pixel units are consistent, and the storage capacity is also consistent. Cst1 = Cst2 = 1 / 2Cst, where Cst is the storage capacity of the pixel electrode in the conventional technology or the conventional pixel electrode. Based on the traditional method of charging pixel units through a single voltage input path, a new input path is added, namely the first input module 20 and the second input module 30. The pixel electrode is divided into two pixel units with the same storage capacity, namely the first capacitor C1 and the second capacitor C2. Thus, within the same charging time, two paths are simultaneously activated, charging the first capacitor C1 and the second capacitor C2 through the first input module 20 and the second input module 30 respectively. This improves charging efficiency, solves the problem of uneven display on the display panel caused by insufficient charging time, and helps to improve the display effect.

[0082] Optionally, in some feasible embodiments, reference is made to Figure 2 , Figure 3 and Figure 4 , Figure 2 This is a schematic diagram of the framework of an embodiment of the data input module of the pixel driving circuit of this application. Figure 3 This is a circuit structure diagram of one embodiment of the pixel driving circuit of this application. Figure 4 This is a charging timing diagram of an embodiment of the pixel driving circuit of this application. The data input module 10 includes: a first data signal input terminal DATA1. Step S10 may include the following steps:

[0083] Step S101: Increase the voltage value at the first data signal input terminal;

[0084] In this embodiment, the first data signal input terminal DATA1 charges the first capacitor C1 and the second capacitor C2 through the first input module 20 and the second input module 30 respectively. It should be noted that the first data signal input terminal DATA1 is a data line. Since the first capacitor C1 and the second capacitor C2 are powered by the first input module 20 and the second input module 30 simultaneously through a single data line, it is necessary to increase the voltage of the first data signal input terminal DATA1. The increased voltage of the first data signal input terminal DATA1 simultaneously powers the first capacitor C1 and the second capacitor C2 through the first input module 20 and the second input module 30 respectively. Thus, it is possible to simultaneously open two paths to charge the first capacitor C1 and the second capacitor C2 through the first input module 20 and the second input module 30 within the same charging time. This improves the charging efficiency, solves the problem of uneven display on the display panel caused by insufficient charging time, and helps to improve the display effect.

[0085] For example, in this embodiment, the voltage of the conventional first data signal input terminal DATA1 is 5V. In conventional technology, the pixel electrode is powered only through a 5V data line via one input path. In this application, the voltage of the first data signal input terminal DATA1 can be increased to 7V. The 7V input voltage is used to charge the first capacitor C1 and the second capacitor C2 through the first input module 20 and the second input module 30 respectively, thereby improving the charging efficiency, solving the problem of uneven display on the display panel caused by insufficient charging time, and improving the display effect.

[0086] Step S102: The increased voltage value is used to charge the first capacitor through the first input module and the second capacitor through the second input module.

[0087] In this embodiment, reference Figure 4 The input voltage of the first data signal input terminal DATA1 is set to 7V. At this time, T1 in the figure is the pixel charging time. T1 is the pixel charging time between the rising edge and the falling edge of the first data signal input terminal DATA1. The rising edge is the instant when the signal changes from low level to high level, and the falling edge is the instant when the signal changes from high level to low level. The pixel charging time T1 is longer than the traditional pixel charging time during high refresh rate, thereby improving the charging efficiency, solving the problem of uneven display on the display panel caused by insufficient charging time, and helping to improve the display effect.

[0088] Optionally, in some feasible embodiments, reference is made to... Figure 5 , Figure 6 and Figure 7 , Figure 5 This is a schematic diagram of another embodiment of the data input module of the pixel driving circuit of this application. Figure 6 This is a circuit diagram of another embodiment of the pixel driving circuit of this application. Figure 7 This is a charging timing diagram of another embodiment of the pixel driving circuit of this application. The data input module 10 includes: a second data signal input terminal DATA2 and a third data signal input terminal DATA3. Step S10 may further include the following steps:

[0089] Step S103: Charge the first capacitor through the second data signal input terminal via the first input module, and charge the second capacitor through the third data signal input terminal via the second input module.

[0090] In this embodiment, the first capacitor C1 is charged via the second data signal input terminal DATA2 through the first input module 20, and the second capacitor C2 is charged via the third data signal input terminal DATA3 through the second input module 30. In addition to the traditional single data line (i.e., the second data signal input terminal DATA2), an extra IC (bidirectional two-wire synchronous serial bus) interface is added. Since the first capacitor C1 and the second capacitor C2 are charged via two data lines (the third data signal input terminal DATA3 and the second data module 30, respectively) through the first input module 20 and the second data module 30, the input voltages of the second data signal input terminal DATA2 and the third data signal input terminal DATA3 are the same as those in the conventional technology. Therefore, it is possible to simultaneously open two paths to charge the first capacitor C1 and the second capacitor C2 via the first input module 20 and the second input module 30 within the same charging time, thereby improving charging efficiency, solving the problem of uneven display on the display panel caused by insufficient charging time, and improving the display effect.

[0091] For example, in this embodiment, the voltage of the conventional data signal input terminal DATA is 5V. In conventional technology, the pixel electrode is powered through an input path via a 5V data line. In this embodiment, the first capacitor C1 and the second capacitor C2 are charged through the first input module 20 and the second input module 30, respectively, via the 5V second data signal input terminal DATA2 and the 5V third data signal input terminal DATA3. This improves the charging efficiency, solves the problem of uneven display on the display panel caused by insufficient charging time, and helps to improve the display effect.

[0092] Step S20: Output the electrical energy of the first capacitor and the second capacitor together to the common voltage terminal.

[0093] In this embodiment, by outputting the electrical energy stored in the first capacitor C1 and the second capacitor C2 together to the common voltage terminal Vcom, the high refresh rate mobile phone is fully powered to ensure uniform screen display.

[0094] This application provides a pixel driving circuit that charges a first capacitor via a data input module through a first input module and a second capacitor via a second input module; the electrical energy of the first and second capacitors is then output together to a common voltage terminal. By simultaneously opening two paths within the same charging time to charge the first and second capacitors via the first and second input modules respectively, this application solves the problem of uneven display on the display panel caused by insufficient charging time, thereby improving the display effect.

[0095] This application also proposes a pixel driving component, which includes a pixel driving circuit. The specific structure of the pixel driving circuit is as described in the above embodiments. Since this pixel driving component adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0096] This application also proposes a display panel, which includes a pixel driving component. The specific structure of the pixel driving circuit in the pixel driving component is as described in the above embodiments. Since this display panel adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0097] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural transformations made based on the content of the specification and drawings of this application under the concept of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A pixel driving circuit, characterized in that, The pixel driving circuit includes: a data input module, a first input module, a second input module, and a pixel electrode; the pixel electrode includes: a first capacitor and a second capacitor; the data input module includes: a first data signal input terminal; The data input module is connected to the first input module and the second input module respectively. The first input module is connected to the first capacitor, the second input module is connected to the second capacitor, the first capacitor is connected to the second capacitor, and the connection terminals of the first capacitor and the second capacitor are connected to a common voltage terminal. The pixel driving circuit further includes a control signal terminal; the first input module includes a first transistor, a third capacitor, and a fourth capacitor; and the second input module includes a second transistor, a fifth capacitor, and a sixth capacitor. The control signal terminal is connected to the control terminal of the first transistor, the first terminal of the third capacitor, and the first terminal of the fourth capacitor, respectively. The first terminal of the first transistor is connected to the second terminal of the third capacitor and the first data signal input terminal in the data input module, respectively. The second terminal of the first transistor is connected to the second terminal of the fourth capacitor and the first capacitor, respectively. The control signal terminal is connected to the control terminal of the second transistor, the first terminal of the fifth capacitor, and the first terminal of the sixth capacitor, respectively. The first terminal of the second transistor is connected to the second terminal of the fifth capacitor and the first data signal input terminal, respectively. The second terminal of the second transistor is connected to the second terminal of the sixth capacitor and the second capacitor, respectively. Specifically, the voltage value at the first data signal input terminal is increased; the increased voltage at the first data signal input terminal simultaneously supplies power to the first capacitor and the second capacitor via the first input module and the second input module, respectively.

2. A control method for a pixel driving circuit, characterized in that, The control method for the pixel driving circuit is applied to the pixel driving circuit as described in claim 1, and the control method for the pixel driving circuit includes: The data input module charges the first capacitor through the first input module, and the data input module charges the second capacitor. The electrical energy of the first capacitor and the second capacitor is output together to the common voltage terminal.

3. A pixel driving component, characterized in that, The pixel driving component includes the pixel driving circuit as described in claim 1.

4. A display panel, characterized in that, The display panel includes the pixel driving component as described in claim 3.

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