Display control circuit, display control device, and display device

Abstract

Embodiments of the present application relate to a display control circuit, a display control device, and a display device, which are applied to a display panel, wherein the display panel is connected to N cascaded drive control modules, including: the display panel is provided with N gate connection lines, and N display units, each display unit includes 2 rows and M columns of pixel units, and the drive control module is provided with a gate drive unit and a switch control unit; the input end of the gate drive unit is correspondingly connected to one of the N gate connection lines; one gate drive unit is correspondingly connected to one of the N display units; thereby, dual-rate drive and hardware super-resolution technical functions can be realized; the problem of insufficient high-frequency drive / low-frequency leakage is improved, the problem of pixel color deviation is solved, and the technical effect of improving product adaptability and reliability is achieved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of display technology, and in particular to a display control circuit, a display control device, and a display device. Background Art

[0002] The current Liquid Crystal Display (LCD) industry is gradually developing towards high refresh rates and high resolutions. At the same time, cost control has become an urgent issue to be addressed. In order to achieve high refresh rates at a low cost, a new display mode, the Hardware Super Resolution (HSR) mode, has been introduced. The HSR mode uses a gate driver (GDL) signal multiplication method, the data signal remains unchanged, and the same data signal is used between adjacent rows, thereby reducing the vertical resolution and increasing the refresh rate of the screen. At the same time, in order to further reduce costs, a dual rate driver (DRD) driving method is adopted. When using the DRD driving method, two sets of scanning signals are used to drive the pixels in the same row, and two adjacent signals are used to drive the pixels in the first row. This solution reduces the number of data lines and the number of COFs, thereby achieving the goal of reducing costs.

[0003] However, the DRD method cannot realize the HSR function and brings color deviation problems to a single pixel channel. This is because for the data line, adjacent scanning data signals are connected to different pixel structures, so the HSR function cannot be realized. Summary of the Invention

[0004] In view of this, in order to solve the technical problem of pixel color deviation and the inability to implement the HSR function using the DRD method, the embodiments of the present application provide a display control circuit, a display control device and a display device.

[0005] In a first aspect, an embodiment of the present application provides a display control circuit, which is applied to a display panel, wherein the display panel is connected to N cascaded drive control modules, including:

[0006] The display panel is provided with N gate connection lines and N display units, each of the display units includes 2 rows and M columns of pixel units, wherein the conditions N≥1 and M≥3 are satisfied;

[0007] The drive control module is provided with a gate drive unit and a switch control unit;

[0008] The input end of the gate driving unit is correspondingly connected to one of the N gate connection lines;

[0009] One of the gate driving units is correspondingly connected to one of the N display units;

[0010] The first output terminal of the gate driving unit is connected to the first input terminal of one of the display units, the second output terminal is connected to the first input terminal of the switch control unit, the third output terminal is connected to the second input terminal of the switch control unit, and the fourth output terminal is connected to the sixth input terminal of the display unit;

[0011] The first output end of the switch control unit is connected to the second input end of the display unit, the second output end is connected to the third input end of the display unit, the third output end is connected to the fourth input end of the display unit, and the fourth output end is connected to the fifth input end of the display unit.

[0012] In one possible embodiment, the gate connection line inputs a gate signal to the gate driving unit, the gate driving unit inputs the gate signal to the switch control unit, the switch control unit selects and controls the input gate signal and then inputs a control signal to the display unit, and the display unit uses the control signal to control the state of the internal pixel unit.

[0013] In a possible implementation, the gate connection line includes: a first gate connection line, a second gate connection line, a third gate connection line, and a fourth gate connection line;

[0014] The gate driving unit includes: a first gate driving sub-unit, a second gate driving sub-unit, a third gate driving sub-unit and a fourth gate driving sub-unit, and the first gate driving sub-unit, the second gate driving sub-unit, the third gate driving sub-unit and the fourth gate driving sub-unit have the same structure;

[0015] The first gate connection line is connected to the input terminal of the first gate driving sub-unit, and the output terminal of the first gate driving sub-unit is connected to the first input terminal of the display unit;

[0016] The second gate connection line is connected to the input terminal of the second gate driving sub-unit, and the output terminal of the second gate driving sub-unit is connected to the first input terminal of the switch control unit;

[0017] The third gate connection line is connected to the input end of the third gate driving sub-unit, and the output end of the third gate driving sub-unit is connected to the second input end of the switch control unit;

[0018] The fourth gate connection line is connected to the input terminal of the fourth gate driving sub-unit, and the output terminal of the fourth gate driving sub-unit is connected to the sixth input terminal of the display unit.

[0019] In a possible implementation, the switch control unit includes: a first switch subunit and a second switch subunit;

[0020] The input end of the first switch subunit is connected to the second output end of the gate driving unit, the first output end is connected to the second input end of the display unit, and the second output end is connected to the third input end of the display unit;

[0021] The input end of the second switch subunit is connected to the third output end of the gate driving unit, the first output end is connected to the fourth input end of the display unit, and the second output end is connected to the fifth input end of the display unit.

[0022] In a possible implementation, the first switch subunit includes: a first switch transistor and a second switch transistor;

[0023] A first end of the first switching transistor is connected to the second output end of the gate driving unit and the first end of the second switching transistor, a second end is connected to the output end of the control voltage source and the second end of the second switching transistor, and a third end is connected to the second input end of the display unit;

[0024] The third terminal of the second switch transistor is connected to the fifth input terminal of the display unit.

[0025] In a possible implementation, the second switch subunit includes: a third switch transistor and a fourth switch transistor, the first switch transistor and the third switch transistor are of the same type, and the second switch transistor and the fourth switch transistor are of the same type;

[0026] The first end of the third switching transistor is connected to the third output end of the gate driving unit and the first end of the fourth switching transistor, the second end is connected to the output end of the control voltage source and the second end of the fourth switching transistor, and the third end is connected to the third input end of the display unit;

[0027] The third terminal of the fourth switch transistor is connected to the fourth input terminal of the display unit.

[0028] In one possible implementation, the display unit includes: a first display odd subunit, a first display even subunit, a second display odd subunit, and a second display even subunit, wherein the first display odd subunit and the first display even subunit are pixel units corresponding to odd columns and even columns in a first row and M columns display area of the display unit, and the second display odd subunit and the second display even subunit are pixel units corresponding to odd columns and even columns in a second row and M columns display area of the display unit;

[0029] The input terminal of the first display odd sub-unit is connected to the first output terminal of the gate driving unit;

[0030] The first input terminal of the first display even subunit is connected to the first output terminal of the switch control unit, and the second input terminal is connected to the second output terminal of the switch control unit;

[0031] The first input terminal of the second display odd sub-unit is connected to the third output terminal of the switch control unit, and the second input terminal is connected to the fourth input terminal of the switch control unit;

[0032] The input terminal of the second display even sub-unit is connected to the fourth output terminal of the gate driving unit.

[0033] In a possible implementation, the first gate driving subunit includes: a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, a ninth switching transistor, a tenth switching transistor, and a first capacitor;

[0034] A first end of the fifth switching transistor is connected to the first gate connection end of the upper layer gate driving unit to which the current gate driving unit is cascade-connected, a second end is connected to the output end of the control voltage source and the second end of the sixth switching transistor, and a third end is connected to the third end of the sixth switching transistor and the first end of the seventh switching transistor;

[0035] The first terminal of the sixth switch transistor is connected to the output terminal of the control voltage source;

[0036] The second end of the seventh switch transistor is connected to the first gate connection end of the gate driving unit in the upper layer connected in cascade to the current gate driving unit, and the third end and the first end of the ninth switch transistor are connected to the first node;

[0037] A first end of the eighth switching transistor is connected to the clock signal output end corresponding to the current gate driving unit, a second end is connected to the first node and one end of the first capacitor, and a third end is connected to the other end of the first capacitor, the first end of the tenth switching transistor, and the first gate connection end of the current gate driving unit;

[0038] The second end of the tenth switching transistor is connected to the second end of the ninth switching transistor and the first gate connection end of the next gate driving unit in the cascade connection of the current gate driving unit, and the third end is connected to the third end of the ninth switching transistor and the output end of the ground voltage source.

[0039] In a second aspect, an embodiment of the present application provides a display control device, comprising: a housing and a display control circuit as described in the first aspect.

[0040] In a third aspect, an embodiment of the present application provides a display device, including a display panel, and the display device further includes: a display control device as described in the second aspect.

[0041] The display control circuit provided in an embodiment of the present application is applied to a display panel, wherein the display panel is connected to N cascaded drive control modules, the display panel is provided with N gate connection lines, and N display units, each of the display units includes 2 rows and M columns of pixel units, wherein the conditions N≥1 and M≥3 are satisfied; the drive control module is provided with a gate drive unit and a switch control unit; the input end of the gate drive unit is correspondingly connected to one of the N gate connection lines; one gate drive unit is correspondingly connected to one of the N display units; the first output end of the gate drive unit is connected to the first input end of one of the display units, the second output end is connected to the first input end of the switch control unit, the third output end is connected to the second input end of the switch control unit, and the fourth output end is connected to the sixth input end of the display unit; the first output end of the switch control unit is connected to the second input end of the display unit, the second output end is connected to the third input end of the display unit, the third output end is connected to the fourth input end of the display unit, and the fourth output end is connected to the fifth input end of the display unit. By adding a switch control unit between the gate drive unit and the display unit, and controlling the switch control unit's on / off state correspondingly when selecting high and low frequencies, the gate drive unit controls different display units, achieving the goal of implementing HSR based on the DRD method and resolving the color shift problem of pixels in the display unit. This solution enables dual-rate drive and hardware super-resolution technology, improves high-frequency drive underpoweredness and low-frequency leakage, resolves pixel color shift, and improves product adaptability and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0043] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0044] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0045] Figure 1A A schematic diagram of a pixel waveform of an HSR function display panel provided in the prior art;

[0046] Figure 1B A schematic diagram of pixel waveforms of a display panel under a DRD driving mode provided in the prior art;

[0047] Figure 1C A structural diagram of a display control circuit in a DRD driving mode provided in the prior art;

[0048] Figure 1D A schematic diagram of pixel waveforms of a display control circuit under a DRD driving mode provided in the prior art;

[0049] Figure 2 A schematic diagram of the structure of a display control circuit provided in an embodiment of the present application;

[0050] Figure 3 A schematic structural diagram of another display control circuit provided in an embodiment of the present application;

[0051] Figure 4 A schematic diagram of pixel waveforms of a display control circuit provided in an embodiment of the present application;

[0052] Figure 5 A schematic structural diagram of a gate drive unit provided in an embodiment of the present application;

[0053] Figure 6 A schematic diagram of an output waveform of a gate drive unit provided in an embodiment of the present application;

[0054] Figure 7 A schematic structural diagram of a display control device provided in an embodiment of the present application;

[0055] Figure 8 A schematic structural diagram of a display device provided in an embodiment of the present application.

[0056] Description of reference numerals:

[0057] The display panel 100, the display control device 1000, the display device 10000, the driving control module 20, are provided with a gate driving unit 201, a switch control unit 202, a first gate driving sub-unit 31, a second gate driving sub-unit 32, a third gate driving sub-unit 33, a fourth gate driving sub-unit 34, a first gate connection line G1, a second gate connection line G2, a third gate connection line G3, a fourth gate connection line G4, a first switch sub-unit 35, a second switch sub-unit 36, a display unit 30, a first display odd sub-unit 301, a first display even sub-unit 302, a second display odd sub-unit 303, a second display even sub-unit 304, a gate connection line G, a control voltage source V1, a first switch transistor T1, a second switch transistor T2, a third switch transistor T4 3, fourth switching transistor T4, data line D1, data line D2, data line D3, fifth gate connection line G5, sixth gate connection line G6, seventh gate connection line G7, eighth gate connection line G8, ninth gate connection line G9, tenth gate connection line G10, fifth switching transistor T5, sixth switching transistor T6, seventh switching transistor T7, eighth switching transistor T8, ninth switching transistor T9, tenth switching transistor T10, first capacitor C(N), first gate connection terminal G(N-4), first node P, first gate connection terminal G(N), clock signal CK(N), first gate connection terminal G(N+4), ground voltage source VSS, potential Q(N) corresponding to the first node P, voltage region A, voltage region B, green pixel G, red pixel R, blue pixel B. DETAILED DESCRIPTION

[0058] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0059] In the embodiments of this application, the terms "including" and "having" are intended to convey an open-ended, inclusive meaning and indicate that additional elements / components / etc. may be present in addition to the listed elements / components / etc. The terms "first" and "second" are used merely as labels and do not limit the quantity of their objects. Furthermore, the various elements and regions in the drawings are shown for schematic purposes only, and thus this application is not limited to the sizes or distances shown in the drawings.

[0060] To facilitate understanding of the embodiments of the present application, further explanation will be given below with reference to specific embodiments in conjunction with the accompanying drawings. The embodiments do not constitute a limitation on the embodiments of the present application.

[0061] DRD, or dual-gate drive, doubles the drive speed, allowing a single source driver IC to perform the work of two. Due to the increased drive speed, DRD requires only one source driver IC with 1536 channels, each capable of driving two sub-pixels.

[0062] GDL technology, or gate drive technology, utilizes the existing array manufacturing process of liquid crystal display panels to fabricate the driver circuitry for the horizontal scan lines on the substrate surrounding the display area, replacing the need for an external integrated circuit board to drive the horizontal scan lines. By implementing GDL technology on the thin-film transistor array substrate, the gate driver can be fabricated in a space-saving manner, making the LCD panel more suitable for narrow-border or borderless display products.

[0063] HSR, also known as hardware super-resolution, is the process of reconstructing low-resolution images or videos into high-resolution images. This is achieved by using various algorithms and techniques to increase the number of pixels and modify their colors. HSR is widely used in image and video processing, such as television, surveillance, medical imaging, satellite imagery, and remote sensing imagery, effectively improving the clarity and detail of images and videos.

[0064] Figure 1A Schematic diagram of pixel waveform of a HSR function display panel provided in the prior art. Figure 1A The diagram provided shows that the pixel array on the display panel is RGB primary colors. The gate signals and source signals in the HSR mode are arranged vertically, horizontally and vertically. The gate signal G1 in the first row and the pixel arrangement order corresponding to the gate signal G2 in the second row are the same. The third row gate signal G3 and the fourth row gate signal G4 are set in the same order. The vertical column is the data signal corresponding to the source. By using the GDL signal multiplication method, the data signal remains unchanged, and the same data signal is used between adjacent pixel unit rows, thereby reducing the vertical resolution, but increasing the refresh rate of the screen. It can be seen from the waveform that the same data signal D1 is obtained between the corresponding two adjacent gate signals (for example, G1 and G2), and the overlapping part of the data signal and the gate signal determines the display color.

[0065] Figure 1B Schematic diagram of pixel waveform of a display panel under a DRD driving mode provided in the prior art. Figure 1B The diagram provided uses DRD drive mode to further reduce costs. Figure 1BThe provided diagram shows that the pixel array on the display panel is RGB primary colors. The gate signals G1, G3 and G5 on the display panel connect the odd-numbered columns of pixels in the pixel array, and the gate signals G2, G4 and G6 connect the even-numbered columns of pixels in the pixel array; the data line D1 connects the first column of red pixels R and the second column of green pixels G, the data signal D2 connects the third column of blue pixels B and the fourth column of red pixels R, and the data signal D3 connects the fifth column of green pixels G and the sixth column of blue pixels B. When the DRD driving method is used, two groups of scanning signals are used to drive the pixels in the same row, and the two signals G1 / G2 are used to drive the pixels in the first row. The states of multiple rows of pixels are controlled by one data signal to obtain the waveform diagram after the gate signal and the data signal are controlled separately. According to Figure 1B In the diagram provided, after the four gate signals corresponding to the first two rows of pixels are turned on with high-level signals, data signal D1 controls the red pixels R in the first and second columns of the pixel array to light up and the green pixels G to turn off, resulting in the display panel displaying only red pixels. This solution reduces the number of data lines and COFs, thereby lowering costs.

[0066] in, Figure 1C The figure is a structural diagram of a display control circuit in a DRD driving mode provided in the prior art. Figure 1C To correspond Figure 1B Drive control circuit. Figure 1C The diagram provided clearly shows that the gate signals (e.g. G1, G2, ..., G7) are connected to the corresponding GDL driving circuit units, and the GDL circuit unit connected to the gate signal G1 is set to control the pixels of the first row and odd columns of the display area, and the GDL circuit unit connected to the gate signal G2 is set to control the pixels of the first row and even columns of the display area. According to this rule, the corresponding connection relationship of the gate signals G3, G4, G5, G6 and G7 is set. The purpose of controlling a row of pixel arrays by two adjacent rows of gate signals is achieved. Figure 1C Based on the provided structure, the method of implementing GDL driver in DRD mode is referenced Figure 1D . Figure 1D This is a pixel waveform diagram of a display control circuit under a DRD driving mode provided in the prior art. Figure 1D In the diagram provided, the data line D1 connects the first column of red pixels and the second column of green pixels, the data signal D2 connects the third column of blue pixels and the fourth column of red pixels, and the data signal D3 connects the fifth column of green pixels and the sixth column of blue pixels. Different from the pixel arrangement order corresponding to HSR, according to Figure 1D and Figure 1BThe arrangement order of the pixel array in the corresponding display panel is obtained in the order that the first row of odd-numbered columns corresponds to the gate signal G1, the first row of even-numbered columns corresponds to the gate signal G2, the second row of odd-numbered columns corresponds to the gate signal G3, and the second row of even-numbered columns corresponds to the gate signal G4. Figure 1D Corresponding pixel waveforms. To achieve a pure color design, the red pixel on data signal D1 is controlled to turn on and the green pixel to turn off, resulting in a pure red display on the display panel. However, using DRD cannot achieve HSR because adjacent scan data signals on the data line connect to different pixel structures. For example, the pixel connected to D1 is RRGG, making HSR impossible.

[0067] In this regard, the present application provides a display control circuit, which adds a switch control unit on the basis of the GDL drive unit, changes the connection mode of the GDL drive unit to the pixels in the display unit, and then changes the waveform diagram of the pixels, thereby realizing the HSR function based on the DRD method, improving the high refresh rate of the display panel, and solving the color deviation problem by changing the internal structure of the GDL drive. The present invention will be described in detail below with reference to examples. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments will be described below with reference to the accompanying drawings.

[0068] Figure 2 This is a schematic diagram of the structure of a display control circuit provided in an embodiment of the present application. Figure 2 The provided diagram shows that the control circuit specifically includes:

[0069] Applied to a display panel, the display panel is connected to N cascaded drive control modules 20, the display panel is provided with N gate connection lines G, and N display units 30, each display unit 30 includes 2 rows and M columns of pixel units, wherein the conditions N≥1, M≥3 are satisfied.

[0070] The driving control module 20 is provided with a gate driving unit 201 and a switch control unit 202 .

[0071] An input terminal of the gate driving unit 201 is correspondingly connected to one of the N gate connection lines G.

[0072] One gate driving unit 201 is correspondingly connected to one of the N display units 30 .

[0073] The first output end of the gate driving unit 201 is connected to the first input end of a display unit 30, the second output end is connected to the first input end of the switch control unit 202, the third output end is connected to the second input end of the switch control unit 202, and the fourth output end is connected to the sixth input end of the display unit 30.

[0074] The first output terminal of the switch control unit 202 is connected to the second input terminal of the display unit 30, the second output terminal is connected to the third input terminal of the display unit 30, the third output terminal is connected to the fourth input terminal of the display unit 30, and the fourth output terminal is connected to the fifth input terminal of the display unit 30.

[0075] The gate driving unit 201 mentioned here is a GDL circuit unit.

[0076] according to Figure 2 The provided diagram shows a possible example scenario in which a switch control unit is internally connected to an external power supply, and a gate signal cascades to a gate driver unit 201 (i.e., a GDL circuit unit). A gate signal is input to the gate driver unit 201 via the display panel's gate connection line G. The gate driver unit then inputs the gate signal to the switch control unit 202. The switch control unit selects and controls the input gate signal and then inputs a control signal to the display unit 30. The display unit 30 uses the control signal to control the state of the internal pixel unit. Two rows of pixels in the display unit are controlled by a single gate driver unit, and the gate driver unit is controlled by adjacent gate signals. The switching logic of the switch control unit is controlled by the gate driver unit and the external power supply, achieving the purpose of GDL pixel frequency doubling, thereby realizing the HSR function based on the DRD method.

[0077] The display control circuit provided in the embodiment of the present application is applied to a display panel, where the display panel is connected to N cascaded drive control modules. The display panel is provided with N gate connection lines and N display units, each display unit including 2 rows and M columns of pixel units, wherein the conditions N≥1 and M≥3 are satisfied; the drive control module is provided with a gate drive unit and a switch control unit; the input end of the gate drive unit is correspondingly connected to one of the N gate connection lines; one gate drive unit is correspondingly connected to one of the N display units; the first output end of the gate drive unit is connected to the first input end of a display unit, the second output end is connected to the first input end of the switch control unit, the third output end is connected to the second input end of the switch control unit, and the fourth output end is connected to the sixth input end of the display unit; the first output end of the switch control unit is connected to the second input end of the display unit, the second output end is connected to the third input end of the display unit, the third output end is connected to the fourth input end of the display unit, and the fourth output end is connected to the fifth input end of the display unit. By adding a switch control unit between the gate drive unit and the display unit, and controlling the switch control unit's on / off state correspondingly when selecting high and low frequencies, the gate drive unit controls different display units, achieving the goal of implementing HSR based on the DRD method and resolving the color shift problem of pixels in the display unit. This enables dual-rate drive and hardware super-resolution technology, improves high-frequency drive underpoweredness and low-frequency leakage, resolves pixel color shift, and improves product adaptability and reliability.

[0078] Figure 3 A schematic structural diagram of another display control circuit provided in an embodiment of the present application. Figure 3 This is introduced based on the previous embodiment. Figure 3 The provided diagram shows that the control circuit specifically includes:

[0079] Applied to a display panel, the display panel is connected to N cascaded drive control modules 20, the display panel is provided with N gate connection lines G, and N display units 30, each display unit 30 includes 2 rows and M columns of pixel units, wherein the conditions N≥1, M≥3 are satisfied.

[0080] The driving control module 20 is provided with a gate driving unit 201 and a switch control unit 202 .

[0081] Among them, the gate connection line inputs a gate signal to the gate driving unit, the gate driving unit inputs the gate signal to the switch control unit, the switch control unit selects and controls the input gate signal and then inputs a control signal to the display unit, and the display unit uses the control signal to control the state of the internal pixel unit.

[0082] according to Figure 3The provided diagram shows that the gate connection lines in the control circuit include: a first gate connection line G1, a second gate connection line G2, a third gate connection line G3 and a fourth gate connection line G4.

[0083] The gate driving unit 201 includes: a first gate driving subunit 31, a second gate driving subunit 32, a third gate driving subunit 33 and a fourth gate driving subunit 34. The first gate driving subunit 31, the second gate driving subunit 32, the third gate driving subunit 33 and the fourth gate driving subunit 34 have the same structure.

[0084] The first gate connection line G1 is connected to an input terminal of the first gate driving sub-unit 31 , and an output terminal of the first gate driving sub-unit 31 is connected to a first input terminal of the display unit 30 .

[0085] The second gate connection line G2 is connected to the input terminal of the second gate driving sub-unit 32 , and the output terminal of the second gate driving sub-unit 32 is connected to the first input terminal of the switch control unit 202 .

[0086] The third gate connection line G3 is connected to the input terminal of the third gate driving sub-unit 33 , and the output terminal of the third gate driving sub-unit 33 is connected to the second input terminal of the switch control unit 202 .

[0087] The fourth gate connection line G4 is connected to the input terminal of the fourth gate driving sub-unit 34 , and the output terminal of the fourth gate driving sub-unit 34 is connected to the sixth input terminal of the display unit 30 .

[0088] Furthermore, the display panel includes N gate connection lines, each of which is further divided into four corresponding connection lines, each of which has the same function. Similarly, the display panel includes N drive control modules 20, each of which includes a gate drive unit 201 and a switch control unit 202. Each gate drive unit 201 includes four gate drive sub-units. The internal circuit structure of each gate drive sub-unit is the same.

[0089] according to Figure 3In the diagram provided, during the GDL driving process, a first gate connection line G1, a second gate connection line G2, a third gate connection line G3 and a fourth gate connection line G4 are set, and are connected to the gate driving units through the gate connection lines, so that the first gate connection line G1 controls the first gate driving sub-unit 31, the second gate connection line G2 controls the second gate driving sub-unit 32, the third gate connection line G3 controls the third gate driving sub-unit 33, and the fourth gate connection line G4 controls the fourth gate driving sub-unit 34. The switch control unit 202 is then controlled by the second gate driving sub-unit 32 and the third gate driving sub-unit 33. The gate signal output by the second gate connection line G2 and the gate signal output by the third gate connection line G3 are received by the second gate driving sub-unit 32 and the third gate driving sub-unit 33 to control the switch control unit 202. The power supply signal inside the switch control unit 202 is controlled to output a low level, so that the second gate driving sub-unit 32 outputs a control signal to the pixel units in the first row and even columns in the display panel to control the lighting state of the pixel units on the right side of the first row in the data signal; and the third gate driving sub-unit 33 outputs a control signal to the pixel units in the second row and odd columns in the display panel to control the lighting state of the pixel units on the left side of the second row in the data signal. The switch control unit 202 is used to control the power supply signal to output a high level, so that the second gate driving sub-unit 32 outputs a control signal to the second row and odd column pixel units in the display panel to control the lighting state of the pixel units on the left side of the second row in the data signal; at the same time, the third gate driving sub-unit 33 outputs a control signal to the first row and even column pixel units in the display panel to control the lighting state of the pixel units on the right side of the first row in the data signal, thereby realizing the HSR function based on the DRD method.

[0090] according to Figure 3 The provided diagram shows that the switch control unit in the control circuit includes: a first switch subunit 35 and a second switch subunit 36.

[0091] The input terminal of the first switch subunit 35 is connected to the second output terminal of the gate driving unit 201, the first output terminal is connected to the second input terminal of the display unit 30, and the second output terminal is connected to the third input terminal of the display unit 30;

[0092] The input terminal of the second switch subunit 36 is connected to the third output terminal of the gate driving unit 201 , the first output terminal is connected to the fourth input terminal of the display unit 30 , and the second output terminal is connected to the fifth input terminal of the display unit 30 .

[0093] according to Figure 3The provided diagram shows that during the GDL driving process, a gate connection line G and a gate driving unit 201 are provided, and the gate driving unit 201 is controlled by the gate connection line G. The gate driving unit 201 then controls the first switching subunit 35 and the second switching subunit 36. The gate driving unit 201 receives a gate signal output from the gate connection line G and controls the first switching subunit 35 and the second switching subunit 36. The control voltage source V1 inside the first switching subunit 35 outputs a low level, causing the gate driving unit 201 to output a control signal to the pixel units in the first row and even columns of the display panel, thereby controlling the lighting state of the pixel units on the right side of the first row in the data signal. The control voltage source V1 inside the second switching subunit 36 outputs a low level, causing the gate driving subunit 201 to output a control signal to the pixel units in the second row and odd columns of the display panel, thereby controlling the lighting state of the pixel units on the left side of the second row in the data signal. The voltage source V1 inside the first switch subunit 35 is controlled to output a high level, so that a control signal is output to the pixel unit of the second row and odd column in the display panel through the gate drive unit 201, thereby controlling the lighting state of the pixel unit on the left side of the second row in the data signal; at the same time, the voltage source V1 inside the second switch subunit 36 is controlled to output a high level, so that a control signal is output to the pixel unit of the first row and even column in the display panel through the gate drive unit 201, thereby controlling the lighting state of the pixel unit on the right side of the first row in the data signal, thereby realizing the HSR function based on the DRD method.

[0094] according to Figure 3 The provided diagram shows that the first switch subunit 35 in the control circuit includes: a first switch transistor T1 and a second switch transistor T2.

[0095] The first end of the first switching transistor T1 is connected to the second output end of the gate driving unit 201 and the first end of the second switching transistor T2, the second end is connected to the output end of the control voltage source V1 and the second end of the second switching transistor T2, and the third end is connected to the second input end of the display unit 30.

[0096] The third terminal of the second switch transistor T2 is connected to the fifth input terminal of the display unit 30 .

[0097] The first transistor and the second transistor here are different types of transistors, and the transistor types mentioned here include PMOS transistors, NMOS transistors, N-type TFT transistors, P-type TFT transistors or IGBTs, etc.

[0098] This solution selects one of the cases, setting the first switch transistor T1 to be a P-type TFT thin film transistor, and setting the second switch transistor T2 to be an N-type TFT thin film transistor.

[0099] The first end of the first switching transistor and the second switching transistor mentioned here is the source of the thin film transistor, the second end is the gate of the thin film transistor, and the third end is the drain of the thin film transistor.

[0100] Furthermore, the first end and the third end of the first switching transistor and the second switching transistor may be respectively configured as the drain and the source of the thin film transistor.

[0101] according to Figure 3 The provided diagram shows that the second switch subunit in the control circuit includes: a third switch transistor T3 and a fourth switch transistor T4, the first switch transistor T1 and the third switch transistor T3 are of the same type, and the second switch transistor T2 and the fourth switch transistor T4 are of the same type.

[0102] The first end of the third switch transistor T3 is connected to the third output end of the gate driving unit 201 and the first end of the fourth switch transistor T4, the second end is connected to the output end of the control voltage source V1 and the second end of the fourth switch transistor T4, and the third end is connected to the third input end of the display unit 30.

[0103] A third terminal of the fourth switch transistor T4 is connected to a fourth input terminal of the display unit 30 .

[0104] The third transistor and the fourth transistor here are different types of transistors, and the transistor types mentioned here include PMOS transistors, NMOS transistors, N-type TFT transistors, P-type TFT transistors or IGBTs, etc.

[0105] This application selects one of the cases, setting the third switch transistor T3 to a P-type TFT thin film transistor, and setting the fourth switch transistor T4 to an N-type TFT thin film transistor.

[0106] The first end of the third switch transistor and the fourth switch transistor mentioned here is the source of the thin film transistor, the second end is the gate of the thin film transistor, and the third end is the drain of the thin film transistor.

[0107] Furthermore, the first end and the third end of the third switch transistor and the fourth switch transistor may be respectively configured as the drain and the source of the thin film transistor.

[0108] according to Figure 3The provided diagram shows that the switch control unit includes four TFT thin-film transistors (TFTs), namely, a first switch transistor T1, a second switch transistor T2, a third switch transistor T3, and a fourth switch transistor T4, as well as a control voltage source V1 signal. The second switch transistor T2 and the third switch transistor T3 are configured as N-type TFT thin-film transistors, with a high level switching on and a low level switching off. The first switch transistor T1 and the fourth switch transistor T4 are configured as P-type TFT thin-film transistors, with a low level switching on and a high level switching off. During normal DRD display, the control voltage source V1 output is low, turning on the first switch transistor T1 and the fourth switch transistor T4. This causes the gate signals in the gate drive unit 201 to control the pixel units in the first row and even columns of the display area and the pixel units in the second row and odd columns, respectively. When it is necessary to switch to the DRD+HSR mode, the control voltage source V1 is output to a high level, and the gate driving unit exchanges the output control signal of the display unit 30. At this time, the second switching transistor T2 is turned on, and the control gate signal outputs the control signal to the pixel unit in the second row and odd column of the display unit in the display area. At the same time, the fourth switching transistor T4 is turned on, and the control gate signal outputs the control signal to the pixel unit in the first row and even column of the display unit in the display area, thereby realizing the DRD+HSR function.

[0109] according to Figure 3 In the provided diagram, the display unit 30 in the display control circuit includes: a first display odd sub-unit 301, a first display even sub-unit 302, a second display odd sub-unit 303 and a second display even sub-unit 304. The first display odd sub-unit 301 and the first display even sub-unit 302 are pixel units corresponding to odd columns and even columns in the first row and M columns display area of the display unit, and the second display odd sub-unit 303 and the second display even sub-unit 304 are pixel units corresponding to odd columns and even columns in the second row and M columns display area of the display unit.

[0110] An input terminal of the first display odd sub-unit 301 is connected to a first output terminal of the gate driving unit 201 .

[0111] A first input terminal of the first display even sub-unit 302 is connected to a first output terminal of the switch control unit 202 , and a second input terminal of the first display even sub-unit 302 is connected to a second output terminal of the switch control unit 202 .

[0112] The first input terminal of the second display odd sub-unit 303 is connected to the third output terminal of the switch control unit 202 , and the second input terminal is connected to the fourth input terminal of the switch control unit 202 .

[0113] An input terminal of the second display even sub-unit 304 is connected to the fourth output terminal of the gate driving unit 201 .

[0114] The display unit mentioned here is composed of multiple pixel units in the display area.

[0115] according to Figure 3 The diagram provided includes N display units, each display unit including two rows of pixel units in the display area. Figure 3 The diagram provides seven rows of pixel units in a display area. The first display odd sub-unit 301 is set to the odd column of the first row of the display area, the first display even sub-unit 302 is set to the even column of the first row of the display area, the second display odd sub-unit 303 is set to the odd column of the second row of the display area, and the second display even sub-unit 304 is set to the even column of the second row of the display area. Similarly, the second display unit includes the first display odd sub-unit 301, the first display even sub-unit 302, and the second display odd sub-unit 303. The first display odd sub-unit 301 is set to the odd column of the third row of the display area, the first display even sub-unit 302 is set to the even column of the third row of the display area, and the second display odd sub-unit 303 is set to the odd column of the fourth row of the display area.

[0116] according to Figure 3 In the diagram provided, the gate drive unit 201 outputs gate signals to the odd columns in the first row of the display area and the even columns in the second row of the display area. Simultaneously, the next gate drive unit 201 cascaded with the current gate drive unit 201 outputs gate signals to the odd columns in the third row of the display area and the even columns in the fourth row of the display area. Simultaneously, when the control voltage source in the current switch control unit 202 outputs a high / low level, it alternately outputs control signals to the even columns in the first row of the display area and the odd columns in the second row of the display area, controlling the pixel units in the even columns in the first row of the display area and the odd columns in the second row of the display area. Simultaneously, the next cascaded switch control unit 202 alternately outputs control signals to the even columns in the third row of the display area and the odd columns in the fourth row of the display area, controlling the pixel units in the even columns in the third row of the display area and the odd columns in the fourth row of the display area, thereby achieving DRD+HSR functionality.

[0117] In one possible example scenario, Figure 4 A schematic diagram of pixel waveforms of a display control circuit provided in an embodiment of the present application. Figure 4 This is introduced based on the previous embodiment. Figure 4In the diagram provided, the data line D1 connects the first column of red pixels and the second column of green pixels, the data line D2 connects the third column of blue pixels and the fourth column of red pixels, and the data line D3 connects the fifth column of green pixels and the sixth column of blue pixels. The first gate connection line G1 connects the pixels of the first row of odd columns in the display unit 30, the second gate connection line G2 connects the pixel units of the first row of even columns in the display unit 30, the third gate connection line G3 connects the pixel units of the second row of odd columns in the display unit 30, and the fourth gate connection line G4 connects the pixel units of the second row of even columns in the display unit 30. By analogy, the connection mode of the connection lines G5, G6, G7, G8, G9, and G10 is obtained. Then we get Figure 4 Corresponding pixel waveform diagram. To achieve pure color design requirements, during normal DRD display, the control voltage source V1 output is low, the first switching transistor T1 and the fourth switching transistor T4 are turned on, and the second gate connection line G2 and the third gate connection line G3 control the green pixels in the first row of the display area and the red pixels in the second row of the display area, respectively. When switching to DRD+HSR mode, V1 is output high, and the output signals of the second gate connection line G2 and the third gate connection line G3 are swapped. At this time, the first gate connection line G1 signal corresponds to the red pixels in the first row of the display area, the second gate connection line G2 signal corresponds to the red pixels in the second row of the display area, the third gate connection line G3 signal corresponds to the green pixels in the first row of the display area, and the fourth gate connection line G4 signal corresponds to the green pixels in the second row of the display area. Therefore, the red pixels in the first row of the display area or the red pixels in the second row of the display area in the display unit can be charged using a common data signal, realizing the DRD+HSR function.

[0118] Figure 5 This is a schematic diagram of the structure of a gate drive unit provided in an embodiment of the present application. Figure 5 The provided diagram shows that the first gate driving subunit 31 in the control circuit includes: a fifth switch transistor T5, a sixth switch transistor T6, a seventh switch transistor T7, an eighth switch transistor T8, a ninth switch transistor T9, a tenth switch transistor T10 and a first capacitor C(N).

[0119] The first end of the fifth switching transistor T5 is connected to the first gate connection terminal G(N-4) in the upper layer gate driving unit 201 to which the current gate driving unit 201 is cascade-connected, the second end is connected to the output end of the control voltage source V1 and the second end of the sixth switching transistor T6, and the third end is connected to the third end of the sixth switching transistor T6 and the first end of the seventh switching transistor T7.

[0120] A first terminal of the sixth switch transistor T6 is connected to the output terminal of the control voltage source V1 .

[0121] The second end of the seventh switching transistor T7 is connected to the first gate connection terminal G(N-4) in the upper layer gate driving unit 201 to which the current gate driving unit 201 is cascade-connected, and the third end is connected to the first end of the ninth switching transistor T9 to the first node P (hereinafter collectively referred to as P).

[0122] A first end of the eighth switching transistor T8 is connected to the clock signal CK(N) output end corresponding to the current gate driving unit 201, a second end is connected to the first node P and one end of the first capacitor C(N), and a third end is connected to the other end of the first capacitor C(N), a first end of the tenth switching transistor T10, and the first gate connection end G(N) in the current gate driving unit 201.

[0123] A second end of the tenth switching transistor T10 is connected to the second end of the ninth switching transistor T9 and the first gate connection terminal G(N+4) in the next layer of gate driving unit 201 to which the current gate driving unit 201 is cascade-connected, and a third end is connected to the third end of the ninth switching transistor T9 and the output end of the ground voltage source VSS.

[0124] The fifth transistor and the sixth transistor here are different types of transistors, and the transistor types mentioned here include PMOS transistors, NMOS transistors, N-type TFT transistors, P-type TFT transistors or IGBTs, etc.

[0125] This solution selects one of the cases, setting the fifth switch transistor T5 to a P-type TFT thin film transistor, setting the sixth switch transistor T6 to an N-type TFT thin film transistor, setting the seventh switch transistor T7, the eighth switch transistor T8, the ninth switch transistor T9, and the tenth switch transistor T10 to all be N-type TFT thin film transistors.

[0126] The first end of the switching transistor mentioned here is the source of the thin film transistor, the second end is the gate of the thin film transistor, and the third end is the drain of the thin film transistor.

[0127] Furthermore, the first end and the third end of the fifth switch transistor and the sixth switch transistor may also be set as the drain and the source of the thin film transistor, respectively.

[0128] according to Figure 5In the diagram provided, since the HSR function improves the refresh rate, higher requirements are placed on the GDL driving capability. A fifth switch transistor T5 and a sixth switch transistor T6 are added. The fifth switch transistor T5 is a P-type semiconductor, and the sixth switch transistor T6 is an N-type semiconductor. The signal output by the pull-up controlled seventh switch transistor T7 is processed separately. When the control voltage source V1 is at a low level, the fifth switch transistor T5 is turned on, the sixth switch transistor T6 is turned off, and the seventh switch transistor T7 is driven by a diode. The gate and source of the seventh switch transistor T7 are both gate connection terminals G The gate signal of (N-4) is obtained by the signal difference between the two ends of the first capacitor C(N) to obtain the potential Q(N) corresponding to the first node P; when the control voltage source V1 is at a high level, it switches to the HSR mode, the fifth switch transistor T5 is turned off, the sixth switch transistor T6 is turned on, and the drive of the seventh switch transistor T7 becomes the gate connection line G(N-4) corresponding to the gate, and the control voltage source V1 is used as the source. At this time, the pull-up potential of the seventh switch transistor T7 becomes higher, so that the potential at the first node P is increased, which is beneficial to improving the driving capability of Q(N) and improving the problem of insufficient driving of Q(N) in the high-frequency state.

[0129] Figure 6 A schematic diagram of an output waveform of a gate drive unit provided in an embodiment of the present application.

[0130] according to Figure 6 The diagram shows that for the potential Q(N) signal at the first node P, using the control voltage source V1 as input and the G(N) output voltage Gout as input will affect the peak value of the potential Q(N) signal at the first node P. When the device is in a high-frequency operating environment, the time spent in voltage region A of the potential Q(N) at the first node P is reduced, affecting the peak value of the potential Q(N) at the first node P. Using the control voltage source V1 as the input can increase the peak value of the potential Q(N) at the first node P, thereby improving the high-frequency output stability of the device. When operating in a low-frequency environment, the time spent in voltage region B of the potential Q(N) at the first node P is longer, increasing the risk of leakage and the risk of Q(N) collapse. Therefore, the input of Q(N) requires dynamic switching between the control voltage source V1 and the G(N) output voltage Gout to achieve a high- and low-frequency compatible design.

[0131] Figure 7 A schematic structural diagram of a display control device provided in an embodiment of the present application includes: a housing and Figure 2-6 Provides display control circuit.

[0132] The display device provided in this embodiment can be Figure 7 The display device shown in FIG. 1 may perform the following steps: Figure 2-6 All steps of the control method in order to achieve Figure 2-6For details on the technical effects of the control method shown, please refer to Figure 2-6 For the sake of brevity, the relevant description will not be repeated here.

[0133] Figure 8 A schematic diagram of the structure of a display device provided in an embodiment of the present application. The display device includes a display panel, and further includes: Figure 7 Display controls provided.

[0134] The specific implementation methods described above further illustrate the purpose, technical solutions and beneficial effects of this application. It should be understood that the above description is only the specific implementation methods of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. A display control circuit, applied to a display panel, wherein the display panel is connected to N cascaded drive control modules, characterized in that: include: The display panel is provided with N gate connection lines and N display units, each of the display units includes 2 rows and M columns of pixel units, wherein the conditions N≥1 and M≥3 are satisfied; The drive control module is provided with a gate drive unit and a switch control unit; The input end of the gate driving unit is correspondingly connected to one of the N gate connection lines; One of the gate driving units is correspondingly connected to one of the N display units; The first output terminal of the gate driving unit is connected to the first input terminal of one of the display units, the second output terminal is connected to the first input terminal of the switch control unit, the third output terminal is connected to the second input terminal of the switch control unit, and the fourth output terminal is connected to the sixth input terminal of the display unit; The first output terminal of the switch control unit is connected to the second input terminal of the display unit, the second output terminal is connected to the third input terminal of the display unit, the third output terminal is connected to the fourth input terminal of the display unit, and the fourth output terminal is connected to the fifth input terminal of the display unit; The display unit includes: a first display odd sub-unit, a first display even sub-unit, a second display odd sub-unit, and a second display even sub-unit, wherein the first display odd sub-unit and the first display even sub-unit are pixel units corresponding to odd columns and even columns in a first row and M columns display area of the display unit, and the second display odd sub-unit and the second display even sub-unit are pixel units corresponding to odd columns and even columns in a second row and M columns display area of the display unit; The input terminal of the first display odd sub-unit is connected to the first output terminal of the gate driving unit; The first input terminal of the first display even subunit is connected to the first output terminal of the switch control unit, and the second input terminal is connected to the second output terminal of the switch control unit; The first input terminal of the second display odd sub-unit is connected to the third output terminal of the switch control unit, and the second input terminal is connected to the fourth input terminal of the switch control unit; The input terminal of the second display even sub-unit is connected to the fourth output terminal of the gate driving unit; The display control circuit controls the level of the power signal outputted by the switch control unit so that the display unit switches between the normal DRD display mode and the HSR mode.

2. The circuit according to claim 1, wherein: The gate connection line inputs a gate signal to the gate driving unit, and the gate driving unit inputs the gate signal to the switch control unit. The switch control unit selects and controls the input gate signal and then inputs a control signal to the display unit. The display unit uses the control signal to control the state of the internal pixel unit.

3. The circuit according to claim 1, wherein: The gate connection lines include: a first gate connection line, a second gate connection line, a third gate connection line and a fourth gate connection line; The gate driving unit includes: a first gate driving sub-unit, a second gate driving sub-unit, a third gate driving sub-unit and a fourth gate driving sub-unit, and the first gate driving sub-unit, the second gate driving sub-unit, the third gate driving sub-unit and the fourth gate driving sub-unit have the same structure; The first gate connection line is connected to the input terminal of the first gate driving sub-unit, and the output terminal of the first gate driving sub-unit is connected to the first input terminal of the display unit; The second gate connection line is connected to the input terminal of the second gate driving sub-unit, and the output terminal of the second gate driving sub-unit is connected to the first input terminal of the switch control unit; The third gate connection line is connected to the input end of the third gate driving sub-unit, and the output end of the third gate driving sub-unit is connected to the second input end of the switch control unit; The fourth gate connection line is connected to the input terminal of the fourth gate driving sub-unit, and the output terminal of the fourth gate driving sub-unit is connected to the sixth input terminal of the display unit.

4. The circuit according to claim 1, wherein: The switch control unit includes: a first switch subunit and a second switch subunit; The input end of the first switch subunit is connected to the second output end of the gate driving unit, the first output end is connected to the second input end of the display unit, and the second output end is connected to the third input end of the display unit; The input end of the second switch subunit is connected to the third output end of the gate driving unit, the first output end is connected to the fourth input end of the display unit, and the second output end is connected to the fifth input end of the display unit.

5. The circuit according to claim 4, characterized in that The first switch subunit includes: a first switch transistor and a second switch transistor; A first end of the first switching transistor is connected to the second output end of the gate driving unit and the first end of the second switching transistor, a second end is connected to the output end of the control voltage source and the second end of the second switching transistor, and a third end is connected to the second input end of the display unit; The third terminal of the second switch transistor is connected to the fifth input terminal of the display unit.

6. The circuit according to claim 5, characterized in that The second switch subunit includes: a third switch transistor and a fourth switch transistor, the first switch transistor and the third switch transistor are of the same type, and the second switch transistor and the fourth switch transistor are of the same type; The first end of the third switching transistor is connected to the third output end of the gate driving unit and the first end of the fourth switching transistor, the second end is connected to the output end of the control voltage source and the second end of the fourth switching transistor, and the third end is connected to the third input end of the display unit; The third terminal of the fourth switch transistor is connected to the fourth input terminal of the display unit.

7. The circuit according to claim 3, characterized in that The first gate driving subunit includes: a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, a ninth switching transistor, a tenth switching transistor and a first capacitor; A first end of the fifth switching transistor is connected to the first gate connection end of the upper layer gate driving unit to which the current gate driving unit is cascade-connected, a second end is connected to the output end of the control voltage source and the second end of the sixth switching transistor, and a third end is connected to the third end of the sixth switching transistor and the first end of the seventh switching transistor; The first terminal of the sixth switch transistor is connected to the output terminal of the control voltage source; The second end of the seventh switch transistor is connected to the first gate connection end of the gate driving unit in the upper layer connected in cascade to the current gate driving unit, and the third end and the first end of the ninth switch transistor are connected to the first node; A first end of the eighth switching transistor is connected to the clock signal output end corresponding to the current gate driving unit, a second end is connected to the first node and one end of the first capacitor, and a third end is connected to the other end of the first capacitor, the first end of the tenth switching transistor, and the first gate connection end of the current gate driving unit; The second end of the tenth switching transistor is connected to the second end of the ninth switching transistor and the first gate connection end of the next gate driving unit in the cascade connection of the current gate driving unit, and the third end is connected to the third end of the ninth switching transistor and the output end of the ground voltage source.

8. A display control device, characterized in that: include: A housing and a display control circuit as described in claims 1-7.

9. A display device comprising a display panel, characterized in that: The display device further comprises: a display control device as claimed in claim 8.

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