Display substrate, manufacturing method thereof and display device

Abstract

A display substrate, its manufacturing method, and a display device are disclosed, which can avoid screen abnormalities and belong to the field of display technology. The display substrate includes: a first signal line (07) and a second signal line (09) located in the peripheral region of a substrate; a first insulating layer located on the side of the first signal line (07) away from the substrate; the first signal line (07) and the second signal line (09) are connected by a connecting trace, the connecting trace being located on the side of the first insulating layer away from the substrate, a groove (04) is formed on the side of the first insulating layer away from the substrate, the groove (04) having a depth greater than a preset threshold, and the orthographic projection of the connecting trace on the substrate overlapping the orthographic projection of the groove (04) on the substrate; the connecting trace includes: a first connecting line (15), the first connecting line (15) including a first portion (151) and a second portion (152), wherein the first portion (151) covers the bottom and sidewalls of the groove (04), and the second portion (152) covers the area of ​​the first insulating layer outside the groove (04).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate, a method for manufacturing the same, and a display device. Background Technology

[0002] In touch desktop display products, the addition of a touch module to the display module causes parasitic capacitance between the touch traces and the signal lines of the display module, which can exacerbate staining and other defects. Therefore, it is necessary to introduce an organic film layer between the display module and the touch module to reduce the parasitic capacitance between the touch traces and the signal lines. Summary of the Invention

[0003] The technical problem to be solved by this disclosure is to provide a display substrate and its manufacturing method, as well as a display device, which can avoid screen abnormalities.

[0004] To address the aforementioned technical problems, the embodiments of this disclosure provide the following technical solutions:

[0005] On one hand, a display substrate is provided, comprising a substrate, the substrate including a display area and a peripheral area surrounding the display area, characterized in that the display substrate includes:

[0006] The first signal line and the second signal line are located in the peripheral region of the substrate.

[0007] A first insulating layer is located on the side of the first signal line away from the substrate.

[0008] The first signal line and the second signal line are connected by a connecting trace. The connecting trace is located on the side of the first insulating layer away from the substrate. A groove is formed on the side of the first insulating layer away from the substrate. The groove depth is greater than a preset threshold. The orthographic projection of the connecting trace on the substrate overlaps with the orthographic projection of the groove on the substrate.

[0009] The connection traces include:

[0010] The first connecting line includes a first portion and a second portion, wherein the first portion covers the bottom and sidewalls of the groove, and the second portion covers the area of ​​the first insulating layer outside the groove.

[0011] In some embodiments, the display substrate further includes:

[0012] A second insulating layer located on the side of the first connecting line away from the substrate.

[0013] The connection traces also include:

[0014] A second connecting line is located on the side of the second insulating layer away from the substrate. The second connecting line is connected to the first connecting line through a via penetrating the second insulating layer. The second connecting line is used to connect the first connecting line with the first signal line and the second signal line. The orthographic projection of the second connecting line on the substrate does not overlap with the orthographic projection of the groove on the substrate. The depth of the via is less than the groove depth.

[0015] In some embodiments, the first orthographic projection of the first portion on the substrate is located within the orthographic projection of the groove on the substrate, and the second orthographic projection of the second portion on the substrate is located outside the orthographic projection of the groove on the substrate, wherein the area ratio of the first orthographic projection to the second orthographic projection is 6:1 to 1:1.

[0016] In some embodiments, the extension direction of the first connecting line is parallel to the extension direction of the first signal line.

[0017] In some embodiments, the distance between adjacent first connecting lines is 10-15 μm.

[0018] In some embodiments, the second connecting line includes a cutout area, the extension direction of which is parallel to the extension direction of the second connecting line.

[0019] In some embodiments, the second connecting line includes a third portion and a fourth portion, wherein the third portion has a third orthographic projection on the substrate within the orthographic projection of the first connecting line on the substrate, and the fourth portion has a fourth orthographic projection on the substrate outside the orthographic projection of the first connecting line on the substrate, and the area ratio of the third orthographic projection to the fourth orthographic projection is 1:20-1:25.

[0020] In some embodiments, the second connecting line includes a fifth portion and a sixth portion, wherein the fifth portion has a fifth orthographic projection on the substrate within the orthographic projection of the via on the substrate, and the sixth portion has a sixth orthographic projection on the substrate outside the orthographic projection of the via on the substrate, and the area ratio of the fifth orthographic projection to the sixth orthographic projection is 1:20-1:25.

[0021] In some embodiments, the second connecting line includes a seventh portion and an eighth portion, the seventh portion connecting the first connecting line and the first signal line, the eighth portion connecting the first connecting line and the second signal line, the seventh portion extending in a direction parallel to the first signal line, the eighth portion being L-shaped, and the eighth portion including a first sub-portion parallel to the first signal line and a second sub-portion parallel to the second signal line.

[0022] In some embodiments, the via is a rectangular via with a side length of 6-8 μm.

[0023] In some embodiments, the preset threshold is 2µm.

[0024] In some embodiments, the connection traces are made of a transparent conductive material.

[0025] In some embodiments, the second connection line is in the same layer and made of the same material as the pixel electrode of the display substrate; and / or,

[0026] The first connecting line is in the same layer and made of the same material as the common electrode of the display substrate.

[0027] In some embodiments,

[0028] The first signal line is the clock signal line of the gate driving unit;

[0029] The second signal line is the signal trace for the sector area.

[0030] Embodiments of this disclosure also provide a display device, including the display substrate described above.

[0031] Embodiments of this disclosure also provide a method for manufacturing a display substrate, the display substrate including a substrate, the substrate including a display area and a peripheral area surrounding the display area, the method including:

[0032] A first signal line and a second signal line are formed in the peripheral region of the substrate.

[0033] A first insulating layer is formed on the side of the first signal line away from the substrate.

[0034] A connection trace is formed to connect the first signal line and the second signal line. The connection trace is located on the side of the first insulating layer away from the substrate. A groove is formed on the side of the first insulating layer away from the substrate. The groove depth is greater than a preset threshold. The orthographic projection of the connection trace on the substrate overlaps with the orthographic projection of the groove on the substrate.

[0035] Forming the connection trace includes:

[0036] A first conductive layer is formed on the side of the first insulating layer away from the substrate. A photoresist pattern is formed on the first conductive layer. The photoresist pattern is overexposed. Using the photoresist pattern as a mask, the first conductive layer is etched to form a first connection line. The first connection line includes a first part and a second part, wherein the first part covers the bottom and sidewalls of the groove, and the second part covers the area of ​​the first insulating layer outside the groove.

[0037] In some embodiments, the method further includes:

[0038] A second insulating layer is formed on the side of the first connecting line away from the substrate, and the second insulating layer is patterned to form a via that exposes the first connecting line, wherein the depth of the via is less than the groove depth.

[0039] The formation of the connection trace also includes:

[0040] A second connection line is formed on the side of the second insulating layer away from the substrate. The second connection line is connected to the first connection line through a via penetrating the second insulating layer. The second connection line is used to connect the first connection line with the first signal line and the second signal line. The orthographic projection of the second connection line on the substrate does not overlap with the orthographic projection of the groove on the substrate. The depth of the via is less than the groove depth.

[0041] The embodiments disclosed herein have the following beneficial effects:

[0042] In the above scheme, the first signal line and the second signal line are connected by a first connecting line. The first connecting line does not include the hollow area. When forming the first connecting line, the photoresist on the conductive film layer forming the first connecting line can be overexposed to form the first connecting line, so as to avoid the conductive film layer remaining in the groove, thereby avoiding the residual conductive film layer from short-circuiting different signal lines together, avoiding screen abnormalities, and ensuring the yield of display products. Attached Figure Description

[0043] Figure 1 This is a planar schematic diagram of the display substrate;

[0044] Figure 2 and Figure 3 This is a schematic diagram of a display substrate for related technologies;

[0045] Figure 4 This is a planar schematic diagram of the second transparent conductive layer;

[0046] Figures 5-13 A schematic diagram illustrating the fabrication of a display substrate according to an embodiment of this disclosure.

[0047] Figure Labels

[0048] 01 Display Area

[0049] 02 GOA area

[0050] 03 Power supply voltage line

[0051] 04 Groove

[0052] 05 Second transparent conductive layer

[0053] 07 Clock signal line

[0054] 08, 10 vias

[0055] 09 Signal routing

[0056] 11. Residual second transparent conductive layer

[0057] 12 Organic film layer

[0058] 13 Second Insulation Layer

[0059] 14. Grid insulation layer

[0060] 15 First connecting line

[0061] 151 Part One

[0062] 152 Part Two

[0063] 161-164 vias

[0064] 17 Second connecting line

[0065] 171 Part Seven

[0066] 172 Part Eight

[0067] 173 Part Three

[0068] 174 Part Four

[0069] 175 Part Five

[0070] 176 Part Six

[0071] 18. Hollowed-out area Detailed Implementation

[0072] To make the technical problems, technical solutions and advantages to be solved by the embodiments of this disclosure clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0073] After introducing an organic film layer between the display module and the touch module, a short circuit may occur on the clock signal line surrounding region 02 of the gate drive circuit (GOA). Because the organic film layer is hygroscopic, to prevent external moisture from penetrating the display product, such as... Figure 1As shown, grooves 04 are formed by carving grooves in the organic film layer in the encapsulation area. After applying encapsulating adhesive within the grooves 04, it serves to isolate moisture. The X direction is parallel to one edge of the display substrate, the Y direction is parallel to the other edge of the display substrate, and the Z direction is perpendicular to the display substrate. The X and Y directions are perpendicular, the X and Z directions are perpendicular, and the Y and Z directions are perpendicular. In related technologies, such as... Figure 2 and Figure 3 As shown, the clock signal line 07 on the periphery of the GOA region 02 is connected to the signal trace 09 in the display region 01 through a trace made of the second transparent conductive layer 05. Figure 3 for Figure 2 A cross-sectional view along the AA direction. During trace fabrication, a second transparent conductive layer 05 is formed on the organic film layer 12 with the groove 04. Photoresist is coated on the second transparent conductive layer 05. After exposure and development of the photoresist, a photoresist pattern is formed. Using the photoresist pattern as a mask, the second transparent conductive layer 05 is patterned to form the trace. The trace is connected to the clock signal line 07 through via 08 and to the signal trace 09 through via 10. Due to the relatively large thickness of the organic film layer 12 and the relatively deep groove 04, the photoresist at the bottom of the groove 04 cannot be completely exposed. Figure 2 As shown, this results in the presence of a second transparent conductive layer 11 remaining at the bottom of the groove 04. The remaining second transparent conductive layer 11 will short-circuit different signal lines together, causing abnormal images.

[0074] The embodiments of this disclosure provide a display substrate and its manufacturing method, as well as a display device, which can avoid screen abnormalities.

[0075] Embodiments of this disclosure provide a display substrate, including a substrate, the substrate including a display area and a peripheral area surrounding the display area, the display substrate including:

[0076] The first signal line and the second signal line are located in the peripheral region of the substrate.

[0077] A first insulating layer is located on the side of the first signal line away from the substrate.

[0078] The first signal line and the second signal line are connected by a connecting trace. The connecting trace is located on the side of the first insulating layer away from the substrate. A groove is formed on the side of the first insulating layer away from the substrate. The groove depth is greater than a preset threshold. The orthographic projection of the connecting trace on the substrate overlaps with the orthographic projection of the groove on the substrate.

[0079] The connection traces include:

[0080] The first connecting line includes a first portion and a second portion, wherein the first portion covers the bottom and sidewalls of the groove, and the second portion covers the area of ​​the first insulating layer outside the groove.

[0081] In this embodiment, the first signal line and the second signal line are connected by a first connecting line. The first connecting line does not include a cutout area. When forming the first connecting line, the photoresist on the conductive film layer forming the first connecting line can be overexposed to form the first connecting line, so as to avoid the conductive film layer remaining in the groove, thereby avoiding the residual conductive film layer from short-circuiting different signal lines together, avoiding screen abnormalities, and ensuring the yield of display products.

[0082] The first insulating layer can be an organic film layer located between the display module and the touch module. To reduce parasitic capacitance between the touch traces and signal lines, the thickness of the organic film layer is generally relatively large, such as greater than 2.5 μm, and the depth of the groove is relatively large, generally greater than 2 μm. During the fabrication of the first interconnect, a first conductive layer is formed on the side of the first insulating layer away from the substrate. A photoresist pattern is formed on the first conductive layer. To prevent the first conductive layer from remaining at the bottom of the groove, the photoresist pattern used to form the first interconnect on the first conductive layer is overexposed to ensure that the photoresist at the bottom of the groove is fully exposed. This allows for etching of the first conductive layer to form the first interconnect, thus preventing the first conductive layer from remaining at the bottom of the groove.

[0083] In some embodiments, the display substrate further includes:

[0084] A second insulating layer located on the side of the first connecting line away from the substrate.

[0085] The connection traces also include:

[0086] A second connecting line is located on the side of the second insulating layer away from the substrate. The second connecting line is connected to the first connecting line through a via penetrating the second insulating layer. The second connecting line is used to connect the first connecting line with the first signal line and the second signal line. The orthographic projection of the second connecting line on the substrate does not overlap with the orthographic projection of the groove on the substrate. The depth of the via is less than the groove depth.

[0087] In this embodiment, the first signal line, the second signal line, and the first connecting line are located in different film layers. The first signal line, the second signal line, and the first connecting line are connected by the second connecting line. The second insulating layer can be an inorganic insulating layer. The thickness of the second insulating layer is relatively small, less than the thickness of the first insulating layer. The depth of the via used to connect the first connecting line and the second connecting line is less than the depth of the groove, so that the second conductive layer forming the second connecting line is less likely to remain in the via.

[0088] To avoid affecting the transmittance of the display substrate, transparent conductive materials such as ITO and IZO can be used for the interconnect traces. To avoid increasing the number of patterning processes required for the display substrate, the first and second interconnect traces can be made of the same layer and material as the existing film layers of the display substrate. For example, the second interconnect trace can be made of the same layer and material as the pixel electrode of the display substrate, allowing both the second interconnect trace and the pixel electrode to be formed in a single patterning process. Similarly, the first interconnect trace can be made of the same layer and material as the common electrode of the display substrate, allowing both the first interconnect trace and the common electrode to be formed in a single patterning process.

[0089] In this embodiment, the first signal line and the second signal line can be any signal line on the display substrate that needs to be connected. In some embodiments, the first signal line can be the clock signal line of the gate driving unit; the second signal line can be the signal trace of the fan-shaped area.

[0090] In a specific example, in Figure 1 The position indicated by the dashed box is as follows: Figure 11 and Figure 12 ( Figure 12 for Figure 11 As shown in the cross-sectional diagram in the Z direction (i.e., the cross-section on the YZ plane) along the BB direction, clock signal line 07 and signal trace 09 are connected by connecting traces. The connecting traces include a first connecting line 15 and a second connecting line 17. The first connecting line 15 is connected to the second connecting line 17 via vias 161 and 162, and the extension direction of the first connecting line 15 can be parallel to the extension direction of the signal trace 09. The second connecting line 17 includes a seventh part 171 and an eighth part 172. The seventh part 171 connects the first connecting line 15 and the signal trace 09, and the seventh part 171 is connected to the signal trace 09 via via 163. The connection is made through via 161 to the first connection line 15; the eighth part 172 connects the first connection line 15 and the clock signal line 07, the eighth part 172 is connected to the first connection line 15 through via 162, and connected to the signal trace 07 through via 164; the extension direction of the seventh part 171 is parallel to the signal trace 09, the eighth part 172 is L-shaped, and the eighth part 172 includes a first sub-part parallel to the clock signal line 07 and a second sub-part parallel to the signal trace 09; in some embodiments, the eighth part 172 can be straight and its extension direction is parallel to the clock signal line 07.

[0091] In this embodiment, a plurality of parallel and spaced clock signal lines 07 are provided in the peripheral area of ​​the display substrate. The line width of adjacent clock signal lines 07 may be the same or different from each other, and the spacing between adjacent clock signal lines 07 may be the same or different.

[0092] The vias (including vias 161, 162, 163 and 164) can be elliptical, circular or rectangular. An elliptical via means that the cross-section of the via in the direction parallel to the substrate (the cross-section in the XY plane) is elliptical. A circular via means that the cross-section of the via in the direction parallel to the substrate (the cross-section in the XY plane) is circular. A rectangular via means that the cross-section of the via in the direction parallel to the substrate (the cross-section in the XY plane) is rectangular. In some embodiments, the vias can be rectangular vias, and the side length of the rectangle can be 6-8 μm.

[0093] like Figure 12 As shown, the cross-section of the groove 04 in the direction perpendicular to the substrate (the cross-section on the YZ plane) can be an inverted trapezoid, with the upper side length of the inverted trapezoid being 63 μm and the lower side length being 60 μm, and the groove depth being 2.5 μm. In this embodiment, the first connecting line 15 can be formed using the first transparent conductive layer of the display substrate. The first connecting line 15 covers the sidewalls and bottom of the groove and extends beyond the groove.

[0094] In some embodiments, such as Figure 12 As shown, the first connecting line 15 includes a first part 151 and a second part 152. The first orthographic projection of the first part 151 on the substrate is located within the orthographic projection of the groove on the substrate. The second orthographic projection of the second part 152 on the substrate is located outside the orthographic projection of the groove on the substrate. The area ratio of the first orthographic projection to the second orthographic projection can be 6:1 to 1:1.

[0095] A second insulating layer 13 is formed on the side of the first connecting line 15 away from the substrate. The second insulating layer 13 can be a passivation layer with a thickness of less than 1 μm. A second connecting line 17 is formed on the side of the second insulating layer 13 away from the substrate. The second connecting line 17 can be fabricated using the second transparent conductive layer of the display substrate. Figure 4 As shown, the second transparent conductive layer forming the second connecting line 17 includes a slit-shaped hollow area 18, the extension direction of the hollow area 18 being parallel to the extension direction of the second connecting line 17.

[0096] If the second transparent conductive layer is directly used to form the second connection line 17 to connect the clock signal line 07 and the signal trace 09, in order to avoid the second transparent conductive layer remaining in the groove, the photoresist used to form the second connection line on the second transparent conductive layer needs to be overexposed during the formation of the second connection line. However, if... Figure 4As shown, the second connecting line 17 formed by the second transparent conductive layer 05 includes a slit-shaped cutout area 18. Overexposure will cause the second connecting line 17 to be too thin, resulting in poor circuit breakage. The first connecting line 15, on the other hand, is a complete conductive pattern that does not include the cutout area. Thus, when forming the first connecting line, the photoresist used to form the first connecting line on the first transparent conductive layer can be overexposed to form the first connecting line without causing the first connecting line to break.

[0097] To avoid crosstalk between adjacent first connection lines, the distance between adjacent first connection lines is 10-15µm.

[0098] In this embodiment, as Figure 11 As shown, the line width of the first connecting line 15 can be equal to, slightly larger than, or slightly smaller than the line width of the second connecting line 17. The line width of the second connecting line 17 can be equal to, slightly larger than, or slightly smaller than the line width of the clock signal line 07. The line width of the second connecting line 17 can be equal to, slightly larger than, or slightly smaller than the line width of the signal trace 09.

[0099] In some embodiments, such as Figure 12 As shown, the second connecting line 17 includes a third portion 173 and a fourth portion 174. The third orthographic projection of the third portion 173 on the substrate is located within the orthographic projection of the first connecting line 15 on the substrate. The fourth orthographic projection of the fourth portion 174 on the substrate is located outside the orthographic projection of the first connecting line 15 on the substrate. The area ratio of the third orthographic projection to the fourth orthographic projection is 1:20-1:25.

[0100] In some embodiments, such as Figure 12 As shown, the second connecting line 17 includes a fifth portion 175 and a sixth portion 176. The fifth orthographic projection of the fifth portion 175 on the substrate is located within the orthographic projections of the vias 161 and 162 on the substrate. The sixth orthographic projection of the sixth portion 176 on the substrate is located outside the orthographic projections of the vias 161 and 162 on the substrate. The area ratio of the fifth orthographic projection to the sixth orthographic projection is 1:20-1:25.

[0101] Embodiments of this disclosure also provide a display device, including the display substrate described above.

[0102] The display device includes, but is not limited to, components such as: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Those skilled in the art will understand that the structure of the display device described above does not constitute a limitation on the display device; the display device may include more or fewer of the aforementioned components, or combine certain components, or arrange different components. In the embodiments of this disclosure, the display device includes, but is not limited to, a monitor, a mobile phone, a tablet computer, a television set, a wearable electronic device, a navigation display device, etc.

[0103] The display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes a flexible circuit board, a printed circuit board, and a backplate.

[0104] Embodiments of this disclosure also provide a method for manufacturing a display substrate, comprising:

[0105] The display substrate includes a substrate, the substrate including a display area and a peripheral area surrounding the display area, the method including:

[0106] A first signal line and a second signal line are formed in the peripheral region of the substrate.

[0107] A first insulating layer is formed on the side of the first signal line away from the substrate.

[0108] A connection trace is formed to connect the first signal line and the second signal line. The connection trace is located on the side of the first insulating layer away from the substrate. A groove is formed on the side of the first insulating layer away from the substrate. The groove depth is greater than a preset threshold. The orthographic projection of the connection trace on the substrate overlaps with the orthographic projection of the groove on the substrate.

[0109] Forming the connection trace includes:

[0110] A first conductive layer is formed on the side of the first insulating layer away from the substrate. A photoresist pattern is formed on the first conductive layer. The photoresist pattern is overexposed. Using the photoresist pattern as a mask, the first conductive layer is etched to form a first connection line. The first connection line includes a first part and a second part, wherein the first part covers the bottom and sidewalls of the groove, and the second part covers the area of ​​the first insulating layer outside the groove.

[0111] In this embodiment, the first signal line and the second signal line are connected by a first connecting line. The first connecting line does not include a cutout area. When forming the first connecting line, the photoresist on the conductive film layer forming the first connecting line can be overexposed to form the first connecting line, so as to avoid the conductive film layer remaining in the groove, thereby avoiding the residual conductive film layer from short-circuiting different signal lines together, avoiding screen abnormalities, and ensuring the yield of display products.

[0112] The first insulating layer can be an organic film layer located between the display module and the touch module. To reduce parasitic capacitance between the touch traces and signal lines, the thickness of the organic film layer is generally relatively large, such as greater than 2.5 μm, and the depth of the groove is relatively large, generally greater than 2 μm. During the fabrication of the first interconnect, a first conductive layer is formed on the side of the first insulating layer away from the substrate. A photoresist pattern is formed on the first conductive layer. To prevent the first conductive layer from remaining at the bottom of the groove, the photoresist pattern used to form the first interconnect on the first conductive layer is overexposed to ensure that the photoresist at the bottom of the groove is fully exposed. This allows for etching of the first conductive layer to form the first interconnect, thus preventing the first conductive layer from remaining at the bottom of the groove.

[0113] In some embodiments, the method further includes:

[0114] A second insulating layer is formed on the side of the first connecting line away from the substrate, and the second insulating layer is patterned to form a via that exposes the first connecting line, wherein the depth of the via is less than the groove depth.

[0115] The formation of the connection trace also includes:

[0116] A second connection line is formed on the side of the second insulating layer away from the substrate. The second connection line is connected to the first connection line through a via penetrating the second insulating layer. The second connection line is used to connect the first connection line with the first signal line and the second signal line. The orthographic projection of the second connection line on the substrate does not overlap with the orthographic projection of the groove on the substrate. The depth of the via is less than the groove depth.

[0117] In this embodiment, the first signal line, the second signal line, and the first connecting line are located in different film layers. The first signal line, the second signal line, and the first connecting line are connected by the second connecting line. The second insulating layer can be an inorganic insulating layer. The thickness of the second insulating layer is relatively small, less than the thickness of the first insulating layer. The depth of the via used to connect the first connecting line and the second connecting line is less than the depth of the groove, so that the second conductive layer forming the second connecting line is less likely to remain in the via.

[0118] To avoid affecting the transmittance of the display substrate, transparent conductive materials such as ITO and IZO can be used for the interconnect traces. To avoid increasing the number of patterning processes required for the display substrate, the first and second interconnect traces can be made of the same layer and material as the existing film layers of the display substrate. For example, the second interconnect trace can be made of the same layer and material as the pixel electrode of the display substrate, allowing both the second interconnect trace and the pixel electrode to be formed in a single patterning process. Similarly, the first interconnect trace can be made of the same layer and material as the common electrode of the display substrate, allowing both the first interconnect trace and the common electrode to be formed in a single patterning process.

[0119] In this embodiment, the first signal line and the second signal line can be any signal line on the display substrate that needs to be connected. In some embodiments, the first signal line can be the clock signal line of the gate driving unit; the second signal line can be the signal trace of the fan-shaped area.

[0120] In a specific example, such as Figures 5-12 As shown, the manufacturing method of this embodiment includes the following steps:

[0121] Step 1, as follows Figure 5 As shown, an organic film layer 12 is formed on the display substrate where clock signal line 07 and signal trace 09 are formed. Grooves 04 are formed in the organic film layer 12. Figure 6 for Figure 5 A cross-sectional schematic diagram in the BB direction, wherein the organic film layer 12 is located on the gate insulating layer 14;

[0122] Step 2, as follows Figure 7 and Figure 8 As shown, the first connecting line 15 is formed;

[0123] Specifically, a first transparent conductive layer can be formed on the display substrate after step 1. The first transparent conductive layer can be ITO, IZO, or other transparent metal oxides. A layer of photoresist is coated on the first transparent conductive layer. The photoresist is exposed using a mask to form areas where the photoresist is not retained and areas where it is retained. The areas where the photoresist is retained correspond to the area where the first connection line 15 is located, and the areas where the photoresist is not retained correspond to the areas outside the aforementioned pattern. A development process is performed to completely remove the photoresist in the areas where the photoresist is not retained, while the thickness of the photoresist in the areas where the photoresist is retained remains unchanged. The first transparent conductive layer is etched using the photoresist as a mask to form the first connection line 15. When exposing the photoresist, the exposure amount is increased to avoid any first transparent conductive layer residue at the bottom of the groove through overexposure.

[0124] Figure 8 for Figure 7 A schematic diagram of the cross-section in the BB direction, where, as shown... Figure 13As shown, the portion of the first connecting line 15 that overlaps the sidewall of the groove can be smooth.

[0125] Step 3, as follows Figure 9 and Figure 10 As shown, a second insulating layer 13 is formed;

[0126] Specifically, a film thickness of [thickness value missing] can be deposited on the display substrate after step 2 using magnetron sputtering, thermal evaporation, PECVD, or other film deposition methods. The passivation layer serves as the second insulating layer 13. The passivation layer can be an oxide, nitride, or oxynitride compound. Specifically, the passivation layer material can be SiNx, SiOx, or Si(ON)x, and Al2O3 can also be used. The passivation layer can be a single-layer structure or a two-layer structure composed of silicon nitride and silicon oxide. The reaction gas corresponding to the silicon oxide can be SiH4 or N2O; the gas corresponding to the nitride or oxynitride compound can be SiH4, NH3, N2, or SiH2Cl2, NH3, N2. A pattern including a passivation layer with vias is formed through a single patterning process, exposing the first connection line 15.

[0127] in, Figure 10 for Figure 9 A schematic diagram of the cross-section in the BB direction.

[0128] Step 4, as follows Figure 11 and Figure 12 As shown, a second connecting line 17 is formed.

[0129] Specifically, a thickness of approximately [thickness missing] is deposited on the display substrate after step 3 by sputtering or thermal evaporation. The second transparent conductive layer can be ITO, IZO, or other transparent metal oxides. A photoresist layer is coated on the second transparent conductive layer. The photoresist is exposed using a mask to form a photoresist non-retained area and a photoresist retained area. The photoresist retained area corresponds to the area where the pattern of the second connection line 17 is located, and the photoresist non-retained area corresponds to the area outside the pattern. A development process is performed to completely remove the photoresist in the non-retained area, while the photoresist thickness in the retained area remains unchanged. The transparent conductive layer film in the non-retained area is completely etched away by an etching process, and the remaining photoresist is peeled off to form the second connection line 17. The second connection line 17 is connected to the first connection line 15 through vias 161 and 162.

[0130] In this embodiment, a connection trace is formed by the first connection line 15 and the second connection line 17, connecting the signal trace 09 and the clock signal line 07. Since the first connection line 15 is a complete conductive pattern without any hollow areas, the photoresist used to form the first connection line on the first transparent conductive layer can be overexposed to form the first connection line, thus avoiding the first transparent conductive layer remaining in the groove, which could cause the signal line to short-circuit.

[0131] In this embodiment, a plurality of parallel and spaced clock signal lines 07 are provided in the peripheral area of ​​the display substrate. The line width of adjacent clock signal lines 07 may be the same or different from each other, and the spacing between adjacent clock signal lines 07 may be the same or different.

[0132] The vias (including vias 161, 162, 163 and 164) can be elliptical, circular or rectangular. An elliptical via means that the cross-section of the via in the direction parallel to the substrate (the cross-section in the XY plane) is elliptical. A circular via means that the cross-section of the via in the direction parallel to the substrate (the cross-section in the XY plane) is circular. A rectangular via means that the cross-section of the via in the direction parallel to the substrate (the cross-section in the XY plane) is rectangular. In some embodiments, the vias can be rectangular vias, and the side length of the rectangle can be 6-8 μm.

[0133] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, since the embodiments are basically similar to the product embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the product embodiments.

[0134] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0135] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0136] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0137] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising a substrate, the substrate including a display area and a peripheral area surrounding the display area, characterized in that, The display substrate includes: The first signal line and the second signal line are located in the peripheral region of the substrate. A first insulating layer is located on the side of the first signal line away from the substrate. The first signal line and the second signal line are connected by a connecting trace. The connecting trace is located on the side of the first insulating layer away from the substrate. A groove is formed on the side of the first insulating layer away from the substrate. The groove depth is greater than a preset threshold. The orthographic projection of the connecting trace on the substrate overlaps with the orthographic projection of the groove on the substrate. The connection traces include: A first connecting line, comprising a first portion and a second portion, wherein the first portion covers the bottom and sidewalls of the groove, and the second portion covers the area outside the groove where the first insulating layer is located; A second insulating layer located on the side of the first connecting line away from the substrate. The connection traces also include: A second connecting line is located on the side of the second insulating layer away from the substrate. The second connecting line is connected to the first connecting line through a via penetrating the second insulating layer. The second connecting line is used to connect the first connecting line with the first signal line and the second signal line. The orthographic projection of the second connecting line on the substrate does not overlap with the orthographic projection of the groove on the substrate. The depth of the via is less than the groove depth.

2. The display substrate according to claim 1, characterized in that, The first orthographic projection of the first part on the substrate is located within the orthographic projection of the groove on the substrate, and the second orthographic projection of the second part on the substrate is located outside the orthographic projection of the groove on the substrate. The area ratio of the first orthographic projection to the second orthographic projection is 6:1 to 1:

1.

3. The display substrate according to claim 1, characterized in that, The extension direction of the first connecting line is parallel to the extension direction of the first signal line.

4. The display substrate according to claim 1, characterized in that, The distance between adjacent first connecting lines is 10-15 μm.

5. The display substrate according to claim 1, characterized in that, The second connecting line includes a hollow area, and the extension direction of the hollow area is parallel to the extension direction of the second connecting line.

6. The display substrate according to claim 5, characterized in that, The second connecting line includes a third part and a fourth part. The third part has a third orthographic projection on the substrate within the orthographic projection of the first connecting line on the substrate. The fourth part has a fourth orthographic projection on the substrate outside the orthographic projection of the first connecting line on the substrate. The area ratio of the third orthographic projection to the fourth orthographic projection is 1:20-1:

25.

7. The display substrate according to claim 5, characterized in that, The second connecting line includes a fifth part and a sixth part. The fifth orthographic projection of the fifth part on the substrate is located within the orthographic projection of the via on the substrate. The sixth orthographic projection of the sixth part on the substrate is located outside the orthographic projection of the via on the substrate. The area ratio of the fifth orthographic projection to the sixth orthographic projection is 1:20-1:

25.

8. The display substrate according to claim 5, characterized in that, The second connecting line includes a seventh part and an eighth part. The seventh part connects the first connecting line and the first signal line, and the eighth part connects the first connecting line and the second signal line. The extension direction of the seventh part is parallel to the first signal line. The eighth part is L-shaped and includes a first sub-part parallel to the first signal line and a second sub-part parallel to the second signal line.

9. The display substrate according to claim 1, characterized in that, The via is a rectangular via with a side length of 6-8 μm.

10. The display substrate according to claim 1, characterized in that, The preset threshold is 2µm.

11. The display substrate according to claim 1, characterized in that, The connection traces are made of transparent conductive material.

12. The display substrate according to claim 1, characterized in that, The second connecting line is in the same layer and made of the same material as the pixel electrode of the display substrate; and / or, The first connecting line is in the same layer and made of the same material as the common electrode of the display substrate.

13. The display substrate according to claim 1, characterized in that, The first signal line is the clock signal line of the gate driving unit; The second signal line is the signal trace for the sector area.

14. A display device, characterized in that, Includes the display substrate as described in any one of claims 1-13.

15. A method for manufacturing a display substrate, characterized in that, The display substrate includes a substrate, the substrate including a display area and a peripheral area surrounding the display area, the method including: A first signal line and a second signal line are formed in the peripheral region of the substrate. A first insulating layer is formed on the side of the first signal line away from the substrate. A connection trace is formed to connect the first signal line and the second signal line. The connection trace is located on the side of the first insulating layer away from the substrate. A groove is formed on the side of the first insulating layer away from the substrate. The groove depth is greater than a preset threshold. The orthographic projection of the connection trace on the substrate overlaps with the orthographic projection of the groove on the substrate. Forming the connection trace includes: A first conductive layer is formed on the side of the first insulating layer away from the substrate. A photoresist pattern is formed on the first conductive layer. The photoresist pattern is overexposed. Using the photoresist pattern as a mask, the first conductive layer is etched to form a first connection line. The first connection line includes a first part and a second part, wherein the first part covers the bottom and sidewalls of the groove, and the second part covers the area of ​​the first insulating layer outside the groove. A second insulating layer is formed on the side of the first connecting line away from the substrate, and the second insulating layer is patterned to form a via that exposes the first connecting line, wherein the depth of the via is less than the groove depth. The formation of the connection trace also includes: A second connection line is formed on the side of the second insulating layer away from the substrate. The second connection line is connected to the first connection line through a via penetrating the second insulating layer. The second connection line is used to connect the first connection line with the first signal line and the second signal line. The orthographic projection of the second connection line on the substrate does not overlap with the orthographic projection of the groove on the substrate. The depth of the via is less than the groove depth.

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