A data transmission method, apparatus, device, and storage medium

Abstract

The application discloses a data transmission method and device, equipment and storage medium, and is applied to a high-speed serial point-to-point double-channel PCIE system. The PCIE system comprises a sending end, a direct memory access (DMA) control end and a receiving end. The method is executed by the sending end and comprises the following steps: when it is determined that the current sending condition is met based on a preset sending buffer queue, current to-be-sent data in the sending buffer queue is determined by a woken sending thread; data description information corresponding to the current to-be-sent data is filled into a chain buffer table of the DMA control end, so that the current to-be-sent data is transmitted to the receiving end by the DMA control end; and a blocking state is entered until a receiving feedback signal sent by the receiving end is received, and then the determination operation of the current to-be-sent data is returned to be executed again. The above technical scheme guarantees the safety and reliability of data transmission, improves the efficiency of data transmission, and can be applied to various data transmission scenes.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a data transmission method, apparatus, device, and storage medium. Background Technology

[0002] Currently, when end-to-end devices transmit data, they can use high-speed serial point-to-point dual-channel (Peripheral Component Interconnect Express, PCIE) PCIE transmission. PCIE transmission mainly relies on the Direct Memory Access (DMA) feature to transmit data from the sending end to the receiving end.

[0003] PCIe transfers that rely on DMA are essentially initiated by the sending end, which then transmits the data to the receiving end based on the DMA feature. However, the receiving end does not provide feedback on the reception status of the received data, making it impossible for the sending end to know the reception status. This can easily lead to the problem that the transmitted data is not received by the receiving end, affecting the reliability of data transmission. Summary of the Invention

[0004] This invention provides a data transmission method, apparatus, device, and storage medium, which solves the problem that the transmitting end cannot know the receiving status, resulting in the transmitted data not being received by the receiving end. It ensures the security and reliability of data transmission, improves the efficiency of data transmission, and can be applied to various data transmission scenarios.

[0005] In a first aspect, embodiments of this disclosure provide a data transmission method applied to a high-speed serial point-to-point dual-channel PCIe system. The PCIe system includes a transmitting end, a direct memory access (DMA) control end, and a receiving end. The method is executed by the transmitting end and includes:

[0006] When the sending conditions are met based on the preset sending buffer queue, the currently pending data in the sending buffer queue is determined by the awakened sending thread;

[0007] The data description information corresponding to the current data to be sent is filled into the linked cache table of the DMA control terminal, so that the current data to be sent can be transmitted to the receiving terminal through the DMA control terminal;

[0008] The system enters a blocking state until it receives a reception feedback signal from the receiving end, after which it returns and re-executes the operation to determine the current data to be sent.

[0009] Secondly, embodiments of this disclosure provide a data transmission method applied to a high-speed serial point-to-point dual-channel PCIe system. The PCIe system includes a transmitting end, a direct memory access (DMA) control end, and a receiving end. The method is executed by the receiving end and includes:

[0010] After receiving the transmission completion signal sent by the DMA control terminal, the awakened receiving thread fills the determined data information into the receiving buffer. The transmission completion signal is generated by the DMA control terminal after transmitting the data to be sent from the linked buffer table to the receiving terminal.

[0011] After detecting a message signal indicating successful data filling, the filling length is determined and the set data description information is filled into the linked cache table according to the filling length;

[0012] Send a reception feedback signal to the sending end so that the sending end can start a new round of data transmission operations.

[0013] Thirdly, embodiments of this disclosure provide a data transmission device integrated into a high-speed serial point-to-point dual-channel PCIe system. The PCIe system includes a transmitting end, a direct memory access (DMA) control end, and a receiving end. The data transmission device is the transmitting end, comprising:

[0014] The data determination module is used to determine the current data to be sent in the sending buffer queue by waking up the sending thread when it is determined that the sending conditions are met based on the preset sending buffer queue.

[0015] The data transmission module is used to fill the data description information corresponding to the currently to be transmitted data into the linked cache table of the DMA control terminal, so as to transmit the currently to be transmitted data to the receiving terminal through the DMA control terminal;

[0016] The feedback signal receiving module is used to enter a blocking state until it receives the reception feedback signal sent by the receiving end, and then returns to re-execute the determination operation of the current data to be sent.

[0017] Fourthly, embodiments of this disclosure provide a data transmission device integrated into a high-speed serial point-to-point dual-channel PCIe system. The PCIe system includes a transmitting end, a direct memory access (DMA) control end, and a receiving end. The data transmission device is the receiving end and includes:

[0018] The receive buffer filling module is used to fill the received buffer with the determined data information through the awakened receiving thread after receiving the transmission completion signal sent by the DMA control terminal. The transmission completion signal is generated by the DMA control terminal after transmitting the data to be sent cached in the linked buffer table to the receiving terminal.

[0019] The chained cache filling module is used to determine the filling length and fill the chained cache table with the set data description information according to the filling length after detecting the message signal of successful data filling;

[0020] The feedback signal sending module is used to send a reception feedback signal to the sending end so that the sending end can start a new round of data transmission operation.

[0021] Fifthly, embodiments of this disclosure provide an electronic device, including:

[0022] At least one processor; and

[0023] A memory that is communicatively connected to at least one processor; wherein,

[0024] The memory stores a computer program that can be executed by at least one processor, such that the at least one processor is able to perform the data transmission method provided in the first and / or second aspect embodiments described above.

[0025] In a sixth aspect, embodiments of this disclosure provide a computer-readable storage medium storing computer instructions that, when executed by a processor, implement the data transmission method provided in the first and / or second aspect embodiments described above.

[0026] This invention discloses a data transmission method, apparatus, device, and storage medium. When a preset transmission buffer queue determines that the current transmission conditions are met, a woken-up transmission thread determines the currently pending data in the transmission buffer queue. The data description information corresponding to the currently pending data is filled into a linked cache table of a DMA control terminal, so that the currently pending data is transmitted to the receiving terminal via the DMA control terminal. A blocking state is entered until a reception feedback signal is received from the receiving terminal, after which the process returns and re-executes the determination operation for the currently pending data. This technical solution solves the problem of the transmitting end being unable to know the receiving status, resulting in the transmitted data not being received by the receiving end. It ensures the security and reliability of data transmission, improves data transmission efficiency, and can be applied to various data transmission scenarios.

[0027] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a flowchart of a data transmission method provided in Embodiment 1 of the present invention;

[0030] Figure 2 This is a flowchart illustrating the sending function call involved in a data transmission method provided in Embodiment 1 of the present invention;

[0031] Figure 3 This is a flowchart illustrating the sending thread involved in a data transmission method provided in Embodiment 1 of the present invention.

[0032] Figure 4 This is a flowchart of a data transmission method provided in Embodiment 2 of the present invention;

[0033] Figure 5 This is a flowchart illustrating the receiving function call involved in a data transmission method provided in Embodiment 2 of the present invention;

[0034] Figure 6 This is a flowchart illustrating the receiving thread involved in a data transmission method provided in Embodiment 2 of the present invention.

[0035] Figure 7 This is a schematic diagram of a data transmission link provided in an embodiment of the present invention;

[0036] Figure 8 This is a schematic diagram of the structure of a data transmission device provided in Embodiment 3 of the present invention;

[0037] Figure 9 This is a schematic diagram of the structure of a data transmission device provided in Embodiment 4 of the present invention;

[0038] Figure 10 This is a schematic diagram of the structure of an electronic device provided in Embodiment 5 of the present invention. Detailed Implementation

[0039] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0040] It should be noted that the terms "first," "second," and "target," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0041] Example 1

[0042] Figure 1 This is a flowchart of a data transmission method provided in Embodiment 1 of the present invention. This embodiment is applicable to situations where data transmission is performed at the sending end and is applied to a high-speed serial point-to-point dual-channel PCIe system. The method can be executed by the data transmission device corresponding to the sending end in the high-speed serial point-to-point dual-channel PCIe system, and the device can be implemented in hardware and / or software.

[0043] In this embodiment, the high-speed serial point-to-point dual-channel PCIe system can be understood as a high-bandwidth transmission system based on PCIe, including a transmitter, a Direct Memory Access (DMA) controller, and a receiver. In the PCIe system, the transmitter transmits data to be transmitted to the DMA controller. The DMA controller then moves the data to the receiver, and the receiver feeds back the reception status to the transmitter, thus completing one data transmission. The transmitter is a data sending device or apparatus, primarily used to send data, enabling the data to be transmitted to the receiver via the DMA controller. The receiver is a data receiving device or apparatus, primarily used to receive data sent by the transmitter via the DMA controller and send a reception feedback signal to the transmitter. The DMA controller is a unique peripheral that transfers data within the system; it can be considered a controller that connects internal and external memory to each DMA-capable peripheral via a set of dedicated buses.

[0044] like Figure 1 As shown, the method includes:

[0045] S101. When it is determined that the current sending conditions are met based on the preset sending buffer queue, the current data to be sent in the sending buffer queue is determined by the awakened sending thread.

[0046] In this embodiment, the preset send buffer queue can be understood as a pre-determined buffer queue of data to be sent. The sending condition can be understood as the condition used to wake up the sending thread; for example, it could be that the send buffer queue is not empty, or other conditions. The sending condition is determined according to actual needs, and this embodiment does not impose any limitations on it. The sending thread can be understood as the process of initiating the sending of the data to be sent. The sending thread is a kernel thread in kernel mode, responsible for transferring the data in the sender's send buffer queue to the receiver via the DMA chain. The current data to be sent can be understood as the data used for data transmission between the sender and receiver, sent by the sender, handled by the DMA control unit, and received by the receiver.

[0047] Specifically, it determines whether the preset sending buffer queue meets the sending conditions at the current moment. If so, it wakes up the sending thread, starts to execute the data transmission operation, and determines the quantity and size of the data to be sent in the sending buffer queue for the current data transmission. If not, the sending thread is blocked and the sending end does not take any action.

[0048] For example, when the sending condition is that the sending buffer queue is not empty, it is determined whether the preset sending buffer queue at the current moment meets the sending condition, that is, whether there is data in the sending buffer queue. If the sending condition is met and there is data in the sending buffer queue, the sending thread is woken up to determine the data to be sent in the sending buffer queue; if the sending condition is not met and there is no data in the sending buffer queue, the sending thread is blocked and the sending end does not take any action.

[0049] S102. Fill the data description information corresponding to the data to be sent into the linked cache table of the DMA control terminal, so as to transmit the data to be sent to the receiving terminal through the DMA control terminal.

[0050] In this embodiment, the data description information can be understood as information used to describe the data to be sent, such as the source address and data transmission length of the data to be sent. The linked cache table can be understood as a DMA-based linked structure that can store the contents of multiple data blocks. The linked cache table can store the data description information of the data to be sent, as well as data information generated by the receiving device.

[0051] Specifically, after determining the data to be sent, the determined data is transmitted from the sending end to the DMA control end. Simultaneously, the source address and data transfer length of the data to be transmitted are filled into the linked buffer table of the DMA control end, so that the corresponding data information can be directly retrieved based on the source address during data retrieval. The DMA control end then transmits the data to be transmitted, along with the source address and data transfer length filled into the linked buffer table, to the receiving end.

[0052] S103. Enter the blocking state until a reception feedback signal is received from the receiving end, then return to re-execute the determination operation of the current data to be sent.

[0053] In this embodiment, the blocking state can be understood as a data transmission interruption state, where the sending end suspends data transmission. The receive feedback signal can be understood as a signal indicating that the receiving end has received the currently to-be-sent data transmitted by the DMA control end and completed the corresponding storage processing; it is a feedback signal issued by the receiving end.

[0054] Specifically, after the sending end completes the transmission of the current data to be transmitted and its corresponding data description information, it enters a blocking state and suspends the next data transmission until it receives a reception feedback signal from the receiving end indicating that the receiving end has received the data and completed the corresponding storage processing. Then, it unblocks and returns to re-execute the determination operation of the current data to be transmitted as shown in step S101 until the data transmission is completely completed.

[0055] In this embodiment, when the sending conditions are met based on a preset sending buffer queue, the awakened sending thread determines the data to be sent in the sending buffer queue. The data description information corresponding to the data to be sent is filled into the linked cache table of the DMA control terminal, so that the data to be sent is transmitted to the receiving terminal via the DMA control terminal. The thread enters a blocking state until a reception feedback signal is received from the receiving terminal, after which it returns and re-executes the determination operation for the data to be sent. This technical solution solves the problem of the sending terminal being unable to know the receiving status, resulting in the transmitted data not being received by the receiving terminal. It ensures the security and reliability of data transmission, improves data transmission efficiency, and can be applied to various data transmission scenarios.

[0056] As a first optional embodiment of the embodiments, based on the above embodiments, this first optional embodiment further optimizes and adds: the sending condition is that the sending buffer queue is not empty; correspondingly, determining the current data to be sent in the sending buffer queue includes:

[0057] a1) Determine the number of data blocks currently cached in the send buffer queue, and compare the number of blocks with the current available length of the linked list of the linked cache table.

[0058] In this embodiment, the number of currently cached data blocks can be understood as the number of data blocks to be sent in the sending cache queue. The current available length of the linked list can be understood as the current usable length of the linked cache table, for example, 64 nodes. It can be understood that each node in the linked cache table can correspond to one data block.

[0059] The sending condition is that the sending buffer queue is not empty. Therefore, when it is determined that the sending buffer queue currently meets the sending condition, that is, the sending buffer queue is currently not empty, the currently waiting data in the sending buffer queue is determined by the awakened sending thread.

[0060] Specifically, before sending data to the DMA controller, it is necessary to determine the data capacity that the DMA controller can transmit, i.e., the current available length of the linked list in the linked cache table. The number of data blocks currently cached in the send buffer queue is compared with the current available length of the linked list in the linked cache table to obtain the comparison result, thus determining the DMA controller's data block transmission capacity.

[0061] For example, the maximum transmission length for each node in the chain is 1 megabyte, and the maximum chain length (number of nodes) is 64. Before each transmission, the chain length and the transmission length for each node are configured according to the actual situation. Each node's configuration includes a source address, a destination address, and a transmission length. The source address and transmission length are data description information configured by the sender, while the destination address is data description information configured by the receiver.

[0062] b1) If the number of blocks is less than the current available length of the linked list, then the currently cached data block is used as the current data to be sent; otherwise, proceed to step c1).

[0063] In this embodiment, the number of blocks is compared with the current available length of the linked list of the linked cache table. After obtaining the comparison result, if the number of blocks is less than the current available length of the linked list, it can be determined that the linked cache table is capable of transmitting all data blocks in the sending cache queue at one time. Then, the currently cached data block is taken as the data to be sent.

[0064] For example, if the number of data blocks currently cached in the send buffer queue is 40 and the current available length of the linked cache table is 64, then all (40) currently cached data blocks in the send buffer queue will be used as the data to be sent.

[0065] c1) Take a data block from the send buffer queue that has the same length as the currently available length of the linked list as the current data to be sent.

[0066] In this embodiment, the number of blocks is compared with the current available length of the linked list of the linked cache table. After obtaining the comparison result, if the number of blocks is greater than the current available length of the linked list, it can be determined that the linked cache table cannot complete the transmission of all data blocks in the sending cache queue at one time. The minimum value between the number of blocks and the current available length is taken, i.e., the current available length. The data block with the same current available length as the linked list is taken from the sending cache queue as the current data to be sent.

[0067] For example, if the number of data blocks currently cached in the send buffer queue is 72 and the current available length of the linked list in the linked cache table is 64, then 64 currently cached data blocks in the send buffer queue are taken as the current data to be sent.

[0068] As a second optional embodiment, based on the above embodiment, this second optional embodiment further optimizes and adds the following:

[0069] a2) After listening to the initiated data transmission request in user mode, the send function is called through the interface function to enter kernel mode.

[0070] In this embodiment, to restrict access between different programs and prevent them from accessing other programs' memory data or peripheral device data and sending it to the network, the Central Processing Unit (CPU) is divided into two permission levels: user mode and kernel mode. User mode is the human-computer interaction level, allowing only limited access to memory and prohibiting access to peripheral devices. CPU usage is restricted, and CPU resources can be acquired by other programs. Kernel mode is the computer-level permission level, where the CPU can access all data in memory, including peripheral devices such as hard drives and network cards. The CPU can also switch itself from one program to another. A data transmission request can be understood as a request to send data. An interface function can be understood as a program interface used to implement calls to other application functions. A send function can be understood as a function used to send data and start a sending thread; it is a function used to switch between user mode and kernel mode, similar to the sending and receiving of a socket.

[0071] Specifically, after listening for a data sending request initiated by the user in user space, the sending function is called through the interface function to enter kernel space and start the sending thread.

[0072] b2) Input buffered data blocks into the send buffer queue in kernel mode through the send function.

[0073] In this embodiment, the sending thread is called through the sending function in kernel mode to input the buffered data block into the sending buffer queue, and data transmission begins in kernel mode, executing steps S101-103.

[0074] For example, Figure 2 This is a flowchart illustrating the sending function call involved in a data transmission method provided in Embodiment 1 of the present invention; Figure 3 This is a flowchart illustrating the sending thread involved in a data transmission method provided in Embodiment 1 of the present invention; as shown... Figure 2As shown, the process involves calling the send function in user mode to enter kernel mode and wake up the sending thread for data transmission. This includes: S10, execution of the user-mode send function: After listening for the initiated data transmission request in user mode, the send function is called through the interface function; S11, entering kernel mode: The send function called through the interface function switches from user mode to kernel mode; S12, whether the data copy to the send buffer queue is successful: After entering kernel mode, the send function inputs the buffered data block to the send buffer queue in kernel mode and determines whether the buffered data block has been successfully copied to the send buffer queue; if yes, then S13, return success: the send function returns success; if no, then S14, return failure: the send function returns failure.

[0075] In execution such Figure 2 In the flowchart shown, after S13 returns a successful response, it is confirmed that the cached data block has been successfully copied to the send cache queue. At this point, as follows... Figure 3 As shown, the sending thread is awakened, and data transmission is performed according to the sending thread, including: S131, blocking (whether the sending condition is met): Entering the blocking state, it is determined whether the preset sending buffer queue meets the sending condition at the current moment, that is, whether the sending buffer queue is not empty. If yes, step S132 is executed; if no, the blocking state is maintained. S132, taking the smaller value between the number of currently cached data blocks in the sending buffer queue and the current available length of the linked list of the linked cache table: Determine the number of currently cached data blocks in the sending buffer queue, compare the number of blocks with the current available length of the linked list of the linked cache table. If the number of blocks is less than the current available length of the linked list, the currently cached data block is taken as the data to be sent; otherwise, it is taken from the sending buffer queue. S133. Take out a data block with the same available length as the current data to be sent from the linked list as the current data to be sent; S134. Fill the data description information of the current data to be sent into the linked buffer table of the DMA control terminal: Fill the data description information corresponding to the current data to be sent into the linked buffer table of the DMA control terminal so as to transmit the current data to be sent to the receiving end through the DMA control terminal; S135. Start sending: After the data filling of the linked list is completed, start sending, and continue to enter the blocking state after sending; S136. Block (whether the receiving feedback signal is received): Determine whether the receiving feedback signal sent by the receiving end is received. If yes, return to re-execute step S131 and enter the next round of data transmission. If no, keep the blocking state until the receiving feedback signal is received.

[0076] Example 2

[0077] Figure 4This is a flowchart of a data transmission method provided in Embodiment 2 of the present invention. This embodiment is applicable to situations where data transmission is performed at the receiving end and is applied to a high-speed serial point-to-point dual-channel PCIe system. The method can be executed by the data transmission device corresponding to the receiving end in the high-speed serial point-to-point dual-channel PCIe system, and the device can be implemented in hardware and / or software.

[0078] In this embodiment, the high-speed serial point-to-point dual-channel PCIe system can be understood as a high-bandwidth transmission system based on PCIe, including a transmitter, a Direct Memory Access (DMA) controller, and a receiver. In the PCIe system, the transmitter transmits data to be transmitted to the DMA controller. The DMA controller then moves the data to the receiver, and the receiver feeds back the reception status to the transmitter, thus completing one data transmission. The transmitter is a data sending device or apparatus, primarily used to send data, enabling the data to be transmitted to the receiver via the DMA controller. The receiver is a data receiving device or apparatus, primarily used to receive data sent by the transmitter via the DMA controller and send a reception feedback signal to the transmitter. The DMA controller is a unique peripheral that transfers data within the system; it can be considered a controller that connects internal and external memory to each DMA-capable peripheral via a set of dedicated buses.

[0079] like Figure 2 As shown, the method includes:

[0080] S201. After receiving the transmission completion signal sent by the DMA control terminal, the awakened receiving thread fills the determined data information into the receiving buffer. The transmission completion signal is generated by the DMA control terminal after transmitting the data to be sent from the linked buffer table to the receiving terminal.

[0081] In this embodiment, the transmission completion signal can be understood as a signal indicating that the DMA control has transmitted the data sent by the sender to the receiver. The receiving thread can be understood as the process of receiving the data transmitted by the sender. The receiving thread is a kernel thread in kernel mode, responsible for storing the data in the linked cache table of the DMA control into the receive buffer. Data information can be understood as the data information of the transmitted data (data to be sent), such as the data storage address of the transmitted data in a designated storage area, or other information; this embodiment does not limit this. The receive buffer can be understood as a buffer that receives and stores the data information of the transmitted data, corresponding to the send buffer (send buffer queue). It can be understood that the send buffer stores the data itself, while the receive buffer stores the data information of the data.

[0082] Specifically, after the DMA controller transmits the data to be sent from the linked buffer to the receiver, it generates a transmission completion signal. Upon receiving the transmission completion signal from the DMA controller, the receiver determines that the DMA controller has completed the data transfer. The awakened receiver thread verifies whether the receiver has received the data. If the data is received, the data information of the data transmitted from the DMA controller to the receiver is filled into the receiver buffer, so that the data can be directly accessed through the data information in the receiver buffer when the data is used.

[0083] S202. After detecting a message signal indicating successful data filling, determine the filling length and fill the linked cache table with the set data description information according to the filling length.

[0084] In this embodiment, the message signal can be understood as a signal generated by the sending end indicating that data information has been filled into the receive buffer, signifying that the data transmission has been successfully completed. The fill length can be understood as the number of data blocks filled in the receive buffer. The data description information can be understood as the destination address of the data, i.e., the address of the data in the receive buffer, to facilitate data transmission from the DMA control end to the sending end.

[0085] Specifically, after detecting a message signal indicating successful data filling, it is determined that the data transmission has been successfully completed. At this point, the length already filled in the receive buffer is determined, and the unfilled length is determined based on the filled length. The set data description information is then filled into the linked buffer table based on the unfilled length and the available length of the linked list in the linked buffer table. This ensures that in the next data transmission, the DMA controller can directly perform data transmission from the DMA controller to the receiver based on the set data description information stored in the linked buffer table.

[0086] It is understandable that the filling of the data description information in the linked cache table is based on the previous data transmission process. In the first data transmission, the filling of the data description information in the linked cache table can be based on the data description information preset by the operator.

[0087] S203. Send a reception feedback signal to the sending end so that the sending end can start a new round of data transmission operation.

[0088] In this embodiment, after filling the data in the receive buffer at the receiving end and filling the data description information in the linked cache table at the DMA control end, a receive feedback signal is generated and sent to the sending end so that the sending end can start a new round of data transmission operation.

[0089] Understandably, in a new round of data transmission, the DMA control unit can quickly and conveniently transfer data in the middle based on the data description information filled in the linked storage table by the sending end in this transmission and the set data description information filled in the linked storage table by the receiving end in the previous transmission.

[0090] In this embodiment, after receiving the transmission completion signal from the DMA control terminal, the awakened receiving thread fills the received buffer with the determined data information. The transmission completion signal is generated by the DMA control terminal after transmitting the data to be sent from the linked buffer table to the receiving terminal. Upon detecting a successful data filling message signal, the filling length is determined, and the set data description information is filled into the linked buffer table according to the filling length. A receive feedback signal is sent to the sending terminal to initiate a new round of data transmission. This technical solution solves the problem of the sending terminal being unaware of the receiving status, resulting in the transmitted data not being received by the receiving terminal. It ensures the security and reliability of data transmission, improves data transmission efficiency, and can be applied to various data transmission scenarios.

[0091] As a first optional embodiment of the embodiments, based on the above embodiments, this first optional embodiment further optimizes and adds: the data to be transmitted in the linked buffer table transmitted by the DMA control terminal is transmitted to the designated storage area and has a corresponding data storage address; accordingly, in step S201, filling the determined data information into the receiving buffer includes:

[0092] Determine the data storage address of the received data, and fill the receive buffer with the data storage address as data information. The received data is the data to be sent in the linked buffer table transmitted by the DMA controller.

[0093] In this embodiment, the data storage address is the storage address within the designated storage area where the received data is transmitted.

[0094] Specifically, after receiving the transmission completion signal sent by the DMA control terminal, the receiving thread that is awakened determines the data storage address of the received data, fills the receiving buffer with the data storage address as data information, realizes the filling of data in the receiving buffer, and completes the transmission operation in this data transmission.

[0095] As a second optional embodiment of the example, based on the above embodiment, this second optional embodiment further optimizes and adds a description of step S202, determining the fill length and filling the set data description information into the linked cache table according to the fill length, including:

[0096] a3) Determine the number of free blocks in the current free memory block in the receive buffer.

[0097] In this embodiment, the current empty memory block can be understood as the unfilled portion of the memory data block in the receive cache. The number of free blocks can be understood as the number of free data blocks in the receive cache, or as the available nodes in the receive cache.

[0098] Specifically, determine the fill length of the received buffer, and based on the fill length and the memory capacity of the received buffer itself, determine the unfilled length, that is, determine the number of free blocks in the received buffer.

[0099] b3) Compare the number of free blocks with the current available length of the linked list in the linked cache table.

[0100] In this embodiment, the current available length of the linked list can be understood as the current usable length of the linked cache table, for example, 64 nodes. It is understood that each node in the linked cache table can correspond to a data block.

[0101] Specifically, before filling the linked cache table in the DMA control terminal with the set data description information, it is necessary to first determine the current available length of the linked cache table. The number of free memory blocks in the receive buffer is compared with the current available length of the linked cache table to obtain the comparison result.

[0102] For example, the maximum transmission length of each node in the chain is 1 megabyte, and the maximum length of the chain (number of nodes) is 64.

[0103] c3) If the number of empty blocks is greater than the current available length of the linked list, then the current available length of the linked list is used as the fill length; otherwise, the number of empty blocks is used as the fill length.

[0104] In this embodiment, the number of free memory blocks in the current receive cache is compared with the current available length of the linked list in the linked cache table. After obtaining the comparison result, the length (number) of the smaller number in the comparison result is used as the padding length. Specifically, if the comparison result shows that the number of free blocks is greater than the current available length of the linked list, then the current available length of the linked list is used as the padding length; if the comparison result shows that the number of free blocks is less than the current available length of the linked list, then the number of free blocks is used as the padding length.

[0105] For example, if the number of free memory blocks in the receive cache is 40 and the current available length of the linked list of the linked cache table is 64, and it is determined that the number of free blocks is less than the current available length of the linked list, then the number of free blocks (40) is used as the fill length of the linked cache table.

[0106] d3) Using the determined destination address information as the setting data description information, select the fill length linked list node in the linked cache table to fill the setting data description information.

[0107] In this embodiment, the destination address information can be understood as the address where the data is stored in the receive buffer at the receiving end. The fill length linked list node can be understood as the position of the fill node for filling the specified description information, determined based on the determined fill length and the data nodes in the linked buffer table.

[0108] Specifically, the determined destination address information is used as the set data description information. The set data description information is filled in the selected linked list node of the linked cache table. In the linked cache table, each node that has been filled includes the source address of the sending cache and the destination address of the receiving cache.

[0109] Understandably, the length of the linked list in the linked cache table and the transmission length of each node are configured according to the actual situation. Each node's configuration includes the source address, destination address, and transmission length. The source address and transmission length are data description information configured by the sender, while the destination address is a set data description information configured by the receiver.

[0110] As a third optional embodiment, based on the above embodiments, this third optional embodiment further optimizes and adds the following:

[0111] a4) Enter kernel mode from user mode by calling the receive function.

[0112] In this embodiment, the receive function can be understood as a function used to receive data and start a send thread. It is a function used to switch between user mode and kernel mode, similar to the send and receive form of a socket.

[0113] Specifically, the kernel mode is entered from user mode by calling the receive function, so as to realize data transmission in kernel mode.

[0114] b4) When the receive buffer is detected to be non-empty, the data received from the sender is provided to the application layer based on the data information filled into the receive buffer.

[0115] In this embodiment, when it is detected that the receive buffer is not empty, that is, when there is data stored in the receive buffer, the data storage address of the received data is accessed based on the data information filled into the receive buffer, and the data stored in the data storage address is provided to the application layer. That is, the data received from the sender is provided to the application layer.

[0116] Optionally, after providing data to the application layer, since both the send and receive buffers are circular structures, once the send and receive buffers are full, the previously stored data can be replaced by subsequently stored data. This avoids situations where data transmission cannot continue due to memory exhaustion.

[0117] For example, Figure 5 This is a flowchart illustrating the receiving function call involved in a data transmission method provided in Embodiment 2 of the present invention; Figure 6 This is a flowchart illustrating the receiving thread involved in a data transmission method according to Embodiment 2 of the present invention; as shown... Figure 5 As shown, the process involves calling the receive function in user mode and waking up the receive thread in kernel mode to perform data transmission, including: S20, User-mode receive function execution: The receive function is called in user mode, and the switch between user mode and kernel mode is implemented according to the receive function; S21, Entering kernel mode: Entering kernel mode through the receive function, and executing the process of the receive thread in kernel mode; S22, Blocking (whether the receive buffer is empty): After the receive thread finishes execution, it enters a blocked state and checks whether the receive buffer is empty, that is, whether the receive buffer stores the data transmitted from the sender. If the receive buffer is empty, it means that the receiver has not received the data sent by the sender, and the blocked state is maintained. If the receive buffer is not empty, it means that the receiver has received the data sent by the sender, and S23 is executed; S23, Data copying to user mode: After confirming that the receiver has received the data sent by the sender, after this data transmission is completed, it responds to the data transmission command in user mode and copies the data stored in the receive buffer to user mode through the receive function, realizing the application-level applicability of the data; S24, Return success: The receive function returns success, completing this data transmission.

[0118] In execution such Figure 5 In the flowchart shown, during S21, when entering kernel mode, the receiving thread is executed in kernel mode, as follows: Figure 6As shown, it includes: S211, Blocking (whether a transmission completion signal sent by the DMA controller has been received): Entering the blocking state, it determines whether a transmission completion signal sent by the DMA controller has been received, that is, whether the DMA controller has completed the data transfer. If yes, the awakened receiving thread fills the determined data information into the receiving buffer and executes step S212. If no, it continues to maintain the blocking state; S212, Blocking (detection of a data filling success message signal): After the awakened receiving thread fills the determined data information into the receiving buffer, it determines whether a data filling success message signal has been generated. If yes, it indicates that the data information filling into the receiving buffer has been completed, and step S213 is executed. If no, it indicates that the receiving buffer... The filling is not yet complete, so the system remains blocked. S213: Fill the set data description information into the linked buffer table: Determine the filled length of the receive buffer, and fill the set data description information into the linked buffer table according to the unfilled length of the receive buffer and the currently available length of the linked list in the linked buffer table. Fill the data description information (destination address) corresponding to the received data into the linked buffer table of the DMA control end, so that the data can be directly transmitted to the receiving end in the next data transmission through the DMA control end. S214: Send the receive feedback signal: After the linked buffer table is filled, send the receive feedback signal to the sending end according to the source address of the data stored in the linked buffer table, so that the sending end can start a new round of data transmission operation.

[0119] Based on a data transmission method provided in Embodiment 1 and a data transmission method provided in Embodiment 2 of the present invention, a general description of data transmission is given. Figure 7 This is a schematic diagram of a data transmission link provided in an embodiment of the present invention; as shown. Figure 7As shown, both the send buffer (send buffer list) and the receive buffer are circular buffers, and the DMA's transfer buffer (linked buffer table) is a linked buffer. The maximum number of nodes in the circular buffer is 1024, and the maximum number of nodes in the linked buffer is 64. Specifically, the data transmission method provided by this invention calls the send thread according to the send function call. The size of the data to be sent is determined by the smaller of the number of data blocks currently cached in the send buffer queue and the currently available length of the linked list in the linked buffer table. The data to be sent, along with its data description information, is sent to the DMA control end. The DMA control end moves the data to be sent to the receiving end, and simultaneously, the DMA control end fills each node in the linked buffer table with the source address from the data description information of the data to be sent. The receiving end receives the data moved by the DMA control end as received data. It fills the corresponding data information (data storage address) into the receive buffer. After confirming that the data information has been filled into the receive buffer, it determines the filled length and the unfilled length. Based on the smaller value between the number of free memory blocks in the receive buffer (unfilled length) and the currently available length of the linked list of the linked cache table, it determines the size of the set data description information (destination address information). The destination address of the set data description information is filled into each node of the linked cache table. After the destination address in the linked cache table is filled, the receiving end sends a receive feedback signal to the sending end, indicating that the data sent by the sending end has been received and stored, so that the sending end can unblock and start the next round of data transmission.

[0120] It is understood that, in practical applications of the data transmission method provided by the present invention, the reliability of data transmission can be guaranteed in at least the following two exemplary scenarios:

[0121] In scenarios where the receiver stops receiving while the sender continues sending: After the sender finishes sending the data, the receiver's receive buffer becomes full, preventing the filling of the destination address configuration in the DMA linked cache table. Consequently, the receiver cannot generate a receive feedback signal and will not send one to the sender. The sender, not receiving the feedback signal, remains blocked, further filling its send buffer and preventing it from adding information to the send buffer queue, leading to a failure. In other words, when the receiver stops receiving, both the receive and send buffers fill sequentially. The backpressure mechanism described above causes the sender's sending function to fail, preventing data loss and ensuring reliable data transmission.

[0122] In scenarios where the receiver experiences jitter while the transmitter continues to send data at a low speed: The increased number of transmissible data blocks due to the transmit buffer, the chained structure of the DMA control, and the receive buffer mechanisms significantly alleviate data backlog caused by receive jitter, preventing data loss. In other words, the transmitter continuously sends data at a low speed while the receiver experiences jitter, adjusting the data throughput per unit time, reducing data transmission efficiency, avoiding data loss, and ensuring data transmission reliability.

[0123] Example 3

[0124] Figure 8 This is a schematic diagram of a data transmission device provided in Embodiment 3 of the present invention. Figure 8 As shown, this device is integrated into a high-speed serial point-to-point dual-channel PCIe system, including:

[0125] The data determination module 31 is used to determine the current data to be sent in the sending buffer queue by waking up the sending thread when it is determined that the sending conditions are met based on the preset sending buffer queue.

[0126] Data transmission module 32 is used to fill the data description information corresponding to the current data to be sent into the linked cache table of the DMA control terminal, so as to transmit the current data to be sent to the receiving terminal through the DMA control terminal;

[0127] The feedback signal receiving module 33 is used to enter a blocking state until it receives the receiving feedback signal sent by the receiving end, and then return to re-execute the determination operation of the current data to be sent.

[0128] The data transmission device used in this technical solution solves the problem that the transmitting end cannot know the receiving status, resulting in the transmitted data not being received by the receiving end. It ensures the security and reliability of data transmission, improves the efficiency of data transmission, and can be applied to various data transmission scenarios.

[0129] Optionally, the sending condition is that the sending buffer queue is not empty; the data determination module 31 is specifically used for:

[0130] Determine the number of data blocks currently cached in the sending buffer queue, and compare the number of blocks with the current available length of the linked list of the linked cache table;

[0131] If the number of blocks is less than the current maximum linked list length, then the currently cached data block is used as the current data to be sent; otherwise,

[0132] Take a data block with the same available length as the linked list from the send buffer queue as the current data to be sent.

[0133] Optionally, the device further includes:

[0134] The system switching module is used to listen for data transmission requests in user mode and then enter kernel mode by calling the transmission function through the interface function.

[0135] The data input module is used to input cached data blocks into the send buffer queue through the send function in the kernel mode.

[0136] The data transmission device provided in this embodiment of the invention can execute the data transmission method provided in Embodiment 1 of the invention, and has the corresponding functional modules and beneficial effects of executing the method.

[0137] Example 4

[0138] Figure 9 This is a schematic diagram of a data transmission device provided in Embodiment 4 of the present invention. Figure 9 As shown, this device is integrated into a high-speed serial point-to-point dual-channel PCIe system, including:

[0139] The receive buffer filling module 41 is used to fill the received buffer with the determined data information by waking up the receiving thread after receiving the transmission completion signal sent by the DMA control terminal. The transmission completion signal is generated by the DMA control terminal after transmitting the data to be sent cached in the linked buffer table to the receiving terminal.

[0140] The chained cache filling module 42 is used to determine the filling length and fill the chained cache table with the set data description information according to the filling length after detecting the message signal that the data filling is successful;

[0141] The feedback signal sending module 43 is used to send a reception feedback signal to the sending end so that the sending end can start a new round of data transmission operation.

[0142] The data transmission device used in this technical solution solves the problem that the transmitting end cannot know the receiving status, resulting in the transmitted data not being received by the receiving end. It ensures the security and reliability of data transmission, improves the efficiency of data transmission, and can be applied to various data transmission scenarios.

[0143] Optionally, the data to be transmitted from the linked cache table transmitted by the DMA control terminal is transferred to a designated storage area and has a corresponding data storage address; accordingly,

[0144] The receiving buffer filling module 41 is specifically used for:

[0145] The data storage address of the received data is determined, and the data storage address is filled into the receive buffer as data information. The received data is the data to be sent in the linked buffer table transmitted by the DMA control terminal.

[0146] Optionally, the chained cache filling module 42 is specifically used for:

[0147] Determine the number of free blocks in the currently available memory blocks in the receive buffer;

[0148] Compare the number of free blocks with the current available length of the linked list in the linked cache table;

[0149] If the number of empty blocks is greater than the current available length of the linked list, then the current available length of the linked list is used as the fill length; otherwise, the number of empty blocks is used as the fill length.

[0150] The determined destination address information is used as the set data description information, and the set data description information is filled by selecting the linked list node of the specified fill length in the linked cache table.

[0151] Optionally, the device further includes:

[0152] The system call module is used to enter kernel mode from user mode by calling the receiving function;

[0153] The data providing module is used to provide the application layer with the data received from the sending end based on the data information filled into the receiving buffer when the receiving buffer is detected to be non-empty.

[0154] The data transmission device provided in this embodiment of the invention can execute the data transmission method provided in Embodiment 1 of the invention, and has the corresponding functional modules and beneficial effects of executing the method.

[0155] Example 5

[0156] Figure 10 A schematic diagram of an electronic device 50 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0157] like Figure 10As shown, the electronic device 50 includes at least one processor 51 and a memory, such as a read-only memory (ROM) 52 and a random access memory (RAM) 53, communicatively connected to the at least one processor 51. The memory stores computer programs executable by the at least one processor. The processor 51 can perform various appropriate actions and processes based on the computer program stored in the ROM 52 or loaded into the RAM 53 from storage unit 58. The RAM 53 can also store various programs and data required for the operation of the electronic device 50. The processor 51, ROM 52, and RAM 53 are interconnected via a bus 54. An input / output (I / O) interface 55 is also connected to the bus 54.

[0158] Multiple components in electronic device 50 are connected to I / O interface 55, including: input unit 56, such as keyboard, mouse, etc.; output unit 57, such as various types of monitors, speakers, etc.; storage unit 58, such as disk, optical disk, etc.; and communication unit 9, such as network card, modem, wireless transceiver, etc. Communication unit 9 allows electronic device 50 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0159] Processor 51 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 51 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 51 performs the various methods and processes described above, such as data transfer methods.

[0160] In some embodiments, the data transfer method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 58. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 50 via ROM 52 and / or communication unit 9. When the computer program is loaded into RAM 53 and executed by processor 51, one or more steps of the data transfer method described above may be performed. Alternatively, in other embodiments, processor 51 may be configured to perform the data transfer method by any other suitable means (e.g., by means of firmware).

[0161] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0162] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0163] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0164] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0165] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0166] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0167] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0168] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A data transmission method, characterized in that, This method is applied to a high-speed serial point-to-point dual-channel PCIe system, which includes a transmitter, a direct memory access (DMA) controller, and a receiver. The method is executed by the transmitter and includes: When the sending conditions are met based on the preset sending buffer queue, the currently pending data in the sending buffer queue is determined by the awakened sending thread; The data description information corresponding to the current data to be sent is filled into the linked cache table of the DMA control terminal, so that the current data to be sent can be transmitted to the receiving terminal through the DMA control terminal; The system enters a blocking state until it receives a reception feedback signal from the receiving end, after which it returns and re-executes the operation to determine the current data to be sent.

2. The method according to claim 1, characterized in that, The sending condition is that the sending buffer queue is not empty; Determining the currently pending data in the sending buffer queue includes: Determine the number of data blocks currently cached in the sending buffer queue, and compare the number of blocks with the current available length of the linked list of the linked cache table; If the number of blocks is less than the current available length of the linked list, then the currently cached data block is used as the current data to be sent; otherwise, Take a data block with the same available length as the linked list from the send buffer queue as the current data to be sent.

3. The method according to claim 1, characterized in that, Also includes: After listening for a data transmission request in user space, the kernel mode is entered by calling the send function through the interface function. In the kernel mode, the send function inputs a buffered data block into the send buffer queue.

4. A data transmission method, characterized in that, This method is applied to a high-speed serial point-to-point dual-channel PCIe system, which includes a transmitting end, a direct memory access (DMA) control end, and a receiving end. The method is executed by the receiving end and includes: After receiving the transmission completion signal sent by the DMA control terminal, the awakened receiving thread fills the determined data information into the receiving buffer. The transmission completion signal is generated by the DMA control terminal after transmitting the data to be sent from the linked buffer table to the receiving terminal. After detecting a message signal indicating successful data filling, the filling length is determined and the set data description information is filled into the linked cache table according to the filling length; Send a reception feedback signal to the sending end so that the sending end can start a new round of data transmission operations.

5. The method according to claim 4, characterized in that, The data to be sent in the chained cache table transmitted by the DMA control terminal is sent to the designated storage area and has the corresponding data storage address. The step of filling the received buffer with the determined data information includes: The data storage address of the received data is determined, and the data storage address is filled into the receive buffer as data information. The received data is the data to be sent in the linked buffer table transmitted by the DMA control terminal.

6. The method according to claim 4, characterized in that, The process of determining the fill length and filling the chained cache table with set data description information according to the fill length includes: Determine the number of free blocks in the currently available memory blocks in the receive buffer; Compare the number of free blocks with the current available length of the linked list in the linked cache table; If the number of empty blocks is greater than the current available length of the linked list, then the current available length of the linked list is used as the fill length; otherwise, the number of empty blocks is used as the fill length. The determined destination address information is used as the set data description information, and the set data description information is filled by selecting the linked list node of the specified fill length in the linked cache table.

7. The method according to claim 4, characterized in that, Also includes: Entering kernel mode from user mode by calling the receive function; When the receive buffer is detected to be non-empty, the data received from the sender is provided to the application layer based on the data information filled into the receive buffer.

8. A data transmission device, characterized in that, Integrated into a high-speed serial point-to-point dual-channel PCIe system, the PCIe system includes a transmitter, a direct memory access (DMA) controller, and a receiver. The data transmission device is the device corresponding to the transmitter, including: The data determination module is used to determine the current data to be sent in the sending buffer queue by waking up the sending thread when it is determined that the sending conditions are met based on the preset sending buffer queue. The data transmission module is used to fill the data description information corresponding to the currently to be transmitted data into the linked cache table of the DMA control terminal, so as to transmit the currently to be transmitted data to the receiving terminal through the DMA control terminal; The feedback signal receiving module is used to enter a blocking state until it receives the reception feedback signal sent by the receiving end, and then returns to re-execute the determination operation of the current data to be sent.

9. A data transmission device, characterized in that, Integrated into a high-speed serial point-to-point dual-channel PCIe system, the PCIe system includes a transmitting end, a direct memory access (DMA) control end, and a receiving end. The data transmission device is the device corresponding to the receiving end, including: The receive buffer filling module is used to fill the received buffer with the determined data information through the awakened receiving thread after receiving the transmission completion signal sent by the DMA control terminal. The transmission completion signal is generated by the DMA control terminal after transmitting the data to be sent cached in the linked buffer table to the receiving terminal. The chained cache filling module is used to determine the filling length and fill the chained cache table with the set data description information according to the filling length after detecting the message signal of successful data filling; The feedback signal sending module is used to send a reception feedback signal to the sending end so that the sending end can start a new round of data transmission operation.

10. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the data transmission method of any one of claims 1-3, or the data transmission method of any one of claims 4-7.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the data transmission method of any one of claims 1-3, or the data transmission method of any one of claims 4-7.

Images