Shift register, pixel driving circuit and display device

Abstract

The present disclosure provides a shift register, belonging to the technical field of display. The shift register comprises a pre-charge sub-circuit, a storage sub-circuit, a duty cycle adjustment sub-circuit, a NOT gate and an output sub-circuit. The pre-charge sub-circuit is configured to transmit a first level signal to a first node in response to an input signal. The storage sub-circuit controls the working duration of the duty cycle adjustment sub-circuit according to a second level signal and the voltage of the first node. The duty cycle adjustment sub-circuit is configured to transmit a first clock signal to the first node in response to the voltage of the first node. The NOT gate is configured to transmit the first level signal or the second level signal to a second node in response to the voltage of the first node, or configured to transmit the first level signal or the second level signal to a third node in response to the input signal. The output sub-circuit is configured to transmit the first level signal or the second level signal to a signal output terminal in response to the voltage of the second node and the voltage of the third node.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a shift register, a pixel driving circuit, and a display device. Background Technology

[0002] A crucial circuit design technology in current display products is the GOA (Gate Driver On Array) circuit design. With increasing demands for high PPI and extremely narrow bezels in display products, the GOA circuit area needs to be further reduced. However, the existing GOA circuits utilize thin-film transistors (TFTs) with large aspect ratios and a high number of signals, leading to complex noise reduction.

[0003] Based on the above problems, the inventors proposed a novel GOA circuit, which includes fewer TFTs and uses the same aspect ratio design, which can significantly reduce the area occupied by the TFTs, thereby reducing the GOA area. In addition, the GOA circuit in this disclosure only requires the previous row to trigger the output of the current row, without the need for reset and complex noise reduction design, which simplifies the manufacturing process, reduces the defect rate, and increases stability. Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art, and to provide a shift register, a pixel driving circuit and a display device.

[0005] In a first aspect, embodiments of this disclosure provide a shift register, which includes: a precharge sub-circuit, a storage sub-circuit, a duty cycle adjustment sub-circuit, a NOT gate, and an output sub-circuit;

[0006] The pre-charge sub-circuit is configured to transmit a first-level signal to a first node in response to an input signal; the first node is the connection node of the pre-charge sub-circuit, the storage sub-circuit, and the duty cycle adjustment sub-circuit.

[0007] The storage sub-circuit is configured to control the operating duration of the duty cycle adjustment sub-circuit based on the second level signal and the first node voltage;

[0008] The duty cycle adjustment sub-circuit is configured to transmit a first clock signal to the first node in response to the first node voltage;

[0009] The NOT gate is configured to transmit either a first-level signal or a second-level signal to the second node in response to the voltage of the first node; or, the NOT gate is configured to transmit either the first-level signal or the second-level signal to the third node in response to an input signal; the second node is the connection node between the NOT gate and the output sub-circuit, or the second node is the connection node between the duty cycle adjustment sub-circuit and the output sub-circuit; the third node is the connection node between the input signal terminal and the output sub-circuit, or the third node is the connection node between the NOT gate and the output sub-circuit.

[0010] The output sub-circuit is configured to output either the first level signal or the second level signal to the signal output terminal in response to the second node voltage and the third node voltage.

[0011] Preferably, the precharged electronic circuit includes: a third transistor;

[0012] The control electrode of the third transistor is connected to the cascaded signal terminal, the first electrode is connected to the first node, and the second electrode is connected to the first level signal terminal.

[0013] Preferably, the duty cycle adjustment sub-circuit includes: a first transistor and a second transistor; the switching characteristics of the first transistor and the second transistor are the same as the switching characteristics of the third transistor;

[0014] The control electrode of the first transistor is connected to the first node, the first electrode is connected to the first clock signal terminal, and the second electrode is connected to the first electrode of the second transistor.

[0015] The control electrode of the second transistor is connected to the first node, the first electrode is connected to the second electrode of the first transistor, and the second electrode is connected to the first node.

[0016] Preferably, the storage sub-circuit includes: a first storage capacitor;

[0017] One terminal of the first storage capacitor is connected to the second level signal terminal, and the other terminal is connected to the first node.

[0018] Preferably, the NOT gate includes a fourth transistor and a fifth transistor; the switching characteristics of the fourth transistor are opposite to those of the fifth transistor.

[0019] Preferably, the control electrode of the fourth transistor is connected to the first node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the second node; the control electrode of the fifth transistor is connected to the first node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the second node.

[0020] Preferably, the control electrode of the fourth transistor is connected to the input signal terminal, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the third node; the control electrode of the fifth transistor is connected to the input signal terminal, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the third node.

[0021] Preferably, the output sub-circuit includes a sixth transistor, a seventh transistor, and an eighth transistor; the switching characteristics of the sixth transistor are the same as those of the seventh transistor.

[0022] Preferably, the control electrode of the sixth transistor is connected to the third node, the first electrode is connected to the first-level signal terminal, and the second electrode is connected to the first electrode of the seventh transistor; the control electrode of the seventh transistor is connected to the second node, the first electrode is connected to the second electrode of the sixth transistor, and the second electrode is connected to the signal output terminal; the control electrode of the eighth transistor is connected to the third-level signal terminal, the first electrode is connected to the signal output terminal, and the second electrode is connected to the second-level signal terminal; or...

[0023] Preferably, the control electrode of the sixth transistor is connected to the third node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first electrode of the seventh transistor; the control electrode of the seventh transistor is connected to the second node, the first electrode is connected to the second electrode of the sixth transistor, and the second electrode is connected to the signal output terminal; the control electrode of the eighth transistor is connected to the second level signal terminal, the first electrode is connected to the signal output terminal, and the second electrode is connected to the second level signal terminal.

[0024] Preferably, the output sub-circuit further includes: a ninth transistor; the switching characteristics of the sixth transistor are the same as those of the seventh transistor, the switching characteristics of the eighth transistor are the same as those of the ninth transistor, and the switching characteristics of the sixth transistor are opposite to those of the eighth transistor.

[0025] The control electrode of the sixth transistor is connected to the third node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first electrode of the seventh transistor.

[0026] The control electrode of the seventh transistor is connected to the second node, the first electrode is connected to the second electrode of the sixth transistor, and the second electrode is connected to the signal output terminal.

[0027] The control electrode of the eighth transistor is connected to the second node, the first electrode is connected to the signal output terminal, and the second electrode is connected to the second level signal terminal.

[0028] The control electrode of the ninth transistor is connected to the third node, the first electrode is connected to the signal output terminal, and the second electrode is connected to the second level signal terminal.

[0029] Secondly, embodiments of this disclosure provide a pixel driving circuit, wherein the pixel driving circuit includes: a plurality of cascaded shift registers as described above;

[0030] The signal input terminal of the shift register described in this stage is connected to the signal output terminal of the shift register described in the previous stage.

[0031] Thirdly, embodiments of this disclosure provide a display device, wherein the display device includes the pixel driving circuit described above. Attached Figure Description

[0032] Figure 1 A schematic diagram of the structure of a shift register, which is a first example of this disclosure;

[0033] Figure 2 This is a schematic diagram of the structure of a shift register, which is a second example of the present disclosure.

[0034] Figure 3 A schematic diagram of the shift register structure for the third example of this disclosure;

[0035] Figure 4 This is a schematic diagram of the structure of a shift register, which is the fourth example of this disclosure;

[0036] Figure 5 This is a schematic diagram of the structure of a shift register, which is the fifth example of this disclosure.

[0037] Figure 6 A schematic diagram of the structure of a shift register, which is the sixth example of this disclosure;

[0038] Figure 7 A schematic diagram of the structure of a shift register, which is the seventh example of this disclosure;

[0039] Figure 8 This is a schematic diagram of the structure of a shift register, which is the eighth example of this disclosure.

[0040] Figure 9 A schematic diagram of the structure of a shift register for the ninth example of this disclosure;

[0041] Figure 10 A schematic diagram of the structure of a shift register, which is the tenth example of this disclosure;

[0042] Figure 11 A schematic diagram of the structure of a shift register, which is the eleventh example of this disclosure;

[0043] Figure 12 This is a schematic diagram of the structure of a shift register, which is the twelfth example of this disclosure;

[0044] Figure 13Timing diagrams of the input signals and the first clock signal for twelve embodiments of this disclosure;

[0045] Figure 14 The simulation results of the shift register are shown in the first example of this disclosure.

[0046] Figure 15 Simulation results of shift registers according to the first to sixth embodiments of this disclosure;

[0047] Figure 16 Simulation results of an eight-stage cascaded circuit of a shift register, which is the first example of this disclosure;

[0048] Figure 17 The simulation results are shown for the shift register of the seventh example of this disclosure.

[0049] Figure 18 Simulation results of shift registers according to the ninth to twelfth embodiments of this disclosure;

[0050] Figure 19 The simulation results are shown in the diagram of the eight-stage cascaded circuit of the shift register, which is the seventh example of this disclosure. Detailed Implementation

[0051] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0052] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0053] It should be noted that the transistors in this embodiment can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. The switching characteristics of the transistors in this embodiment can be N-type or P-type. To achieve duty cycle adjustment, the first, second, and third transistors have the same switching characteristics, while the fourth and fifth transistors, which form the NOT gate, have opposite switching characteristics. The voltage level signal connected to the first terminal of the P-type transistor is a high-level signal, and the voltage level signal connected to the first terminal of the N-type transistor is a low-level signal. In the output sub-circuit, the sixth and seventh transistors have the same switching characteristics, which are opposite to the switching characteristics of the eighth transistor. In some examples, the output sub-circuit also includes a ninth transistor, which has the same switching characteristics as the eighth transistor.

[0054] In this embodiment, the source and drain of each transistor are structurally identical and interchangeable. The terminology used here is to distinguish the two terminals (excluding the gate), with one terminal referred to as the source and the other as the drain. The first terminal can be the source, and the second terminal can be the drain. For an N-type transistor, the transistor is turned on when a high-level signal is input to the gate and turned off when a low-level signal is input to the gate. For a P-type transistor, the transistor is turned on when a low-level signal is input to the gate and turned off when a high-level signal is input to the gate.

[0055] In this embodiment, the first level signal can be either a high-level signal or a low-level signal, set according to the switching characteristics of the transistor. Correspondingly, the second level signal has the same absolute voltage value as the first level signal but opposite sign; the third level signal has the same voltage sign as the first level signal but a smaller amplitude; and the fourth level signal has the same absolute voltage value as the third level signal but opposite sign. The input signal in this disclosure can be an STV signal or the output signal of the previous stage circuit. The first clock signal in this disclosure is a square wave signal with a certain duty cycle, and the first clock signal of the next stage is delayed by a quarter cycle compared to the first clock signal of the previous stage.

[0056] In this embodiment of the disclosure, the first node is the connection node of the storage sub-circuit, the pre-charge sub-circuit, and the duty cycle adjustment sub-circuit; the second node is the node of the control electrode port of the seventh transistor; and the third node is the node of the control electrode port of the sixth transistor.

[0057] In a first aspect, embodiments of this disclosure provide a shift register with duty cycle adjustment function, the shift register including a pre-charge sub-circuit, a storage sub-circuit, a duty cycle adjustment sub-circuit, a NOT gate, and an output sub-circuit.

[0058] The pre-charge sub-circuit includes a third transistor. The pre-charge sub-circuit is configured to respond to an input signal by controlling the switching of the third transistor based on a high-level or low-level signal of the input signal, transmitting a first-level signal to the first node to create a voltage difference across the storage capacitor, thereby performing a charging or discharging operation.

[0059] The storage sub-circuit includes a storage capacitor, which is configured to adjust the discharge and charging speed of the storage capacitor based on the voltage difference between the second level signal and the first node voltage, thereby controlling the operating time of the duty cycle adjustment sub-circuit.

[0060] The duty cycle adjustment sub-circuit is configured to respond to the first node voltage and control the switching on and off of the first transistor and the second transistor based on the voltage difference between the first node voltage and the first clock signal voltage, thereby controlling the duration of the first clock signal transmission to the first node, i.e., adjusting the duty cycle.

[0061] In some embodiments, the NOT gate is configured to transmit a first-level signal or a second-level signal to the second node in response to the voltage of the first node.

[0062] In other embodiments, the NOT gate is configured to transmit a first level signal or a second level signal to a third node in response to an input signal.

[0063] The output sub-circuit is configured to respond to the second node voltage and the third node voltage, and control the switching on and off of multiple transistors according to the different states of the two voltages, thereby outputting a square wave signal with a certain duty cycle.

[0064] In some embodiments, the output sub-circuit includes a sixth transistor, a seventh transistor, and an eighth transistor, which together constitute one of the four logic gates: AND gate, OR gate, NAND gate, and NOR gate. Controlled by the second node voltage and the third node voltage, the output is a square wave signal with a certain duty cycle.

[0065] In other embodiments, the output sub-circuit includes a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, which together constitute one of the four logic gates: AND gate, OR gate, NAND gate, and NOR gate. These gates are controlled by the voltages of the second node and the third node, and output a square wave signal with a certain duty cycle.

[0066] The shift register provided in this embodiment is equipped with a duty cycle adjustment sub-circuit, which can generate a clock signal with an adjustable duty cycle. In this case, the trigger circuit can be applied to the pixel driving circuit to control the turn-on time of the driving transistor according to the clock signal generated by the shift register, thereby controlling the light emission brightness of the light-emitting device.

[0067] To better illustrate the shift register in the embodiments of this disclosure, the touch controller circuit in the embodiments of this disclosure will be specifically described below with reference to specific examples.

[0068] First example: Figure 1 This is a schematic diagram of a shift register according to a first example of an embodiment of this disclosure; as shown Figure 1 As shown, the shift register includes a pre-charge sub-circuit 1, a storage sub-circuit 2, a duty cycle adjustment sub-circuit 3, a NOT gate 4, and a NOR gate. The following simulation uses only the following example: a first-level signal VDD = 10V, a second-level signal VSS = -10V; first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, eighth transistor M8, and ninth transistor M9 are all N-type transistors, while fifth transistor M5, sixth transistor M6, and seventh transistor M7 are all P-type transistors; the high level of the input signal is 10V, and the low level is -10V; the high level of the first clock signal CLK1 is 10V, and the low level is -10V; and the storage capacitor C1 = 1μF. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0069] The pre-charge sub-circuit 1 includes a third transistor M3. The storage sub-circuit 2 includes C1. The duty cycle adjustment sub-circuit 3 includes a first transistor M1 and a second transistor M2. The NOT gate 4 includes a fourth transistor M4 and a fifth transistor M5. The NOT gate 4 is configured to transmit a first-level signal VDD or a second-level signal VSS to the second node Q2 in response to the voltage of the first node Q1. The signal at the input terminal of the NOT gate 4 is a digital signal 1. The NOR gate 4 is composed of a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9. The first node Q1 is the connection node of the pre-charge sub-circuit 1, the storage sub-circuit 2, and the duty cycle adjustment sub-circuit 3. The second node Q2 is the node of the control electrode of the seventh transistor M7. The third node Q3 is the node of the control electrode of the sixth transistor M6. The input signal can be an STV signal or the output signal of the previous stage circuit.

[0070] For details, please refer to... Figure 1The control electrode of the third transistor M3 is connected to the input signal, its first electrode is connected to the first node Q1, and its second electrode is connected to the first level signal VDD. This first level signal VDD is transmitted to the first node Q1 to control the control electrode voltages of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first transistor M1 and the second transistor M2. Simultaneously, the first level signal VDD transmitted to the first node Q1 serves as the voltage of one electrode of the storage capacitor C1, working together with the second level signal VSS connected to the other electrode of the storage capacitor C1 to control the charging or discharging speed of the storage capacitor C1. The control electrodes of both the first transistor M1 and the second transistor M2 are connected to the first node Q1. The first electrode of the first transistor M1 is connected to the first clock signal CLK1, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The second electrode of the second transistor M2 is connected to the first node Q1. Responding to the voltage of the first clock signal CLK1 and the first node Q1, the first transistor M1 and the second transistor M2 are connected in series to control the duration of the transmission of the first clock signal CLK1 to the first node Q1, i.e., adjusting the duty cycle of the first clock signal CLK1. The control electrodes of the fourth transistor M4 and the fifth transistor M5 are both connected to the first node Q1. The first electrode of the fourth transistor M4 is connected to the second level signal VSS, and the second electrode of the fourth transistor M4 is connected to the second node Q2. The first electrode of the fifth transistor M5 is connected to the first level signal VDD, and the second electrode of the fifth transistor M5 is connected to the second node Q2. The fourth transistor M4 and the fifth transistor M5 together form NOT gate 4, which outputs a signal opposite to the voltage of digital signal 1. The control electrode of the sixth transistor M6 is connected to the third node Q3. The first electrode of the sixth transistor M6 is connected to the first level signal VDD. The second electrode of the sixth transistor M6 is connected to the first electrode of the seventh transistor M7. The control electrode of the seventh transistor M7 is connected to the second node Q2. The first electrode of the seventh transistor M7 is connected to the second electrode of the sixth transistor M6. The second electrode of the seventh transistor M7 is connected to the signal output terminal OUTPUT. The control electrode of the eighth transistor M8 is connected to the second node Q2. The first electrode of the eighth transistor M8 is connected to the signal output terminal OUTPUT. The second electrode of the eighth transistor M8 is connected to the second level signal VSS. The control electrode of the ninth transistor M9 is connected to the third node Q3. The first electrode of the ninth transistor M9 is connected to the signal output terminal OUTPUT. The second electrode of the ninth transistor M9 is connected to the second level signal VSS. The sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 together constitute NOR gate 4, which responds to the voltages of the second node Q2 and the third node Q3, that is, responds to the voltage of the input signal terminal and the voltage of the third node Q3, and outputs either the first level signal VDD or the second level signal VSS to the signal output terminal OUTPUT.

[0071] The following describes the operation of the first example shift register. (Continue referring to...) Figure 1 and Figure 14The steps for generating each clock cycle signal of the clock signal using the shift register in the first example include:

[0072] In the first stage, there is no input signal and no first clock signal CLK1, and the voltage of each node in the circuit is 0V.

[0073] In the second stage, a 10V voltage is written to the input signal terminal, a 10V voltage is written to the first clock signal CLK1, the first transistor M1 and the second transistor M2 are turned off, the third transistor M3 is turned on, after passing through NOT gate 4, the voltage of the second node Q2 is -10V, the voltage of the third node is 10V, the sixth transistor M6 is turned off, the ninth transistor M9 is turned on, and the second level signal VSS = -10V is written to the signal output terminal OUTPUT.

[0074] In the third stage, -10V voltage is written to the input signal terminal, 10V voltage is written to the first clock signal terminal CLK1, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off, the high voltage stored in the storage voltage C1 becomes low level after passing through the NOT gate 4, the sixth transistor M6 and the seventh transistor M7 are both turned on, the eighth transistor M8 and the ninth transistor M9 are both turned off, and the first level signal VDD=10V is written to the signal output terminal OUTPUT.

[0075] In the fourth stage, -10V voltage is written to the input signal terminal, -10V voltage is written to the first clock signal terminal CLK1, the third transistor M3 is turned off, the voltage difference between the gate and source of the first transistor M1 and the second transistor M2 is 10V-(-10V)=20V, so the first transistor M1 and the second transistor M2 are turned on, the CLK1 signal is written to the first node Q1, and becomes high level after passing through NOT gate 4, the seventh transistor M7 is turned off, the eighth transistor M8 is turned on, and the second level signal VSS=-10V is written to the signal output terminal OUTPUT.

[0076] The above four stages constitute the specific driving process of a single-row GOA circuit. Multiple GOA circuits are cascaded, and the next-row GOA circuit continues to output a square wave signal with a certain duty cycle under the control of its clock signal CLKA and the output signal of the previous-row GOA circuit. Simulation results are as follows... Figure 16 As shown, the circuit does not require an additional reset circuit, which simplifies the manufacturing process and reduces the area of ​​the circuit board.

[0077] Second example: Figure 2 This is a schematic diagram of a shift register according to a first example of an embodiment of this disclosure; as shown Figure 2As shown, the shift register includes a precharge sub-circuit 1, a storage sub-circuit 2, a duty cycle adjustment sub-circuit 3, a NOT gate 4, and a NOR gate. The difference between the second example and the first example is that the ninth transistor M9 is not included, and the NOR gate 4 is composed of the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8. The following simulation uses the following parameters as an example: first level signal VDD = 10V, second level signal VSS = -10V, fourth level signal VSSH = -7V; first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, and eighth transistor M8 are all N-type transistors, fifth transistor M5, sixth transistor M6, and seventh transistor M7 are all P-type transistors; the high level of the input signal is 10V, the low level is -10V, the high level of the first clock signal CLK1 is 10V, and the low level is -10V; and the storage capacitor C1 = 1μf. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0078] The pre-charge sub-circuit 1 includes a third transistor M3. The storage sub-circuit 2 includes C1. The duty cycle adjustment sub-circuit 3 includes a first transistor M1 and a second transistor M2. The NOT gate 4 includes a fourth transistor M4 and a fifth transistor M5. The NOT gate 4 is configured to transmit a first-level signal VDD or a second-level signal VSS to the second node Q2 in response to the voltage of the first node Q1. The signal at the input terminal of the NOT gate 4 is a digital signal 1. The NOR gate 4 is composed of a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first node Q1 is the connection node of the pre-charge sub-circuit 1, the storage sub-circuit 2, and the duty cycle adjustment sub-circuit 3. The second node Q2 is the connection node of the control electrode of the seventh transistor M7 and the output terminal of the NOT gate 4. The third node Q3 is the connection node of the control electrode of the sixth transistor M6 and the input signal terminal. The input signal can be an STV signal or the output signal of the previous stage circuit.

[0079] For details, please refer to... Figure 2The control electrode of the third transistor M3 is connected to the input signal, its first electrode is connected to the first node Q1, and its second electrode is connected to the first level signal VDD. This first level signal VDD is transmitted to the first node Q1 to control the control electrode voltages of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first transistor M1 and the second transistor M2. Simultaneously, the first level signal VDD transmitted to the first node Q1 serves as the voltage of one electrode of the storage capacitor C1, working together with the second level signal VSS connected to the other electrode of the storage capacitor C1 to control the charging or discharging speed of the storage capacitor C1. The control electrodes of both the first transistor M1 and the second transistor M2 are connected to the first node Q1. The first electrode of the first transistor M1 is connected to the first clock signal CLK1, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The second electrode of the second transistor M2 is connected to the first node Q1. Responding to the voltage of the first clock signal CLK1 and the first node Q1, the first transistor M1 and the second transistor M2 are connected in series to control the duration of the transmission of the first clock signal CLK1 to the first node Q1, i.e., adjusting the duty cycle of the first clock signal CLK1. The control electrodes of the fourth transistor M4 and the fifth transistor M5 are both connected to the first node Q1. The first electrode of the fourth transistor M4 is connected to the second level signal VSS, and the second electrode of the fourth transistor M4 is connected to the second node Q2. The first electrode of the fifth transistor M5 is connected to the first level signal VDD, and the second electrode of the fifth transistor M5 is connected to the second node Q2. The fourth transistor M4 and the fifth transistor M5 together form NOT gate 4, which outputs a signal opposite to the voltage of digital signal 1. The control electrode of the sixth transistor M6 is connected to the third node Q3. The first electrode of the sixth transistor M6 is connected to the first level signal VDD. The second electrode of the sixth transistor M6 is connected to the first electrode of the seventh transistor M7. The control electrode of the seventh transistor M7 is connected to the second node Q2. The first electrode of the seventh transistor M7 is connected to the second electrode of the sixth transistor M6. The second electrode of the seventh transistor M7 is connected to the signal output terminal OUTPUT. The control electrode of the eighth transistor M8 is connected to the fourth level signal VSSH. The first electrode of the eighth transistor M8 is connected to the signal output terminal OUTPUT. The second electrode of the eighth transistor M8 is connected to the second level signal VSS. The sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 together form a NOR gate 4, which responds to the voltages of the second node Q2 and the third node Q3, that is, responds to the voltage of the input signal terminal and the voltage of the third node Q3, and outputs either the first level signal VDD or the second level signal VSS to the signal output terminal OUTPUT.

[0080] The operation of the second example shift register will be described next. (Continue referring to...) Figure 2 and Figure 15 The steps for generating each clock cycle signal of the clock signal using the shift register in the second example include:

[0081] In the first stage, there is no input signal and no first clock signal CLK1, and the voltage of each node in the circuit is 0V.

[0082] In the second stage, a 10V voltage is written to the input signal terminal, a 10V voltage is written to the first clock signal CLK1, the first transistor M1 and the second transistor M2 are turned off, the third transistor M3 is turned on, after passing through NOT gate 4, the voltage of the second node Q2 is -10V, the voltage of the third node is 10V, the sixth transistor M6 is turned off, the seventh transistor M7 is turned on, the eighth transistor M8 is normally open, and the second level signal VSS = -10V is written to the signal output terminal OUTPUT.

[0083] In the third stage, -10V voltage is written to the input signal terminal, 10V voltage is written to the first clock signal terminal CLK1, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off, the high voltage stored in the storage voltage C1 becomes low level after passing through the NOT gate 4, the sixth transistor M6 and the seventh transistor M7 are both turned on, and the first level signal VDD = 10V is written to the signal output terminal OUTPUT.

[0084] In the fourth stage, -10V voltage is written to the input signal terminal, -10V voltage is written to the first clock signal terminal CLK1, the third transistor M3 is turned off, the voltage difference between the gate and source of the first transistor M1 and the second transistor M2 is 10V-(-10V)=20V, so the first transistor M1 and the second transistor M2 are turned on, the CLK1 signal is written to the first node Q1, and becomes high level after passing through NOT gate 4, the seventh transistor M7 is turned off, the eighth transistor M8 is normally open, and the second level signal VSS=-10V is written to the signal output terminal OUTPUT.

[0085] The above four stages constitute the specific driving process of a row of GOA circuits. By cascading multiple GOA circuits, the GOA circuit in the next row continues to output a square wave signal with a certain duty cycle under the control of its clock signal CLKA and the output signal of the GOA circuit in the previous row. The circuit does not require an additional reset circuit, which simplifies the process and reduces the area of ​​the circuit board.

[0086] The third example: Figure 3 This is a schematic diagram of a shift register according to a first example of an embodiment of this disclosure; as shown Figure 3As shown, the shift register includes a precharge sub-circuit 1, a storage sub-circuit 2, a duty cycle adjustment sub-circuit 3, a NOT gate 4, and a NOR gate. The difference between the third example and the second example is that the eighth transistor M8 is a P-type transistor. The control and second terminals of the eighth transistor M8 are both connected to the second-level signal VSS, eliminating the need for a fourth-level signal VSSH and reducing circuit complexity. The following simulation uses the following example with the first-level signal VDD = 10V, the second-level signal VSS = -10V; the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 all being N-type transistors, and the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 all being P-type transistors; the high level of the input signal being 10V and the low level being -10V; the high level of the first clock signal CLK1 being 10V and the low level being -10V; and the storage capacitor C1 = 1μf as an example to simulate the shift register in the first example. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0087] The pre-charge sub-circuit 1 includes a third transistor M3. The storage sub-circuit 2 includes C1. The duty cycle adjustment sub-circuit 3 includes a first transistor M1 and a second transistor M2. The NOT gate 4 includes a fourth transistor M4 and a fifth transistor M5. The NOT gate 4 is configured to transmit a first-level signal VDD or a second-level signal VSS to the second node Q2 in response to the voltage of the first node Q1. The signal at the input terminal of the NOT gate 4 is a digital signal 1. The NOR gate 4 is composed of a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first node Q1 is the connection node of the pre-charge sub-circuit 1, the storage sub-circuit 2, and the duty cycle adjustment sub-circuit 3. The second node Q2 is the connection node of the control electrode of the seventh transistor M7 and the output terminal of the NOT gate 4. The third node Q3 is the connection node of the control electrode of the sixth transistor M6 and the input signal terminal. The input signal can be an STV signal or the output signal of the previous stage circuit.

[0088] For details, please refer to... Figure 3The control electrode of the third transistor M3 is connected to the input signal, its first electrode is connected to the first node Q1, and its second electrode is connected to the first level signal VDD. This first level signal VDD is transmitted to the first node Q1 to control the control electrode voltages of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first transistor M1 and the second transistor M2. Simultaneously, the first level signal VDD transmitted to the first node Q1 serves as the voltage of one electrode of the storage capacitor C1, working together with the second level signal VSS connected to the other electrode of the storage capacitor C1 to control the charging or discharging speed of the storage capacitor C1. The control electrodes of both the first transistor M1 and the second transistor M2 are connected to the first node Q1. The first electrode of the first transistor M1 is connected to the first clock signal CLK1, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The second electrode of the second transistor M2 is connected to the first node Q1. Responding to the voltage of the first clock signal CLK1 and the first node Q1, the first transistor M1 and the second transistor M2 are connected in series to control the duration of the transmission of the first clock signal CLK1 to the first node Q1, i.e., adjusting the duty cycle of the first clock signal CLK1. The control electrodes of the fourth transistor M4 and the fifth transistor M5 are both connected to the first node Q1. The first electrode of the fourth transistor M4 is connected to the second level signal VSS, and the second electrode of the fourth transistor M4 is connected to the second node Q2. The first electrode of the fifth transistor M5 is connected to the first level signal VDD, and the second electrode of the fifth transistor M5 is connected to the second node Q2. The fourth transistor M4 and the fifth transistor M5 together form NOT gate 4, which outputs a signal opposite to the voltage of digital signal 1. The control electrode of the sixth transistor M6 is connected to the third node Q3, the first electrode of the sixth transistor M6 is connected to the first level signal VDD, the second electrode of the sixth transistor M6 is connected to the first electrode of the seventh transistor M7, the control electrode of the seventh transistor M7 is connected to the second node Q2, the first electrode of the seventh transistor M7 is connected to the second electrode of the sixth transistor M6, and the second electrode of the seventh transistor M7 is connected to the signal output terminal OUTPUT. The control electrode of the eighth transistor M8 is connected to the second level signal VSS, the first electrode of the eighth transistor M8 is connected to the signal output terminal OUTPUT, and the second electrode of the eighth transistor M8 is connected to the second level signal VSS. The sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 together form a NOR gate 4, which responds to the voltages of the second node Q2 and the third node Q3, that is, responds to the voltage of the input signal terminal and the voltage of the third node Q3, and outputs either the first level signal VDD or the second level signal VSS to the signal output terminal OUTPUT.

[0089] The operation of the third example shift register will be described next. (Continue referring to...) Figure 3 and Figure 15 The steps for generating each clock cycle signal of the clock signal using the shift register in the third example include:

[0090] In the first stage, there is no input signal and no first clock signal CLK1, and the voltage of each node in the circuit is 0V.

[0091] In the second stage, a 10V voltage is written to the input signal terminal, a 10V voltage is written to the first clock signal CLK1, the first transistor M1 and the second transistor M2 are turned off, the third transistor M3 is turned on, after passing through NOT gate 4, the voltage of the second node Q2 is -10V, the voltage of the third node is 10V, the sixth transistor M6 is turned off, the seventh transistor M7 is turned on, the eighth transistor M8 is turned on, and the second level signal VSS = -10V is written to the signal output terminal OUTPUT.

[0092] In the third stage, -10V voltage is written to the input signal terminal, 10V voltage is written to the first clock signal terminal CLK1, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off, the high voltage stored in the storage voltage C1 becomes low level after passing through the NOT gate 4, the sixth transistor M6 and the seventh transistor M7 are both turned on, and the first level signal VDD = 10V is written to the signal output terminal OUTPUT.

[0093] In the fourth stage, -10V voltage is written to the input signal terminal, -10V voltage is written to the first clock signal terminal CLK1, the third transistor M3 is turned off, the voltage difference between the gate and source of the first transistor M1 and the second transistor M2 is 10V-(-10V)=20V, so the first transistor M1 and the second transistor M2 are turned on, the CLK1 signal is written to the first node Q1, and becomes high level after passing through NOT gate 4, the seventh transistor M7 is turned off, the eighth transistor M8 is turned on, and the second level signal VSS=-10V is written to the signal output terminal OUTPUT.

[0094] The above four stages constitute the specific driving process of a row of GOA circuits. By cascading multiple GOA circuits, the GOA circuit in the next row continues to output a square wave signal with a certain duty cycle under the control of its clock signal CLKA and the output signal of the GOA circuit in the previous row. The circuit does not require an additional reset circuit, which simplifies the process and reduces the area of ​​the circuit board.

[0095] Fourth example: Figure 4 This is a schematic diagram of a shift register according to a first example of an embodiment of this disclosure; as shown Figure 4As shown, the shift register includes a precharge sub-circuit 1, a storage sub-circuit 2, a duty cycle adjustment sub-circuit 3, a NOT gate 4, and an AND gate. The difference between the fourth example and the first example is that the NOT gate 4 responds to the input signal and transmits the first level signal VDD or the second level signal VSS to the third node Q3, and the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 form an AND gate as the output sub-circuit 5. The following simulation uses only the following parameters for the shift register in the first example: first level signal VDD = 10V, second level signal VSS = -10V; first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, sixth transistor M6, and seventh transistor M7 are all N-type transistors, and fifth transistor M5, eighth transistor M8, and ninth transistor M9 are all P-type transistors; input signal high level is 10V, low level is -10V, first clock signal CLK1 high level is 10V, low level is -10V; storage capacitor C1 = 1μf. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0096] The pre-charge sub-circuit 1 includes a third transistor M3. The storage sub-circuit 2 includes C1. The duty cycle adjustment sub-circuit 3 includes a first transistor M1 and a second transistor M2. The NOT gate 4 includes a fourth transistor M4 and a fifth transistor M5. The NOT gate 4 is configured to transmit a first-level signal VDD or a second-level signal VSS to the second node Q2 in response to the voltage of the first node Q1. The signal at the input terminal of the NOT gate 4 is a digital signal 1. The AND gate is composed of a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9. The first node Q1 is the connection node of the pre-charge sub-circuit 1, the storage sub-circuit 2, and the duty cycle adjustment sub-circuit 3. The second node Q2 is the node of the control electrode of the seventh transistor M7. In this embodiment, the second node Q2 and the first node Q1 are the same node. The third node Q3 is the connection node between the control electrode of the sixth transistor M6 and the output terminal of the NOT gate 4. The input signal can be an STV signal or the output signal of the previous stage circuit.

[0097] For details, please refer to... Figure 4The control electrode of the third transistor M3 is connected to the input signal, its first electrode is connected to the first node Q1, and its second electrode is connected to the first level signal VDD. This first level signal VDD is transmitted to the first node Q1 to control the control electrode voltages of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first transistor M1 and the second transistor M2. Simultaneously, the first level signal VDD transmitted to the first node Q1 serves as the voltage of one electrode of the storage capacitor C1, working together with the second level signal VSS connected to the other electrode of the storage capacitor C1 to control the charging or discharging speed of the storage capacitor C1. The control electrodes of both the first transistor M1 and the second transistor M2 are connected to the first node Q1. The first electrode of the first transistor M1 is connected to the first clock signal CLK1, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The second electrode of the second transistor M2 is connected to the first node Q1. Responding to the voltage of the first clock signal CLK1 and the first node Q1, the first transistor M1 and the second transistor M2 are connected in series to control the duration of the transmission of the first clock signal CLK1 to the first node Q1, i.e., adjusting the duty cycle of the first clock signal CLK1. The control electrodes of the fourth transistor M4 and the fifth transistor M5 are both connected to the first node Q1. The first electrode of the fourth transistor M4 is connected to the second level signal VSS, and the second electrode of the fourth transistor M4 is connected to the second node Q2. The first electrode of the fifth transistor M5 is connected to the first level signal VDD, and the second electrode of the fifth transistor M5 is connected to the second node Q2. The fourth transistor M4 and the fifth transistor M5 together form NOT gate 4, which outputs a signal opposite to the voltage of digital signal 1. The control electrode of the sixth transistor M6 is connected to the third node Q3. The first electrode of the sixth transistor M6 is connected to the first level signal VDD. The second electrode of the sixth transistor M6 is connected to the first electrode of the seventh transistor M7. The control electrode of the seventh transistor M7 is connected to the second node Q2. The first electrode of the seventh transistor M7 is connected to the second electrode of the sixth transistor M6. The second electrode of the seventh transistor M7 is connected to the signal output terminal OUTPUT. The control electrode of the eighth transistor M8 is connected to the second node Q2. The first electrode of the eighth transistor M8 is connected to the signal output terminal OUTPUT. The second electrode of the eighth transistor M8 is connected to the second level signal VSS. The control electrode of the ninth transistor M9 is connected to the third node Q3. The first electrode of the ninth transistor M9 is connected to the signal output terminal OUTPUT. The second electrode of the ninth transistor M9 is connected to the second level signal VSS. The sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 together form an AND gate. In response to the voltages of the second node Q2 and the third node Q3, that is, in response to the voltage of the input signal terminal and the voltage of the third node Q3, the first level signal VDD or the second level signal VSS is output to the signal output terminal OUTPUT.

[0098] The operation of the fourth example shift register will be described next. (Continue referring to...) Figure 4 and Figure 15The steps for generating each clock cycle signal of the clock signal using the shift register in the fourth example include:

[0099] In the first stage, there is no input signal and no first clock signal CLK1, and the voltage of each node in the circuit is 0V.

[0100] In the second stage, a 10V voltage is written to the input signal terminal, a 10V voltage is written to the first clock signal CLK1, the first transistor M1 and the second transistor M2 are turned off, the third transistor M3 is turned on, after passing through NOT gate 4, the voltage of the second node Q2 is 10V, the voltage of the third node is -10V, the seventh transistor M7 and the ninth transistor M9 are turned on, and the second level signal VSS = -10V is written to the signal output terminal OUTPUT.

[0101] In the third stage, -10V voltage is written to the input signal terminal, 10V voltage is written to the first clock signal terminal CLK1, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off, the input signal becomes high voltage after passing through NOT gate 4, the sixth transistor M6 is turned on, the high voltage stored in the storage voltage C1 turns on the seventh transistor M7, and the first level signal VDD=10V is written to the signal output terminal OUTPUT.

[0102] In the fourth stage, -10V voltage is written to the input signal terminal, -10V voltage is written to the first clock signal terminal CLK1, the third transistor M3 is turned off, the voltage difference between the gate and source of the first transistor M1 and the second transistor M2 is 10V-(-10V)=20V, so the first transistor M1 and the second transistor M2 are turned on, the CLK1 signal is written to the first node Q1, the input signal becomes high voltage after passing through NOT gate 4, the eighth transistor M8 is turned on, and the second level signal VSS=-10V is written to the signal output terminal OUTPUT.

[0103] The above four stages constitute the specific driving process of a row of GOA circuits. By cascading multiple GOA circuits, the GOA circuit in the next row continues to output a square wave signal with a certain duty cycle under the control of its clock signal CLKA and the output signal of the GOA circuit in the previous row. The circuit does not require an additional reset circuit, which simplifies the process and reduces the area of ​​the circuit board.

[0104] Fifth example: Figure 5 This is a schematic diagram of a shift register according to a first example of an embodiment of this disclosure; as shown Figure 5As shown, the shift register includes a precharge sub-circuit 1, a storage sub-circuit 2, a duty cycle adjustment sub-circuit 3, a NOT gate 4, and an AND gate. The difference between the fifth example and the fourth example is that the ninth transistor M9 is not included, and it is composed of the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8. The following simulation uses the following example: first level signal VDD = 10V, second level signal VSS = -10V; first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, sixth transistor M6, and seventh transistor M7 are all N-type transistors, fifth transistor M5, and eighth transistor M8 are all P-type transistors; input signal high level is 10V, low level is -10V; first clock signal CLK1 high level is 10V, low level is -10V; storage capacitor C1 = 1μf. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0105] The pre-charge sub-circuit 1 includes a third transistor M3. The storage sub-circuit 2 includes C1. The duty cycle adjustment sub-circuit 3 includes a first transistor M1 and a second transistor M2. The NOT gate 4 includes a fourth transistor M4 and a fifth transistor M5. The NOT gate 4 is configured to transmit a first-level signal VDD or a second-level signal VSS to the second node Q2 in response to the voltage of the first node Q1. The signal at the input terminal of the NOT gate 4 is a digital signal 1. The AND gate is composed of a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first node Q1 is the connection node of the pre-charge sub-circuit 1, the storage sub-circuit 2, and the duty cycle adjustment sub-circuit 3. The second node Q2 is the node of the control electrode of the seventh transistor M7. In this embodiment, the second node Q2 and the first node Q1 are the same node. The third node Q3 is the connection node between the control electrode of the sixth transistor M6 and the output terminal of the NOT gate 4. The input signal can be an STV signal or the output signal of the previous stage circuit.

[0106] For details, please refer to... Figure 5The control electrode of the third transistor M3 is connected to the input signal, its first electrode is connected to the first node Q1, and its second electrode is connected to the first level signal VDD. This first level signal VDD is transmitted to the first node Q1 to control the control electrode voltages of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first transistor M1 and the second transistor M2. Simultaneously, the first level signal VDD transmitted to the first node Q1 serves as the voltage of one electrode of the storage capacitor C1, working together with the second level signal VSS connected to the other electrode of the storage capacitor C1 to control the charging or discharging speed of the storage capacitor C1. The control electrodes of both the first transistor M1 and the second transistor M2 are connected to the first node Q1. The first electrode of the first transistor M1 is connected to the first clock signal CLK1, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The second electrode of the second transistor M2 is connected to the first node Q1. Responding to the voltage of the first clock signal CLK1 and the first node Q1, the first transistor M1 and the second transistor M2 are connected in series to control the duration of the transmission of the first clock signal CLK1 to the first node Q1, i.e., adjusting the duty cycle of the first clock signal CLK1. The control electrodes of the fourth transistor M4 and the fifth transistor M5 are both connected to the first node Q1. The first electrode of the fourth transistor M4 is connected to the second level signal VSS, and the second electrode of the fourth transistor M4 is connected to the second node Q2. The first electrode of the fifth transistor M5 is connected to the first level signal VDD, and the second electrode of the fifth transistor M5 is connected to the second node Q2. The fourth transistor M4 and the fifth transistor M5 together form NOT gate 4, which outputs a signal opposite to the voltage of digital signal 1. The control electrode of the sixth transistor M6 is connected to the third node Q3. The first electrode of the sixth transistor M6 is connected to the first level signal VDD. The second electrode of the sixth transistor M6 is connected to the first electrode of the seventh transistor M7. The control electrode of the seventh transistor M7 is connected to the second node Q2. The first electrode of the seventh transistor M7 is connected to the second electrode of the sixth transistor M6. The second electrode of the seventh transistor M7 is connected to the signal output terminal OUTPUT. The control electrode and the second electrode of the eighth transistor M8 are both connected to the second level signal VSS. The first electrode is connected to the signal output terminal OUTPUT. The sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 together form an AND gate. In response to the voltage of the second node Q2 and the third node Q3, that is, in response to the voltage of the input signal terminal and the voltage of the third node Q3, the first level signal VDD or the second level signal VSS is output to the signal output terminal OUTPUT.

[0107] The operation of the fifth example shift register will be described next. (Continue referring to...) Figure 5 and Figure 15 The steps for generating each clock cycle signal of the clock signal using the shift register in the fifth example include:

[0108] In the first stage, there is no input signal and no first clock signal CLK1, and the voltage of each node in the circuit is 0V.

[0109] In the second stage, a 10V voltage is written to the input signal terminal, a 10V voltage is written to the first clock signal CLK1, the first transistor M1 and the second transistor M2 are turned off, the third transistor M3 is turned on, after passing through NOT gate 4, the input signal becomes low voltage, the sixth transistor M6 is turned off, the seventh transistor M7 is turned on, the eighth transistor M8 is turned on, and the second level signal VSS = -10V is written to the signal output terminal OUTPUT.

[0110] In the third stage, -10V voltage is written to the input signal terminal, 10V voltage is written to the first clock signal terminal CLK1, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off, the input signal becomes high voltage after passing through NOT gate 4, the sixth transistor M6 is turned on, the high voltage stored in the storage voltage C1 turns on the seventh transistor M7, and the first level signal VDD=10V is written to the signal output terminal OUTPUT.

[0111] In the fourth stage, -10V voltage is written to the input signal terminal, -10V voltage is written to the first clock signal terminal CLK1, the third transistor M3 is turned off, the voltage difference between the gate and source of the first transistor M1 and the second transistor M2 is 10V-(-10V)=20V, so the first transistor M1 and the second transistor M2 are turned on, the CLK1 signal is written to the first node Q1, the input signal becomes high voltage after passing through NOT gate 4, the seventh transistor M7 is turned off, the eighth transistor M8 is turned on, and the second level signal VSS=-10V is written to the signal output terminal OUTPUT.

[0112] The above four stages constitute the specific driving process of a row of GOA circuits. By cascading multiple GOA circuits, the GOA circuit in the next row continues to output a square wave signal with a certain duty cycle under the control of its clock signal CLKA and the output signal of the GOA circuit in the previous row. The circuit does not require an additional reset circuit, which simplifies the process and reduces the area of ​​the circuit board.

[0113] Sixth example: Figure 6 This is a schematic diagram of a shift register according to a sixth example of an embodiment of this disclosure; as shown Figure 6As shown, the shift register includes a precharge sub-circuit 1, a storage sub-circuit 2, a duty cycle adjustment sub-circuit 3, a NOT gate 4, and an AND gate. The difference between the fifth and sixth examples is that the sixth transistor M6 and the seventh transistor M7 are connected in parallel, and the control electrode of the eighth transistor M8 is connected to the third-level signal VDDL. The following simulation uses the following parameters as an example: first-level signal VDD = 10V, second-level signal VSS = -10V, third-level signal VDDL = 7V; first transistor M1, second transistor M2, third transistor M3, and fourth transistor M4 are all N-type transistors, fifth transistor M5, sixth transistor M6, seventh transistor M7, and eighth transistor M8 are all P-type transistors; input signal high level is 10V, low level is -10V, first clock signal CLK1 high level is 10V, low level is -10V; storage capacitor C1 = 1μf. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0114] The pre-charge sub-circuit 1 includes a third transistor M3. The storage sub-circuit 2 includes C1. The duty cycle adjustment sub-circuit 3 includes a first transistor M1 and a second transistor M2. The NOT gate 4 includes a fourth transistor M4 and a fifth transistor M5. The NOT gate 4 is configured to transmit a first-level signal VDD or a second-level signal VSS to the second node Q2 in response to the voltage of the first node Q1. The signal at the input terminal of the NOT gate 4 is a digital signal 1. The AND gate is composed of a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first node Q1 is the connection node of the pre-charge sub-circuit 1, the storage sub-circuit 2, and the duty cycle adjustment sub-circuit 3. The second node Q2 is the node of the control electrode of the seventh transistor M7. In this embodiment, the second node Q2 and the first node Q1 are the same node. The third node Q3 is the connection node between the control electrode of the sixth transistor M6 and the output terminal of the NOT gate 4. The input signal can be an STV signal or the output signal of the previous stage circuit.

[0115] For details, please refer to... Figure 6The control electrode of the third transistor M3 is connected to the input signal, its first electrode is connected to the first node Q1, and its second electrode is connected to the first level signal VDD. This first level signal VDD is transmitted to the first node Q1 to control the control electrode voltages of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first transistor M1 and the second transistor M2. Simultaneously, the first level signal VDD transmitted to the first node Q1 serves as the voltage of one electrode of the storage capacitor C1, working together with the second level signal VSS connected to the other electrode of the storage capacitor C1 to control the charging or discharging speed of the storage capacitor C1. The control electrodes of both the first transistor M1 and the second transistor M2 are connected to the first node Q1. The first electrode of the first transistor M1 is connected to the first clock signal CLK1, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The second electrode of the second transistor M2 is connected to the first node Q1. Responding to the voltage of the first clock signal CLK1 and the first node Q1, the first transistor M1 and the second transistor M2 are connected in series to control the duration of the transmission of the first clock signal CLK1 to the first node Q1, i.e., adjusting the duty cycle of the first clock signal CLK1. The control electrodes of the fourth transistor M4 and the fifth transistor M5 are both connected to the first node Q1. The first electrode of the fourth transistor M4 is connected to the second level signal VSS, and the second electrode of the fourth transistor M4 is connected to the second node Q2. The first electrode of the fifth transistor M5 is connected to the first level signal VDD, and the second electrode of the fifth transistor M5 is connected to the second node Q2. The fourth transistor M4 and the fifth transistor M5 together form NOT gate 4, which outputs a signal opposite to the voltage of digital signal 1. The control electrode of the sixth transistor M6 is connected to the third node Q3, the first electrode of the sixth transistor M6 is connected to the second level signal VSS, and the second electrode of the sixth transistor M6 is connected to the signal output terminal OUTPUT. The control electrode of the seventh transistor M7 is connected to the second node Q2, the first electrode of the seventh transistor M7 is connected to the second level signal VSS, and the second electrode of the seventh transistor M7 is connected to the signal output terminal OUTPUT. The control electrode of the eighth transistor M8 is connected to the third level signal VDDL, the first electrode of the eighth transistor M8 is connected to the signal output terminal OUTPUT, and the second electrode of the eighth transistor M8 is connected to the first level signal VDD. The sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 together form an AND gate, which responds to the voltages of the second node Q2 and the third node Q3, that is, responds to the voltage of the input signal terminal and the voltage of the third node Q3, and outputs either the first level signal VDD or the second level signal VSS to the signal output terminal OUTPUT.

[0116] The following describes the operation of the sixth example shift register. (Continue referring to...) Figure 6 and Figure 15 The steps for generating each clock cycle signal of the clock signal using the shift register in the sixth example include:

[0117] In the first stage, there is no input signal and no first clock signal CLK1, and the voltage of each node in the circuit is 0V.

[0118] In the second stage, a 10V voltage is written to the input signal terminal, a 10V voltage is written to the first clock signal CLK1, the first transistor M1 and the second transistor M2 are turned off, the third transistor M3 is turned on, after passing through NOT gate 4, the input signal becomes low voltage, the sixth transistor M6 is turned on, the seventh transistor M7 is turned off, and the second level signal VSS = -10V is written to the signal output terminal OUTPUT.

[0119] In the third stage, -10V voltage is written to the input signal terminal, 10V voltage is written to the first clock signal terminal CLK1, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off, the input signal becomes high voltage after passing through NOT gate 4, the sixth transistor M6 is turned off, the high voltage stored in the storage voltage C1 turns off the seventh transistor M7, the eighth transistor M8 is normally open, and the first level signal VDD=10V is written to the signal output terminal OUTPUT.

[0120] In the fourth stage, -10V voltage is written to the input signal terminal, -10V voltage is written to the first clock signal terminal CLK1, the third transistor M3 is turned off, the first transistor M1 and the second transistor M2 are turned on, the CLK1 signal is written to the first node Q1, the input signal becomes high voltage after passing through NOT gate 4, the seventh transistor M7 is turned on, and the second level signal VSS = -10V is written to the signal output terminal OUTPUT.

[0121] The above four stages constitute the specific driving process of a row of GOA circuits. By cascading multiple GOA circuits, the GOA circuit in the next row continues to output a square wave signal with a certain duty cycle under the control of its clock signal CLKA and the output signal of the GOA circuit in the previous row. The circuit does not require an additional reset circuit, which simplifies the process and reduces the area of ​​the circuit board.

[0122] Seventh example: Figure 7 This is a schematic diagram of a shift register according to a first example of an embodiment of this disclosure; as shown Figure 7As shown, the shift register includes a precharge sub-circuit 1, a storage sub-circuit 2, a duty cycle adjustment sub-circuit 3, a NOT gate 4, and a NAND gate 4. The difference between the seventh example and the first example is that, except for gate 4, the switching characteristics of all transistors are reversed. The sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 together constitute NAND gate 4 as the output sub-circuit 5. The following simulation uses the following example: first level signal VDD = 10V, second level signal VSS = -10V; first transistor M1, second transistor M2, third transistor M3, fifth transistor M5, eighth transistor M8, and ninth transistor M9 are all P-type transistors, fourth transistor M4, sixth transistor M6, and seventh transistor M7 are all N-type transistors; input signal high level is 10V, low level is -10V; first clock signal CLK1 high level is 10V, low level is -10V; storage capacitor C1 = 1μf. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0123] The circuit includes a pre-charge sub-circuit 1, a third transistor M3, a storage sub-circuit 2, a C1, a duty cycle adjustment sub-circuit 3, a first transistor M1, and a second transistor M2. A NOT gate 4 includes a fourth transistor M4 and a fifth transistor M5. The NOT gate 4 is configured to transmit a first-level signal VDD or a second-level signal VSS to a second node Q2 in response to the voltage at the first node Q1. The input signal of the NOT gate 4 is a digital signal 1. A NAND gate 4 is composed of a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9. The first node Q1 is the connection node between the pre-charge sub-circuit 1, the storage sub-circuit 2, the duty cycle adjustment sub-circuit 3, and the NOT gate 4. The second node Q2 is the connection node between the output of the NOT gate 4 and the control electrode of the seventh transistor M7. The third node Q3 is the connection node between the control electrode of the sixth transistor M6 and the input signal terminal. The input signal can be an STV signal or the output signal of the previous stage circuit.

[0124] For details, please refer to... Figure 7The control electrode of the third transistor M3 is connected to the input signal, its first electrode is connected to the first node Q1, and its second electrode is connected to the first level signal VSS. This first level signal VSS is transmitted to the first node Q1 to control the control electrode voltages of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first transistor M1 and the second transistor M2. Simultaneously, the first level signal VSS transmitted to the first node Q1 serves as the voltage of one electrode of the storage capacitor C1, working together with the second level signal VDD connected to the other electrode of the storage capacitor C1 to control the charging or discharging speed of the storage capacitor C1. The control electrodes of both the first transistor M1 and the second transistor M2 are connected to the first node Q1. The first electrode of the first transistor M1 is connected to the first clock signal CLK1, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The second electrode of the second transistor M2 is connected to the first node Q1. Responding to the voltage of the first clock signal CLK1 and the first node Q1, the first transistor M1 and the second transistor M2 are connected in series to control the duration of the transmission of the first clock signal CLK1 to the first node Q1, i.e., adjusting the duty cycle of the first clock signal CLK1. The control electrodes of the fourth transistor M4 and the fifth transistor M5 are both connected to the first node Q1. The first electrode of the fourth transistor M4 is connected to the second level signal VDD, and the second electrode of the fourth transistor M4 is connected to the second node Q2. The first electrode of the fifth transistor M5 is connected to the first level signal VSS, and the second electrode of the fifth transistor M5 is connected to the second node Q2. The fourth transistor M4 and the fifth transistor M5 together form NOT gate 4, which outputs a signal that is opposite to the voltage of digital signal 1. The control electrode of the sixth transistor M6 is connected to the third node Q3. The first electrode of the sixth transistor M6 is connected to the first level signal VSS. The second electrode of the sixth transistor M6 is connected to the first electrode of the seventh transistor M7. The control electrode of the seventh transistor M7 is connected to the second node Q2. The first electrode of the seventh transistor M7 is connected to the second electrode of the sixth transistor M6. The second electrode of the seventh transistor M7 is connected to the signal output terminal OUTPUT. The control electrode of the eighth transistor M8 is connected to the second node Q2. The first electrode of the eighth transistor M8 is connected to the signal output terminal OUTPUT. The second electrode of the eighth transistor M8 is connected to the second level signal VDD. The control electrode of the ninth transistor M9 is connected to the third node Q3. The first electrode of the ninth transistor M9 is connected to the signal output terminal OUTPUT. The second electrode of the ninth transistor M9 is connected to the second level signal VDD. The sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 together constitute NAND gate 4, which responds to the voltages of the second node Q2 and the third node Q3, that is, responds to the voltage of the input signal terminal and the voltage of the third node Q3, and outputs either the first level signal VSS or the second level signal VDD to the signal output terminal OUTPUT.

[0125] The operation of the seventh example shift register will be described next. (Continue referring to...) Figure 7 and Figure 17The steps for generating each clock cycle signal of the clock signal using the shift register in the seventh example include:

[0126] In the first stage, there is no input signal and no first clock signal CLK1, and the voltage of each node in the circuit is 0V.

[0127] In the second stage, -10V voltage is written to the input signal terminal, -10V voltage is written to the first clock signal CLK1, the first transistor M1 and the second transistor M2 are turned off, the third transistor M3 is turned on, after passing through NOT gate 4, the voltage of the second node Q2 is 10V, the voltage of the third node is -10V, the sixth transistor M6 is turned off, the ninth transistor M9 is turned on, and the second level signal VDD = 10V is written to the signal output terminal OUTPUT.

[0128] In the third stage, a 10V voltage is written to the input signal terminal, a -10V voltage is written to the first clock signal terminal CLK1, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off, the low voltage stored in the storage voltage C1 becomes a high level after passing through the NOT gate 4, the sixth transistor M6 and the seventh transistor M7 are both turned on, the eighth transistor M8 and the ninth transistor M9 are both turned off, and the first level signal VSS = -10V is written to the signal output terminal OUTPUT.

[0129] In the fourth stage, a 10V voltage is written to the input signal terminal, a 10V voltage is written to the first clock signal terminal CLK1, the third transistor M3 is turned off, the first transistor M1 and the second transistor M2 are turned on, the CLK1 signal is written to the first node Q1, and becomes low level after passing through NOT gate 4, the seventh transistor M7 is turned off, the eighth transistor M8 is turned on, and the second level signal VDD=10V is written to the signal output terminal OUTPUT.

[0130] The above four stages constitute the specific driving process of a single-row GOA circuit. Cascading multiple GOA circuits yields simulation results as follows: Figure 19 As shown, the GOA circuit in the next row continues to output a square wave signal with a certain duty cycle under the control of its clock signal CLKA and the output signal of the GOA circuit in the previous row. The circuit does not require an additional reset circuit, which simplifies the process and reduces the area of ​​the circuit board.

[0131] Example 8: Figure 8 This is a schematic diagram of a shift register according to a first example of an embodiment of this disclosure; as shown Figure 8As shown, the shift register includes a precharge sub-circuit 1, a storage sub-circuit 2, a duty cycle adjustment sub-circuit 3, a NOT gate 4, and a NAND gate 4. The difference between the eighth example and the seventh example is that the ninth transistor M9 is not included. The following simulation uses the following parameters as an example: first level signal VDD = 10V, second level signal VSS = -10V, third level signal VDDL = 7V; first transistor M1, second transistor M2, third transistor M3, fifth transistor M5, and eighth transistor M8 are all P-type transistors, fourth transistor M4, sixth transistor M6, and seventh transistor M7 are all N-type transistors; input signal high level is 10V, low level is -10V, first clock signal CLK1 high level is 10V, low level is -10V; storage capacitor C1 = 1μf. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0132] The circuit includes a pre-charge sub-circuit 1, a third transistor M3, a storage sub-circuit 2, a C1, a duty cycle adjustment sub-circuit 3, a first transistor M1, and a second transistor M2. A NOT gate 4 includes a fourth transistor M4 and a fifth transistor M5. The NOT gate 4 is configured to transmit a first-level signal VDD or a second-level signal VSS to a second node Q2 in response to the voltage at the first node Q1. The input signal of the NOT gate 4 is a digital signal 1. A NAND gate 4 is composed of a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9. The first node Q1 is the connection node between the pre-charge sub-circuit 1, the storage sub-circuit 2, the duty cycle adjustment sub-circuit 3, and the NOT gate 4. The second node Q2 is the connection node between the output of the NOT gate 4 and the control electrode of the seventh transistor M7. The third node Q3 is the connection node between the control electrode of the sixth transistor M6 and the input signal terminal. The input signal can be an STV signal or the output signal of the previous stage circuit.

[0133] For details, please refer to... Figure 8The control electrode of the third transistor M3 is connected to the input signal, its first electrode is connected to the first node Q1, and its second electrode is connected to the first level signal VSS. This first level signal VSS is transmitted to the first node Q1 to control the control electrode voltages of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first transistor M1 and the second transistor M2. Simultaneously, the first level signal VSS transmitted to the first node Q1 serves as the voltage of one electrode of the storage capacitor C1, working together with the second level signal VDD connected to the other electrode of the storage capacitor C1 to control the charging or discharging speed of the storage capacitor C1. The control electrodes of both the first transistor M1 and the second transistor M2 are connected to the first node Q1. The first electrode of the first transistor M1 is connected to the first clock signal CLK1, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The second electrode of the second transistor M2 is connected to the first node Q1. Responding to the voltage of the first clock signal CLK1 and the first node Q1, the first transistor M1 and the second transistor M2 are connected in series to control the duration of the transmission of the first clock signal CLK1 to the first node Q1, i.e., adjusting the duty cycle of the first clock signal CLK1. The control electrodes of the fourth transistor M4 and the fifth transistor M5 are both connected to the first node Q1. The first electrode of the fourth transistor M4 is connected to the second level signal VDD, and the second electrode of the fourth transistor M4 is connected to the second node Q2. The first electrode of the fifth transistor M5 is connected to the first level signal VSS, and the second electrode of the fifth transistor M5 is connected to the second node Q2. The fourth transistor M4 and the fifth transistor M5 together form NOT gate 4, which outputs a signal that is opposite to the voltage of digital signal 1. The control electrode of the sixth transistor M6 is connected to the third node Q3. The first electrode of the sixth transistor M6 is connected to the first level signal VSS. The second electrode of the sixth transistor M6 is connected to the first electrode of the seventh transistor M7. The control electrode of the seventh transistor M7 is connected to the second node Q2. The first electrode of the seventh transistor M7 is connected to the second electrode of the sixth transistor M6. The second electrode of the seventh transistor M7 is connected to the signal output terminal OUTPUT. The control electrode of the eighth transistor M8 is connected to the third level signal VDDL. The first electrode of the eighth transistor M8 is connected to the signal output terminal OUTPUT. The second electrode of the eighth transistor M8 is connected to the second level signal VDD. The sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 together constitute NAND gate 4, which responds to the voltages of the second node Q2 and the third node Q3, that is, responds to the voltage of the input signal terminal and the voltage of the third node Q3, and outputs either the first level signal VSS or the second level signal VDD to the signal output terminal OUTPUT.

[0134] The working process of the eighth example shift register will be described next. (Continue referring to...) Figure 8 and Figure 18 The steps for generating each clock cycle signal of the clock signal using the shift register in the eighth example include:

[0135] In the first stage, there is no input signal and no first clock signal CLK1, and the voltage of each node in the circuit is 0V.

[0136] In the second stage, a -10V voltage is written to the input signal terminal, a -10V voltage is written to the first clock signal CLK1, the first transistor M1 and the second transistor M2 are turned off, the third transistor M3 is turned on, after passing through NOT gate 4, the voltage of the second node Q2 is 10V, the voltage of the third node is -10V, the sixth transistor M6 is turned off, the seventh transistor M7 is turned on, the eighth transistor M8 is normally open, and the second level signal VDD = 10V is written to the signal output terminal OUTPUT.

[0137] In the third stage, a 10V voltage is written to the input signal terminal, a -10V voltage is written to the first clock signal terminal CLK1, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off, the low voltage stored in the storage voltage C1 becomes a high level after passing through the NOT gate 4, the sixth transistor M6 and the seventh transistor M7 are both turned on, and the first level signal VSS = -10V is written to the signal output terminal OUTPUT.

[0138] In the fourth stage, a 10V voltage is written to the input signal terminal, a 10V voltage is written to the first clock signal terminal CLK1, the third transistor M3 is turned off, the first transistor M1 and the second transistor M2 are turned on, the CLK1 signal is written to the first node Q1, and becomes low level after passing through NOT gate 4, the seventh transistor M7 is turned off, the eighth transistor M8 is normally open, and the second level signal VDD=10V is written to the signal output terminal OUTPUT.

[0139] The above four stages constitute the specific driving process of a row of GOA circuits. By cascading multiple GOA circuits, the GOA circuit in the next row continues to output a square wave signal with a certain duty cycle under the control of its clock signal CLKA and the output signal of the GOA circuit in the previous row. The circuit does not require an additional reset circuit, which simplifies the process and reduces the area of ​​the circuit board.

[0140] Ninth example: Figure 9 This is a schematic diagram of a shift register according to a first example of an embodiment of this disclosure; as shown Figure 9As shown, the shift register includes a precharge sub-circuit 1, a storage sub-circuit 2, a duty cycle adjustment sub-circuit 3, a NOT gate 4, and a NAND gate 4. The difference between the ninth example and the eighth example is that the control electrode and the second electrode of the eighth transistor M8 are both connected to the second-level signal VDD, eliminating the need to introduce the third-level signal VDDL and reducing circuit complexity. The following simulation uses only the following example: the first-level signal VDD = 10V, the second-level signal VSS = -10V; the first transistor M1, the second transistor M2, the third transistor M3, the fifth transistor M5, and the eighth transistor M8 are all P-type transistors, and the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are all N-type transistors; the high level of the input signal is 10V, the low level is -10V, the high level of the first clock signal CLK1 is 10V, and the low level is -10V; and the storage capacitor C1 = 1μf. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0141] The circuit includes a pre-charge sub-circuit 1, a third transistor M3, a storage sub-circuit 2, a C1, a duty cycle adjustment sub-circuit 3, a first transistor M1, and a second transistor M2. A NOT gate 4 includes a fourth transistor M4 and a fifth transistor M5. The NOT gate 4 is configured to transmit a first-level signal VDD or a second-level signal VSS to a second node Q2 in response to the voltage at the first node Q1. The input signal of the NOT gate 4 is a digital signal 1. A NAND gate 4 is composed of a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9. The first node Q1 is the connection node between the pre-charge sub-circuit 1, the storage sub-circuit 2, the duty cycle adjustment sub-circuit 3, and the NOT gate 4. The second node Q2 is the connection node between the output of the NOT gate 4 and the control electrode of the seventh transistor M7. The third node Q3 is the connection node between the control electrode of the sixth transistor M6 and the input signal terminal. The input signal can be an STV signal or the output signal of the previous stage circuit.

[0142] For details, please refer to... Figure 9The control electrode of the third transistor M3 is connected to the input signal, its first electrode is connected to the first node Q1, and its second electrode is connected to the first level signal VSS. This first level signal VSS is transmitted to the first node Q1 to control the control electrode voltages of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first transistor M1 and the second transistor M2. Simultaneously, the first level signal VSS transmitted to the first node Q1 serves as the voltage of one electrode of the storage capacitor C1, working together with the second level signal VDD connected to the other electrode of the storage capacitor C1 to control the charging or discharging speed of the storage capacitor C1. The control electrodes of both the first transistor M1 and the second transistor M2 are connected to the first node Q1. The first electrode of the first transistor M1 is connected to the first clock signal CLK1, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The second electrode of the second transistor M2 is connected to the first node Q1. Responding to the voltage of the first clock signal CLK1 and the first node Q1, the first transistor M1 and the second transistor M2 are connected in series to control the duration of the transmission of the first clock signal CLK1 to the first node Q1, i.e., adjusting the duty cycle of the first clock signal CLK1. The control electrodes of the fourth transistor M4 and the fifth transistor M5 are both connected to the first node Q1. The first electrode of the fourth transistor M4 is connected to the second level signal VDD, and the second electrode of the fourth transistor M4 is connected to the second node Q2. The first electrode of the fifth transistor M5 is connected to the first level signal VSS, and the second electrode of the fifth transistor M5 is connected to the second node Q2. The fourth transistor M4 and the fifth transistor M5 together form NOT gate 4, which outputs a signal that is opposite to the voltage of digital signal 1. The control electrode of the sixth transistor M6 is connected to the third node Q3. The first electrode of the sixth transistor M6 is connected to the first level signal VSS. The second electrode of the sixth transistor M6 is connected to the first electrode of the seventh transistor M7. The control electrode of the seventh transistor M7 is connected to the second node Q2. The first electrode of the seventh transistor M7 is connected to the second electrode of the sixth transistor M6. The second electrode of the seventh transistor M7 is connected to the signal output terminal OUTPUT. The control electrode of the eighth transistor M8 is connected to the second level signal VDD. The first electrode of the eighth transistor M8 is connected to the signal output terminal OUTPUT. The second electrode of the eighth transistor M8 is connected to the second level signal VDD. The sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 together constitute NAND gate 4, which responds to the voltages of the second node Q2 and the third node Q3, that is, responds to the voltage of the input signal terminal and the voltage of the third node Q3, and outputs either the first level signal VSS or the second level signal VDD to the signal output terminal OUTPUT.

[0143] The operation of the ninth example shift register will be described next. (Continue referring to...) Figure 9 and Figure 18 The steps for generating each clock cycle signal of the clock signal using the shift register in the ninth example include:

[0144] In the first stage, there is no input signal and no first clock signal CLK1, and the voltage of each node in the circuit is 0V.

[0145] In the second stage, a -10V voltage is written to the input signal terminal, a -10V voltage is written to the first clock signal CLK1, the first transistor M1 and the second transistor M2 are turned off, the third transistor M3 is turned on, after passing through NOT gate 4, the voltage of the second node Q2 is 10V, the voltage of the third node is -10V, the sixth transistor M6 is turned off, the seventh transistor M7 is turned on, the eighth transistor M8 is turned on, and the second level signal VDD = 10V is written to the signal output terminal OUTPUT.

[0146] In the third stage, a 10V voltage is written to the input signal terminal, a -10V voltage is written to the first clock signal terminal CLK1, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off, the low voltage stored in the storage voltage C1 becomes a high level after passing through the NOT gate 4, the sixth transistor M6 and the seventh transistor M7 are both turned on, and the first level signal VSS = -10V is written to the signal output terminal OUTPUT.

[0147] In the fourth stage, a 10V voltage is written to the input signal terminal, a 10V voltage is written to the first clock signal terminal CLK1, the third transistor M3 is turned off, the first transistor M1 and the second transistor M2 are turned on, the CLK1 signal is written to the first node Q1, and becomes low level after passing through NOT gate 4, the seventh transistor M7 is turned off, the eighth transistor M8 is turned on, and the second level signal VDD=10V is written to the signal output terminal OUTPUT.

[0148] The above four stages constitute the specific driving process of a row of GOA circuits. By cascading multiple GOA circuits, the GOA circuit in the next row continues to output a square wave signal with a certain duty cycle under the control of its clock signal CLKA and the output signal of the GOA circuit in the previous row. The circuit does not require an additional reset circuit, which simplifies the process and reduces the area of ​​the circuit board.

[0149] Example 10: Figure 10 This is a schematic diagram of a shift register according to a first example of an embodiment of this disclosure; as shown Figure 10As shown, the shift register includes a precharge sub-circuit 1, a storage sub-circuit 2, a duty cycle adjustment sub-circuit 3, a NOT gate 4, and an OR gate. The difference between the tenth example and the seventh example is that the NOT gate 4 responds to the input signal and transmits the first level signal or the second level signal to the third node Q3, and the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 constitute an OR gate as the output sub-circuit 5. The following simulation of the shift register in the first example uses the following parameters: first level signal VSS = -10V, second level signal VDD = 10V; first transistor M1, second transistor M2, third transistor M3, fifth transistor M5, sixth transistor M6, and seventh transistor M7 are all P-type transistors, fourth transistor M4, eighth transistor M8, and ninth transistor M9 are all N-type transistors; input signal high level is 10V, low level is -10V, first clock signal CLK1 high level is 10V, low level is -10V; storage capacitor C1 = 1μf. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0150] The pre-charge sub-circuit 1 includes a third transistor M3. The storage sub-circuit 2 includes C1. The duty cycle adjustment sub-circuit 3 includes a first transistor M1 and a second transistor M2. The NOT gate 4 includes a fourth transistor M4 and a fifth transistor M5. The NOT gate 4 is configured to transmit a first-level signal VSS or a second-level signal VDD to the second node Q2 in response to an input signal. The signal at the input terminal of the NOT gate 4 is a digital signal 1. The OR gate is composed of a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9. The first node Q1 is the connection node of the pre-charge sub-circuit 1, the storage sub-circuit 2, and the duty cycle adjustment sub-circuit 3. The second node Q2 is the node of the control electrode of the seventh transistor M7. In this embodiment, the second node Q2 and the first node Q1 are the same node. The third node Q3 is the connection node between the control electrode of the sixth transistor M6 and the output terminal of the NOT gate 4. The input signal can be an STV signal or the output signal of the previous stage circuit.

[0151] For details, please refer to... Figure 10The control electrode of the third transistor M3 is connected to the input signal, its first electrode is connected to the first node Q1, and its second electrode is connected to the first level signal VSS. This first level signal VSS is transmitted to the first node Q1 to control the control electrode voltages of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first transistor M1 and the second transistor M2. Simultaneously, the first level signal VSS transmitted to the first node Q1 serves as the voltage of one electrode of the storage capacitor C1, working together with the second level signal VDD connected to the other electrode of the storage capacitor C1 to control the charging or discharging speed of the storage capacitor C1. The control electrodes of both the first transistor M1 and the second transistor M2 are connected to the first node Q1. The first electrode of the first transistor M1 is connected to the first clock signal CLK1, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The second electrode of the second transistor M2 is connected to the first node Q1. Responding to the voltage of the first clock signal CLK1 and the first node Q1, the first transistor M1 and the second transistor M2 are connected in series to control the duration of the transmission of the first clock signal CLK1 to the first node Q1, i.e., adjusting the duty cycle of the first clock signal CLK1. The control electrodes of the fourth transistor M4 and the fifth transistor M5 are both connected to the first node Q1. The first electrode of the fourth transistor M4 is connected to the second level signal VDD, and the second electrode of the fourth transistor M4 is connected to the third node Q3. The first electrode of the fifth transistor M5 is connected to the first level signal VSS, and the second electrode of the fifth transistor M5 is connected to the third node Q3. The fourth transistor M4 and the fifth transistor M5 together constitute NOT gate 4. The control electrode of the sixth transistor M6 is connected to the third node Q3. The first electrode of the sixth transistor M6 is connected to the first level signal VSS. The second electrode of the sixth transistor M6 is connected to the first electrode of the seventh transistor M7. The control electrode of the seventh transistor M7 is connected to the second node Q2. The first electrode of the seventh transistor M7 is connected to the second electrode of the sixth transistor M6. The second electrode of the seventh transistor M7 is connected to the signal output terminal OUTPUT. The control electrode of the eighth transistor M8 is connected to the second node Q2. The first electrode of the eighth transistor M8 is connected to the signal output terminal OUTPUT. The second electrode of the eighth transistor M8 is connected to the second level signal VDD. The control electrode of the ninth transistor M9 is connected to the third node Q3. The first electrode of the ninth transistor M9 is connected to the signal output terminal OUTPUT. The second electrode of the ninth transistor M9 is connected to the second level signal VDD. The sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 together form an OR gate, which responds to the voltages of the second node Q2 and the third node Q3, that is, responds to the voltage of the input signal terminal and the voltage of the third node Q3, and outputs either the first level signal VSS or the second level signal VDD to the signal output terminal OUTPUT.

[0152] The following describes the operation of the tenth example shift register. (Continue referring to...) Figure 10 and Figure 18The steps for generating each clock cycle signal of the clock signal using the shift register in the tenth example include:

[0153] In the first stage, there is no input signal and no first clock signal CLK1, and the voltage of each node in the circuit is 0V.

[0154] In the second stage, a -10V voltage is written to the input signal terminal, a -10V voltage is written to the first clock signal CLK1, the first transistor M1 and the second transistor M2 are turned off, the third transistor M3 is turned on, after passing through NOT gate 4, the voltage of the second node Q2 is -10V, the voltage of the third node is 10V, the seventh transistor M7 and the ninth transistor M9 are turned on, and the second level signal VDD = 10V is written to the signal output terminal OUTPUT.

[0155] In the third stage, a 10V voltage is written to the input signal terminal, a -10V voltage is written to the first clock signal terminal CLK1, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off, the input signal becomes a low voltage after passing through NOT gate 4, the sixth transistor M6 is turned on, the low voltage stored in the storage voltage C1 turns on the seventh transistor M7, and the first level signal VSS = -10V is written to the signal output terminal OUTPUT.

[0156] In the fourth stage, a 10V voltage is written to the input signal terminal, a 10V voltage is written to the first clock signal terminal CLK1, the third transistor M3 is turned off, the first transistor M1 and the second transistor M2 are turned on, the CLK1 signal is written to the first node Q1, the input signal becomes low voltage after passing through NOT gate 4, the eighth transistor M8 is turned on, and the second level signal VDD=10V is written to the signal output terminal OUTPUT.

[0157] The above four stages constitute the specific driving process of a row of GOA circuits. By cascading multiple GOA circuits, the GOA circuit in the next row continues to output a square wave signal with a certain duty cycle under the control of its clock signal CLKA and the output signal of the GOA circuit in the previous row. The circuit does not require an additional reset circuit, which simplifies the process and reduces the area of ​​the circuit board.

[0158] Example 11: Figure 11 This is a schematic diagram of a shift register according to a first example of an embodiment of this disclosure; as shown Figure 11As shown, the shift register includes a pre-charge sub-circuit 1, a storage sub-circuit 2, a duty cycle adjustment sub-circuit 3, a NOT gate 4, and an OR gate. The difference between Embodiment Eleven and Embodiment Ten is that the ninth transistor M9 is not included. The following simulation uses the following example: a first level signal VDD = 10V, a second level signal VSS = -10V; first transistor M1, second transistor M2, third transistor M3, fifth transistor M5, sixth transistor M6, and seventh transistor M7 are all P-type transistors, and fourth transistor M4 and eighth transistor M8 are both N-type transistors; the high level of the input signal is 10V, and the low level is -10V; the high level of the first clock signal CLK1 is 10V, and the low level is -10V; and the storage capacitor C1 = 1μf. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0159] The pre-charge sub-circuit 1 includes a third transistor M3. The storage sub-circuit 2 includes C1. The duty cycle adjustment sub-circuit 3 includes a first transistor M1 and a second transistor M2. The NOT gate 4 includes a fourth transistor M4 and a fifth transistor M5. The NOT gate 4 is configured to transmit a first-level signal VDD or a second-level signal VSS to the second node Q2 in response to the voltage of the first node Q1. The signal at the input terminal of the NOT gate 4 is a digital signal 1. The OR gate is composed of a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first node Q1 is the connection node of the pre-charge sub-circuit 1, the storage sub-circuit 2, and the duty cycle adjustment sub-circuit 3. The second node Q2 is the node of the control electrode of the seventh transistor M7. In this embodiment, the second node Q2 and the first node Q1 are the same node. The third node Q3 is the connection node between the control electrode of the sixth transistor M6 and the output terminal of the NOT gate 4. The input signal can be an STV signal or the output signal of the previous stage circuit.

[0160] For details, please refer to... Figure 11The control electrode of the third transistor M3 is connected to the input signal, its first electrode is connected to the first node Q1, and its second electrode is connected to the first level signal VSS. This first level signal VSS is transmitted to the first node Q1 to control the control electrode voltages of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first transistor M1 and the second transistor M2. Simultaneously, the first level signal VSS transmitted to the first node Q1 serves as the voltage of one electrode of the storage capacitor C1, working together with the second level signal VDD connected to the other electrode of the storage capacitor C1 to control the charging or discharging speed of the storage capacitor C1. The control electrodes of both the first transistor M1 and the second transistor M2 are connected to the first node Q1. The first electrode of the first transistor M1 is connected to the first clock signal CLK1, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The second electrode of the second transistor M2 is connected to the first node Q1. Responding to the voltage of the first clock signal CLK1 and the first node Q1, the first transistor M1 and the second transistor M2 are connected in series to control the duration of the transmission of the first clock signal CLK1 to the first node Q1, i.e., adjusting the duty cycle of the first clock signal CLK1. The control electrodes of the fourth transistor M4 and the fifth transistor M5 are both connected to the first node Q1. The first electrode of the fourth transistor M4 is connected to the second level signal VDD, and the second electrode of the fourth transistor M4 is connected to the third node Q3. The first electrode of the fifth transistor M5 is connected to the first level signal VSS, and the second electrode of the fifth transistor M5 is connected to the third node Q3. The fourth transistor M4 and the fifth transistor M5 together constitute NOT gate 4. The control electrode of the sixth transistor M6 is connected to the third node Q3. The first electrode of the sixth transistor M6 is connected to the first level signal VSS. The second electrode of the sixth transistor M6 is connected to the first electrode of the seventh transistor M7. The control electrode of the seventh transistor M7 is connected to the second node Q2. The first electrode of the seventh transistor M7 is connected to the second electrode of the sixth transistor M6. The second electrode of the seventh transistor M7 is connected to the signal output terminal OUTPUT. The control electrode of the eighth transistor M8 is connected to the second level signal VDD. The first electrode of the eighth transistor M8 is connected to the signal output terminal OUTPUT. The second electrode of the eighth transistor M8 is connected to the second level signal VDD. The sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 together form an OR gate, which responds to the voltage of the second node Q2 and the third node Q3, that is, responds to the voltage of the input signal terminal and the voltage of the third node Q3, and outputs the first level signal VSS or the second level signal VDD to the signal output terminal OUTPUT.

[0161] The operation of the eleventh example shift register will be described next. (Continue referring to...) Figure 11 and Figure 18 The steps for generating each clock cycle signal of the clock signal using the shift register in the eleventh example include:

[0162] In the first stage, there is no input signal and no first clock signal CLK1, and the voltage of each node in the circuit is 0V.

[0163] In the second stage, -10V voltage is written to the input signal terminal, -10V voltage is written to the first clock signal CLK1, the first transistor M1 and the second transistor M2 are turned off, the third transistor M3 is turned on, after passing through NOT gate 4, the input signal becomes high voltage, the sixth transistor M6 is turned off, the seventh transistor M7 is turned on, the eighth transistor M8 is turned on, and the second level signal VDD=10V is written to the signal output terminal OUTPUT.

[0164] In the third stage, a 10V voltage is written to the input signal terminal, a -10V voltage is written to the first clock signal terminal CLK1, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off, the input signal becomes a low voltage after passing through NOT gate 4, the sixth transistor M6 is turned on, the low voltage stored in the storage voltage C1 turns on the seventh transistor M7, and the first level signal VSS = -10V is written to the signal output terminal OUTPUT.

[0165] In the fourth stage, a 10V voltage is written to the input signal terminal, a 10V voltage is written to the first clock signal terminal CLK1, the third transistor M3 is turned off, the first transistor M1 and the second transistor M2 are turned on, the CLK1 signal is written to the first node Q1, the input signal becomes low voltage after passing through NOT gate 4, the seventh transistor M7 is turned off, the eighth transistor M8 is turned on, and the second level signal VDD=10V is written to the signal output terminal OUTPUT.

[0166] The above four stages constitute the specific driving process of a row of GOA circuits. By cascading multiple GOA circuits, the GOA circuit in the next row continues to output a square wave signal with a certain duty cycle under the control of its clock signal CLKA and the output signal of the GOA circuit in the previous row. The circuit does not require an additional reset circuit, which simplifies the process and reduces the area of ​​the circuit board.

[0167] Example 12; Figure 12 This is a schematic diagram of a shift register according to a first example of an embodiment of this disclosure; as shown Figure 12As shown, the shift register includes a pre-charge sub-circuit 1, a storage sub-circuit 2, a duty cycle adjustment sub-circuit 3, a NOT gate 4, and an OR gate. The difference between Embodiment Twelve and Embodiment Eleven is that the sixth transistor M6 and the seventh transistor M7 are connected in parallel, and the control electrode of the eighth transistor M8 is connected to the fourth level signal VSSH. The following simulation uses the following example: the first level signal VDD = 10V, the second level signal VSS = -10V; the first transistor M1, the second transistor M2, the third transistor M3, and the fifth transistor M5 are all P-type transistors, and the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all N-type transistors; the high level of the input signal is 10V, the low level is -10V, the high level of the first clock signal CLK1 is 10V, and the low level is -10V; and the storage capacitor C1 = 1μf. It should be understood that in actual product use, the above parameters can be adjusted according to actual needs.

[0168] The pre-charge sub-circuit 1 includes a third transistor M3. The storage sub-circuit 2 includes C1. The duty cycle adjustment sub-circuit 3 includes a first transistor M1 and a second transistor M2. The NOT gate 4 includes a fourth transistor M4 and a fifth transistor M5. The NOT gate 4 is configured to transmit a first-level signal VDD or a second-level signal VSS to the second node Q2 in response to the voltage of the first node Q1. The signal at the input terminal of the NOT gate 4 is a digital signal 1. The OR gate is composed of a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first node Q1 is the connection node of the pre-charge sub-circuit 1, the storage sub-circuit 2, and the duty cycle adjustment sub-circuit 3. The second node Q2 is the node of the control electrode of the seventh transistor M7. In this embodiment, the second node Q2 and the first node Q1 are the same node. The third node Q3 is the connection node between the control electrode of the sixth transistor M6 and the output terminal of the NOT gate 4. The input signal can be an STV signal or the output signal of the previous stage circuit.

[0169] For details, please refer to... Figure 12The control electrode of the third transistor M3 is connected to the input signal, its first electrode is connected to the first node Q1, and its second electrode is connected to the first level signal VSS. This first level signal VSS is transmitted to the first node Q1 to control the control electrode voltages of the first transistor M1 and the second transistor M2, thereby controlling the on / off state of the first transistor M1 and the second transistor M2. Simultaneously, the first level signal VSS transmitted to the first node Q1 serves as the voltage of one electrode of the storage capacitor C1, working together with the second level signal VDD connected to the other electrode of the storage capacitor C1 to control the charging or discharging speed of the storage capacitor C1. The control electrodes of both the first transistor M1 and the second transistor M2 are connected to the first node Q1. The first electrode of the first transistor M1 is connected to the first clock signal CLK1, and the second electrode of the first transistor M1 is connected to the first electrode of the second transistor M2. The second electrode of the second transistor M2 is connected to the first node Q1. Responding to the voltage of the first clock signal CLK1 and the first node Q1, the first transistor M1 and the second transistor M2 are connected in series to control the duration of the transmission of the first clock signal CLK1 to the first node Q1, i.e., adjusting the duty cycle of the first clock signal CLK1. The control electrodes of the fourth transistor M4 and the fifth transistor M5 are both connected to the first node Q1. The first electrode of the fourth transistor M4 is connected to the second level signal VDD, and the second electrode of the fourth transistor M4 is connected to the third node Q3. The first electrode of the fifth transistor M5 is connected to the first level signal VSS, and the second electrode of the fifth transistor M5 is connected to the third node Q3. The fourth transistor M4 and the fifth transistor M5 together constitute NOT gate 4. The control electrode of the sixth transistor M6 is connected to the third node Q3, the first electrode of the sixth transistor M6 is connected to the second level signal VDD, and the second electrode of the sixth transistor M6 is connected to the signal output terminal OUTPUT. The control electrode of the seventh transistor M7 is connected to the second node Q2, the first electrode of the seventh transistor M7 is connected to the second level signal VDD, and the second electrode of the seventh transistor M7 is connected to the signal output terminal OUTPUT. The control electrode of the eighth transistor M8 is connected to the third level signal VDDH, the first electrode of the eighth transistor M8 is connected to the signal output terminal OUTPUT, and the second electrode of the eighth transistor M8 is connected to the second level signal VDD. The sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 together form an OR gate, which responds to the voltages of the second node Q2 and the third node Q3, that is, responds to the voltage of the input signal terminal and the voltage of the third node Q3, and outputs either the first level signal VSS or the second level signal VDD to the signal output terminal OUTPUT.

[0170] The operation of the twelfth example shift register will be described next. (Continue referring to...) Figure 12 and Figure 18 The steps for generating each clock cycle signal of the clock signal using the shift register in the twelfth example include:

[0171] In the first stage, there is no input signal and no first clock signal CLK1, and the voltage of each node in the circuit is 0V.

[0172] In the second stage, -10V voltage is written to the input signal terminal, -10V voltage is written to the first clock signal CLK1, the first transistor M1 and the second transistor M2 are turned off, the third transistor M3 is turned on, after passing through NOT gate 4, the input signal becomes high voltage, the sixth transistor M6 is turned on, the seventh transistor M7 is turned off, and the second level signal VDD=10V is written to the signal output terminal OUTPUT.

[0173] In the third stage, a 10V voltage is written to the input signal terminal, a -10V voltage is written to the first clock signal terminal CLK1, the first transistor M1, the second transistor M2, and the third transistor M3 are all turned off, the input signal becomes a low voltage after passing through NOT gate 4, the sixth transistor M6 is turned off, the low voltage stored in the storage voltage C1 turns off the seventh transistor M7, the eighth transistor M8 is normally open, and the first level signal VSS = -10V is written to the signal output terminal OUTPUT.

[0174] In the fourth stage, a 10V voltage is written to the input signal terminal, a 10V voltage is written to the first clock signal terminal CLK1, the third transistor M3 is turned off, the first transistor M1 and the second transistor M2 are turned on, the CLK1 signal is written to the first node Q1, the input signal becomes low voltage after passing through NOT gate 4, the seventh transistor M7 is turned on, and the second level signal VDD=10V is written to the signal output terminal OUTPUT.

[0175] The above four stages constitute the specific driving process of a row of GOA circuits. By cascading multiple GOA circuits, the GOA circuit in the next row continues to output a square wave signal with a certain duty cycle under the control of its clock signal CLKA and the output signal of the GOA circuit in the previous row. The circuit does not require an additional reset circuit, which simplifies the process and reduces the area of ​​the circuit board.

[0176] Secondly, this disclosure provides a pixel driving circuit, which includes multiple cascaded shift registers as described in any of the above embodiments. The signal input terminal of the shift register in this stage is connected to the signal output terminal of the shift register in the previous stage. Its implementation principle is similar to the working principle of the shift registers described above, and will not be repeated here.

[0177] Thirdly, this disclosure provides a display device that includes the pixel driving circuit provided in any of the above embodiments. The display device can be any product or component with display functionality, such as a television, mobile phone, monitor, laptop computer, or navigator. Its implementation principle is similar to that of the shift register and gate driving circuit described above, and will not be repeated here.

[0178] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A shift register, comprising: Precharge sub-circuit, storage sub-circuit, duty cycle adjustment sub-circuit, NOT gate, output sub-circuit; The pre-charge sub-circuit is configured to transmit a first-level signal to the first node in response to an input signal at the input signal terminal; The first node is the connection node of the pre-charge sub-circuit, the storage sub-circuit, and the duty cycle adjustment sub-circuit; The storage sub-circuit is configured to control the operating duration of the duty cycle adjustment sub-circuit based on the second level signal and the first node voltage; The duty cycle adjustment sub-circuit is configured to transmit a first clock signal to the first node in response to the first node voltage; The NOT gate is configured to transmit either the first level signal or the second level signal to the second node in response to the voltage of the first node. Alternatively, the NOT gate is configured to transmit either the first level signal or the second level signal to the third node in response to an input signal; The second node is the connection node between the output terminal of the NOT gate and the output sub-circuit, or the second node is the connection node between the duty cycle adjustment sub-circuit and the output sub-circuit; the third node is the connection node between the input signal terminal and the output sub-circuit, or the third node is the connection node between the output terminal of the NOT gate and the output sub-circuit. The output sub-circuit is configured to output either the first level signal or the second level signal to the signal output terminal in response to the second node voltage and the third node voltage.

2. The shift register according to claim 1, wherein, The pre-charge sub-circuit includes: a third transistor; The control electrode of the third transistor is connected to the input signal terminal, the first electrode is connected to the first node, and the second electrode is connected to the first level signal terminal.

3. The shift register according to claim 2, wherein, The duty cycle adjustment sub-circuit includes: a first transistor and a second transistor; the switching characteristics of the first transistor and the second transistor are the same as those of the third transistor. The control electrode of the first transistor is connected to the first node, the first electrode is connected to the first clock signal terminal, and the second electrode is connected to the first electrode of the second transistor. The control electrode of the second transistor is connected to the first node, the first electrode is connected to the second electrode of the first transistor, and the second electrode is connected to the first node.

4. The shift register according to claim 1, wherein, The storage sub-circuit includes: a first storage capacitor; One terminal of the first storage capacitor is connected to the second level signal terminal, and the other terminal is connected to the first node.

5. The shift register according to claim 1, wherein, The NOT gate includes a fourth transistor and a fifth transistor; the switching characteristics of the fourth transistor are opposite to those of the fifth transistor; when the NOT gate is configured to respond to the first node voltage, The control electrode of the fourth transistor is connected to the first node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the second node; the control electrode of the fifth transistor is connected to the first node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the second node.

6. The shift register according to claim 1, wherein, The NOT gate includes a fourth transistor and a fifth transistor; the switching characteristics of the fourth transistor are opposite to those of the fifth transistor; when the NOT gate is configured to respond to an input signal, The control electrode of the fourth transistor is connected to the input signal terminal, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the third node; the control electrode of the fifth transistor is connected to the input signal terminal, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the third node.

7. The shift register according to claim 1, wherein, The output sub-circuit includes a sixth transistor, a seventh transistor, and an eighth transistor; the switching characteristics of the sixth transistor are the same as those of the seventh transistor.

8. The shift register according to claim 7, wherein, The control electrode of the sixth transistor is connected to the third node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first electrode of the seventh transistor; the control electrode of the seventh transistor is connected to the second node, the first electrode is connected to the second electrode of the sixth transistor, and the second electrode is connected to the signal output terminal; the control electrode of the eighth transistor is connected to the fourth level signal terminal, the first electrode is connected to the signal output terminal, and the second electrode is connected to the second level signal terminal.

9. The shift register according to claim 7, wherein, The control electrode of the sixth transistor is connected to the third node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first electrode of the seventh transistor; the control electrode of the seventh transistor is connected to the second node, the first electrode is connected to the second electrode of the sixth transistor, and the second electrode is connected to the signal output terminal; the control electrode of the eighth transistor is connected to the second level signal terminal, the first electrode is connected to the signal output terminal, and the second electrode is connected to the second level signal terminal.

10. The shift register according to claim 7, wherein, The control electrode of the sixth transistor is connected to the third node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the signal output terminal; the control electrode of the seventh transistor is connected to the second node, the first electrode is connected to the second level signal terminal, and the second electrode is connected to the signal output terminal; the control electrode of the eighth transistor is connected to the third level signal terminal, the first electrode is connected to the signal output terminal, and the second electrode is connected to the first level signal terminal.

11. The shift register according to claim 7, wherein, The output sub-circuit further includes: a ninth transistor; the switching characteristics of the eighth transistor are the same as those of the ninth transistor, and the switching characteristics of the sixth transistor are opposite to those of the eighth transistor; The control electrode of the sixth transistor is connected to the third node, the first electrode is connected to the first level signal terminal, and the second electrode is connected to the first electrode of the seventh transistor. The control electrode of the seventh transistor is connected to the second node, the first electrode is connected to the second electrode of the sixth transistor, and the second electrode is connected to the signal output terminal. The control electrode of the eighth transistor is connected to the second node, the first electrode is connected to the signal output terminal, and the second electrode is connected to the second level signal terminal. The control electrode of the ninth transistor is connected to the third node, the first electrode is connected to the signal output terminal, and the second electrode is connected to the second level signal terminal.

12. A pixel driving circuit, wherein, The pixel driving circuit includes: a plurality of cascaded shift registers according to any one of claims 1-11; The input signal terminal of the shift register described in this stage is connected to the signal output terminal of the shift register described in the previous stage.

13. A display device, wherein, The display device includes the pixel driving circuit as described in claim 12.

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