Programmable gate array based on three-dimensional writeable memory

Abstract

The present application provides a programmable gate array, which can implement different mathematical functions. The programmable gate array comprises a plurality of programmable connections and a plurality of programmable computing units. Each programmable computing unit comprises at least one memory array, which stores a look-up table (LUT) of a mathematical function. In a setting stage, the LUT of the mathematical function is loaded into the memory array according to user needs; in a computing stage, the value of the mathematical function is obtained by looking up the LUT.

Description

[0001] This application is a divisional application of Chinese patent application No. 201710126067.3, filed on March 6, 2017, entitled "Programmable Gate Array Based on Three-Dimensional Writable Memory". Technical Field

[0002] This invention relates to the field of integrated circuits, and more specifically, to programmable gate arrays. Background Technology

[0003] Programmable gate arrays (PGAs) are a type of semi-custom integrated circuit, meaning that logic circuits can be customized through back-end processes or field programming. US Patent 4,870,302 discloses a PGA. It contains multiple configurable logic elements (or configurable logic blocks) and programmable interconnects (or programmable interconnects). The programmable logic elements, under the control of setting signals, can selectively implement functions such as shifting, logical NOT, AND, OR, NOR, NAND, XOR, +, and -. The programmable interconnects, under the control of setting signals, can selectively implement functions such as connecting and disconnecting two interconnects.

[0004] Currently, many applications involve the computation of complex mathematical functions. To ensure execution speed, high-performance applications require the hardware implementation of these complex mathematical functions. In existing programmable gate arrays (PLA), these complex mathematical functions are implemented using fixed computational units. These fixed computational units are part of a hard block, and their circuitry is fixed and cannot be reconfigured. Clearly, fixed computational units limit the further application of PLAs. To overcome this difficulty, this invention extends the concept of programmable gate circuits, making the fixed computational units programmable. Specifically, in addition to programmable logic units, PLAs also contain programmable computational units. These programmable computational units can selectively implement any of a variety of mathematical functions. Summary of the Invention

[0005] The main purpose of this invention is to promote the application of programmable gate circuits in the field of complex mathematical calculations.

[0006] Another objective of this invention is to provide a programmable gate circuit whose logic function can be customized, and whose computational function can also be customized.

[0007] Another objective of this invention is to provide a programmable gate array (PGA) with more flexible and powerful computing capabilities.

[0008] Another objective of this invention is to provide a programmable gate array with a smaller chip area and lower cost.

[0009] To achieve these and other objectives, this invention proposes a programmable gate array (GGA) based on three-dimensional writable memory (3D-W). It comprises an array of programmable computing units, an array of programmable logic units, and multiple programmable connections. Each programmable computing unit contains at least one 3D-W array, which stores a lookup table (LUT) for a mathematical function. The use of the programmable computing unit is divided into two phases: a setup phase and a computation phase. In the setup phase, the LUT for the required mathematical function is loaded into the 3D-W array according to user needs; in the computation phase, the value of the basic mathematical function is obtained by looking up the LUT. Due to the use of the 3D-W array, different mathematical functions can be implemented even within the same batch of chips. Moreover, for a GGA based on a three-dimensional multiple reprogrammable memory (3D-MTP) array, since different mathematical function LUTs can be loaded onto the 3D-MTP array at different times, this GGA enables reconfigurable computation. In this invention, complex mathematical functions refer to mathematical functions other than arithmetic addition (+) and arithmetic subtraction (-), including transcendental functions, multivariable functions, etc.

[0010] In addition to programmable computing units, programmable gate arrays (PGAs) also contain multiple programmable logic units (PLUs) and programmable connections. In implementation, complex mathematical functions are first decomposed into multiple basic mathematical functions. Then, a corresponding programmable computing unit is set for each basic mathematical function to implement that function. Finally, by configuring the programmable logic units and programmable connections, the desired complex mathematical function is realized.

[0011] Using 3D-W (3D-Warehouse) architecture to implement programmable gate arrays (GGAs) offers several advantages. First, due to its large storage capacity, 3D-W can store larger LUTs (Logical Units). Second, 3D-W arrays can be three-dimensionally integrated, allowing arrays belonging to different programmable computing units to be stacked together, reducing the substrate area required for the GGAs. Finally, since 3D-W arrays occupy virtually no substrate area, programmable logic units and / or programmable connections can be integrated beneath the 3D-W array, further reducing the required substrate area.

[0012] Accordingly, the present invention proposes a programmable computing unit (100), characterized in that it comprises: a semiconductor substrate (0) containing transistors; a three-dimensional writable memory (3D-W) array (110) stacked on the semiconductor substrate (0), the 3D-W array (110) storing at least a partial lookup table (LUT) of a mathematical function; a set signal (125) that, when the set signal (125) is "write", writes the value of a mathematical function into the 3D-W array (110); and when the set signal (125) is "read", reads the value of the mathematical function from the 3D-W array (110).

[0013] The present invention also proposes a programmable gate array (400) for implementing a complex mathematical function, characterized in that it comprises: a programmable computing unit array (100AA-100AD) containing at least one programmable computing unit (100), the programmable computing unit (100) containing a three-dimensional writable memory (3D-W) array (110) and storing at least a partial lookup table (LUT) of a basic mathematical function; a programmable logic unit array (200AA-200AD) containing at least one programmable logic unit (200), the programmable logic unit selectively implementing a logic operation from a logic operation library; a plurality of programmable connections (300) coupling the programmable computing unit array and the programmable logic unit array; the programmable gate array (400) implements the complex mathematical function by programming the programmable computing unit (100AA-100AD), the programmable logic unit (200AA-200AD) and the programmable connections (300), the complex mathematical function being a combination of the basic mathematical functions. Attached Figure Description

[0014] Figure 1 This is a cross-sectional view of a three-dimensional writable memory (3D-W).

[0015] Figure 2 It is a symbol for a programmable computing unit.

[0016] Figure 3 This is the substrate circuit layout diagram of the first programmable computing unit.

[0017] Figure 4 This is a layout diagram of a programmable gate array.

[0018] Figure 5 This represents two usage cycles of a reconfigurable gate array.

[0019] Figure 6A Disclose a connection library that implements programmable connections; Figure 6B A logic operation library implemented using programmable logic units is disclosed.

[0020] Figure 7A This is the substrate circuit layout diagram of the second type of programmable computing unit; Figure 7B yes Figure 4 Cross-sectional view of the 100AA-100AD programmable computing unit.

[0021] Figure 8 It is a layout diagram of a specific implementation of a programmable gate array.

[0022] Please note that these figures are schematic diagrams only and are not drawn to scale. For clarity and convenience, some dimensions and structures in the figures may be enlarged or reduced. In different embodiments, the same symbols generally denote corresponding or similar structures. Implementation

[0023] Figure 1 This is a cross-sectional view of a three-dimensional writable memory (3D-W). 3D-W is a type of three-dimensional memory (3D-M), and its stored information is entered using electrical programming. Based on the number of times it can be programmed, 3D-W is further divided into three-dimensional programmable-once memory (3D-OTP) and three-dimensional programmable-multiple-time memory (3D-MTP). 3D-OTP can be programmed once, while 3D-MTP can be reprogrammed. Common 3D-W types include 3D-XPoint (three-dimensional crosspoint array memory), 3D-RRAM (three-dimensional impedance memory), 3D memristor (three-dimensional resistor), and 3D-OTP (three-dimensional programmable-once memory).

[0024] 3D-W 10 includes a substrate circuit layer 0K formed on a substrate 0. A memory layer 16A is stacked on the substrate circuit 0K, and a memory layer 16B is stacked on top of the memory layer 16A. The substrate circuit layer 0K contains peripheral circuitry for the memory layers 16A and 16B, including transistors 0t and their interconnects 0i (including 0M1-0M2). The transistors 0t are formed in a semiconductor substrate 0; the interconnects 0i contain interconnect layers 0M1-0M3. Each memory layer (e.g., 16A) contains multiple first address lines (e.g., 2a, along the y-direction), multiple second address lines (e.g., 1a, along the x-direction), and multiple 3D-P memory cells (e.g., 1aa). The memory layers 16A and 16B are coupled to the substrate 0 through contact vias 1av and 3av, respectively.

[0025] In a 3D-W chip, each memory layer contains multiple 3D-W arrays. A 3D-W array is a collection of all memory cells in a memory layer that share at least one address line. Within a 3D-W array, all address lines are contiguous and do not share any address lines with different 3D-W arrays. Furthermore, a 3D-W chip contains multiple 3D-W modules. Each 3D-W module includes all memory layers in the 3D-W chip, with its top memory layer containing only one 3D-W array, and the projection of this 3D-W array onto the substrate determines the boundary of the 3D-W module.

[0026] The 3D-W memory cell 1aa contains a programming film 12 and a diode film 14. The programming film 12 can be an antifuse film for 3D-OTP, or another multi-programmable film for 3D-MTP. The diode film 14 has the following generalized characteristics: its resistance is low at the read voltage; its resistance is high when the applied voltage is less than the read voltage or opposite in direction to the read voltage. The diode film can be a PiN diode or a metal oxide (such as TiO2) diode, etc.

[0027] Figure 2 This is a symbol for a programmable computing unit 100. Its input terminal IN includes input data 115, its output terminal OUT includes output data 135, and its setting terminal CFG includes a setting signal 125. When the setting signal 125 is "write", the required basic mathematical function LUT is written into the programmable computing unit 100. When the setting signal 125 is "read", the value in the LUT is read from the programmable computing unit 100.

[0028] Figure 3 This is a layout diagram of the substrate circuit 0K of the first programmable computing unit 100. Since the 3D-W array is stacked above the substrate circuit 0K and is not in the substrate, only dashed lines are used to represent the projection of the 3D-W array onto the substrate 0. In this embodiment, the LUT is stored in at least one 3D-W array 110. The substrate circuit 0K includes peripheral circuitry for the 3D-W array 110: its X decoder 15, Y decoder (including readout circuitry) 17, and Z decoder 19, etc.

[0029] Figure 4This describes a programmable gate array (GGMA) 400. It contains regularly arranged programmable modules 400A and 400B, etc. Each programmable module (e.g., 400A) contains multiple programmable computing units (e.g., 100AA-100AD) and programmable logic units (e.g., 200AA-200AD). Programmable channels 320 and 340 are located between the programmable computing units (e.g., 100AA-100AD) and the programmable logic units (e.g., 200AA-200AD); programmable channels 310, 330, and 350 are also located between programmable modules 400A and 400B. Programmable channels 310-350 contain multiple programmable connections 300. For those skilled in the art, in addition to programmable channels, designs such as sea-of-gates can also be employed.

[0030] Figure 5 The two usage cycles 620 and 660 represent the reconfigurable gate array 400. The first usage cycle 620 is divided into two phases: a setup phase 610 and a computation phase 630. In the setup phase 610, a first lookup table associated with a first mathematical function is loaded into the 3D-MTP array 110 according to user needs; in the computation phase 630, the corresponding LUT is looked up in the 3D-MTP array 110 to obtain the value of the first mathematical function. Similarly, the second usage cycle 660 also contains the same setup phase 650 and computation phase 670. Reconfigurable computing is particularly suitable for SIMD (Single Instruction Multiple Data) data processing. Once the LUT is loaded into the 3D-MTP array 110 in the setup phase 610, a large amount of data can be sent to the programmable computing unit 100 for processing, achieving high processing speed. There are many applications of SIMD, such as the same operation on multiple pixels or vector operations in image processing, and large-scale parallel computing used in scientific computing. In addition, the programmable gate array can also pipeline the computation in its programmable computing unit to further improve throughput.

[0031] Figure 6AA programmable connection library that can be implemented by a programmable connection 300 is disclosed. This programmable connection 300 is similar to the programmable connection disclosed in U.S. Patent 4,870,302. It employs one of the following connection library connection methods: a) interconnects 302 / 304 are connected, and interconnects 306 / 308 are connected, but 302 / 304 is not connected to 306 / 308; b) interconnects 302 / 304 / 306 / 308 are all connected; c) interconnects 306 / 308 are connected, and interconnects 302 and 304 are not connected, nor are they connected to 306 / 308; d) interconnects 302 / 304 are connected, and interconnects 306 and 306 are not connected, nor are they connected to 302 / 304; e) interconnects 302, 304, 306, and 306 are all not connected. In this specification, the symbol “ / ” between two interconnects indicates that the two interconnects are connected, and the symbol “,” between two interconnects indicates that the two interconnects are not connected.

[0032] Figure 6B A logic operation library that can be implemented by a programmable logic unit 200 is disclosed. Its inputs A and B are input data 210 and 220, respectively, and its output C is output data 230. This programmable logic unit 200 is similar to the programmable logic unit disclosed in US Patent 4,870,302. It can implement at least one of the following logic operation libraries: C=A, A logical NOT, A shift, AND(A,B), OR(A,B), NAND(A,B), NOR(A,B), XOR(A,B), arithmetic addition A+B, arithmetic subtraction AB, etc. The programmable logic unit 200 may also contain sequential circuit elements such as registers and flip-flops to implement pipelined operations.

[0033] Figure 7A This is a layout diagram of the second type of programmable computing unit 100. Since the 3D-W array 110 does not occupy substrate area, the programmable logic unit 200 can be integrated below and at least partially covered by the 3D-W array 110. In addition, programmable connections can also be integrated below and at least partially covered by the 3D-W array 110. All these measures can reduce the chip area of ​​the programmable gate array 400.

[0034] Figure 7B yes Figure 4Cross-sectional view of programmable computing units 100AA-100AD. To further reduce the chip area of ​​the programmable gate array 400, the 3D-W array can be three-dimensionally integrated. The 3D-W array 110AA (LUT A storing the first basic mathematical function, located in memory layer 16A) in programmable computing unit 100AA is stacked on the substrate circuit 0K (+z direction). The 3D-W array 110AB (LUT B storing the second basic mathematical function, located in memory layer 16B) in programmable computing unit 100AB is stacked on the 3D-W array 110AA (+z direction). The 3D-W array 110AC (LUT C storing the third basic mathematical function, located in memory layer 16C) in programmable computing unit 100AC is stacked on the 3D-W array 110AB (+z direction). The 3D-W array 110AD (LUT D storing the fourth basic mathematical function, located in memory layer 16D) in programmable computing unit 100AD is stacked on the 3D-W array 110AC (+z direction). Additionally, programmable logic units or programmable connections can be integrated into the substrate circuit 0K, which is at least partially covered by the 3D-W array 110AA-210AD.

[0035] Figure 8 This is a specific implementation of a programmable gate array 400, used to implement a complex mathematical function: e=a . sin(b)+c . cos(d). In programmable channels 310-350, programmable connection 300 adopts... Figure 6A The representation in the code is as follows: a programmable connection with a dot at the intersection indicates that the lines are connected; a programmable connection without a dot at the intersection indicates that the lines are not connected; and a broken programmable connection indicates that the disconnected interconnect line is divided into two unconnected interconnect line segments. In this embodiment, programmable computing unit 100AA is set to log(), and its calculation result log(a) is sent to the first input of programmable logic unit 200AA. Programmable computing unit 100AB is set to log[sin()], and its calculation result log[sin(b)] is sent to the second input of programmable logic unit 200AA. Programmable logic unit 200AA is set to "arithmetic addition", and its calculation result log(a) + log[sin(b)] is sent to programmable computing unit 100BA. Programmable computing unit 100BA is set to exp(), and its calculation result exp{log(a) + log[sin(b)]} = a . sin(b) is sent to the first input of the programmable logic unit 200BA. Similarly, with appropriate settings, the result c of the programmable computing units 100AC, 100AD, programmable logic unit 200AC, and programmable computing unit 100BC is... .cos(d) is fed to the second input of the programmable logic unit 200BA. The programmable logic unit 200BA is configured for "arithmetic addition", a . sin(b) and c . cos(d) is added here, and the final result is sent to output e. Clearly, by changing the settings, the Programmable Gate Array 400 can also implement other complex mathematical functions.

[0036] This manual uses Field-Programmable Gate Arrays (FPGAs) as examples. In an FPGA, the wafer completes all processes (including all programmable computing units, programmable logic units, and programmable connections). In the programming environment, the functionality of the FPGA is defined by configuring the programmable connections. The FPGA example described above can be easily extended to traditional programmable gate arrays. In traditional programmable gate arrays, the wafer is only partially completed; that is, wafer fabrication only completes the programmable computing units and programmable logic units, but not the programmable connections. Once the chip's functionality is determined, the programmable channels 310-350 are customized through back-end processes.

[0037] It should be understood that modifications to the form and details of the invention may be made without departing from the spirit and scope thereof, and such modifications do not preclude the application of the spirit of the invention. Therefore, the invention should not be limited in any way except in accordance with the spirit of the appended claims.

Claims

1. A programmable gate array (400), characterized in that... contain: Multiple programmable connections, each of which selectively implements a connection from a connection library; Multiple programmable computing units, each of the programmable computing units comprising: at least one three-dimensional writable storage 3D-W array (110), the three-dimensional writable storage 3D-W array (110) storing a lookup table LUT of a mathematical function, the mathematical function being a mathematical function other than arithmetic addition '+' and arithmetic subtraction '-'; During the setup phase, the lookup table (LUT) of the mathematical function is loaded into the three-dimensional writable storage 3D-W array (110) according to the user's needs; During the calculation phase, the value of the mathematical function is obtained by looking up the lookup table (LUT). The programmable gate array (400) enables programmable computing by programming the plurality of programmable connections and the plurality of programmable computing units.

2. The programmable gate array (400) according to claim 1, further characterized in that: The mathematical function includes a transcendental function and / or a multivariable function.

3. The programmable gate array (400) according to claim 1, further characterized in that: The three-dimensional writable storage 3D-W array (110) is reprogrammable.

4. The programmable gate array (400) according to claim 1, further characterized in that... It contains: another three-dimensional writable storage 3D-W array (110AB), which is stacked on top of the three-dimensional writable storage 3D-W array (110).

5. The programmable gate array (400) according to any one of claims 1-4, further characterized in that: The programmable computing unit implements different mathematical functions at different times.

6. The programmable gate array (400) according to any one of claims 1-4, further characterized in that: The three-dimensional writable storage 3D-W array (110) covers at least a portion of the programmable connection.

7. The programmable gate array (400) according to any one of claims 1-4, characterized in that... It contains: multiple programmable logic units, each of which selectively implements a logic operation from a logic operation library.

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