Mitigating voltage offset caused by mechanical stress in bandgap voltage reference circuits

Abstract

A bandgap voltage reference circuit includes first and second transistors (Q1 and Q2) (e.g., 3-terminal BJTs or diode-connected BJTs) and a PTAT element (e.g., a resistor or a capacitor). The first transistor (Q1) is located at a first die location and operates at a first base-emitter voltage. The second transistor (Q2) is located at a second die location and operates at a second base-emitter voltage. Each of the first and second transistors can include multiple individually connected transistors in parallel. The PTAT element is operatively coupled to the first and second transistors such that a voltage difference between the first and second base-emitter voltages drops across the PTAT element. The first and second locations are spaced apart by a distance (e.g., 1.5% or more of a die length, or such that respective centroids of the first and second transistors are spaced apart from one another). This spatial distribution helps mitigate voltage shifts caused by mechanical stress and is insensitive to process variations.

Description

Technical Field

[0001] This article relates to bandgap voltage reference circuits, and more specifically to mitigating voltage offsets caused by mechanical stress in bandgap voltage reference circuits. Background Technology

[0002] A bandgap voltage reference is a circuit that outputs a fixed voltage that remains stable regardless of temperature. Generally, a bandgap voltage reference circuit is configured to generate a first internal voltage and a second internal voltage, which are added together to provide the output voltage. Because the temperature coefficient of the first internal voltage source is positive and the temperature coefficient of the second internal voltage source is negative, the output voltage is not sensitive to temperature. Therefore, by adding the first and second internal voltages, the temperature dependence is canceled out or otherwise mitigated. While many examples exist, one such example circuit is implemented in silicon using bipolar junction transistors and has an output voltage of approximately 1.25V, which roughly corresponds to the theoretical bandgap of silicon (approximately 1.22eV at 0K).

[0003] Such bandgap voltage reference circuits have numerous applications. One example application is in the context of a digital-to-analog converter (DAC), which converts a digital input word into an analog output voltage. The analog output voltage is based on the digital word and a voltage reference generated internally by the DAC. A similar application is in the context of an analog-to-digital converter (ADC), which converts an analog input signal into its digital equivalent. The digital output word is based on the analog input and an internal voltage reference. In any of these example applications, the internal voltage reference can be provided by a bandgap voltage reference circuit, which helps maintain the accuracy of the DAC or ADC conversion process over a relatively wide temperature range.

[0004] Unfortunately, there are still unresolved issues regarding the bandgap voltage reference circuit. Summary of the Invention

[0005] Integrated circuits including bandgap voltage reference circuits are described, as well as electronic systems including these integrated circuits.

[0006] In one example, the integrated circuit includes a package and a die housed within the package. The die includes a bandgap voltage reference circuit and has opposing edges that partially define the outer perimeter of the die. These opposing edges are spaced apart by a distance D1. The bandgap voltage reference circuit includes a first transistor, a second transistor, and a resistor or capacitor. The first transistor is located at a first position on the die and operates with a first base-emitter voltage. The second transistor is located at a second position on the die and operates with a second base-emitter voltage. The resistor or capacitor is operatively coupled to the first and second transistors such that the voltage difference between the first and second base-emitter voltages decreases across the resistor or capacitor. The second position is separated from the first position by a distance D2. The distance D2 is at least 1.5% of the distance D1.

[0007] In another example, the integrated circuit includes a package and a die secured within the package. The die includes a bandgap voltage reference circuit. The bandgap voltage reference circuit is configured to add a temperature-to-absolute-temperature (PTAT) voltage and a temperature-to-absolute-temperature (CTAT) voltage, and includes an array, resistors, and a summing circuit. The array includes a first bipolar junction transistor (BJT) and a second BJT, the first BJT operating at a first base-emitter voltage and the second BJT operating at a second base-emitter voltage. The centroids of the array, the first BJT, and the second BJT are spaced apart from each other. A PTAT element is operatively coupled to the first and second BJTs such that the voltage difference between the first and second base-emitter voltages decreases across the PTAT element. The summing circuit is configured to generate a voltage reference output based on (1) the voltage difference between the first base-emitter voltage and the second base-emitter voltage and (2) the first base-emitter voltage or the other base-emitter voltage.

[0008] In another example, the integrated circuit includes a package and a die secured within the package. The die includes a bandgap voltage reference circuit. The die has a center point and a stress distribution such that the surface stress of the die decreases with increasing distance from the center point. The bandgap voltage reference circuit is configured to add a voltage proportional to absolute temperature (PTAT) and a voltage complementary to absolute temperature (CTAT), and includes a first bipolar junction transistor (BJT), a second BJT, a resistor or capacitor, and a summing circuit. The first BJT is located at a first position on the die and operates with a first base-emitter voltage, and the first position is a first distance from the center point of the die and associated with a first stress value. The second BJT is located at a second position on the die and operates with a second base-emitter voltage, and the second position is a second distance from the center point of the die and associated with a second stress value. The second distance differs from the first distance, and the second stress value differs from the first stress value. A resistor or capacitor is operatively coupled to a first bipolar junction transistor and a second bipolar junction transistor such that the voltage difference between the first base-emitter voltage and the second base-emitter voltage decreases across the resistor or capacitor. A summing circuit is configured to generate a voltage reference output based on (1) the voltage difference between the first base-emitter voltage and the second base-emitter voltage and (2) the first base-emitter voltage or the other base-emitter voltage. Attached Figure Description

[0009] Figure 1a The illustration shows an example bandgap voltage reference circuit that is prone to base-emitter voltage shift with temperature changes due to mechanical stress caused by the solder-down process.

[0010] Figure 1b The diagram illustrates the effect of the down-feed welding process, as... Figure 1a The base-emitter voltage shift occurs due to temperature changes in the bandgap voltage reference circuit.

[0011] Figure 1c The diagram shows Figure 1a The non-distributed nature of the transistor array in the bandgap voltage reference circuit.

[0012] Figure 1d The diagram illustrates a bandgap voltage reference circuit (e.g., Figure 1a The image shows a top view of a non-distributed transistor array (example), and illustrates the common centroid shared by the two active devices in the array.

[0013] Figure 2aAn example bandgap voltage reference circuit according to an embodiment is illustrated, which is configured with a spatially distributed transistor array to mitigate temperature-dependent base-emitter voltage offset caused by mechanical stress due to the down-joining process.

[0014] Figure 2b The figure illustrates a simulation or characterization curve according to an embodiment, which shows the base-emitter voltage offset to... Figure 2a The dependence of transistor positioning in the transistor array of the bandgap voltage reference circuit.

[0015] Figures 2c to 2g Each illustration depicts an embodiment. Figure 2a An example of the distributed properties of a transistor array in a bandgap voltage reference circuit.

[0016] Figures 3a to 3c Further details of an example bandgap voltage reference circuit configured with a spatially distributed transistor array according to an embodiment are illustrated.

[0017] Figures 4a to 4c Each illustration depicts an example electronic system with an integrated circuit according to an embodiment, the integrated circuit including a bandgap voltage reference circuit configured with a spatially distributed transistor array.

[0018] Figure 5 The illustration further details the dependence of the voltage offset caused by down-welding on the transistor positioning of the spatially distributed transistor array of various example bandgap voltage reference circuits configured according to embodiments, relative to a bandgap voltage reference circuit with a non-distributed transistor array.

[0019] Figures 6a to 6c Each illustration shows another example bandgap voltage reference circuit according to an embodiment, which is configured with a spatially distributed transistor array to mitigate temperature-dependent base-emitter voltage offset due to mechanical stress caused by the down-welding process.

[0020] Figure 7 The figure illustrates the dependence of the voltage shift caused by downsoldering on the thickness of the printed circuit board of the bandgap voltage reference circuit.

[0021] Figure 8 The illustration shows that when NPN and PNP transistors are used in a transistor array of a bandgap voltage reference circuit, both are similarly prone to voltage shift caused by downsoldering.

[0022] Figures 9a to 9c The illustrations together depict the mechanical stress on the die of an integrated circuit package caused by the bottom-mounted soldering process.

[0023] Figures 10a to 10bThe diagram illustrates how the mechanical stress on the die caused by down-welding is related to the positioning and therefore varies within the region of the die.

[0024] Figures 11a to 11e Each illustration depicts an example electronic system according to an embodiment, which employs a bandgap voltage reference circuit configured with a spatially distributed transistor array. Detailed Implementation

[0025] This article provides techniques for reducing stress-induced output voltage offset in bandgap voltage reference circuits. While these techniques can be useful in many cases where mechanical stress causes voltage offset, they are particularly useful for addressing voltage and temperature coefficient offsets in integrated bandgap voltage reference circuits caused by mechanical stresses induced by the bottom-mount process when attaching integrated circuit packages and die assemblies to a printed circuit board. According to embodiments described herein, the bandgap voltage reference circuit comprises a spatially distributed array of transistors. In some such embodiments, the transistors in the array are bipolar junction transistors (BJTs), but other active junction devices exhibiting linear voltage offsets in terms of temperature and mechanical stress, as will be understood herein, can also be used. In any such case, instead of clustering all the active junction devices of the array to a single die location as is commonly done, one or more active junction devices in the array are intentionally spaced apart from the other active junction devices in the array. In this way, the array is spatially distributed across two distinct die locations, and these locations experience different amounts of mechanical stress induced by the bottom-mount process. For example, for some integrated circuits, the mechanical stress induced by bottom-mount is highest in the middle of the die and lower near the edges of the die. Therefore, in this example scenario, by placing one or more transistors of the array close to the edge of the die and placing one or more remaining transistors of the array in the middle of the die, the absolute temperature coefficient shift is offset, compensated for, or otherwise reduced by the relative temperature coefficient shift between these two different stress locations. Other such transistor array distribution schemes can be used similarly, where the first and second portions of the array are spaced apart from each other in a manner that mitigates the temperature coefficient shift. Many variations will be understood from this document.

[0026] General Overview

[0027] As previously described, a bandgap voltage reference is a circuit that outputs a fixed voltage that remains stable with temperature variations. However, such circuits are also susceptible to stress-induced temperature coefficient and output voltage deviations caused by mechanical stresses in the die containing the circuit. One such stress is down-soldering stress, which refers to the stress applied to the die when the integrated circuit package containing the die is down-soldered onto a printed circuit board (PCB). For example, each of the die (e.g., silicon or (multiple) other semiconductor materials), the package molding compound, and the PCB can have different coefficients of thermal expansion, thereby generating temperature-dependent stresses on the BJT or other active junction devices used to generate a temperature-invariant voltage reference. Furthermore, the rigid attachment of the integrated circuit to the copper PCB traces creates boundary conditions for this stress. Therefore, down-soldering deviations can lead to a performance degradation relative to the performance before down-soldering. The primary factor contributing to this temperature coefficient deviation is considered to be the base-emitter voltage (VT) of the BJT-based array. BE Offset. One technique to address this issue is to integrate stress gauges or sensors onto the die to measure the stress level of critical units and configure feedforward cancellation based on the outputs of the stress and temperature sensors. However, this approach requires additional circuitry, such as stress sensors in the XYZ directions, temperature sensors, a digital signal processor (DSP), and memory. Furthermore, characterizing the optimal coefficients for each temperature and stress sensor output is not a straightforward task.

[0028] Therefore, this paper provides techniques to mitigate or otherwise reduce the temperature coefficient offset caused by down-welding in a bandgap voltage reference circuit without requiring additional circuitry such as strain sensors and temperature sensors. Circuit architectures employing these techniques allow for the offset or reduction of absolute temperature coefficient offsets via relative temperature coefficient offsets, where both the absolute and relative temperature coefficient offsets are caused by mechanical stresses on the die surface resulting from the down-welding process. No additional circuitry is required because, according to some embodiments, the bipolar junction transistors (or other similar devices) of the array itself are effectively used to sense and mitigate down-welding stresses. Specifically, and according to embodiments, by selectively positioning the bipolar junction transistors of the array at first and second die positions spaced apart from each other and subjected to different amounts of mechanical stress, the absolute Vgap... BE The offset can be relative to V BE The offset is offset or otherwise reduced. In this way, the array is considered distributed, unlike standard bandgap voltage reference circuits that utilize non-distributed arrays with a common centroid. It should be understood that, according to some embodiments, these techniques allow for smaller implementations and lower costs, and can be implemented using any number of standard or proprietary process technologies, and are insensitive to process variations.

[0029] The distributed nature of an array can be characterized in several ways. In one example characterization, the spacing between two array sections with different stresses can be considered in an absolute sense as the distance between the two locations, such as in the following example where each location has a discrete perimeter, the individual transistor at that location lies within that perimeter, and the spacing is the distance from one perimeter edge to the other (or the distance to the geometric center of each perimeter or some other consistent measurement point associated with each perimeter). In another example characterization, the spacing between the two array sections with different stresses can be considered in a relative sense as the distance from each location to a common reference point of the die, such as in the following example where the common reference point is the center point of the die and one location is closer to the die center point than the other. It should be noted that neither of these example characterizations knows which individual transistors in the array are located at which location, but rather focuses on the absolute or relative spacing between the two locations. In yet another example characterization, the spacing between the two array sections with different stresses can be considered as the distance between the centroids of the active devices formed by the entire array, such as in the following example where the array includes a first transistor device and a second transistor device, and the centroid of the first transistor device is spaced apart from the centroid of the second transistor device. It should be noted that in a standard bandgap voltage reference circuit, these centroids, along with the centroid of the entire array, are located at the same location. In any of these examples, it should also be noted that one or both active transistor devices may comprise multiple individual transistors connected in parallel, and some of the individual transistors in a given parallel combination may be located at a first location, while the other individual transistors in that given parallel combination may be located at a second location. It should also be noted that each of these two locations (and therefore these two array portions) experiences different stresses, taking into account the stress distribution after the die is down-welded.

[0030] While the different stress locations of the array transistors can vary depending on the configuration of the integrated circuit package containing the bandgap voltage reference circuit, in some examples, the first portion of the array is located in the middle region of the die, while the second portion is located near the edge of the die. In this case, the distance between the spaced-out array portions is relatively large, especially compared to standard bandgap voltage reference circuits, in which all the individual transistors of the array are clustered as close as possible to the same location and have a common centroid with almost no relative space between them, and die stress distribution is not considered. For example, in some embodiments, the distance between array portions with different stresses is in the range of approximately 1.5% to 65% of the total distance from one edge of the die to the other opposite edge. In other embodiments, the distance between array portions with different stresses can be relatively small, but still much larger than the minimum spacing of a standard bandgap voltage reference circuit array. For example, in some such embodiments, the distance between the corresponding array portions is equal to or greater than the lateral width of an individual cell of the array, or even less than that width. Depending on the type of device used in the array (e.g., BJTs or diode-connected BJTs) and the process technology used to form the device, this lateral width can vary considerably, but in some examples it ranges from 50 to 150 micrometers (μm). In any case, this intentional spacing of array portions to die locations with different stresses, whether the spacing is relatively large or relatively small, will result in the centroids of the active devices formed in the array being spaced apart from each other. In contrast, an array of standard bandgap voltage reference circuits has a common centroid shared by the entire array itself and the active devices formed in the array.

[0031] One of the simplest forms of bandgap reference is two bipolar junction transistors (BJTs) with different emitter area sizes. Each transistor has a different base-emitter voltage (Vo) set by its current density. BE ). V of the first transistor BE With the V of the second transistor BE The relative difference (ΔV) between them BE ) has a positive temperature coefficient, while the V of each of the first and second transistors is BE It has a negative temperature coefficient. Therefore, due to the relative V between the first transistor and the second transistor... BE Difference (ΔV) BE As a given temperature change shifts in the positive direction, the V of the first (or second) transistor... BE The bandgap voltage reference shifts negatively with temperature changes, effectively offsetting or otherwise reducing temperature-based offsets in the output voltage. In other words, the bandgap voltage reference is a voltage (V) that is proportional to a specific absolute temperature (PTAT). BEThe voltage is generated when the relative difference between the bandgap energy of silicon (assuming a silicon-based process technology) and the voltage complementary to the absolute temperature (CTAT) are added together, resulting in a voltage (approximately 1.2V) that is approximately the bandgap energy of silicon. It should be noted that, as will be understood, devices made with other semiconductor materials will provide different bandgap energies, therefore the output voltage reference depends on the semiconductor material used and the circuit configuration.

[0032] Therefore, while the techniques presented herein are particularly well-suited for bandgap voltage reference circuits based on silicon-based BJTs, they can be used with any voltage reference circuit in which the voltage difference between two pn junction devices (e.g., 3-terminal BJTs, diode-connected BJTs, or similar devices) operating at different current densities can be used to generate a PTAT voltage across a temperature-to-absolute-temperature (PTAT) element (e.g., a resistor or capacitor), and this PTAT voltage can be used with one of these devices (or another device, as in the case of a Widlar topology, such as...) Figure 6b The absolute temperature complementary (CTAT) voltage across the terminals (as shown in the example) is added to produce an output voltage approximately equal to the bandgap energy of the semiconductor material used to manufacture these devices. This circuit can be expressed more simply by the following equation or otherwise: V ref =V BE1 +λ(V BE1 -V BE2 ), where λ is the scaling factor (set by the bias resistor of the bandgap voltage reference circuit), V BE2 It is the base-emitter voltage of the larger of the two devices, V BE1 It is the base-emitter voltage of another device, and V ref This is the reference output voltage generated by the bandgap voltage reference circuit. As will be described in sequence, it should be noted that a larger transistor can be produced by connecting multiple individual transistors in parallel, or by increasing the emitter area of ​​a single individual transistor relative to another transistor. It should also be noted that the PTAT element (the PTAT voltage across which can be measured or otherwise accessed) can vary depending on the bandgap voltage reference topology used. For example, in some cases (e.g., in Brokaw and Widlar topologies), the PTAT element can be resistive (one or more resistors), or in other cases (e.g., in switched capacitor topologies), it can be capacitive (one or more capacitors).

[0033] Circuit architecture

[0034] Before describing the example topology configured according to the embodiments, it is helpful to first explain that this topology may solve a problem. Therefore, Figure 1aThe illustration shows an example bandgap voltage reference circuit. Due to mechanical stress caused by the downsinking process, this bandgap voltage reference circuit is prone to base-emitter voltage shift (V) with temperature changes. BE-shift (T)). This example shows that the transistor array is non-distributed; that is, all the transistors constituting Q1 and Q2 are densely located at a single die position, such as... Figure 1c As shown. In this example case, Q1 is a single transistor in the array, and Q2 are eight single transistors connected in parallel in the array. It should be noted that Q1, Q2, and the entire array share a common centroid (roughly represented by a bold circle). Figure 1d Another example array with a common centroid is illustrated, comprising a single transistor Q1 and two separate transistors Q2 connected in parallel (the common centroid is shown at the intersection of the dashed lines). Figure 1a As can be further seen, transistor Q1 is an NPN BJT comprising M individual transistors connected in parallel, while transistor Q2 is an NPN BJT comprising N individual transistors connected in parallel, where each of M and N is an integer (1, 2, 3, ...). The circuit further includes bias resistors R1, R2, and R... ptat These bias resistors effectively define the scaling factor of the voltage reference circuit. The circuit further includes an operational amplifier that is operatively coupled to transistors Q1 and Q2 and resistors R1, R2, and R... ptat Coupling, to pass through ΔV RE The resulting positive temperature coefficient and V RE The resulting negative temperature coefficients cancel each other out to achieve a temperature-insensitive output voltage V. ref As expressed in Equations 1-3 below. Note that k is the Boltzmann constant, T is the absolute temperature of the devices constituting the non-distributed transistor array, and q is the magnitude of the electron charge (elementary charge). The changes will be obvious, for example...

[0035]

[0036]

[0037] R tot =R2 (Equation 3)

[0038] A resistor R exists between ground and the emitters of Q1 and Q2. b In the case of, In any such case, such as Figure 1bAs further shown, the base-emitter voltage of the transistor array still shifts due to the downsoldering process. Therefore, the performance of the bandgap voltage reference circuit after downsoldering is lower than its performance before downsoldering. An example post-downsoldering performance test shows that the temperature coefficient shift of this bandgap voltage reference circuit is 11-12 ppm / °C. It should be noted that the amount of shift can depend on various factors, including, for example, PCB thickness, package material, the process technology used to form the die, and the downsoldering process itself.

[0039] In contrast, the bandgap voltage reference circuit techniques presented in this paper not only mitigate temperature-dependent base-emitter voltage drift but also further reduce base-emitter voltage offset caused by mechanical stress on the die due to the bottom-mount process. Furthermore, these techniques are insensitive to process variations and therefore can be implemented in any number of semiconductor process technologies and materials. For example, the circuit system can be implemented with silicon, germanium, silicon-germanium, and III-V materials such as gallium arsenide, to name just a few. It should also be noted that the techniques presented in this paper can be used with any number of topologies, including standard bandgap voltage reference circuit systems such as Brokaw, Widlar, and switched-capacitor topologies, as well as proprietary topologies. In a more general sense, these techniques can be used with any bandgap voltage reference circuit having an array implemented with active junction devices, where ΔV BE The PTAT (proportional to absolute temperature) term equals Here, N is the number of individual devices constituting the larger device, and M is the number of individual devices constituting the other device. For ease of description, it is assumed that the active junction device is a transistor (e.g., a 3-terminal BJT, a diode-connected BJT, or other active junction devices exhibiting a linear voltage offset similar to a BJT in terms of temperature and mechanical stress). It should be noted that the N / M ratio can also be expressed as the ratio of the emitter areas of a single transistor Q2 and Q1, where the emitter of Q2 is larger than the emitter of Q1 (rather than Q2 comprising more parallel-connected individual transistors than Q1). Therefore, multiple parallel-connected individual transistors or single transistors with suitable emitter sizes can be used for the transistor arrays Q1 and Q2. However, it should be noted that the use of parallel-connected transistors is particularly effective for position-dependent stress adjustment, as presented in different ways herein, given that adding / removing individual transistors in a parallel configuration is relatively easy compared to changing emitter sizes.

[0040] In more detail, Figure 2a The illustration is similar to Figure 1aThe example bandgap voltage reference circuit is shown. However, according to an embodiment, this bandgap voltage reference circuit is configured with a spatially distributed transistor array to mitigate the temperature-dependent base-emitter voltage shift caused by mechanical stress due to the down-laying process. It can be seen that the transistor array includes transistors Q1 and Q2, which can be NPN transistors or PNP transistors (such as...). Figure 8 As shown, these two types respond similarly to the mechanical stress caused by the bottom-welding process. As previously described, each of Q1 and Q2 can comprise a single transistor or multiple single transistors connected in parallel, as in the example cases of Q1(M) and Q2(N), where M = 2 and N = 16; however, it should be noted that if M or N equals 1, there is only a single transistor (no transistors connected in parallel). In this particular example case, Q1 and Q2 are implemented using diode-connected NPN BJTs. As will be understood, a diode-connected BJT is a BJT whose collector is connected to its base. The voltage source symbol is shown between the collector and base, used only to indicate V. BE In this example, ground is used as the reference.

[0041] In any such case, the bandgap voltage reference circuit passes through ΔV BE The resulting positive temperature coefficient and V BE The resulting negative temperature coefficients cancel each other out to achieve a temperature-insensitive output voltage V. ref As previously described with reference to Equations 1-3. In short, when the current is the same or lower, a transistor with a larger number of individual transistors connected in parallel (or otherwise, a larger emitter area) generates a smaller base-emitter voltage relative to another transistor, and thus generates a difference between these two base-emitter voltages. This difference between the two base-emitter voltages is expressed as ΔV. BE And it has a positive temperature coefficient (ΔV) BE (As temperature increases). In contrast, the base-emitter voltage V of each transistor Q1 and Q2... BE It has a negative temperature coefficient (V BE (Decreases with temperature). Circuit output V ref Equal to base-emitter voltage V BE One of them is the base-emitter voltage difference ΔV BE The sum of N / M times. By selecting individual components suitable for a given application, these two opposing temperature coefficients will cancel each other out or otherwise compensate for each other, and the V output of the circuit will... ref It is not sensitive to temperature.

[0042] also, Figure 2a The circuit also makes the output voltage V refIt is less sensitive to temperature coefficient shifts caused by mechanical strain due to the down-lay bonding process. This insensitivity is achieved by intentionally positioning the transistors constituting the distributed array at two different die locations spaced apart from each other, at different points in the overall die stress distribution. It should be noted that this intentional spacing in the distributed array is relatively large compared to the negligible or otherwise very small spacing between individual transistors constituting a non-distributed array. Specifically, the transistors in a non-distributed array are formed directly on and / or in the die and spaced apart by process-specific pitches or critical dimensions, and therefore as close as possible. Furthermore, standard practice is to arrange a single array such that Q1 and Q2 share a common centroid, as... Figures 1c to 1d As shown. In contrast, the spacing of the distributed array according to the embodiment results in a relatively large distance between the locations of two different stresses in the array, causing the centroid of Q1 to be spaced apart from the centroid of Q2, as shown. Figures 2c to 2g Each example is shown.

[0043] Figure 2b The figure illustrates a simulation or characterization curve according to an embodiment, which shows the base-emitter voltage offset to... Figure 2a The dependence of the transistor array's positioning in the bandgap voltage reference circuit. It can be seen that the base-emitter voltage offset (V) of transistor Q1 relative to the first die positioning location... BE1-shift (T) differs from the base-emitter voltage offset (V) of transistor Q2 relative to the second die location. BE2-shift (T)). For example. Figure 2b The curve can be obtained from stress simulation (e.g., based on pre-manufacturing modeling) or characterization (e.g., based on post-manufacturing testing) of a given integrated circuit package and die assembly mounted on a given PCB, or a combination of such simulation and characterization (e.g., where simulated data is refined from actual data). In any case, the curve illustrates how different distances of the two arrays from the die's centerline result in base-emitter voltage shifts.

[0044] This location dependence of the base-emitter voltage offset can be used advantageously. For example, in some examples, by placing all M transistors of Q1, along with some of the N transistors of Q2, at a first location close to the edge of the die (e.g., within 50 μm to 250 μm of the die edge), and placing the remaining N transistors of Q2 at a second location in the middle region of the die (e.g., within 250 μm of the die center), the absolute base-emitter voltage offset can be canceled out or otherwise reduced by the relative base-emitter voltage offset between the first and second locations to maintain the offset of the voltage reference (ΔV). refThis offsetting effect can be ignored or otherwise kept within the desired tolerance. This offsetting effect can be expressed as shown in Equations 4 and 5, where V BE1-shift (T) represents the absolute base-emitter voltage offset, and V BE1-shift (T)-V BE2-shift (T) represents the relative base-emitter voltage offset.

[0045]

[0046] R tot =R2 (Equation 5)

[0047] It should be noted that, according to some embodiments, it can be based on Figure 2b The curve and Equation 4 are used to select the first and second positions of the array. For example, in one example case, assume ΔV ret It is 0 volts (+ / - acceptable tolerance) and the first position of the array is known. For example, the first position could be the original position of the array before any distribution of the array. Therefore, the distance of this first position from the centerline of the die can be used to identify the V corresponding to that distance. BE1-shift Value (e.g.) Figure 2b (As indicated by the curve). With ΔV ref and V BE1-shift The value of V can be used to solve equation 4. BE2-shift The value can then be found by comparing it with the obtained V. BE2-shift The corresponding value Figure 2b The distance between the centerline points of the curve is used to determine the second position. This process can be used for, for example... Figures 2d to 2g The example configuration shown determines the first and second positions of the array. In some cases, such as for Figure 2c The example configuration can be adjusted by splitting the individual transistors constituting Q1 or Q2 between the first and second positions, to provide greater flexibility regarding the first and second positions, as will be discussed in reference. Figure 3c Described.

[0048] The changes will be obvious, such as the previously mentioned resistor R between ground and the emitters of Q1 and Q2. b In the example case, where, In addition, it should be noted that ΔV BE Scaling version and V BE The reaction produces a temperature-stable V ref The summing circuit can be configured to sum V ref The sum is determined to be V BE +ΔV BEThe summing circuit can be implemented using any number of (R2+R1) / R2 circuits, regardless of whether the summing circuit is an operational amplifier configured with negative feedback (e.g., Figure 2a , Figures 3a to 3c , Figure 6a and Figure 6c (example), or transistor (e.g.) Figure 6b (shown as Q3 in the diagram), or configured for the opposite temperature coefficient value ΔV. BE PTAT and V BE Any other circuitry for CTAT summation, as will be understood from this document.

[0049] Therefore, the base-emitter voltage offset depends on the amount of mechanical stress on the individual transistors constituting the array, and this mechanical stress is related to the positioning on the die surface. For this purpose, the base-emitter voltage offset can be achieved through methods such as... Figure 2b The stress of the die is simulated or characterized to predict the stress. Specifically, by selectively positioning individual transistors in the array to achieve a canceling effect, the absolute offset of Q1 (the first term of Equation 4) can be canceled or compensated by the relative offset between Q1 and Q2 (the second term of Equation 4). For example, consider an example case where the stress distribution of the die is symmetrical, with the stress being maximum at the die center and decreasing with increasing radial distance from the center. In such a case, different distances of each array from the die centerline provide different stresses. Figure 2b and Figure 10a In this context, this arrangement is more generally referred to as the difference in distance between the centerline points of the two arrays. In any such case, this selective positioning requires providing a first array of one or more transistors at a first location and a second array of one or more transistors at a second location, as will now be referred to... Figures 2c to 2g Further description.

[0050] exist Figure 2cAs can be seen in the example, the rectangular die comprises a distributed array. This array is distributed because it comprises two distinct, spaced-apart sections, denoted as Array 1 and Array 2. It can be further seen that Arrays 1 and 2 are used to form transistors Q1 and Q2. Specifically, transistor Q1 is formed by a single individual transistor from Array 2, and transistor Q2 is formed by a parallel connection of two individual transistors from Array 1 and six individual transistors from Array 2. Arrays 1 and 2 can be, for example, two different and independently formed arrays, or subarrays of a larger array. Alternatively, these array sections can simply be individual transistors formed in the corresponding positions shown. For the purposes of this document, it is assumed that these arrays are two different and independently formed arrays. For example, Array 1 could be a 3×1 array with a middle dummy cell, and Array 2 could be a 3×3 array with two dummy cells on either side of a single Q1 transistor in the middle row. As will be understood, a dummy cell (or dummy device) is an individual transistor in the array that is not connected to, nor otherwise part of, an active circuit. In all cases, it should be noted that the centroids of Q1, Q2, and the entire array are spaced apart from each other, with the centroid of Q1 shown as a bold square, the centroid of Q2 shown as a bold circle, and the centroid of the entire array shown as a bold triangle. It can be seen that the centroids of Q1 and Q2 are spaced approximately 16.5% of the die length (as measured from the center of the bold circle to the center of the bold square), and the centroid of the entire array lies between these two centroids. In some such embodiments, each centroid lies on an imaginary horizontal line passing through the die's center point, and the surface stress of the die along the imaginary line near the center point is greater than the surface stress along the imaginary line near the edge. Therefore, the surface stress applied to the individual transistors of array 1 is greater than the surface stress applied to the individual transistors of array 2. Other embodiments may have different stress distributions.

[0051] Figure 2d Example cases are similar to Figure 2c The example shown differs in that array 1 is closer to array 2, and array 2 includes a single transistor Q1. (Previous information regarding...) Figure 2c The relevant description also applies here. It can be seen that the centroid of Q1 is spaced approximately 13% of the die length from the centroid of Q2 (as measured from the center of the thickened circle to the center of the thickened square), and the centroid of the entire array lies between these two centroids, but is biased towards the centroid of Q2. In some such embodiments, each centroid lies on an imaginary horizontal line passing through the die's center point, and the surface stress of the die along the imaginary line near the center point is greater than the surface stress along the imaginary line near the edge. Therefore, the surface stress applied to the individual transistors of array 1 is greater than the surface stress applied to the individual transistors of array 2.

[0052] Figures 2e to 2f Each illustration depicts an example of a distributed array comprising two subarrays, which are part of a larger array.

[0053] exist Figure 2e In the distributed transistor array, the two subarrays are distributed because they are spaced apart from each other by dummy cell arrays. More specifically, transistor Q1 is formed by a single individual transistor of subarray 2, which can be a single individual transistor or a 3×1 array (including two dummy cells) or a 5×1 array (including four dummy cells), and transistor Q2 is formed by the parallel connection of eight individual transistors of subarray 1, which can be a 3×3 array (generally indicated by a dashed border and including one dummy cell) or a 5×3 array (including seven dummy cells). As can be further described, subarray 1 and subarray 2 are separated by an intermediate column of dummy cells, which can be considered, for example, a 5×1 dummy cell array. Therefore, the distance between the opposite edges of subarray 1 and subarray 2 is approximately the lateral width of the dummy cell device (e.g., 50 μm to 100 μm in some embodiments). It should also be noted that, similar to Figures 2c to 2d In the example shown, Q1, Q2, and the corresponding centroids of the entire array are spaced apart from each other, and this description also applies. In any case, the positions of the two subarrays can be selected based on the stress difference between these two locations. In some such embodiments, as previously described, the following can be used: Figure 2b The selection process is guided by the corresponding curves and Equation 4. It can be seen that the centroid of Q1 is spaced approximately 15% of the die length from the centroid of Q2 (measured from the center of the thickened circle to the center of the thickened square), and the centroid of the entire array lies between these two centroids. In some such examples, each centroid lies on an imaginary horizontal line passing through the die's center point, and the surface stress of the die along the imaginary line near the center point is greater than the surface stress along the imaginary line near the edge. Therefore, the surface stress applied to the individual transistors of subarray 1 is greater than the surface stress applied to the individual transistors(s) of subarray 2.

[0054] exist Figure 2fIn the distributed transistor array of the die, the two subarrays are adjacent to each other, such that there are no virtual cells between them. However, it should be noted that, according to the embodiments herein, the entire array is distributed because the centroids of its respective subarrays are spaced apart from each other. More specifically, transistor Q1 is formed by a single individual transistor of subarray 2, and transistor Q2 is formed by a parallel connection of eight individual transistors of subarray 1. It can be seen that the centroid of Q1 is spaced approximately 5.1% of the die length from the centroid of Q2 (as measured from the center of the thickened circle to the center of the thickened square), and the centroid of the entire array lies between these two centroids.

[0055] Figure 2g The illustration depicts an example scenario where the distributed array comprises two distinct and spaced-apart sections, denoted as Array 1 and Array 2, each array comprising a single individual transistor. With both M and N equal to 1, the current density can be set by the ratio of R2 / R1, as will be understood. It can be seen that the centroid of Q1 is spaced approximately 20% of the die length from the centroid of Q2 (e.g., measured from the center of the thickened circle to the center of the thickened square), and the centroid of the entire array lies between these two centroids. As in other examples, considering the overall stress distribution of the die, the positions of the two arrays can be chosen based on the stress difference between these two locations, whether the stress distribution is symmetrical (e.g., the stress is highest at the center of the die and decreases with increasing radial distance from the center) or asymmetrical (e.g., the stress is highest at locations away from the die center and does not necessarily decrease with increasing radial distance from that location). In some such embodiments, each centroid lies on an imaginary horizontal line passing through the center point of the die, and the surface stress of the die along the imaginary line near the center point is greater than the surface stress of the die along the imaginary line near the edge. Therefore, the surface stress applied to the individual transistors of array 1 is greater than the surface stress applied to the individual transistors of array 2.

[0056] It should also be noted that in any such embodiment, assuming a relatively symmetrical stress distribution—for example, where the stress is greatest in the central region of the die and decreases with increasing radial distance from the center—the spacing between the centroids can vary, for example, by spacing the centroid of Q1 from the centroid of Q2 by approximately 1.5% of the die length, or 2% of the die length, or 3% or 4% of the die length, etc., up to a maximum of approximately 50% of the die length. In some example cases, the distance between the centroids of Q1 and Q2 ranges from 5 μm to 500 μm (or larger, for example, in cases where one centroid is close to the center point of the relatively larger die, and the other centroid is close to the edge of that die, such that the distance between the centroids of Q1 and Q2 exceeds 1000 μm, or approximately up to about half the lateral width of the die). The centroids of the entire array are typically located between these two centroids and are biased towards the centroid associated with the larger mass (e.g., a device with the most individual transistors connected in parallel, or the largest emitter).

[0057] As will be understood, the term "centroid" as used herein refers to electrical properties and is similar to the mass centroid, and is a commonly used term in simulation layout practice. For example, Figures 1c to 1d The common centroid layout shown generally aligns with the idea of ​​averaging the linear processing gradients that affect the electrical properties of the transistors. In practice, the common centroid layout positions the centroid (center of mass) of each transistor at the same location. In contrast, the distributed arrays presented herein have non-common centroids spaced apart from each other. As mentioned above, the spacing between centroids can vary depending on the embodiment, but is relatively small in some embodiments, such as in the range of 50 μm to 100 μm. It should be noted that in some embodiments, the spacing between centroids can be approximately the same as the lateral width of a single array cell. Figure 2e ), or even smaller than that width ( Figure 2f ).

[0058] As will be further understood, the standard bandgap voltage reference circuit utilizes a common centroid array because it has long been considered necessary for initial matching and production variability. Therefore, using a bandgap voltage reference circuit with a non-common centroid array, as described in different ways herein, yields surprising results. The embodiments described herein are less sensitive to initial matching and production variability because the array spacing and configuration can be adjusted as described herein. It should also be noted that only when V... BE Absolute stress offset and encapsulation variable (downward welding stress versus V) BE Only when the effects of (array) centroid offset and (core) consistent gradient stress distribution are considered together can the benefits be utilized, as described in this paper.

[0059] It should be noted that, as described in different ways herein, an array with the centroids of Q1 spaced apart from those of Q2 can be detected by inspection. For example, according to some embodiments, Q1 and Q2 can be traced back to their respective independent base and emitter connections to distinguish them within the array. The spacing between the centroids is related to stress gradient effects. Knowing these connections, the non-common centroid layout becomes apparent. The larger the space, the better.

[0060] Figures 3a to 3c Further details of example bandgap voltage reference circuits configured with spatially distributed transistor arrays according to embodiments are illustrated. In each example configuration, it can be seen that the transistors constituting the array are distributed such that some transistors are located at die location A, while the remaining transistors are located at die location B. Figure 3a In the example embodiment, the M transistors of Q1 are all located at position A, while the N transistors of Q2 are split between positions A and B. In this example case, it should be noted that: M, N, and X are integers; M is 1 or higher; N is 2 or higher; and X is N-1 or lower. Some example configurations have any of the following integer values: M = 1 to 8; N = 8 to 24; and X = 1 to 23. It should be noted that these example ranges do not limit this document; rather, as will be understood, the values ​​of M, N, and X can vary from embodiment to embodiment, including embodiments where M and / or N are higher, or embodiments where M and N are both 1 and X is 0 (e.g., ...). Figure 2g (As shown). Reference Figure 5 Further examples are described.

[0061] exist Figure 3b In the example embodiment, the M transistors of Q1 are split between locations A and B, while the N transistors of Q2 are all located at location B. In this example case, it should be noted that: M, N, and X are integers; M is 2 or higher; N is 1 or higher; and X is M-1 or lower. Some example configurations have any of the following integer values: M = 8 to 24; N = 1 to 8; and X = 1 to 23. Again, it should be noted that these example ranges are not limiting of this document. It should also be noted that, as previously described, Figures 3a to 3c The two different stress locations in the configuration could both lie on an imaginary straight line passing through the center point of the core, but they do not necessarily have to be arranged in this way, as referenced... Figure 4c and Figure 10b Further description.

[0062] As previously referenced Figures 2c to 2g As described, according to some embodiments, it can be based on Figure 2b The corresponding curve and Equation 4 are used to select the first and second positions of the array. In some cases, such as for Figure 2cThe example configuration can be adjusted by splitting the individual transistors constituting Q1 or Q2 between the first and second positions. For example, according to... Figure 2b This configuration can be helpful if one or two of the locations determined by the curve and Equation 4 are roughly estimated or unavailable (e.g., because other circuits occupy those locations). For this reason, Figure 3c It shows Figure 3a The specific implementation of the illustrated embodiment allows for the selective addition of individual transistors at location B, to be adjusted based on characterization (actual performance data of the manufactured circuit).

[0063] More specifically, according to embodiments, the results are obtained based on stress simulations and / or past characterizations of the device. Figure 2b The corresponding curve. As will be understood, by modeling the actual behavior of a given component, stress simulation is performed on a simulation tool to determine the estimated stress. Figure 2b The curve. This simulation can be performed before device fabrication to establish a baseline for the desired values ​​in the actual device. On the other hand, characterization is based on measurements of the actual device and is therefore performed after a given device becomes a manufactured device. In this latter characterization case, at least in the initial die design, tuning elements can be provided to allow for tuning of die performance after manufacturing. Example tuning elements include, for example: switches (e.g., electronically switching one or more individual transistors into or out of an array circuit); wire bonds (e.g., where multiple individual transistors are initially connected to the circuit via wire bonds, and the wire bonds of those unwanted transistors are broken to remove these transistors from the functional array circuit); and disconnectable links (e.g., where multiple individual transistors are initially connected to the circuit via links, and the links for those unwanted transistors are burned off, melted, or otherwise disconnected to remove these transistors from the functional array circuit), to name just a few.

[0064] It can be used in any situation Figure 2b The curves and Equation 4 are used to identify the two array locations A and B to compensate for the stress difference. Assume location A is the current location of the array to be distributed. Figure 3a and Figure 3c As shown, by splitting multiple Q2 transistors between positions A and B, V can be adjusted or fine-tuned through interpolation. BE2-shift For simulation purposes, the value of X (the number of Q2 transistors moving from position A to B) can be determined, for example, by representing each individual transistor at positions A and B with voltage sources. Then, one or more voltage sources from one position can be moved to another, and the simulation can be rerun until the desired stress difference compensation level is achieved.

[0065] For characterization purposes, the value of X can be determined using adjustment elements, such as... Figure 3c As shown in the example. It can be seen that, according to the embodiment, Figure 3c The example bandgap voltage reference circuit is similar to Figure 3a The circuit differs in that it includes adjusting elements (in this case, switches) that can switch different portions of the Q2 transistor at position B to achieve the desired value of X. More specifically: switch S1 is used to turn on (or off) the parallel combination of four individual transistors in position B of the Q2 transistor; switch S2 is used to turn on (or off) the parallel combination of two individual transistors in position B of the Q2 transistor; and switch S3 is used to turn on (or off) a single individual transistor in position B of the Q2 transistor. Each of switches S1, S2, and S3 can be controlled to connect the base of its respective transistor(s) to: (1) ground, to effectively remove the transistor(s) from the functional circuit, or (2) the collector of the transistor(s) to place the transistor(s) in the functional circuit. In the current configuration, switch S1 connects the parallel combination of four individual transistors in position B of Q2, and switches S2 and S3 are both switched to ground to remove the transistors corresponding to these switches from the functional circuit. The circuit can then be tested to see if the desired stress difference compensation level is achieved. If not, switches S1, S2, and S3 can be controlled to the next arrangement, and the circuit can be tested again to see if the desired stress difference compensation level is achieved, and so on, until the desired stress difference compensation level is achieved or all switch combinations are exhausted (in which case a different set of switchable transistor sections can be implemented in the design, so the process can be repeated). It should be noted that once a configuration providing the desired stress difference compensation level is found, this configuration can be implemented without switches as needed. Other embodiments can use wire bonding or ablation-compatible links to add or remove individual location B sections of the Q2 transistor, thereby allowing some post-manufacturing adjustments. Many adjustable embodiments will be understood.

[0066] In operation, regarding Figures 3a to 3c In the example topology, transistors Q1 and Q2 can operate at different current densities to allow resistor R to... ptat (or some other PTAT component, such as) Figure 6c A temperature-to-absolute (PTAT) current is generated in capacitor C1, and the resulting PTAT voltage across the PTAT element can be compared with the temperature-to-absolute (CTAT) voltage V of Q1. BE Added together, this produces a temperature-insensitive output voltage V, which is approximately the bandgap energy of the semiconductor material used to manufacture the transistor. refIt should be noted that the summing circuit adds the scaled PTAT and CTAT voltages; in this example, the summing circuit is an operational amplifier configured with negative feedback. Resistors R1 and R2 can be selected to set the desired current through Q1 and Q2.

[0067] Figures 4a to 4c Each illustration depicts an example electronic system with an integrated circuit according to an embodiment, the integrated circuit including a bandgap voltage reference circuit configured with a spatially distributed transistor array. It can be seen that each example system includes an integrated circuit with a semiconductor die contained within a package soldered to a printed circuit board (PCB). Therefore, the stress distribution of the die can be determined using standard die stress modeling techniques, and this distribution can be utilized by selecting the array location, as described in different ways herein. This system can be any electronic system suitable for a given application, and the specific details of the PCB and integrated circuit will be primarily defined by the application. Figures 11a to 11e Some examples of such applications are shown. In any such case, it is assumed that the application requires a bandgap voltage reference. As will be understood, this article is not limited to any of these specific example applications.

[0068] A PCB can be any standard or proprietary printed circuit board, such as a PCB that includes copper pads and traces forming part of a circuit on a dielectric core. Integrated circuits and other discrete components (e.g., capacitors, inductors, resistors, displays, RF component sections, processors, controllers, digital logic devices) can be packed onto the PCB to complete the circuitry. In some example cases, the PCB may include multiple conductive patterned layers within a laminated structure, where metallized vias connect features of one layer to features of another layer. In a more general sense, a PCB can be any board suitable for coupling to an integrated circuit package via a bottom-mount process. As will be understood, the size and specific configuration of the PCB will vary depending on the application and embodiment.

[0069] Integrated circuit packages can be any standard or proprietary package. In some cases, the package is a QFN (Quad Flat No Leads) package, including pads on its bottom surface that can be bonded to corresponding pads on the PCB during the bottom-side bonding process. In other cases, the package is a dual in-line package (DIP), small outline package (SALC), or lead grid array package, which includes leads that can be bonded to corresponding pads or holes on the PCB during the bottom-side bonding process. In any case, the die is bonded or otherwise secured within the package and electrically connected to input / output pads or leads within the package, which in turn connect to external pads or leads of the package coupled to the PCB. Additional space within the package can be filled with molding compounds to, for example, improve the structural robustness of the integrated circuit.

[0070] As previously described, a die can be implemented using any number of standard or proprietary semiconductor materials and process technologies, and can have any number of circuits on it, but typically includes a bandgap voltage reference circuit configured with a spatially distributed array of transistors as described in different ways herein. In some embodiments, the die is a system-on-a-chip configured to perform a specific set of functions (e.g., signal processing), but in other embodiments, it may be dedicated to a single function (e.g., digital-to-analog conversion, power-on reset, low-dropout linear regulator, or power conversion). In any case, the functions provided by the die utilize an internally temperature-stable voltage reference provided by a bandgap voltage reference circuit configured with a distributed array. It should be understood that the die may further include other components that facilitate the functionality of the chip.

[0071] As previously described, each of the die (e.g., silicon, germanium, gallium arsenide, or other semiconductor materials), the packaging molding compound, and the PCB can have different coefficients of thermal expansion, which creates temperature-dependent stresses on the active pn junction components (e.g., silicon BJTs) used to generate a temperature-invariant voltage reference. The rigid attachment of the integrated circuit to the PCB traces creates boundary conditions for this stress. Therefore, because the die is fixed within the package, and the package is fixed to the PCB, mechanical stress is applied to the die, causing a downward soldering-induced offset in the output voltage of the reference circuit.

[0072] As in Figures 4a to 4c As can be further seen in these example cases, the spatially distributed array is located at two locations A and B on the die. Therefore, for example, recall... Figure 3a The distributed array of the example embodiment shown has M individual transistors Q1 all located at position A, while N individual transistors Q2 are split between positions A and B; similarly, recall Figure 3b The example distributed array shown has M individual transistors Q1 split between positions A and B, while N individual transistors Q2 are all located at position B. Assume... Figures 4a to 4c These specific examples use two distinct and independently formed arrays, each with a perimeter or edge. The absolute interval between these two arrays at positions A and B, respectively, is denoted as D. A-B And in these example cases, it is the edge-to-edge spacing. As previously stated, this distance D A-B It is greater than the minimum spacing between individual transistors that make up a non-distributed array or other relatively small spacing.

[0073] It should be noted that, according to some embodiments, the array portions with different stresses can be located on a horizontal line passing through the center point of the die. Figure 4a ), or on a vertical line passing through the center point of the tube ( Figure 4b ( ), where position B is approximately at the center point of the die, and position A is near the edge of the die. This is because, in some such embodiments, the mechanical stress applied to the die by the bottom-welding process is maximum at the center point of the die and decreases with increasing radial distance from the center point, thus minimizing the mechanical stress near the edge of the die, thereby providing a relatively symmetrical stress distribution. In such cases, each array is at a different distance from the center point of the die, thereby applying different stresses to the array. However, as will be understood, the stress applied to a given die can vary and may not always be maximum at the center point of the die and minimum near the edge of the die. For example, in one such embodiment, the array portion may, for example, be located diagonally across two non-central regions of the die ( Figure 4c On the ), position B is laterally offset from the center point to the left side of the die, and position A is close to the upper right corner of the die. For this reason, the array does not necessarily have to be positioned along an imaginary horizontal or vertical line passing through the center point of the die; instead, depending on the stress model of the given die, they can be positioned along an imaginary diagonal passing through the upper part of the die, the lower part of the die, the left part of the die, or the right part of the die, etc.

[0074] The distance D is relative to the minimum distance between individual transistors in a non-distributed array. A-B It is a non-trivial distance. For example, according to some embodiments, the distance D A-B Within the range of 1.5% to 65% of the main dimension of the die extending in the same direction as the spacing. More specifically, as in Figures 4a to 4c As can be further seen, the die has a major dimension D1 along the x-axis and another major dimension D2 along the y-axis. Therefore, for example, in... Figure 4a and Figure 4c In the example, the interval extends roughly along the x-axis and is a distance of D. A-B It is 1.5% to 65% of D1. In a similar manner, in Figure 4b In the example, the interval extends along the y-axis and is a distance D. A-B It is 1.5% to 65% of D2. In some such embodiments, the distance from D... A-BWithin the range of 3% to 50%, or 5% to 45%, or 10% to 50%, or 20% to 40% of the relevant major dimensions (D1 or D2). It should be noted that these example distances are not merely a matter of design choice. Rather, these example distances assume that the stress is highest in the central region of the die. In such cases, it should be noted that locations A and B equidistant from the die center are unlikely to produce offsetting benefits (because the stress is substantially the same at these two locations), as will be understood; instead, in such cases, differences in the distance of each array from the die center will produce different stress locations and offsetting benefits. That is, and as will be further understood, the techniques presented herein can also be used for cases where the stress is highest in non-central regions of the die, i.e., forming some transistors in the high-stress region of the die and others in the relatively low-stress region of the die.

[0075] Therefore, for example, consider a square die where the principal dimensions D1 and D2 are both 5000 μm. In some such embodiments, the distance D... A-B Within a range of 75 μm to 2500 μm, such as approximately 100 μm to 2250 μm (e.g., 200 μm or 500 μm, 750 μm, 1000 μm, 1600 μm or 2000 μm from the center to the edge). As will be readily understood, the shape and major dimensions of a given die can vary considerably, and this example embodiment does not limit this document to a particular shape or geometry. As will be further understood, “near the edge” as used herein can vary depending on the major dimensions of the die. For example, for a die with a major dimension of 5000 μm, near the edge of the die means, for example, a location within 500 μm of the edge, or 10% or less of that major dimension from the edge, such as a location between 50 μm and 250 μm from the edge of the die. It should also be noted that, as will be understood, process limitations may restrict the degree of proximity to the edge. Similarly, terms such as “central region” or “central location” as used herein can vary depending on the major dimensions of the die. For example, for a die with a major dimension of 5000 μm, being located in the central region of the die means, for example, being located within 10% or less of the major dimension of the die's center point, such as within 250 μm of the die's center point. As will be further understood, the center point of the die is the geometric center of the die (e.g., the geometric center of a rectangular die).

[0076] Recalling further, the interval between these two array sections with different stresses can be considered in several ways. For example, the interval between these two array sections can be considered in an absolute sense as... Figures 4a to 4c The distance D from edge to edge depicted A-BWhen the mechanical stress applied to the die by the down-welding process is greatest in the central region of the die and decreases with increasing radial distance from the central region, the spacing between the array sections can be considered, in a relative sense, as the distance of each array section from the central region of the die, for example... Figure 10b Example. Similarly, where the mechanical stress applied to the die by the down-welding process is maximum at a certain eccentric region of the die and decreases with increasing radial distance from the eccentric region, the spacing between array sections can be considered, in a relative sense, as the distance of each array section from that eccentric region. And as referenced Figures 2c to 2g As described, the spacing between the array sections can be considered as the distance between the centroids of the active devices (Q1 and Q2) formed in the array. In any such case, each of the two array sections is subjected to different stresses.

[0077] Figure 5 The illustration further details the dependence of the voltage offset caused by down-soldering on the positioning of the spatially distributed transistor arrays of the various example bandgap voltage reference circuits configured according to embodiments, relative to a bandgap voltage reference circuit with a non-distributed transistor array. The transistors used for the five examples described are n-type BJTs, but as will be understood, other similar pn-junction devices with similar positioning and behavior may also be used. It should also be noted that locations A and B can be, for example... Figures 2c to 2g or Figures 4a to 4c or Figure 10b The locations depicted, where location B experiences a higher degree of stress than location A. Further assumptions... Figure 3a The bandgap voltage reference circuit configuration is used for Figure 5 The simulation depicted in the figure has M=2 and N=16, but this particular configuration is only an example.

[0078] from Figure 5 The bottom two curves show that example array configurations 1 and 2 (Ex 1 and Ex 2) are non-distributed. In example array configuration 1, all transistors are located at position B in the middle region of the die, and in example array configuration 2, all transistors are located at position A near the edge of the die. Based on these two corresponding curves from left to right, it can be seen that these non-distributed array configurations exhibit an upward-downward solder offset of approximately 1 mV over a temperature range of -40°C to 140°C. This offset may be unacceptable for some applications, and therefore mitigating this offset could be beneficial.

[0079] about Figure 5Example array configuration 3 (Ex 3) shows that all M transistors Q1, along with one transistor from the N transistors Q2, are located at position A near the edge of the die, and the remaining transistors of the N transistors Q2 are located at position B in the middle region of the die. The corresponding curves show that, over the same temperature range, this distributed array configuration exhibits an improvement (reduction) of approximately 25% to 30% in the downward solder offset compared to a non-distributed configuration. Therefore, the distributed transistors in the array provide at least some degree of voltage output reduction, which is advantageous.

[0080] about Figure 5 As can be seen from Example Array Configuration 4 (Ex 4), all M transistors Q1, along with four of the N transistors Q2, are located at position A near the edge of the die, and the remaining N transistors Q2 are located at position B in the middle region of the die. The corresponding curves show that, within the same temperature range, this distributed array configuration effectively cancels, neutralizes, or significantly reduces the downward soldering offset attributable to the non-distributed configuration. Therefore, relative to Example Array Configuration 2 (Ex 2), and according to... Figure 3a In one specific embodiment, where M=2 and N=16, the absolute offset is canceled out or otherwise reduced by moving 12 of the 16 transistors Q2 to the center position of the die. It should be noted that in other embodiments, the mitigation effect can be achieved by moving a different number of transistors from the 16 transistors Q2 to the center position (e.g., by moving 4 transistors). It should also be noted that in some such embodiments, the same cancellation effect can be achieved by moving only a smaller number of transistors out of N as the distance between the two positions A and B increases. Therefore, there are a range of discrete possibilities for the choice of X (the number of transistors to be moved) and the distance between the positions, and the mitigation effect resulting from moving the array of transistors from one position to another can be adjusted accordingly for a given application.

[0081] about Figure 5 Example array configuration 5 (Ex 5) shows that all M transistors Q1 are located at position A near the edge of the die, and all N transistors Q2 are located at position B in the middle region of the die. The corresponding curves show that this distributed array configuration exhibits a downward solder offset of approximately 3 mV over the same temperature range. This example configuration demonstrates that a wide range of compensation can be provided by fine-tuning the number of transistors at each location in the distributed array.

[0082] Figures 6a to 6cEach illustration depicts another example bandgap voltage reference circuit according to an embodiment, which is configured with a spatially distributed transistor array to mitigate temperature-dependent base-emitter voltage shifts caused by mechanical stresses resulting from the downsinking process. As can be seen, Figure 6a The Brokaw topology is provided. Figure 6b Widlar topology is provided, and Figure 6c The switched capacitor topology is provided. In any such case, it should be noted that, as will be understood, the distributed array technique presented herein can be readily applied to transistors Q1 and Q2. For example, in Figure 6a In the Brokaw topology, transistors Q1 and Q2 can operate at different current densities (Q2 has a lower V0). BE This generates a temperature-to-absolute (PTAT) voltage across resistor R2, which can be compared with the temperature-to-absolute (CTAT) complementary voltage V of Q1. BE Added together, this produces a temperature-insensitive output voltage V, which is approximately equal to the bandgap energy of the semiconductor material used to manufacture the transistor. ref Similarly, in Figure 6b In the Widlar topology, transistors Q1 and Q2 can operate at different current densities (Q2 has a lower V0). BE This generates a temperature-to-absolute (PTAT) voltage across resistor R3. An amplified version of this PTAT voltage drops across R1 and is complementary to the temperature-to-absolute (CTAT) voltage V of Q3. BE Added together, this produces a temperature-insensitive output voltage V, which is approximately equal to the bandgap energy of the semiconductor material used to manufacture the transistor. ref . Figure 6c The switched capacitor topology illustrates an example case where PTATΔV BE The components are capacitively coupled (via capacitors C1 and C2) to the summing operational amplifier with a certain gain, rather than resistively coupled as in the example Brokaw and Widlar topologies. In any case, transistors Q1 and Q2 can similarly combine switching actions to operate at different currents to generate PTAT and CTAT voltages, thereby producing a temperature-insensitive output voltage V approximately equal to the bandgap energy of the semiconductor material used to manufacture the transistors. ref It should be noted that in any such case, additional components, such as buffer circuitry (e.g., unity-gain buffers), can be used to drive, for example, PTAT elements or the output of a bandgap voltage reference circuit. Many such modifications will be readily apparent.

[0083] Figure 7The diagram illustrates the dependence of the voltage shift caused by downsoldering on the thickness of the printed circuit board for the bandgap voltage reference circuit. Two curves are shown: the upper curve shows the output voltage shift caused by downsoldering of the bandgap voltage reference circuit to a first PCB with a first thickness (62 mils), and the lower curve shows the output voltage shift caused by downsoldering of the bandgap voltage reference circuit to a second PCB with a second thickness (90 mils). All other things being equal, it should be noted that the thicker the PCB, the greater the output voltage shift caused by downsoldering of the bandgap voltage reference circuit. Therefore, this detail can be considered when designing and modeling a specific system.

[0084] Figure 8 The illustration shows that when NPN and PNP transistors are used in a transistor array of a bandgap voltage reference circuit, both are similarly prone to voltage shift due to downsoldering. Therefore, while the various example circuits presented herein are implemented using NPN transistors, it is clear that such examples can also be easily implemented using PNP transistors and still achieve similar benefits. For this reason, this article applies equally to both NPN and PNP transistors.

[0085] Figures 9a to 9c The illustration shows the mechanical stress on the die of an integrated circuit package caused by the bottom-mount soldering process. From Figure 9a As can be seen, an integrated circuit is provided, which includes a package containing a die. It should be noted that... Figure 9a A quarter of the full dimensions of a given die is depicted (upper right quadrant of the top view). Figures 9b to 9c Simulations of mechanical stress in the die before and after the down-welding process are shown. While the absolute values ​​of the stress (megapascals, MPa) will vary from embodiment to embodiment, it should be noted that a significant increase in die stress after down-welding can be apparent, particularly in the central region of the die, where, in some simulations, the stress increase ranges from 50 to 100 MPa. For example, in the example simulation shown, the post-down-welding stress in the central region of the die was approximately 60 MPa higher than before the down-welding process.

[0086] Figures 10a to 10b The diagram illustrates how the mechanical stress on the die caused by down-welding is related to positioning and therefore varies within the region of the die. From Figure 10a As can be seen, the stress in the package exhibits both temperature and location dependence. Specifically, according to this example embodiment, the stress tends to decrease with increasing distance from the center of the die. It should be noted that the stress is measured as von Mises stress in megapascals (MPa), which is a theoretical measure of stress (compared to...). Figures 9a to 9c(The simulation shown is the same). It should also be noted that this distance refers to the absolute mm distance from the center of the die. Therefore, the distance from the die center in the opposite direction (to the other opposite edge of the die) will produce a symmetrical curve. By utilizing the positioning dependence of package stress, this paper provides a method for reducing V... BE The technique of temperature coefficient offset. Therefore, it can be seen that after downward welding, V BE V caused by offset ref The amount of temperature coefficient offset depends on the distance of each array section that makes up the entire array from the die center point. Specifically, by placing the transistors of the array at die positions with different stresses relative to the die center point, the absolute offset can be compensated for by the relative offset.

[0087] Therefore, and refer to Figure 10b The top view, and it should also be noted that the use of the techniques provided herein can be detected, for example, by a top view of a die showing two distinct transistor arrays (or subarrays) spaced apart from each other, where distance D is the distance between the two subarrays constituting the entire array, and distance D is greater than the spacing between two adjacent individual transistors in either array. In this particular example, array A is at distance D1 from the die center point, and array B is at distance D2 from the die center point. It should be noted that in some examples, these distances are relative to the geometric center of the respective array portion, but according to other embodiments, they may be relative to other points (such as the distance to the edge of the array portion). In any case, considering the radially symmetrical stress distribution about the die center point, array A will experience less stress than array B. This stress difference between positions A and B is as follows: Figure 10a As shown, the pressure is approximately 17 MPa, where position A is approximately 0.78 mm from the center of the die and position B is approximately 0.22 mm from the center of the die.

[0088] Figures 11a to 11e Each illustration depicts an example electronic system according to an embodiment, which employs a bandgap voltage reference circuit configured with a spatially distributed transistor array. It should be noted that, apart from the fact that a bandgap voltage reference circuit is used, the specific implementation details of the example circuits are not particularly relevant. Figure 11a This illustrates the use of a bandgap voltage reference circuit 1100 to provide V. ref Example DC-DC converter circuit. Figure 11b This illustrates the use of a bandgap voltage reference circuit 1100 to provide V. ref Example of a low dropout linear regulator (LDO) circuit. Figure 11c This illustrates the use of a bandgap voltage reference circuit 1100 to provide V. ref Example of a power-on reset (POR) circuit. Figure 11dThis illustrates the use of a bandgap voltage reference circuit 1100 to provide V. ref Example digital-to-analog converter (DAC) circuit. Figure 11e This illustrates the use of a bandgap voltage reference circuit 1100 to provide V. ref Examples of analog-to-digital converter (ADC) circuits. As will be understood, in any of these example electronic systems, the bandgap voltage reference circuit 1100 can be any of the examples provided in different ways herein.

[0089] Further example embodiments

[0090] Example 1 is an integrated circuit comprising: a package; and a die, the die being disposed within the package and including a bandgap voltage reference circuit, the die having opposing edges partially defining the outer perimeter of the die, the opposing edges being spaced apart by a distance D1. The bandgap voltage reference circuit includes: a first transistor located at a first position on the die and operating with a first base-emitter voltage; a second transistor located at a second position on the die and operating with a second base-emitter voltage, the second position being spaced apart from the first position by a distance D2; and a resistor or capacitor operatively coupled to the first transistor and the second transistor such that the voltage difference between the first base-emitter voltage and the second base-emitter voltage decreases across the resistor or capacitor. The distance D2 is at least 1.5% of the distance D1.

[0091] Example 2 includes the integrated circuit according to Example 1, wherein the distance D2 is in the range of 3% to 55% of the distance D1.

[0092] Example 3 includes an integrated circuit according to Example 1 or 2, wherein the distance D2 is in the range of 5% to 45% of the distance D1.

[0093] Example 4 includes an integrated circuit according to any one of Examples 1 to 3, wherein the die is rectangular in shape and has a center point, and wherein the first position is within 10% of the center point of the die, and the second position is within 10% of one of the opposite edges of the die.

[0094] Example 5 includes an integrated circuit according to any one of Examples 1 to 4, wherein the die is rectangular in shape and has a center point, and wherein the surface stress of the die near the center point is greater than the surface stress of the die near one of the opposing edges. The first transistor is included in a first transistor array at the first location, and the second transistor is included in a second transistor array at the second location. The first location is associated with a first surface stress, and the second location is associated with a second surface stress, and wherein the first location is closer to the center point than the second location, such that the first surface stress is greater than the second surface stress.

[0095] Example 6 includes an integrated circuit according to any one of Examples 1 to 5, wherein the second transistor is a plurality of individual transistors connected in parallel and operating at the second base-emitter voltage, and at least one of the individual transistors is included in an array at the first location, the array further including the first transistor.

[0096] Example 7 includes an integrated circuit according to any one of Examples 1 to 6, and further includes a summing circuit configured to generate a voltage reference output based on (1) the voltage difference between the first base-emitter voltage and the second base-emitter voltage and (2) the first base-emitter voltage or another base-emitter voltage.

[0097] Example 8 is an electronic system comprising: a printed circuit board; and an integrated circuit according to any one of Examples 1 to 7 soldered to the printed circuit board.

[0098] Example 9 is a digital-to-analog converter including an integrated circuit according to any one of Examples 1 to 7, or an electronic system according to Example 8.

[0099] Example 10 is an integrated circuit comprising: a package; and a die, the die being disposed within the package and including a bandgap voltage reference circuit configured to add a voltage proportional to absolute temperature (PTAT) and a voltage complementary to absolute temperature (CTAT). The bandgap voltage reference circuit includes: an array comprising a first bipolar junction transistor (BJT) and a second BJT, the first BJT operating at a first base-emitter voltage and the second BJT operating at a second base-emitter voltage, wherein the centroids of the array, the first BJT, and the second BJT are spaced apart from each other; a PTAT element operatively coupled to the first BJT and the second BJT such that the voltage difference between the first base-emitter voltage and the second base-emitter voltage decreases across the PTAT element; and a summing circuit configured to generate a voltage reference output based on (1) the voltage difference between the first base-emitter voltage and the second base-emitter voltage and (2) the first base-emitter voltage or another base-emitter voltage.

[0100] Example 11 includes an integrated circuit according to Example 10, wherein the array includes: one or more individual BJTs operating at a first base-emitter voltage to provide a first BJT; one or more individual BJTs operating at a second base-emitter voltage to provide a second BJT; and one or more individual BJTs not connected to provide one or more dummy devices; wherein the one or more individual BJTs of the first BJT are spaced apart from the one or more individual BJTs of the second BJT via the one or more dummy devices.

[0101] Example 12 includes an integrated circuit according to Example 10 or 11, wherein: the array includes a first array and a second array spaced apart from each other, and wherein the first BJT includes one or more individual BJTs from the first array and / or the second array, and the second BJT includes one or more individual BJTs from the first array and / or the second array, the distance between the first array and the second array being greater than or equal to the lateral width of one individual BJT of the array; or the array includes a first subarray and a second subarray spaced apart from each other, and wherein the first BJT includes one or more individual BJTs from the first subarray and / or the second subarray, and the second BJT includes one or more individual BJTs from the first subarray and / or the second subarray, the distance between the first subarray and the second subarray being greater than or equal to the lateral width of one individual BJT of the array.

[0102] Example 13 includes an integrated circuit according to any one of Examples 10 to 12, wherein the first BJT is located at a first position on the die, and the second BJT is located at a second position on the die, the second position being spaced apart from the first position, and wherein the second BJT is a plurality of individual BJTs connected in parallel and operating at the second base-emitter voltage, and at least one of the individual BJTs is located at the first position.

[0103] Example 14 includes an integrated circuit according to any one of Examples 10 to 13, wherein the first BJT and the second BJT each include one or more diode-connected BJTs, and the PTAT element includes one or more resistors or one or more capacitors.

[0104] Example 15 is an electronic system comprising: a printed circuit board; and an integrated circuit according to any one of Examples 10 to 14 soldered to the printed circuit board, wherein the integrated circuit includes an analog-to-digital converter and / or a digital-to-analog converter.

[0105] Example 16 is an integrated circuit comprising: a package; and a die, the die being fixed within the package and including a bandgap voltage reference circuit, the die having a center point and a stress distribution such that the surface stress of the die decreases with increasing distance from the center point, the bandgap voltage reference circuit being configured to add a voltage proportional to absolute temperature (PTAT) and a voltage complementary to absolute temperature (CTAT). The bandgap voltage reference circuit includes: a first bipolar junction transistor (BJT) located at a first position on the die and operating with a first base-emitter voltage, the first position being a first distance from the center point of the die and associated with a first stress value; a second BJT located at a second position on the die and operating with a second base-emitter voltage, the second position being a second distance from the center point of the die and associated with a second stress value, the second distance being different from the first distance, and the second stress value being different from the first stress value; a resistor or capacitor operatively coupled to the first BJT and the second BJT such that the voltage difference between the first base-emitter voltage and the second base-emitter voltage decreases across the resistor or capacitor; and a summing circuit configured to generate a voltage reference output based on (1) the voltage difference between the first base-emitter voltage and the second base-emitter voltage and (2) the first base-emitter voltage or another base-emitter voltage.

[0106] Example 17 includes the integrated circuit according to Example 16, wherein the resistor or capacitor is a resistor.

[0107] Example 18 includes an integrated circuit according to Example 16 or 17, wherein the second bipolar junction transistor is a plurality of individual bipolar junction transistors connected in parallel and operating at the second base-emitter voltage, and at least one of these individual bipolar junction transistors is included in an array at the first location, the array further including the first bipolar junction transistor.

[0108] Example 19 includes an integrated circuit according to any one of Examples 16 to 18, wherein the first bipolar junction transistor is M individual bipolar junction transistors connected in parallel and operating at the first base-emitter voltage, and the second bipolar junction transistor is N individual bipolar junction transistors connected in parallel and operating at the second base-emitter voltage, and at least one of the N individual bipolar junction transistors is located at the first position.

[0109] Example 20 includes the integrated circuit according to Example 19, wherein: M equals 2 and N equals 16; the second location includes the center point of the die; and the second stress value is greater than the first stress value.

[0110] The above description of the examples herein has been presented for illustrative and descriptive purposes. The above description is exhaustive and does not limit the document to the precise forms described. Many modifications and variations are possible based on this description. The scope of this document is not limited to this specific embodiment but is limited by the appended claims.

Claims

1. An integrated circuit, comprising: Package components; as well as A die, secured within the package and including a bandgap voltage reference circuit, the die having opposing edges partially defining the outer periphery of the die, the opposing edges being spaced apart by a distance D1, the bandgap voltage reference circuit including... A first transistor, located at a first position on the die and operating with a first base-emitter voltage. A second transistor, located at a second position on the die and operating with a second base-emitter voltage, the second position being separated from the first position by a distance D2. A resistor or capacitor operatively coupled to the first transistor and the second transistor such that the voltage difference between the first base-emitter voltage and the second base-emitter voltage decreases across the resistor or capacitor; Wherein, the distance D2 is at least 1.5% of the distance D1.

2. The integrated circuit according to claim 1, wherein, The distance D2 is in the range of 3% to 55% of the distance D1.

3. The integrated circuit according to claim 1, wherein, The distance D2 is within 5% to 45% of the distance D1.

4. The integrated circuit according to claim 1, wherein, The die is rectangular in shape and has a center point, wherein the first position is within 10% of the center point of the die, and the second position is within 10% of one of the opposite edges of the die.

5. The integrated circuit according to claim 1, wherein, The die is rectangular in shape and has a center point, wherein the surface stress of the die near the center point is greater than the surface stress of the die near each of the opposite edges, wherein the first transistor is included in a first transistor array at the first location, and the second transistor is included in a second transistor array at the second location, wherein the first location is associated with a first surface stress, and the second location is associated with a second surface stress, and wherein the first location is closer to the center point than the second location, such that the first surface stress is greater than the second surface stress.

6. The integrated circuit according to claim 1, wherein, The second transistor is a plurality of individual transistors connected in parallel and operating at the second base-emitter voltage, and at least one of the individual transistors is included in an array at the first location, the array further including the first transistor.

7. The integrated circuit of claim 1, further comprising a summing circuit configured to generate a voltage reference output based on (1) the voltage difference between the first base-emitter voltage and the second base-emitter voltage and (2) the first base-emitter voltage or another base-emitter voltage.

8. An electronic system comprising: Printed circuit boards; as well as The integrated circuit according to claim 1 is soldered to the printed circuit board.

9. A digital-to-analog converter, comprising the integrated circuit according to claim 1.

10. An integrated circuit, comprising: Package components; as well as A die, the die being secured within the package and including a bandgap voltage reference circuit configured to add a temperature-to-absolute (PTAT) voltage and a temperature-to-absolute (CTAT) complementary voltage, the bandgap voltage reference circuit including... An array comprising a first bipolar junction transistor (BJT) and a second BJT, the first BJT operating with a first base-emitter voltage and the second BJT operating with a second base-emitter voltage, wherein the centroids of the array, the first BJT, and the second BJT are spaced apart from each other. A PTAT element, operatively coupled to the first BJT and the second BJT, such that the voltage difference between the first base-emitter voltage and the second base-emitter voltage decreases across the PTAT element. A summing circuit configured to generate a voltage reference output based on (1) the voltage difference between the first base-emitter voltage and the second base-emitter voltage and (2) the first base-emitter voltage or another base-emitter voltage.

11. The integrated circuit according to claim 10, wherein, The array includes: one or more individual BJTs operating at the first base-emitter voltage to provide the first BJT; one or more individual BJTs operating at the second base-emitter voltage to provide the second BJT; and one or more individual BJTs not connected to provide one or more virtual devices; wherein the one or more individual BJTs of the first BJT are spaced apart from the one or more individual BJTs of the second BJT via the one or more virtual devices.

12. The integrated circuit according to claim 10, wherein: The array includes a first array and a second array spaced apart from each other, wherein the first BJT includes one or more individual BJTs from the first array and / or the second array, and the second BJT includes one or more individual BJTs from the first array and / or the second array, and the distance between the first array and the second array is greater than or equal to the lateral width of one individual BJT of the array; or The array includes a first subarray and a second subarray spaced apart from each other, wherein the first BJT includes one or more individual BJTs from the first subarray and / or the second subarray, and the second BJT includes one or more individual BJTs from the first subarray and / or the second subarray, and the distance between the first subarray and the second subarray is greater than or equal to the lateral width of one individual BJT of the array.

13. The integrated circuit according to claim 10, wherein, The first BJT is located at a first position on the die, and the second BJT is located at a second position on the die, the second position being spaced apart from the first position by a certain distance, wherein the second BJT is a plurality of individual BJTs connected in parallel and operating with the second base-emitter voltage, and at least one of the individual BJTs is located at the first position.

14. The integrated circuit according to claim 10, wherein, The first BJT and the second BJT each include one or more diode-connected BJTs, and the PTAT element includes one or more resistors or one or more capacitors.

15. An electronic system comprising: Printed circuit boards; as well as The integrated circuit of claim 10, soldered to the printed circuit board, wherein the integrated circuit includes an analog-to-digital converter and / or a digital-to-analog converter.

16. An integrated circuit, comprising: Package components; as well as A die, secured within the package and including a bandgap voltage reference circuit, the die having a center point and stress distribution such that the surface stress of the die decreases with increasing distance from the center point, the bandgap voltage reference circuit being configured to add a temperature-proportional-to-absolute-temperature (PTAT) voltage and a temperature-complementary-to-absolute-temperature (CTAT) voltage, the bandgap voltage reference circuit including... A first bipolar junction transistor (BJT) is located at a first position on the die and operates with a first base-emitter voltage. This first position is a first distance from the center point of the die and is associated with a first stress value. A second bipolar junction transistor (BJT) is located at a second position on the die and operates with a second base-emitter voltage. This second position is a second distance from the center point of the die and is associated with a second stress value, which differs from a first distance and a second stress value, respectively. A resistor or capacitor, operatively coupled to the first bipolar junction transistor and the second bipolar junction transistor, such that the voltage difference between the first base-emitter voltage and the second base-emitter voltage decreases across the resistor or capacitor. A summing circuit configured to generate a voltage reference output based on (1) the voltage difference between the first base-emitter voltage and the second base-emitter voltage and (2) the first base-emitter voltage or another base-emitter voltage.

17. The integrated circuit according to claim 16, wherein, The resistor or capacitor is a resistor.

18. The integrated circuit according to claim 16, wherein, The second bipolar junction transistor is a plurality of individual bipolar junction transistors connected in parallel and operating at the second base-emitter voltage, and at least one of the individual bipolar junction transistors is included in an array at the first location, the array further including the first bipolar junction transistor.

19. The integrated circuit according to claim 16, wherein, The first bipolar junction transistor consists of M individual bipolar junction transistors connected in parallel and operating at the first base-emitter voltage, and the second bipolar junction transistor consists of N individual bipolar junction transistors connected in parallel and operating at the second base-emitter voltage, and at least one of the N individual bipolar junction transistors is located at the first position.

20. The integrated circuit according to claim 19, wherein: M equals 2 and N equals 16; the second position includes the center point of the die; Furthermore, the second stress value is greater than the first stress value.

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