Anti-latch low-dropout voltage regulator

Abstract

The application discloses a latch-preventing low-dropout voltage regulator, which comprises a low-dropout voltage regulating circuit and a clamping circuit connected to a current-limiting detection unit detection end in the low-dropout voltage regulating circuit; the low-dropout voltage regulating circuit is used for outputting a stable working voltage under the action of the current-limiting detection unit; and the clamping circuit is used for providing a low voltage to the current-limiting detection unit detection end, so as to realize soft starting of the low-dropout voltage regulating circuit and avoid latch of the low-dropout voltage regulating circuit when the working voltage output by the low-dropout voltage regulating circuit is lower than a preset value. The application adds a dynamic clamping circuit to a current-limiting loop of the low-dropout voltage regulating circuit, so that the latch phenomenon is avoided when the low-dropout voltage regulating circuit is in a soft starting process or when an output load current exceeds a nominal maximum value; and then the LDO can normally work in an extreme case; and the output can automatically recover to a nominal value when external factors, such as overloading and short circuit, disappear.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a latch-up-proof low-dropout voltage regulator. Background Technology

[0002] Low dropout regulators (LDOs) have significant advantages such as simple structure, low noise, low power consumption, small package size, and fewer external components, making them widely used in portable electronic products. An LDO is a step-down transformer in a DC-DC converter; under a fixed load, its output voltage remains within a certain range. Therefore, an LDO circuit system can ensure stable output voltage and improve battery life.

[0003] When the output load current of an LDO exceeds its nominal maximum value, the output voltage will drop below the nominal value, leading to greater power dissipation in the internal power transistor. To protect the power transistor from burnout, a current-limiting circuit is typically used to limit the maximum output current. Current-limiting methods include constant current limiting and foldback current limiting. Foldback current limiting is a technique where the current limit decreases as the output voltage decreases. When the LDO's output load current exceeds its nominal maximum value, the circuit enters a "latch-up" state. Even after the excessive load current disappears, the circuit remains "latch-up," meaning the output cannot automatically recover unless power is restored or the circuit is restarted with an external signal. This negatively impacts the LDO's reliability. During the LDO's startup process, the soft-start circuit, designed to prevent surges, also limits the output current, which can also easily trigger a "latch-up" phenomenon. Summary of the Invention

[0004] The purpose of this application is to provide a latch-up low-dropout voltage regulator to solve the problem that the circuit cannot automatically recover after entering a "latch-up" state during the current limiting output process of existing LDO output load current is too large or surge prevention soft-start circuit.

[0005] In a first aspect, this application provides an anti-latch-up low-dropout voltage regulator, including a low-dropout voltage regulation circuit and a clamping circuit connected to the detection terminal of a current-limiting detection unit in the low-dropout voltage regulation circuit.

[0006] The low-dropout voltage regulation circuit is used to output a stable operating voltage under the action of the current limiting detection unit;

[0007] The clamping circuit is used to provide a low voltage to the detection terminal of the current limiting detection unit to achieve soft start of the low dropout voltage regulation circuit, and to prevent the low dropout voltage regulation circuit from latching up when the operating voltage output by the low dropout voltage regulation circuit is lower than a preset value.

[0008] In one embodiment of this application, the low dropout voltage regulation circuit includes an error amplifier, a voltage buffer, a first PMOS voltage regulator, a feedback network, and a current limiting detection unit. The inverting input terminal of the error amplifier receives a reference voltage, the output terminal of the error amplifier is connected to the non-inverting input terminal of the voltage buffer, the output terminal of the voltage buffer is connected to the gate of the first PMOS voltage regulator, the source of the first PMOS voltage regulator is connected to the power supply voltage, and the drain of the first PMOS voltage regulator serves as the output terminal of the low dropout voltage regulation circuit.

[0009] The feedback network is connected between the drain of the first PMOS voltage regulator and the ground terminal. The feedback network includes a first resistor, a second resistor, and a third resistor connected in series. The non-inverting input terminal of the error amplifier is connected to the output terminal of the second resistor. The detection terminal of the current limiting detection unit is connected to the output terminal of the first resistor. The output terminal of the current limiting detection unit is connected to the non-inverting input terminal of the voltage buffer.

[0010] In one embodiment of this application, the current limiting detection unit includes a second PMOS voltage regulator, a fourth resistor, and a third amplifier. The gate of the second PMOS voltage regulator is connected to the output terminal of the voltage buffer, the source of the second PMOS voltage regulator is connected to the power supply voltage, and the drain of the second PMOS voltage regulator is grounded through the fourth resistor. The non-inverting input terminal of the third amplifier serves as the detection terminal, the inverting input terminal of the third amplifier is connected to the input terminal of the fourth resistor, and the output terminal of the third amplifier is connected to the inverting input terminal of the voltage buffer.

[0011] In one embodiment of this application, the clamping circuit includes a soft-start low-voltage supply unit and a load overcurrent low-voltage supply unit;

[0012] The soft-start low-voltage providing unit is used to provide a first preset low voltage to the detection terminal of the current limiting detection unit when the low-dropout voltage regulation circuit is started, so as to realize the soft start of the low-dropout voltage regulation circuit.

[0013] The load overcurrent low voltage providing unit is used to provide a second preset low voltage to the detection terminal of the current limiting detection unit after the low voltage difference regulation circuit is started, so that when the operating voltage output by the low voltage difference regulation circuit is lower than the preset value, the detection terminal of the current limiting detection unit maintains a low voltage, thereby preventing the low voltage difference regulation circuit from latching up.

[0014] In one embodiment of this application, the soft-start low-voltage supply unit includes a first PMOS transistor, a third PMOS transistor, a sixth PMOS transistor, a first current source, and a soft-start sub-circuit. The sources of the first and third PMOS transistors are both connected to the power supply voltage. The drain of the first PMOS transistor is connected to the gate of the first PMOS transistor. The gates of the first and third PMOS transistors are connected. The drain of the first PMOS transistor is grounded through the first current source. The drain of the third PMOS transistor is connected to the source of the sixth PMOS transistor. The soft-start sub-circuit is connected to the gate of the sixth PMOS transistor. The drain of the sixth PMOS transistor serves as the first preset low-voltage output terminal.

[0015] In one embodiment of this application, the soft starter circuit includes a second PMOS transistor and a capacitor C1. The source of the second PMOS transistor is connected to the power supply voltage, the gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the drain of the second PMOS transistor is grounded through the capacitor C1, and the drain of the second PMOS transistor serves as the output terminal of the soft starter circuit.

[0016] In one embodiment of this application, the load overcurrent low-side voltage providing unit includes a ninth PMOS transistor, a second current source, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The source of the ninth PMOS transistor and the source of the fourth PMOS transistor are both connected to the power supply voltage. The gate of the ninth PMOS transistor and the gate of the fourth PMOS transistor are connected. The drain of the ninth PMOS transistor is grounded through the second current source. The gate of the ninth PMOS transistor and the drain of the ninth PMOS transistor are connected. The drain of the fourth PMOS transistor is connected to the drain of the second NMOS transistor.

[0017] The gate of the second NMOS transistor is connected to the gate of the third NMOS transistor, the gate of the second NMOS transistor is connected to the drain of the second NMOS transistor, the gate and drain of the first NMOS transistor are both connected to the source of the second NMOS transistor, the source of the first NMOS transistor is grounded, the drain of the third NMOS transistor is connected to the power supply voltage, and the source of the third NMOS transistor serves as the output terminal of the second preset low voltage.

[0018] In one embodiment of this application, the output terminal of the soft-start low-voltage supply unit is connected to the output terminal of the load overcurrent low-voltage supply unit, and the first PMOS transistor is equivalent to the ninth PMOS transistor, and the first current source is equivalent to the second current source.

[0019] In one embodiment of this application, the load overcurrent low-side voltage providing unit includes a tenth PMOS transistor, a third current source, a twelfth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The source of the tenth PMOS transistor and the source of the twelfth PMOS transistor are both connected to the power supply voltage. The gate of the tenth PMOS transistor and the gate of the twelfth PMOS transistor are connected. The drain of the tenth PMOS transistor is grounded through the third current source. The gate of the tenth PMOS transistor and the drain of the tenth PMOS transistor are connected. The drain of the twelfth PMOS transistor is connected to the drain of the sixth NMOS transistor.

[0020] The gate of the sixth NMOS transistor is connected to the gate of the seventh NMOS transistor, the gate of the sixth NMOS transistor is connected to the drain of the sixth NMOS transistor, the gate and drain of the fifth NMOS transistor are both connected to the source of the sixth NMOS transistor, the source of the fifth NMOS transistor is grounded, the drain of the seventh NMOS transistor is connected to the drain of the third PMOS transistor, and the source of the seventh NMOS transistor serves as the second preset low-level voltage output terminal.

[0021] In one embodiment of this application, the output terminal of the soft-start low-voltage supply unit is connected to the output terminal of the load overcurrent low-voltage supply unit, and the first PMOS transistor is equivalent to the tenth PMOS transistor, and the first current source is equivalent to the third current source.

[0022] In one embodiment of this application, the load overcurrent low-voltage supply unit includes an eleventh PMOS transistor, a fourth current source, a resistor Rc, a thirteenth PMOS transistor, a fifth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a fourth NMOS transistor. The sources of the eleventh PMOS transistor, the thirteenth PMOS transistor, and the fifth PMOS transistor are all connected to the power supply voltage. The gate of the eleventh PMOS transistor is connected to the gates of the thirteenth PMOS transistor and the fifth PMOS transistor, respectively. The drain of the eleventh PMOS transistor is grounded through the fourth current source. The drain of the fourth NMOS transistor is connected to the drain of the eleventh PMOS transistor. The source of the fourth NMOS transistor is grounded through the resistor Rc. The gate of the fourth NMOS transistor is connected to the output terminal of the low-dropout voltage regulation circuit.

[0023] The drain of the ninth NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the ninth NMOS transistor is connected to the gate of the eighth PMOS transistor, the gate and drain of the ninth NMOS transistor are connected, the gate and drain of the eighth NMOS transistor are both connected to the source of the ninth NMOS transistor, the source of the eighth NMOS transistor is grounded, the drain of the eighth PMOS transistor is grounded, the source of the eighth PMOS transistor is connected to the source of the seventh PMOS transistor, the source of the seventh PMOS transistor is also connected to the drain of the fifth PMOS transistor, the gate of the seventh PMOS transistor is connected to the output terminal of the low dropout voltage regulation circuit, and the drain of the seventh PMOS transistor serves as the second preset low voltage output terminal.

[0024] In one embodiment of this application, the output terminal of the soft-start low-voltage supply unit is connected to the output terminal of the load overcurrent low-voltage supply unit, and the first PMOS transistor is equivalent to the eleventh PMOS transistor, and the first current source is equivalent to the fourth current source.

[0025] Compared with the prior art, one or more embodiments of the above solutions may have the following advantages or beneficial effects:

[0026] The latch-up-proof low-dropout voltage regulator provided in this invention, by adding a dynamic clamping circuit to the current-limiting loop of the low-dropout voltage regulation circuit, prevents latch-up during soft-start or when the output load current exceeds the nominal maximum value. This allows the LDO to operate normally under extreme conditions such as overload, short circuit, or high output current startup. Once the external factors causing overload or short circuit disappear, the output automatically returns to the nominal value. The circuit structure of this invention is simple, adding only minimal additional power consumption, and does not affect the steady-state stability of the LDO system.

[0027] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0028] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0029] Figure 1 The diagram shown is a structural schematic of the anti-latch-up low-dropout voltage regulator described in an embodiment of this application.

[0030] Figure 2The diagram shown is a schematic diagram of the first clamping circuit structure in the anti-latch-up low-dropout voltage regulator described in the embodiments of this application.

[0031] Figure 3 The diagram shown is a schematic diagram of the second type of clamping circuit structure in the anti-latch-up low-dropout voltage regulator described in the embodiments of this application;

[0032] Figure 4 The diagram shown is a schematic of the third clamping circuit structure in the anti-latch-up low-dropout voltage regulator described in this application embodiment. Detailed Implementation

[0033] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0034] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show components related to this application and are not drawn according to the actual number, shape, and size of components in the actual implementation. In the actual implementation, the type, quantity, and proportion of each component can be arbitrarily changed, and the component layout may also be more complex. Furthermore, the electronic device reference numerals involved in the following embodiments can not only represent the electronic device itself, but also the physical value of the electronic device. For example, R1 can represent the first resistor in the embodiments and drawings, and can also represent the resistance value of the first resistor in the formula. MOS is an abbreviation for Metal-Oxide-Semiconductor Field-Effect Transistor, where NMOS is N-type Metal-Oxide-Semiconductor and PMOS is P-type Metal-Oxide-Semiconductor.

[0035] The following embodiments of this application provide a latch-up low-dropout voltage regulator suitable for use in integrated circuits of portable electronic products.

[0036] like Figure 1 As shown, this embodiment provides an anti-latch-up low-dropout voltage regulator, including a low-dropout voltage regulation circuit and a clamping circuit. The low-dropout voltage regulation circuit is equipped with a current-limiting detection unit, and the clamping circuit is connected to the detection terminal of the current-limiting detection unit in the low-dropout voltage regulation circuit.

[0037] The low-dropout voltage regulation circuit is mainly used to output a stable operating voltage under the action of the current limiting detection unit. For example... Figure 1As shown, the low-dropout voltage regulation circuit can specifically include an error amplifier A1, a voltage buffer A2, a first PMOS voltage regulator Mc1, a feedback network 1, and a current limiting detection unit 2. The inverting input of the error amplifier A1 receives the reference voltage V. REF The output of error amplifier A1 is connected to the non-inverting input of voltage buffer A2, and the output of voltage buffer A2 is connected to the gate of the first PMOS voltage regulator Mc1. The source of the first PMOS voltage regulator Mc1 is connected to the power supply voltage V. DD The drain of the first PMOS voltage regulator transistor Mc1 is used as the output terminal V of the low dropout voltage regulation circuit. OUT Feedback network 1 is connected between the drain of the first PMOS voltage regulator Mc1 and the ground terminal GND. Specifically, feedback network 1 includes a first resistor R1, a second resistor R2, and a third resistor R3 connected in series. The non-inverting input of error amplifier A1 is connected to the output of the second resistor R2. The detection terminal of current limiting detection unit 2 is connected to the output of the first resistor R1, and the output of current limiting detection unit 2 is connected to the non-inverting input of voltage buffer A2. It is necessary to ensure that (R2+R3)>R4.

[0038] Furthermore, the current limiting detection unit 2 can be configured to include a second PMOS voltage regulator Mc2, a fourth resistor R4, and a third amplifier A3. The gate of the second PMOS voltage regulator Mc2 is connected to the output terminal of the voltage buffer A2, and the source of the second PMOS voltage regulator Mc2 is connected to the power supply voltage V. DD The drain of the second PMOS voltage regulator Mc2 is grounded through the fourth resistor R4. The non-inverting input of the third amplifier A3 serves as the detection terminal of the current limiting detection unit 2. The inverting input of the third amplifier A3 is connected to the input terminal of the fourth resistor R4. The output of the third amplifier A3 is connected to the inverting input of the voltage buffer.

[0039] In the aforementioned low-dropout voltage regulation circuit, when the output voltage V OUT When pulled close to ground potential by excessive load current, due to the effect of the current limiting loop, the detection terminal voltage of current limiting detection unit 2 approaches ground potential, causing the output terminal voltage VC of current limiting detection unit 2 to approach ground potential, resulting in the output terminal voltage PDRV of voltage buffer A2 being equal to V. DD This further enables the first PMOS voltage regulator Mc1 and the second PMOS voltage regulator Mc2 to be turned off, thereby connecting the inverting input of the current limiting detection unit 2 and the output of the low-dropout voltage regulation circuit V. OUTThe low-dropout voltage regulator circuit remains latched up, maintaining a constant ground potential. Even after the excessive load current disappears, the circuit remains latched, preventing automatic output recovery. Unless power is restored or the circuit is restarted with an external signal, this negatively impacts the LDO's reliability.

[0040] The clamping circuit in this embodiment is used to provide a low voltage to the detection terminal of the current limiting detection unit 2 to prevent the low-dropout voltage regulation circuit from latching up during the soft start process, thereby ensuring the successful soft start of the low-dropout voltage regulation circuit. Simultaneously, the clamping circuit's provision of a low voltage to the detection terminal of the current limiting detection unit 2 also serves to prevent latch-up of the low-dropout voltage regulation circuit when the output operating voltage of the low-dropout voltage regulation circuit is lower than a preset value (i.e., when the output voltage of the low-dropout voltage regulation circuit is pulled close to ground potential by the excessive load current).

[0041] The working principle of the clamping circuit in the anti-latch-up low-dropout voltage regulator is as follows: When the low-dropout voltage regulation circuit is working normally, the low voltage provided by the clamping circuit to the detection terminal of the current limiting detection unit 2 in the low-dropout voltage regulation circuit has almost no effect on the voltage regulation system of the low-dropout voltage regulation circuit. However, when an anomaly occurs, causing the voltage V at the detection terminal of the current limiting detection unit 2 to... FOLD When the voltage is lower than the dynamic set value, the low-level voltage provided by the clamping circuit causes the voltage V at the detection terminal of the current limiting detection unit 2 to decrease. FOLD Maintain the set value. In this state, the output current of the low-dropout voltage regulation circuit can be calculated as: V FOLD / R4*K (K is the width-to-length ratio of the first PMOS voltage regulator Mc1 and the second PMOS voltage regulator Mc2), the voltage at the non-inverting input of the error amplifier is V. FB =V FOLD *R3 / (R2+R3) is used to prevent "latch-up" in the low-dropout voltage regulation circuit. Therefore, when the excessive load current disappears, the clamping circuit's effect is relatively weakened, and the voltage V at the detection terminal of current limiting detection unit 2 decreases. FOLD There was an immediate upward trend, and the output gradually and automatically recovered to the nominal voltage through the adjustment of the current limiting loop.

[0042] Specifically, the clamping circuit can be configured to include a soft-start low-voltage supply unit and a load overcurrent low-voltage supply unit; that is, it includes two types of low-voltage supply units. The soft-start low-voltage supply unit provides a first preset low voltage to the detection terminal of the current limiting detection unit 2 when the low-dropout voltage regulation circuit starts, thereby achieving a soft start for the low-dropout voltage regulation circuit and preventing "latch-up" during the soft start process. The load overcurrent low-voltage supply unit provides a second preset low voltage to the detection terminal of the current limiting detection unit 2 after the low-dropout voltage regulation circuit starts, ensuring that the detection terminal of the current limiting detection unit 2 maintains a low voltage when the operating voltage output by the low-dropout voltage regulation circuit is lower than a preset value, thus preventing "latch-up" from occurring in the low-dropout voltage regulation circuit.

[0043] like Figures 2-4 As shown, the soft-start low-side voltage supply unit can be configured to include a first PMOS transistor MP1, a third PMOS transistor MP3, a sixth PMOS transistor MP6, a first current source I1, and a soft-start sub-circuit. The first PMOS transistor MP1 and the third PMOS transistor MP3 form a current mirror structure, and the mirrored current corresponds to Ia3. Furthermore, the sources of both the first PMOS transistor MP1 and the third PMOS transistor MP3 are connected to the power supply voltage V. DD The drain of the first PMOS transistor MP1 is connected to its gate, and the gate of the first PMOS transistor MP1 is connected to the gate of the third PMOS transistor MP3. The drain of the first PMOS transistor MP1 is grounded through the first current source I1. The drain of the third PMOS transistor MP3 is connected to the source of the sixth PMOS transistor MP6, and the soft-start sub-circuit is connected to the gate of the sixth PMOS transistor MP6. That is, the output signal Softstart of the soft-start sub-circuit is used to control the sixth PMOS transistor MP6, and the drain of the sixth PMOS transistor MP6 serves as the first preset low-level voltage output terminal. When the soft-start is effective, current Ia3 is injected into the detection terminal FOLD of the current limiting detection unit 2. Considering that the output terminal V of the low-dropout voltage regulation circuit is at this time... OUT =0, then the injection of Ia3 results in the following preset low-order voltage value:

[0044] V FOLD1 =Ia3*[R1*(R2+R3) / (R1+R2+R3)].

[0045] More preferably, the soft-starter circuit can be configured to include a second PMOS transistor MP2 and a capacitor C1, wherein the second PMOS transistor MP2 also forms a current mirror structure with the first PMOS transistor MP1, and the mirrored current corresponds to Ia2. The source of the second PMOS transistor MP2 is connected to the power supply voltage V. DDThe gate of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1, and the drain of the second PMOS transistor MP2 is grounded through capacitor C1. The drain of the second PMOS transistor MP2 serves as the output terminal of the soft starter circuit.

[0046] It should be noted that the soft starter circuit can also be configured with other existing reasonable structures, which will not be elaborated on here.

[0047] This invention provides a low-voltage supply unit for load overcurrent. Figures 2-4 The three structures shown below will be explained in detail.

[0048] like Figure 2 As shown, one structure of the load overcurrent low-voltage supply unit can be configured to include a ninth PMOS transistor MP9, a second current source I2, a fourth PMOS transistor MP4, a first NMOS transistor MN1, a second NMOS transistor MN2, and a third NMOS transistor MN3. The ninth PMOS transistor MP9 and the second current source I2 can be shared devices with the soft-start low-voltage supply unit (i.e., the ninth PMOS transistor MP9 is equivalent to the first PMOS transistor MP1, and the second current source I2 is equivalent to the first current source I1). In this case, the soft-start low-voltage supply unit and the load overcurrent low-voltage supply unit are connected, meaning the output terminal of the soft-start low-voltage supply unit is connected to the output terminal of the load overcurrent low-voltage supply unit (e.g., ...). Figure 2 As shown), the low-level voltage provided by the clamping circuit at this time is the larger of the first preset low-level voltage provided by the soft-start low-level voltage providing unit and the second preset low-level voltage provided by the load overcurrent low-level voltage providing unit, that is, the clamping circuit provides a dynamic low-level voltage. If the ninth PMOS transistor MP9 and the second current source I2 are not shared devices with the soft-start low-level voltage providing unit, the ninth PMOS transistor MP9 and the second current source I2 can be set to devices of the same model as those in the soft-start low-level voltage providing unit. At this time, the clamping circuit can provide different low-level voltages in different states of the low-dropout voltage regulation circuit by turning on and off the power supply voltage of the corresponding circuit. Figure 2 (This is not reflected in the text).

[0049] Furthermore, the connection method of each device in the above-mentioned load overcurrent low-voltage supply unit is as follows: the source of the ninth PMOS transistor MP9 and the source of the fourth PMOS transistor MP4 are both connected to the power supply voltage V. DDThe gates of the ninth PMOS transistor MP9 and the fourth PMOS transistor MP4 are connected. The drain of the ninth PMOS transistor MP9 is grounded through the second current source I2. The gates and drains of the ninth PMOS transistor MP9 and the fourth PMOS transistor MP4 are connected. The drain of the fourth PMOS transistor MP4 is connected to the drain of the second NMOS transistor MN2. The ninth PMOS transistor MP9 and the fourth PMOS transistor MP4 form a current mirror structure, and the mirrored current corresponds to Ia4. The gate of the second NMOS transistor MN2 is connected to the gate of the third NMOS transistor MN3. The gate and drain of the second NMOS transistor MN2 are connected. The gate and drain of the first NMOS transistor MN1 are both connected to the source of the second NMOS transistor MN2. The source of the first NMOS transistor MN1 is grounded. The drain of the third NMOS transistor MN3 is connected to the power supply voltage V. DD The source of the third NMOS transistor MN3 is connected as the second preset low-level voltage output terminal.

[0050] The working principle of the above-mentioned load overcurrent low-voltage supply unit is as follows: The current Ia4 provided by the fourth NPOS transistor MP4 flows to the voltage conversion module to generate V. CLAMP Voltage. Assume the gate-source voltage of the PMOS is V. GS Then V CLAMP =2*V GS The current limiting detection unit 2's detection terminal V is connected via the third NMOS transistor MN3. FOLD Clamping is: V FOLD2 =V CLAMP -V GS =V GS When the soft-start low-voltage supply unit and the load overcurrent low-voltage supply unit are connected, the low-voltage provided by the clamping circuit is the larger of the first preset low-voltage provided by the soft-start low-voltage supply unit and the second preset low-voltage provided by the load overcurrent low-voltage supply unit: that is, V FOLD =max(V FOLD1 V FOLD2 In fact, when the low-dropout voltage regulation circuit is in the start-up state, V often FOLD1 Greater than V FOLD2 After the low-dropout voltage regulation circuit has started, V often FOLD1 Less than V FOLD2 Therefore, when the soft start is complete, the sixth PMOS transistor MP6 is turned off, while the third NMOS transistor MN3 remains active, and V... FOLD =V GS The rate limit is V. GS / R4*K>0. If the large external load current disappears, the output voltage V of the low-dropout voltage regulation circuit will decrease. OUT It will rise, at which point we have: V FOLD =[VGS / R4*K]*(R2+R3)=V GS *K*(R2+R3) / R4; Since K>1 is usually the case, and the design can usually guarantee (R2+R3)>R4, then [V GS / R4*K]*(R2+R3)>V GS The voltage V at the detection terminal of the current limiting detection unit 2 FOLD It will gradually rise until the output voltage V of the low-dropout voltage regulation circuit is reached. OUT Restore the nominal voltage.

[0051] Figure 3 The second structure of the load overcurrent low-voltage supply unit shown includes a tenth PMOS transistor, a third current source, a twelfth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The tenth PMOS transistor MP10 and the third current source I3 can be shared devices with the soft-start low-voltage supply unit (i.e., the tenth PMOS transistor MP10 is equivalent to the first PMOS transistor MP1, and the third current source I3 is equivalent to the first current source I1). In this case, the soft-start low-voltage supply unit and the load overcurrent low-voltage supply unit are connected, meaning the output of the soft-start low-voltage supply unit is connected to the output of the load overcurrent low-voltage supply unit (e.g., ...). Figure 3 As shown), the low-level voltage provided by the clamping circuit at this time is the larger of the first preset low-level voltage provided by the soft-start low-level voltage providing unit and the second preset low-level voltage provided by the load overcurrent low-level voltage providing unit, that is, the clamping circuit provides a dynamic low-level voltage. If the tenth PMOS transistor MP10 and the third current source I3 are not shared devices with the soft-start low-level voltage providing unit, the tenth PMOS transistor MP10 and the third current source I3 can be set to devices of the same model as those in the soft-start low-level voltage providing unit. At this time, the clamping circuit can provide different low-level voltages in different states of the low-dropout voltage regulation circuit by turning on and off the power supply voltage of the corresponding circuit. Figure 3 (This is not reflected in the text).

[0052] Furthermore, the connection method of each device in the above-mentioned load overcurrent low-voltage supply unit is as follows: the source of the tenth PMOS transistor and the source of the twelfth PMOS transistor are both connected to the power supply voltage; the gate of the tenth PMOS transistor and the gate of the twelfth PMOS transistor are connected; the drain of the tenth PMOS transistor is grounded through the third current source; the gate of the tenth PMOS transistor and the drain of the tenth PMOS transistor are connected; the drain of the twelfth PMOS transistor is connected to the drain of the sixth NMOS transistor; wherein the tenth PMOS transistor MP10 and the twelfth PMOS transistor MP12 form a current mirror structure, and the mirrored current corresponds to Ia6. The gate of the sixth NMOS transistor is connected to the gate of the seventh NMOS transistor; the gate of the sixth NMOS transistor and the drain of the sixth NMOS transistor are connected; the gate and drain of the fifth NMOS transistor are both connected to the source of the sixth NMOS transistor; the source of the fifth NMOS transistor is grounded; the drain of the seventh NMOS transistor is connected to the drain of the third PMOS transistor; the source of the seventh NMOS transistor serves as the second preset low-voltage output terminal.

[0053] The working principle of the above-mentioned load overcurrent low-voltage supply unit is as follows: When the soft-start low-voltage supply unit and the load overcurrent low-voltage supply unit are connected, the low-voltage provided by the clamping circuit is the larger of the first preset low-voltage provided by the soft-start low-voltage supply unit and the second preset low-voltage provided by the load overcurrent low-voltage supply unit: that is, V FOLD =max(V FOLD1 V FOLD2 In fact, when the low-dropout voltage regulation circuit is in the start-up state, V often FOLD1 Greater than V FOLD2 After the low-dropout voltage regulation circuit has started, V often FOLD1 Less than V FOLD2 After the soft start is complete, the sixth PMOS transistor MP6 is turned off, while the seventh NMOS transistor MN7 remains active. When current limiting is applied after startup, the current limiting detection unit 2's detection terminal V is controlled via the seventh NMOS transistor MN7. FOLD Clamping is: V FOLD2 =Ia3*[R1*(R2+R3) / (R1+R2+R3)] <V GS It offers greater convenience in controlling clamping voltage and power consumption. If the external large load current disappears, the low-dropout voltage regulation circuit outputs a voltage V... OUT It will rise, at which point V FOLD = Ia3*[R1*(R2+R3) / (R1+R2+R3)]*K*(R2+R3) / R4. Since K>1 is usually the case, and the design can usually guarantee (R2+R3)>R4, then: Ia3*[R1*(R2+R3) / (R1+R2+R3)]*K*(R2+R3) / R4>V FOLD=Ia3*[R1*(R2+R3) / (R1+R2+R3)], Voltage V at the detection terminal of current limiting detection unit 2 FOLD It will gradually rise until the output voltage V of the low-dropout voltage regulation circuit is reached. OUT Restore the nominal voltage.

[0054] like Figure 4 As shown, the third structure of the load overcurrent low-voltage supply unit can be configured to include an eleventh PMOS transistor MP11, a fourth current source I4, a resistor Rc, a thirteenth PMOS transistor MP13, a fifth PMOS transistor MP5, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, and a fourth NMOS transistor MN4. The eleventh PMOS transistor MP11 and the fourth current source I4 can be shared devices with the soft-start low-voltage supply unit (i.e., the eleventh PMOS transistor MP11 is equivalent to the first PMOS transistor MP1, and the fourth current source I4 is equivalent to the first current source I1). In this case, the soft-start low-voltage supply unit and the load overcurrent low-voltage supply unit are connected, meaning the output of the soft-start low-voltage supply unit is connected to the output of the load overcurrent low-voltage supply unit (e.g., ...). Figure 4 As shown), the low-level voltage provided by the clamping circuit at this time is the larger of the first preset low-level voltage provided by the soft-start low-level voltage providing unit and the second preset low-level voltage provided by the load overcurrent low-level voltage providing unit, that is, the clamping circuit provides a dynamic low-level voltage. If the eleventh PMOS transistor MP11 and the fourth current source I4 are not shared devices with the soft-start low-level voltage providing unit, the eleventh PMOS transistor MP11 and the fourth current source I4 can be set to devices of the same model as those in the soft-start low-level voltage providing unit. At this time, the clamping circuit can provide different low-level voltages in different states of the low-dropout voltage regulation circuit by turning on and off the power supply voltage of the corresponding circuit. Figure 4 (Not reflected in the text)

[0055] Furthermore, the connection method of each device in the above-mentioned load overcurrent low-voltage supply unit is as follows: the source of the eleventh PMOS transistor MP11, the source of the thirteenth PMOS transistor MP13, and the source of the fifth PMOS transistor MP5 are all connected to the power supply voltage V. DDThe gate of the eleventh PMOS transistor MP11 is connected to the gates of the thirteenth PMOS transistor MP13 and the fifth PMOS transistor MP5, respectively. The drain of the eleventh PMOS transistor MP11 is grounded through a current source. The drain of the fourth NMOS transistor MN4 is connected to the drain of the eleventh PMOS transistor MP11. The source of the fourth NMOS transistor MN4 is grounded through a resistor Rc. The gate of the fourth NMOS transistor MN4 is connected to the output terminal of the low-dropout voltage regulation circuit. The eleventh PMOS transistor MP11, the thirteenth PMOS transistor MP13, and the fifth PMOS transistor MP5 form a current mirror structure, and the mirrored currents are Ia7 and Ia5, respectively. The drain of the ninth NMOS transistor MN9 is connected to the drain of the fourth NMOS transistor MN4. The gate of the ninth NMOS transistor MN9 is connected to the gate of the eighth PMOS transistor MP8. The gate and drain of the ninth NMOS transistor MN9 are connected. The gate and drain of the eighth NMOS transistor MN8 are both connected to the source of the ninth NMOS transistor MN9. The source of the eighth NMOS transistor MN8 is grounded. The drain of the eighth PMOS transistor MP8 is grounded. The source of the eighth PMOS transistor MP8 is connected to the source of the seventh PMOS transistor MP7. The source of the seventh PMOS transistor MP7 is also connected to the drain of the fifth PMOS transistor MP5. The gate of the seventh PMOS transistor MP7 is connected to the output terminal V of the low-dropout voltage regulation circuit. OUT The drain of the seventh PMOS transistor MP7 is connected as the second preset low-level voltage output terminal.

[0056] The working principle of the above-mentioned load overcurrent low-voltage supply unit is as follows: Unlike the above structure, the dynamic current [(V] OUT -V GS The current flows through the eleventh PMOS transistor MP11, therefore Ia5, Ia7, and V... CLAMP All follow V OUT The dynamic current injection at this time results in the following preset low-level voltage value:

[0057] V FOLD1 =[(V OUT -V GS ) / Rc+I1]*[R1*(R2+R3) / (R1+R2+R3)].

[0058] When the soft-start low-voltage supply unit and the load overcurrent low-voltage supply unit are connected, the low-voltage provided by the clamping circuit is the larger of the first preset low-voltage provided by the soft-start low-voltage supply unit and the second preset low-voltage provided by the load overcurrent low-voltage supply unit: that is, V FOLD =max(V FOLD1 V FOLD2 In fact, when the low-dropout voltage regulation circuit is in the start-up state, V oftenFOLD1 Greater than V FOLD2 After the low-dropout voltage regulation circuit has started, V often FOLD1 Less than V FOLD2 The seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 form a differential pair structure. When the soft-start ends and the low-dropout voltage regulation circuit outputs voltage V... OUT <V CLAMP At that time, V FOLD2 =Ia5*[R1*(R2+R3) / (R1+R2+R3)], current limiting is Ia5*[R1*(R2+R3) / (R1+R2+R3)] / R4*K>0; if the external large load current disappears at the moment, the low dropout voltage regulation circuit output voltage V OUT It will rise, V FOLD =Ia7*[R1*(R2+R3) / (R1+R2+R3)]*K*(R2+R3) / R4, usually K>1, and the design usually ensures (R2+R3)>R4. In this case, we have: Ia5*[R1*(R2+R3) / (R1+R2+R3)]*K*(R2+R3) / R4>Ia5*[R1*(R2+R3) / (R1+R2+R3)], where V is the voltage at the detection terminal of the current limiting detection unit 2. FOLD It will gradually rise until the output voltage V of the low-dropout voltage regulation circuit is reached. OUT Restore nominal voltage. Due to Ia5 and V CLAMP All follow V OUT The dynamic clamping circuit can adjust the current limit value to be smaller or V. OUT Recovery is faster.

[0059] It should be noted that the low-level voltage provided by the clamping circuit can also be implemented through a software chip, but this invention does not focus on this, and will not elaborate further on this.

[0060] The latch-up-proof low-dropout voltage regulator provided in this invention prevents latch-up by adding a dynamic clamping circuit to the current-limiting loop of the low-dropout voltage regulation circuit. This prevents latch-up during soft-start or when the output load current exceeds the nominal maximum value. Consequently, the LDO can operate normally under extreme conditions such as overload, short circuit, or high output current startup. Once the external factors causing overload or short circuit disappear, the output automatically returns to the nominal value. The circuit structure of this invention is simple, adding only minimal additional power consumption, and does not affect the steady-state stability of the LDO system.

[0061] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0062] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A latch-up-proof low-dropout voltage regulator, characterized in that, It includes a low-dropout voltage regulation circuit and a clamping circuit connected to the detection terminal of the current limiting detection unit in the low-dropout voltage regulation circuit; The low-dropout voltage regulation circuit is used to output a stable operating voltage under the action of the current limiting detection unit; The clamping circuit is used to provide a low voltage to the detection terminal of the current limiting detection unit to achieve soft start of the low drop voltage regulation circuit, and to prevent the low drop voltage regulation circuit from latching when the operating voltage output by the low drop voltage regulation circuit is lower than a preset value. The clamping circuit includes a soft-start low-voltage supply unit and a load overcurrent low-voltage supply unit. The soft-start low-voltage supply unit provides a first preset low voltage to the current-limiting detection unit when the low-dropout voltage regulation circuit starts, thus enabling a soft start for the low-dropout voltage regulation circuit. The load overcurrent low-voltage supply unit provides a second preset low voltage to the current-limiting detection unit after the low-dropout voltage regulation circuit starts, ensuring that the current-limiting detection unit maintains a low voltage when the operating voltage output by the low-dropout voltage regulation circuit is lower than a preset value, thereby preventing the low-dropout voltage regulation circuit from latching up. The soft-start low-voltage supply unit includes a first PMOS transistor, a third PMOS transistor, a sixth PMOS transistor, a first current source, and a soft-start sub-circuit. The sources of the first and third PMOS transistors are both connected to the power supply voltage. The drain of the first PMOS transistor is connected to the gate of the first PMOS transistor. The gates of the first and third PMOS transistors are connected. The drain of the first PMOS transistor is grounded through the first current source. The drain of the third PMOS transistor is connected to the source of the sixth PMOS transistor. The soft-start sub-circuit is connected to the gate of the sixth PMOS transistor. The drain of the sixth PMOS transistor serves as the first preset low-voltage output terminal.

2. The regulator according to claim 1, characterized in that, The low dropout voltage regulation circuit includes an error amplifier, a voltage buffer, a first PMOS voltage regulator, a feedback network, and a current limiting detection unit. The inverting input of the error amplifier receives a reference voltage, the output of the error amplifier is connected to the non-inverting input of the voltage buffer, the output of the voltage buffer is connected to the gate of the first PMOS voltage regulator, the source of the first PMOS voltage regulator is connected to the power supply voltage, and the drain of the first PMOS voltage regulator serves as the output of the low dropout voltage regulation circuit. The feedback network is connected between the drain of the first PMOS voltage regulator and the ground terminal. The feedback network includes a first resistor, a second resistor, and a third resistor connected in series. The non-inverting input terminal of the error amplifier is connected to the output terminal of the second resistor. The detection terminal of the current limiting detection unit is connected to the output terminal of the first resistor. The output terminal of the current limiting detection unit is connected to the non-inverting input terminal of the voltage buffer.

3. The regulator according to claim 2, characterized in that, The current limiting detection unit includes a second PMOS voltage regulator, a fourth resistor, and a third amplifier. The gate of the second PMOS voltage regulator is connected to the output terminal of the voltage buffer, the source of the second PMOS voltage regulator is connected to the power supply voltage, and the drain of the second PMOS voltage regulator is grounded through the fourth resistor. The non-inverting input terminal of the third amplifier serves as the detection terminal, the inverting input terminal of the third amplifier is connected to the input terminal of the fourth resistor, and the output terminal of the third amplifier is connected to the inverting input terminal of the voltage buffer.

4. The regulator according to claim 1, characterized in that, The soft-starter circuit includes a second PMOS transistor and a capacitor C1. The source of the second PMOS transistor is connected to the power supply voltage, the gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the drain of the second PMOS transistor is grounded through the capacitor C1, and the drain of the second PMOS transistor serves as the output terminal of the soft-starter circuit.

5. The regulator according to claim 1, characterized in that, The load overcurrent low-voltage supply unit includes a ninth PMOS transistor, a second current source, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The source of the ninth PMOS transistor and the source of the fourth PMOS transistor are both connected to the power supply voltage. The gate of the ninth PMOS transistor and the gate of the fourth PMOS transistor are connected. The drain of the ninth PMOS transistor is grounded through the second current source. The gate of the ninth PMOS transistor and the drain of the ninth PMOS transistor are connected. The drain of the fourth PMOS transistor is connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to the gate of the third NMOS transistor, the gate of the second NMOS transistor is connected to the drain of the second NMOS transistor, the gate and drain of the first NMOS transistor are both connected to the source of the second NMOS transistor, the source of the first NMOS transistor is grounded, the drain of the third NMOS transistor is connected to the power supply voltage, and the source of the third NMOS transistor serves as the output terminal of the second preset low voltage.

6. The regulator according to claim 5, characterized in that, The output terminal of the soft-start low voltage supply unit is connected to the output terminal of the load overcurrent low voltage supply unit, and the first PMOS transistor is equivalent to the ninth PMOS transistor, and the first current source is equivalent to the second current source.

7. The regulator according to claim 1, characterized in that, The load overcurrent low-voltage supply unit includes a tenth PMOS transistor, a third current source, a twelfth PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor. The source of the tenth PMOS transistor and the source of the twelfth PMOS transistor are both connected to the power supply voltage. The gate of the tenth PMOS transistor and the gate of the twelfth PMOS transistor are connected. The drain of the tenth PMOS transistor is grounded through the third current source. The gate of the tenth PMOS transistor and the drain of the tenth PMOS transistor are connected. The drain of the twelfth PMOS transistor is connected to the drain of the sixth NMOS transistor. The gate of the sixth NMOS transistor is connected to the gate of the seventh NMOS transistor, the gate of the sixth NMOS transistor is connected to the drain of the sixth NMOS transistor, the gate and drain of the fifth NMOS transistor are both connected to the source of the sixth NMOS transistor, the source of the fifth NMOS transistor is grounded, the drain of the seventh NMOS transistor is connected to the drain of the third PMOS transistor, and the source of the seventh NMOS transistor serves as the second preset low-level voltage output terminal.

8. The regulator according to claim 7, characterized in that, The output terminal of the soft-start low voltage supply unit is connected to the output terminal of the load overcurrent low voltage supply unit, and the first PMOS transistor is equivalent to the tenth PMOS transistor, and the first current source is equivalent to the third current source.

9. The regulator according to claim 1, characterized in that, The load overcurrent low-voltage supply unit includes an eleventh PMOS transistor, a fourth current source, a resistor Rc, a thirteenth PMOS transistor, a fifth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a fourth NMOS transistor. The sources of the eleventh PMOS transistor, the thirteenth PMOS transistor, and the fifth PMOS transistor are all connected to the power supply voltage. The gate of the eleventh PMOS transistor is connected to the gates of the thirteenth PMOS transistor and the fifth PMOS transistor, respectively. The drain of the eleventh PMOS transistor is grounded through the fourth current source. The drain of the fourth NMOS transistor is connected to the drain of the eleventh PMOS transistor. The source of the fourth NMOS transistor is grounded through the resistor Rc. The gate of the fourth NMOS transistor is connected to the output terminal of the low-dropout voltage regulation circuit. The drain of the ninth NMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the ninth NMOS transistor is connected to the gate of the eighth PMOS transistor, the gate and drain of the ninth NMOS transistor are connected, the gate and drain of the eighth NMOS transistor are both connected to the source of the ninth NMOS transistor, the source of the eighth NMOS transistor is grounded, the drain of the eighth PMOS transistor is grounded, the source of the eighth PMOS transistor is connected to the source of the seventh PMOS transistor, the source of the seventh PMOS transistor is also connected to the drain of the fifth PMOS transistor, the gate of the seventh PMOS transistor is connected to the output terminal of the low dropout voltage regulation circuit, and the drain of the seventh PMOS transistor serves as the second preset low voltage output terminal.

10. The regulator according to claim 9, characterized in that, The output terminal of the soft-start low voltage supply unit is connected to the output terminal of the load overcurrent low voltage supply unit, and the first PMOS transistor is equivalent to the eleventh PMOS transistor, and the first current source is equivalent to the fourth current source.

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