Gate driving circuit, gate driver, and display panel

Abstract

The present invention discloses a gate driving circuit, a gate driver, and a display panel. The gate driving circuit includes a frequency adjustment module, a first control module, a second control module, and an output module; the first control module is configured to output a first control signal according to an input signal, a clock signal, a first frequency control signal, a second frequency control signal, a first power supply signal, and a second control signal; the second control module is configured to output a second control signal according to the first control signal, the clock signal, and a second power supply signal; the frequency adjustment module is configured to control the frequency of the clock signal according to the first frequency control signal and the second frequency control signal; the output module is configured to output the first power supply signal or the clock signal according to the first control signal and the second control signal. It can enable pixel units in different display areas to be displayed at different operating frequencies.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of displays, and in particular, to a gate driving circuit, a gate driver, and a display panel. Background Art

[0002] A gate driving circuit is provided in a display panel to provide a gate driving signal for pixel units and control the pixel units in the display panel to be driven row by row. In the prior art, the gate driving signals provided by the gate driving circuit for all pixel units in the display panel have the same frequency, so that all pixel units in the display panel have the same operating frequency. Therefore, it is impossible to achieve different operating frequency displays in different regions of the display panel according to user needs, which is not conducive to reducing the power consumption of the display panel while ensuring user display requirements. Summary of the Invention

[0003] The present invention provides a gate driving circuit, a gate driver, and a display panel to achieve different operating frequencies when the display panel is divided into regions and improve the display effect of the display panel.

[0004] In a first aspect, an embodiment of the present invention provides a gate driving circuit. The operating mode of the gate driving circuit includes at least two operating modes. The gate driving circuit includes a frequency adjustment module, a first control module, a second control module, and an output module;

[0005] The first control module is connected to the first control end of the output module and the second control module. The first control module is configured to output a first control signal according to an input signal, a clock signal, a first frequency control signal, a second frequency control signal, a first power supply signal, and a second control signal;

[0006] The second control module is connected to the first control module and the second control end of the output module. The second control module is configured to output the second control signal according to the first control signal, the clock signal, and a second power supply signal;

[0007] The frequency adjustment module is connected to the first control module, the second control module, and the output module. The frequency adjustment module is configured to control the frequency of the clock signal according to the first frequency control signal and the second frequency control signal;

[0008] The output module is configured to output the first power supply signal or the clock signal according to the first control signal and the second control signal; wherein, the effective duration of the first frequency control signal and the second frequency control signal is greater than the pulse width of the clock signal, and the frequencies of the first frequency control signal and the second frequency control signal are different in different operating modes.

[0009] Optionally, the clock signal includes a first clock signal and a second clock signal; the frequency adjustment module includes a first adjustment unit and a second adjustment unit;

[0010] The input end of the first adjustment unit is connected to the first clock signal input end, the output end of the first adjustment unit is connected to the first control module and the second control module, the control end of the first adjustment unit is connected to the first frequency control signal output end, and the first adjustment unit is configured to control the frequency of the first clock signal provided by the first clock signal input end output to the first control module and the second control module according to the first frequency control signal provided by the first frequency control signal output end;

[0011] The input end of the second adjustment unit is connected to the second clock signal input end, the output end of the second adjustment unit is connected to the first control module and the output module, the control end of the second adjustment unit is connected to the second frequency control signal output end, and the second adjustment unit is configured to control the frequency of the second clock signal provided by the second clock signal input end output to the first control module and the output module according to the second frequency control signal provided by the second frequency control signal output end.

[0012] Optionally, the first adjustment unit includes a first transistor, and the second adjustment unit includes a second transistor and a third transistor;

[0013] The gate of the first transistor is connected to the first frequency control signal output end, the first pole of the first transistor is connected to the first clock signal input end, and the second pole of the first transistor is connected to the first control module and the second control module;

[0014] The gates of the second transistor and the third transistor are connected to the second frequency control signal output end, the first poles of the second transistor and the third transistor are connected to the second clock signal input end, the second pole of the second transistor is connected to the first control module, and the second pole of the third transistor is connected to the output module.

[0015] Optionally, the channel width-to-length ratio of the third transistor is greater than 1.

[0016] Optionally, the first control module includes an input unit, a node control unit, and a misoutput control unit;

[0017] The input unit is used to output the first control signal according to the input signal and the first clock signal, the node control unit is used to output the first control signal according to the second clock signal, the first power supply signal and the second control signal, and the error output control unit is used to control the node control unit and the input unit to output the first control signal in a time-sharing manner according to the first frequency control signal and the second frequency control signal.

[0018] Optionally, the input unit includes a fourth transistor, the node control unit includes a fifth transistor and a sixth transistor, and the erroneous output control unit includes a seventh transistor;

[0019] The gate of the fourth transistor is connected to the second electrode of the first transistor, the first electrode of the fourth transistor is connected to the input signal terminal, the second electrode of the fourth transistor is connected to the second electrode of the fifth transistor, the first control terminal and the second control module, the gate of the fifth transistor is connected to the second electrode of the second transistor, the first electrode of the fifth transistor is connected to the second electrode of the sixth transistor, the first electrode of the sixth transistor is connected to the first power supply signal input terminal, and the gate of the sixth transistor is connected to the second control terminal; the gate of the seventh transistor is connected to the first frequency control signal output terminal, the first electrode of the seventh transistor is connected to the second frequency control signal output terminal, and the second electrode of the seventh transistor is connected to the gate of the fifth transistor.

[0020] Optionally, the second control module includes an eighth transistor and a ninth transistor;

[0021] The gate of the eighth transistor is connected to the first control end, the first electrode of the eighth transistor and the gate of the ninth transistor are connected to the second electrode of the first transistor, the second electrode of the eighth transistor and the second electrode of the ninth transistor are connected to the second control end, and the first electrode of the ninth transistor is connected to the second power supply signal input end.

[0022] Optionally, the output module includes a first output unit and a second output unit;

[0023] The control end of the first output unit serves as the first control end, the input end of the first output unit is connected to the second electrode of the third transistor, the output end of the first output unit is connected to the output end of the second output unit and serves as the output end of the gate drive circuit; the control end of the second output unit serves as the second control end, and the input end of the second output unit is connected to the first power signal input end;

[0024] Preferably, the first output unit includes a tenth transistor and a first capacitor; a gate of the tenth transistor is connected to a first pole of the first capacitor and serves as the first control terminal, a first pole of the tenth transistor is connected to a second pole of the third transistor, and a second pole of the tenth transistor is connected to a second pole of the first capacitor and serves as an output terminal of the gate driving circuit;

[0025] The second output unit includes an eleventh transistor and a second capacitor; a gate of the eleventh transistor is connected to a first pole of the second capacitor and serves as the second control terminal, a first pole of the eleventh transistor and a first pole of the second capacitor are connected to the first power signal input terminal, and a second pole of the eleventh transistor serves as the output terminal of the gate driving circuit;

[0026] Preferably, the gate driving circuit further includes a twelfth transistor; a gate of the twelfth transistor is connected to the second power signal input terminal, and the first control module and the second control module are connected to the first control terminal through the twelfth transistor.

[0027] Optionally, a working mode of the gate driving circuit includes a first working mode and a second working mode. In the first working mode, the first frequency control signal and the second frequency control signal are third power signals; in the second working mode, a frequency of the clock signal is greater than frequencies of the first frequency control signal and the second frequency control signal;

[0028] Preferably, in the second working mode, the frequency of the clock signal is n times the frequencies of the first frequency control signal and the second frequency control signal; where n is an integer greater than 1.

[0029] Second aspect, an embodiment of the present invention further provides a gate driver. The clock signal includes a first clock signal and a second clock signal. The gate driver includes multiple levels of the gate driving circuits described in the first aspect. The first clock signal input terminal of the (2m + 1)-th level of the gate driving circuit is used to access the first clock signal, and the second clock signal input terminal of the (2m + 1)-th level of the gate driving circuit is used to access the second clock signal. The first clock signal input terminal of the 2(m + 1)-th level of the gate driving circuit is used to access the second clock signal, and the second clock signal input terminal of the 2(m + 1)-th level of the gate driving circuit is used to access the first clock signal. The first frequency control signal input terminals of the 2n-level gate driving circuits are used to sequentially input the first frequency control signal to the 2n-th frequency control signal. The second frequency control signal input terminals of the 2n-level gate driving circuits are used to sequentially input the second frequency control signal to the (2n + 1)-th frequency control signal. Wherein, the first frequency control signal is multiplexed as the (2n + 1)-th frequency control signal. m is an integer greater than or equal to 0. The frequencies of the first clock signal and the second clock signal are n times the frequencies of the first frequency control signal and the second frequency control signal, and n is an integer greater than or equal to 1.

[0030] Third aspect, an embodiment of the present invention further provides a display panel, including a pixel driving circuit and the gate driver described in the second aspect. The gate driver is connected to the pixel driving circuit, and the gate driver is used to provide a gate driving signal for the pixel driving circuit.

[0031] The technical solution of the embodiment of the present invention controls the frequencies of the first frequency control signal and the second frequency control signal to be different in different working modes of the gate driving circuit, and then adjusts the frequencies of the clock signals through the frequency adjustment module, so that the gate driving circuit can output gate driving signals with different frequencies. When the gate driving circuit is used in a display panel, pixel units in different display areas in the display panel can be set to correspond to different gate driving circuits, and different frequencies of the gate driving circuits can be set according to display requirements, so that the pixel units in different display areas can be displayed at different working frequencies, which is beneficial to reducing the power consumption of the display panel on the basis of ensuring the display requirements of users. Description of the Drawings

[0032] Figure 1 It is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention;

[0033] Figure 2 It is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present invention;

[0034] Figure 3 It is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present invention;

[0035] Figure 4 Schematic diagram of another structure of the gate driving circuit provided by the embodiment of the present invention;

[0036] Figure 5 Schematic diagram of another structure of the gate driving circuit provided by the embodiment of the present invention;

[0037] Figure 6 Schematic diagram of another structure of the gate driving circuit provided by the embodiment of the present invention;

[0038] Figure 7 Schematic diagram of another structure of the gate driving circuit provided by the embodiment of the present invention;

[0039] Figure 8 is Figure 7 A timing diagram corresponding to the gate driving circuit provided in the first working mode;

[0040] Figure 9 is Figure 7 A timing diagram corresponding to the gate driving circuit provided in the second working mode;

[0041] Figure 10 Schematic diagram of a structure of a gate driver provided by the embodiment of the present invention;

[0042] Figure 11 Schematic diagram of a structure of a display panel provided by the embodiment of the present invention;

[0043] Figure 12 Schematic diagram of a structure of a display device provided by the embodiment of the present invention. Detailed implementation manners

[0044] The present invention will be further described in detail below with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. In addition, it should be noted that for the convenience of description, only the parts related to the present invention are shown in the drawings rather than all the structures.

[0045] A gate driving circuit is provided in the non-display area of the display panel, and pixel units are provided in the display area. The gate driving circuit is connected to the pixel units and is used to provide gate driving signals for the pixel units. With the development of display technology, on the basis of ensuring the display effect of the display panel, users have higher and higher requirements for the low power consumption of the display panel, making the demand for regional display of the display panel clearer and clearer. In the prior art, the gate driving circuit can only provide gate driving signals with the same frequency for the pixel units, so that the working frequencies of the pixel units in the display panel are the same, that is, the working frequencies of the pixel units at different positions in the display area of the same display panel are the same, making it impossible for the display panel to realize that the pixel units at different positions use different working frequencies for display, which is not conducive to reducing the power consumption of the display panel on the basis of ensuring the display requirements of users.

[0046] In view of the above technical problems, an embodiment of the present invention provides a gate driving circuit. Figure 1 The following is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention. As Figure 1 shown, the working mode of the gate driving circuit includes at least two working modes. The gate driving circuit includes a frequency adjustment module 110, a first control module 120, a second control module 130, and an output module 140; the first control module 120 is connected to the first control end CTRL1 of the output module 140 and the second control module 130, and the first control module 120 is used to output a first control signal according to an input signal, a clock signal, a first frequency control signal, a second frequency control signal, a first power supply signal, and a second control signal; the second control module 130 is connected to the first control module 120 and the second control end CTRL2 of the output module 140, and the second control module 130 is used to output a second control signal according to the first control signal, the clock signal, and a second power supply signal; the frequency adjustment module 110 is connected to the first control module 120, the second control module 130, and the output module 140, and the frequency adjustment module 110 is used to control the frequency of the clock signal according to the first frequency control signal and the second frequency control signal; the output module 140 is used to output a first power supply signal or a clock signal according to the first control signal and the second control signal; wherein, the effective duration of the first frequency control signal and the second frequency control signal is greater than the pulse width of the clock signal, and the frequencies of the first frequency control signal and the second frequency control signal are different in different working modes.

[0047] Specifically, the input signal terminal SIN is used to provide an input signal. The clock signal may include a first clock signal and a second clock signal. The first clock signal input terminal CLK1 is used to provide the first clock signal, and the second clock signal input terminal CLK2 is used to provide the second clock signal. The first clock signal and the second clock signal are clock signals with opposite timings. The first power signal input terminal VH is used to provide the first power signal, and the second power signal input terminal VL is used to provide the second power signal. The first frequency control signal input terminal CKA is used to provide the first frequency control signal, and the second frequency control signal input terminal CKB is used to provide the second frequency control signal. The output terminal VOUT of the gate driving circuit is used to output a gate driving signal. The gate driving signal is transmitted to the pixel unit in the display area of the display panel through a signal line to drive the pixel unit to display. Exemplarily, the gate driving signal may be a scanning signal or a light emission control signal. When the display panel includes multiple rows of pixel units, multiple gate driving circuits are cascaded to provide gate driving signals for at least one row of pixel units respectively. Among them, the input signal of the first-stage gate driving circuit is the input signal provided by the input signal terminal SIN, and the input signals of other-stage gate driving circuits are the gate driving signals output by the previous-stage gate driving circuit, that is, clock signals. Since multiple-stage gate driving circuits output clock signals, the delay of the clock signal is relatively large. By setting the effective level width of the input signal to be greater than the pulse width of the clock signal, it is possible to avoid the phenomenon that the level jump of the input signal causes abnormal output of the multiple-stage gate driving circuit during the process of the multiple-stage gate driving circuit outputting the clock signal.

[0048] Exemplarily, the clock signal includes a first clock signal and a second clock signal. Taking the case where the frequency adjustment unit 110 outputs the first clock signal when the first frequency control signal is at a low level and the frequency adjustment unit 110 outputs the second clock signal when the second frequency control signal is at a low level, and the output module 140 outputs the first power signal when the first control terminal CTRL1 is at a low level and the output module 140 outputs the second clock signal when the second control terminal CTRL2 is at a low level as an example for description. In a working mode, the first frequency control signal and the second frequency control signal may be low-level signals. At this time, the frequency adjustment module 110 controls the frequencies of the first clock signal and the second clock signal to be the frequencies of the first clock signal and the second clock signal themselves according to the first frequency control signal and the second frequency control signal. The specific process is as follows:

[0049] In the first stage, the input signal is at a low level, the first clock signal is at a low level, the second clock signal is at a high level, the first frequency control signal is at a low level, the second frequency control signal is at a low level. The frequency adjustment module 110 outputs the first clock signal and the second clock signal according to the first frequency control signal and the second frequency control signal. The first control module 120 outputs the input signal according to the input signal and the first clock signal, making the potential of the first control terminal CTRL1 at a low level. The second control module 130 outputs the first clock signal according to the first control signal and outputs the second power signal according to the first clock signal, making the potential of the second control terminal CTRL2 at a low level. The output module 140 outputs the second clock signal according to the first control signal of the first control terminal CTRL1 and outputs the first power signal according to the second control signal of the second control terminal CTRL2 at the same time. At this time, the gate drive signal output by the output terminal VOUT of the gate drive circuit is at a high level.

[0050] In the second stage, the input signal is at a high level, the first clock signal is at a high level, the second clock signal is at a low level, the first frequency control signal is at a low level, the second frequency control signal is at a low level. The frequency adjustment module 110 outputs the first clock signal and the second clock signal according to the first frequency control signal and the second frequency control signal. The first control module 120 stops outputting the first control signal according to the second clock signal and the second control signal. The maintaining effect of the output module 140 makes the potential of the first control terminal CTRL1 maintain at a low level. The second control module 130 outputs the first clock signal according to the first clock signal and the first control signal, making the potential of the second control terminal CTRL2 at a high level. The output module 140 outputs the second clock signal according to the first control signal of the first control terminal CTRL1 and stops outputting the first power signal according to the second control signal of the second control terminal CTRL2 at the same time. At this time, the gate drive signal output by the output terminal VOUT of the gate drive circuit is at a low level, realizing the shifted output of the input signal.

[0051] In the third stage, the input signal is at a high level, the first clock signal is at a low level, the second clock signal is at a high level, the first frequency control signal is at a low level, the second frequency control signal is at a low level. The frequency adjustment module 110 outputs the first clock signal and the second clock signal according to the first frequency control signal and the second frequency control signal. The first control module 120 outputs the input signal according to the first clock signal and the input signal, making the potential of the first control terminal CTRL1 at a high level. The second control module 130 outputs the second power signal according to the first clock signal and the first control signal, making the potential of the second control terminal CTRL2 at a low level. The output module 140 stops outputting the second clock signal according to the first control signal of the first control terminal CTRL1, and at the same time outputs the first power signal according to the second control signal of the second control terminal CTRL2. At this time, the gate drive signal output by the output terminal VOUT of the gate drive circuit is at a high level.

[0052] As can be seen from the above process, in the current working mode, the gate drive circuit outputs the gate drive signal of the first frequency according to the frequencies of the first clock signal and the second clock signal themselves.

[0053] In another working mode, the frequencies of the first frequency control signal and the second frequency control signal are greater than the frequencies of the first clock signal and the second clock signal, and the effective duration of the first frequency control signal and the second frequency control signal is greater than the pulse width of the clock signal. Among them, the clock signal includes the first clock signal and the second clock signal. Exemplarily, when the first frequency control signal and the second frequency control signal are clock signals, the pulse widths of the first frequency control signal and the second frequency control signal are greater than the pulse widths of the first clock signal and the second clock signal. At this time, it can be set that the starting point of the effective level of the first frequency control signal corresponds to the starting point of the effective level of the first clock signal, and the starting point of the effective level of the second frequency control signal corresponds to the starting point of the effective level of the second clock signal. The frequency adjustment module 110 controls the frequencies of the first clock signal and the second clock signal to be the frequencies of the first frequency control signal and the second frequency control signal according to the first frequency control signal and the second frequency control signal. The specific process is as follows:

[0054] In the first stage, the input signal is at a low level, the first clock signal is at a low level, the second clock signal is at a high level, the first frequency control signal is at a low level, the second frequency control signal is at a high level. The frequency adjustment module 110 outputs the first clock signal according to the first frequency control signal and the second frequency control signal, and cannot output the second clock signal. The first control module 120 outputs the input signal according to the input signal and the first clock signal, so that the potential of the first control terminal CTRL1 is at a low level. The second control module 130 outputs the first clock signal according to the first control signal, and outputs the second power supply signal according to the first clock signal, so that the potential of the second control terminal CTRL2 is at a low level. The output module 140 cannot obtain the second clock signal, that is, the output module 140 cannot output the second clock signal, and at the same time outputs the first power supply signal according to the second control signal of the second control terminal CTRL2. At this time, the gate drive signal output by the output terminal VOUT of the gate drive circuit is at a high level.

[0055] In the second stage, the effective level width of the input signal is greater than the pulse width of the clock signal. At the same time, the pulse widths of the first frequency control signal and the second frequency control signal are greater than the pulse widths of the first clock signal and the second clock signal. At this time, the input signal is at a low level, the first clock signal is at a high level, the second clock signal is at a high level, the first frequency control signal is at a low level, the second frequency control signal is at a high level. The frequency adjustment module 110 outputs the first clock signal according to the first frequency control signal and the second frequency control signal, and cannot output the second clock signal. The first control module 120 stops outputting the first control signal according to the first clock signal, the first frequency control signal and the second frequency control signal. The maintaining effect of the output module 140 keeps the potential of the first control terminal CTRL1 at a low level. The second control module 130 outputs the first clock signal according to the first control signal and the first frequency control signal, so that the potential of the second control terminal CTRL2 is at a high level. The output module 140 stops outputting the first power supply signal according to the second control signal, and cannot obtain the second clock signal according to the second frequency control signal. At this time, the potential of the output terminal VOUT of the gate drive circuit maintains the potential of the previous stage, that is, the gate drive signal output by the output terminal VOUT of the gate drive circuit is at a high level.

[0056] In the third stage, the input signal is at a high level, one of the first clock signal and the second clock signal is at a high level and the other is at a low level, the first frequency control signal is at a high level, and the second frequency control signal is at a high level. The frequency adjustment module 110 cannot output the first clock signal and the second clock signal according to the first frequency control signal and the second frequency control signal. The maintaining effect of the output module 140 keeps the potential of the first control terminal CTRL1 at a low level and the potential of the second control terminal CTRL2 at a high level. The output module 140 cannot obtain the second clock signal, that is, the output module 140 cannot output the second clock signal. At the same time, the first power signal cannot be output according to the second control signal of the second control terminal CTRL2. At this time, the potential of the output terminal VOUT of the gate drive circuit maintains the potential of the previous stage, that is, the gate drive signal output by the output terminal VOUT of the gate drive circuit is at a high level. Among them, in the second stage, the first clock signal can be at a high level, at this time the second clock signal is at a low level, or the first clock signal is at a low level, at this time the second clock signal is at a high level. The second stage includes at least one cycle of the clock signal.

[0057] In the fourth stage, the input signal is at a high level, the first clock signal is at a high level, the second clock signal is at a low level, the first frequency control signal is at a high level, and the second frequency control signal is at a low level. The frequency adjustment module 110 outputs the second clock signal according to the first frequency control signal and the second frequency control signal and cannot output the first clock signal. The first control module 120 stops outputting the first control signal according to the second clock signal and the second control signal. The maintaining effect of the output module 140 keeps the potential of the first control terminal CTRL1 at a low level. The second control module 130 cannot obtain the first clock signal, making the potential of the second control terminal CTRL2 in a floating state. The maintaining effect of the output module 140 maintains the potential of the second control terminal CTRL2 at a high level. The output module 140 outputs the second clock signal according to the first control signal of the first control terminal CTRL1. At the same time, the first power signal cannot be output according to the second control signal of the second control terminal CTRL2. At this time, the gate drive signal output by the output terminal VOUT of the gate drive circuit is at a low level, realizing the shift output of the input signal.

[0058] In the fifth stage, the input signal is at a high level, the first clock signal is at a low level, the second clock signal is at a high level, the first frequency control signal is at a low level, the second frequency control signal is at a high level, and the frequency adjustment module 110 outputs the first clock signal according to the first frequency control signal and the second frequency control signal, and cannot output the second clock signal. The first control module 120 outputs the input signal according to the input signal and the first clock signal, so that the potential of the first control terminal CTRL1 is at a high level. The second control module 130 outputs the second power supply signal according to the first clock signal, so that the potential of the second control terminal CTRL2 is at a low level. The output module 140 stops outputting the second clock signal according to the first control signal of the first control terminal CTRL1, and at the same time outputs the first power supply signal according to the second control signal of the second control terminal CTRL2. At this time, the gate drive signal output by the output terminal VOUT of the gate drive circuit is at a high level.

[0059] It can be seen from this that in another operating mode, the gate drive signal output by the gate drive circuit has an increased shift time in the third stage compared to the gate drive signal output in one operating mode, thereby reducing the frequency of the gate drive signal output by the gate drive circuit, that is, the gate drive circuit outputs the gate drive signal of the second frequency according to the frequencies of the first frequency control signal and the second frequency control signal. When the gate drive circuit is used in a display panel, pixel units in different display areas in the display panel can be set to correspond to different gate drive circuits, and different frequencies of different gate drive circuits can be set according to display requirements, so that pixel units in different display areas can be displayed at different operating frequencies, which is beneficial to reducing the power consumption of the display panel while ensuring the user's display requirements.

[0060] The technical solution of this embodiment controls the frequencies of the first frequency control signal and the second frequency control signal to be different in different operating modes of the gate drive circuit, and then adjusts the frequency of the clock signal through the frequency adjustment module, so that the gate drive circuit can output gate drive signals of different frequencies. When the gate drive circuit is used in a display panel, pixel units in different display areas in the display panel can be set to correspond to different gate drive circuits, and different frequencies of different gate drive circuits can be set according to display requirements, so that pixel units in different display areas can be displayed at different operating frequencies, which is beneficial to reducing the power consumption of the display panel while ensuring the user's display requirements.

[0061] Figure 2 FIG. is a schematic structural diagram of another gate drive circuit provided by an embodiment of the present invention. As Figure 2As shown, the clock signal includes a first clock signal and a second clock signal; the frequency adjustment module 110 includes a first adjustment unit 111 and a second adjustment unit 112; the input end of the first adjustment unit 111 is connected to the first clock signal input end CLK1, the output end of the first adjustment unit 111 is connected to the first control module 120 and the second control module 130, the control end of the first adjustment unit 111 is connected to the first frequency control signal output end CKA, and the first adjustment unit 111 is used to control the frequency of the first clock signal provided by the first clock signal input end CLK1 output to the first control module 120 and the second control module 130 according to the first frequency control signal provided by the first frequency control signal output end CKA; the input end of the second adjustment unit 112 is connected to the second clock signal input end CLK2, the output end of the second adjustment unit 112 is connected to the first control module 120 and the output module 140, the control end of the second adjustment unit 112 is connected to the second frequency control signal output end CKB, and the second adjustment unit 112 is used to control the frequency of the second clock signal provided by the second clock signal input end CLK2 output to the first control module 120 and the output module 140 according to the second frequency control signal provided by the second frequency control signal output end CKB.

[0062] Specifically, the first frequency control signal provided by the first frequency control signal output end CKA can control the conduction state of the first adjustment unit 111, and the second frequency control signal provided by the second frequency control signal output end CKB can control the conduction state of the second adjustment unit 112. Exemplarily, taking the case where the first adjustment unit 111 conducts when the first frequency control signal is at a low level and the second adjustment unit 112 conducts when the second frequency control signal is at a low level as an example. In the first working mode, the first frequency control signal and the second frequency control signal are low-level signals. At this time, the first adjustment unit 111 remains in the conduction state according to the first frequency control signal, so the first adjustment unit 111 can continuously output the first clock signal. At this time, the frequency of the first clock signal is the frequency of the first clock signal itself. The second adjustment unit 112 remains in the conduction state according to the second frequency control signal, so the second adjustment unit 112 can continuously output the second clock signal. At this time, the frequency of the second clock signal is the frequency of the second clock signal itself. In the second working mode, when the first frequency control signal is at a low level, the first adjustment unit 111 conducts according to the first frequency control signal, and the first adjustment unit 111 outputs the first clock signal. When the second frequency control signal is at a low level, the second adjustment unit 112 conducts according to the second frequency control signal, and the second adjustment unit outputs the second clock signal. So that the first adjustment unit 111 controls the frequency of the first clock signal according to the first frequency control signal, and the second adjustment unit 112 controls the frequency of the second clock signal according to the second frequency control signal. Thus, the frequency of the gate drive signal output by the gate drive circuit can be controlled.

[0063] Exemplarily, Figure 3 FIG. 4 is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present invention. As Figure 3 shown, the first adjustment unit 111 includes a first transistor T1, and the second adjustment unit 112 includes a second transistor T2 and a third transistor T3; the gate of the first transistor T1 is connected to the first frequency control signal output terminal CKA, the first pole of the first transistor T1 is connected to the first clock signal input terminal CLK1, and the second pole of the first transistor T1 is connected to the first control module 120 and the second control module 130; the gates of the second transistor T2 and the third transistor T3 are connected to the second frequency control signal output terminal CKB, the first poles of the second transistor T2 and the third transistor T3 are connected to the second clock signal input terminal CLK2, the second pole of the second transistor T2 is connected to the first control module 120, and the second pole of the third transistor T3 is connected to the output module 140.

[0064] Specifically, Figure 3 exemplarily shows that the first transistor T1, the second transistor T2, and the third transistor T3 are P-type transistors. When the first frequency control signal is at a low level, the first transistor T1 is turned on, and the first clock signal is output to the first control module 120 and the second control module 130 through the first transistor T1. Thus, the frequency of the first clock signal output by the first transistor T1 can be controlled by the frequency of the effective level of the first frequency control signal. When the second frequency control signal is at a low level, the second transistor T2 and the third transistor T3 are turned on, and the second clock signal is transmitted to the first control module 120 through the second transistor T2, and at the same time is transmitted to the output module 140 through the third transistor T3. Thus, the frequency of the second clock signal output by the second transistor T2 and the third transistor T3 can be controlled by the frequency of the effective level of the second frequency control signal. Then, the first control module 120, the second control module 130, and the output module 140 output a gate driving signal according to the frequencies of the first clock signal and the second clock signal, so that the gate driving circuit can output gate driving signals of different frequencies.

[0065] Based on the above technical solution, the channel width-to-length ratio of the third transistor is greater than 1.

[0066] Specifically, when the second frequency control signal controls the third transistor to be turned on, the second clock signal output by the third transistor is transmitted to the output module 140, so that the output module 140 outputs the second clock signal when the first control signal is at a low level. By setting the channel width-to-length ratio of the third transistor to be greater than 1, the on-voltage drop of the third transistor can be reduced, and further, when the third transistor transmits the second clock signal, the voltage drop of the second clock signal can be reduced, which is beneficial to improving the reliability of the gate driving signal.

[0067] Figure 4 This is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present invention. As Figure 4 shown, the first control module 120 includes an input unit 121, a node control unit 122, and a misoutput control unit 123; the input unit 121 is configured to output a first control signal according to an input signal and a first clock signal, the node control unit 122 is configured to output a first control signal according to a second clock signal, a first power signal, and a second control signal, and the misoutput control unit 123 is configured to control the node control unit 122 and the input unit 121 to output the first control signal at different times according to a first frequency control signal and a second frequency control signal.

[0068] Specifically, during the operation of the gate driving circuit, when the first clock signal is at a low level, the second clock signal is at a high level, the first frequency control signal is at a low level, and the second frequency control signal is at a high level. The input unit 121 can output the input signal as the first control signal to the first control terminal CTRL1 when the first clock signal is at a low level. At this time, the misoutput control unit 123 outputs the second frequency control signal to the node control unit 122 under the action of the first frequency control signal, so that the node control unit 122 is in a cut-off state under the control of the second frequency control signal, avoiding the misoutput of the first power signal by the node control unit 122. When the first clock signal is at a high level, the second clock signal is at a low level, the first frequency control signal can be at a high level, and the second frequency control signal can be at a low level. At this time, the second transistor T2 outputs the second clock signal under the action of the second frequency control signal. The input unit 121 is in a cut-off state under the control of the first clock signal and stops outputting the input signal. When the second control signal is at a low level, the node control unit 122 outputs the first power signal as the first control signal under the action of the second clock signal and the first control signal. At this time, the potential of the first control terminal CTRL1 is at a high level, avoiding the misoutput of the second clock signal by the output module 140. At the same time, the first power signal is output according to the second control signal of the second control terminal CTRL2, so that the gate driving signal output by the gate driving circuit is at a high level.

[0069] Exemplarily, Figure 5 This is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present invention. As Figure 5As shown in the figure, the input unit 121 includes a fourth transistor T4, the node control unit 122 includes a fifth transistor T5 and a sixth transistor T6, and the mis-output control unit 123 includes a seventh transistor T7; the gate of the fourth transistor T4 is connected to the second pole of the first transistor T1, the first pole of the fourth transistor T4 is connected to the input signal terminal SIN, and the second pole of the fourth transistor T4 is connected to the second pole of the fifth transistor T5, the first control terminal CTRL1 and the second control module 130. The gate of the fifth transistor T5 is connected to the second pole of the second transistor T2, the first pole of the fifth transistor T5 is connected to the second pole of the sixth transistor, the first pole of the sixth transistor is connected to the first power signal input terminal, and the gate of the sixth transistor T6 is connected to the second control terminal CTRL2; the gate of the seventh transistor T7 is connected to the first frequency control signal output terminal CKA, the first pole of the seventh transistor T7 is connected to the second frequency control signal output terminal CKB, and the second pole of the seventh transistor T7 is connected to the gate of the fifth transistor T5.

[0070] Specifically, Figure 5 It is exemplarily shown that the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are P-type transistors. When the first frequency control signal is at a low level and the first clock signal is at a low level, the first transistor T1 and the seventh transistor T7 are turned on. The first transistor T1 transmits the first clock signal to the gate of the fourth transistor T4 to control the fourth transistor T4 to be turned on. The input signal is transmitted to the first control terminal CTRL1 through the fourth transistor T4 as the first control signal. At the same time, the second frequency control signal is transmitted to the gate of the fifth transistor T5 through the seventh transistor T7. At this time, the second frequency control signal is at a high level, controlling the fifth transistor T5 to be turned off to prevent the first power signal from being output to the first control terminal CTRL1 through the fifth transistor T5 and the sixth transistor T6. At this time, the first control signal is the input signal. When the second frequency control signal is at a low level and the second clock signal is at a low level, the second transistor T2 outputs the second frequency control signal to the gate of the fifth transistor T5 to control the fifth transistor T5 to be turned on. When the second control signal is at a low level, the sixth transistor T6 is turned on, and the first power signal is transmitted to the first control terminal CTRL1 through the fifth transistor T5 and the sixth transistor T6, making the potential of the first control terminal CTRL1 at a high level.

[0071] Figure 6 It is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present invention. As Figure 6As shown, the second control module 130 includes an eighth transistor T8 and a ninth transistor T9; the gate of the eighth transistor T8 is connected to the first control terminal CTRL1, the first pole of the eighth transistor T8 and the gate of the ninth transistor T9 are connected to the second pole of the first transistor T1, the second pole of the eighth transistor T8 and the second pole of the ninth transistor T9 are connected to the second control terminal CTRL2, and the first pole of the ninth transistor T9 is connected to the second power supply signal input terminal VL.

[0072] Specifically, Figure 6 In the example, the eighth transistor T8 and the ninth transistor T9 are P-type transistors. When the first frequency control signal is at a low level and the potential of the first control terminal CTRL1 is at a low level, the first transistor T1 and the eighth transistor T8 are turned on. The first transistor T1 transmits the second clock signal to the first pole of the eighth transistor T8 and the gate of the ninth transistor. The eighth transistor T8 outputs the first clock signal to the second control terminal CTRL2, making the potential of the second control terminal CTRL2 the first clock signal. When the first clock signal is at a low level, the ninth transistor T9 is turned on. Both the first clock signal transmitted by the eighth transistor T8 to the second control terminal CTRL2 and the second power supply signal transmitted by the ninth transistor T9 to the second control terminal CTRL2 are at a low level, that is, the potential of the second control terminal CTRL2 is at a low level, and the output module 140 outputs the first power supply signal according to the second control signal. When the first clock signal is at a high level, the ninth transistor T9 is turned off, and the first clock signal transmitted by the eighth transistor T8 to the second control terminal CTRL2 is at a high level. The output module 140 stops outputting the first power supply signal according to the second control signal.

[0073] Figure 7 It is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present invention. As Figure 7 shown, the output module 140 includes a first output unit 141 and a second output unit 142; the control terminal of the first output unit 141 serves as the first control terminal CTRL1, the input terminal of the first output unit 141 is connected to the second pole of the third transistor T3, the output terminal of the first output unit 141 is connected to the output terminal of the second output unit 142 and serves as the output terminal VOUT of the gate driving circuit; the control terminal of the second output unit 142 serves as the second control terminal CTRL2, and the input terminal of the second output unit 142 is connected to the first power supply signal input terminal VH.

[0074] Specifically, the potential of the first control terminal CTRL1 controls the state of the first output unit 141, and the potential of the second control terminal CTRL2 controls the state of the second output unit 142. Taking the first control signal and the second control signal being active low as an example for illustration. When the first control signal is at a low level, the first output unit 141 is in a conducting state. At this time, the first output unit 141 can output the first power signal provided by the first power signal input terminal VH to the output terminal VOUT as the gate driving signal of the gate driving circuit. When the second control signal is at a low level, the second output unit 142 is in a conducting state. When the second frequency control signal controls the third transistor T3 to conduct, the second output unit 142 can output the second clock signal provided by the second clock signal input terminal CLK2 to the output terminal VOUT as the gate driving signal of the gate driving circuit. Additionally, both the first output unit 141 and the second output unit 142 have the function of maintaining the control terminal potential, so that the potentials of the first control terminal CTRL1 and the second control terminal CTRL2 can be maintained when the first control terminal CTRL1 and the second control terminal CTRL2 are in a floating state.

[0075] Exemplarily, with continued reference to Figure 7 , the first output unit 141 includes a tenth transistor T10 and a first capacitor C1; the gate of the tenth transistor T10 is connected to the first pole of the first capacitor C1 and serves as the first control terminal CTRL1, the first pole of the tenth transistor T10 is connected to the second pole of the third transistor T3, and the second pole of the tenth transistor T10 is connected to the second pole of the first capacitor C1 and serves as the output terminal VOUT of the gate driving circuit.

[0076] Specifically, the first control terminal CTRL1 can be the connection point of the gate of the tenth transistor T10 and the first pole of the first capacitor C1. The output terminal VOUT of the gate driving circuit can be the connection point of the second pole of the tenth transistor T10 and the second pole of the first capacitor C1. Figure 7Exemplarily, it is shown that the tenth transistor T10 is a P-type transistor. When the first control signal is at a low level, the potential of the first control terminal CTRL1 is at a low level, and the tenth transistor T10 is turned on. When the second frequency control signal is at a low level and controls the third transistor T3 to be turned on, the second clock signal is output to the output terminal VOUT through the tenth transistor T10 and serves as the gate drive signal of the gate drive circuit. When the first control module 120 is set to an open circuit, the potential of the first control terminal CTRL1 is in a floating state. At this time, the potential of the first control terminal CTRL1 can be maintained through the first capacitor C1. Additionally, the first capacitor C1 has a coupling effect. When the second clock signal is output to the output terminal VOUT through the tenth transistor T10, the gate drive signal output by the output terminal VOUT of the gate drive circuit jumps from a high level to a low level. The coupling effect of the first capacitor C1 makes the gate potential of the tenth transistor T10 lower than the low-level potential of the second clock signal, thereby ensuring the on state of the tenth transistor T10. At the same time, the threshold voltage loss during the transmission of the second clock signal by the tenth transistor T10 can be eliminated, ensuring that the level of the second clock signal output by the output terminal VOUT is relatively low and ensuring the reliability of the gate drive signal output by the gate drive circuit.

[0077] Exemplarily, continue to refer to Figure 7 , the second output unit 142 includes an eleventh transistor T11 and a second capacitor C2; the gate of the eleventh transistor T11 is connected to the first pole of the second capacitor C2 and serves as the second control terminal CTRL2. The first pole of the eleventh transistor T11 and the first pole of the second capacitor C2 are connected to the first power signal input terminal VH. The second pole of the eleventh transistor T11 serves as the output terminal VOUT of the gate drive circuit.

[0078] Specifically, the second control terminal CTRL2 can be the connection point between the gate of the eleventh transistor T11 and the first pole of the second capacitor C2. Figure 7 Exemplarily, it is shown that the eleventh transistor T11 is a P-type transistor. When the second control signal is at a low level, the potential of the second control terminal CTRL2 is at a low level, and the eleventh transistor T11 is turned on. The first power signal is output to the output terminal VOUT through the eleventh transistor T11 and serves as the gate drive signal of the gate drive circuit. When the second control module 130 is set to an open circuit, the potential of the second control terminal CTRL2 is in a floating state. At this time, the potential of the second control terminal CTRL2 can be maintained through the second capacitor C2.

[0079] Continue to refer to Figure 7 [[ID=

[0080] Specifically, Figure 7 exemplarily, the twelfth transistor T12 is a P-type transistor. The second power supply signal provided by the second power supply signal input terminal VL is at a low level. When the first control signal is at a high level, the twelfth transistor T12 is in a conducting state. When the first control signal is at a low level, the twelfth transistor T12 is in a near cut-off state. When the gate drive signal output by the output terminal VOUT of the gate drive circuit jumps from a high level to a low level, and the potential of the first control terminal CTRL1 is less than the low-level potential due to the coupling effect of the first capacitor C1, it can prevent this low potential from being transmitted to the first control module 120 and avoid damage to the devices in the first control module 120. For example, when the first control module 120 includes the fourth transistor T4 and the fifth transistor T5, it can prevent the second-pole potential of the fourth transistor T4 and the fifth transistor T5 from being too low, resulting in device damage caused by too large a difference between the gate potential and the second-pole potential of the fourth transistor T4 and the fifth transistor T5.

[0081] The working modes of the gate drive circuit may include a first working mode and a second working mode. Figure 8 For Figure 7 providing a timing diagram corresponding to the gate drive circuit in the first working mode. Refer to Figure 7 and Figure 8 , taking the first power supply signal as a high level and the second power supply signal as a low level as an example for illustration. Among them, sin is the timing of the input signal provided by the input signal terminal SIN, clk1 is the timing of the first clock signal provided by the first clock signal input terminal CLK1, clk2 is the timing of the second clock signal provided by the second clock signal input terminal CLK2, cka is the timing of the first frequency control signal provided by the first frequency control signal input terminal CKA, ckb is the timing of the first frequency control signal provided by the first frequency control signal input terminal CKB, and vout is the timing of the gate drive signal output by the output terminal VOUT of the gate drive circuit in the first working mode. The working principle of the gate drive circuit is described below through Figure 7 and Figure 8 to illustrate the working principle of the gate drive circuit.

[0082] In the first operating mode of the gate drive circuit, in the first stage t11, the input signal is at a low level, the first clock signal is at a low level, the second clock signal is at a high level, the first frequency control signal is at a low level, and the second frequency control signal is at a low level. The first transistor T1, the second transistor T2, the third transistor T3, and the seventh transistor T7 are turned on. The first clock signal is transmitted through the first transistor T1 to the gates of the fourth transistor T4 and the ninth transistor T9, controlling the fourth transistor T4 and the ninth transistor T9 to turn on. The fourth transistor T4 transmits the input signal to the first control terminal CTRL1, making the potential of the first control terminal CTRL1 at a low level, and controlling the eighth transistor T8 to turn on. The first clock signal is transmitted through the first transistor T1 to the first pole of the eighth transistor T8, and then transmitted through the eighth transistor T8 to the second control terminal CTRL2. At the same time, the ninth transistor T9 transmits the second power supply signal to the second control terminal CTRL2, making the potential of the second control terminal CTRL2 at a low level. The second clock signal is transmitted through the second transistor T2 to the gate of the fifth transistor T5, making the gate potential of the fifth transistor T5 the sum of the second clock signal and the second frequency control signal, controlling the fifth transistor T5 to turn off. The low level of the second control terminal CTRL2 controls the sixth transistor T6 to turn on, and at the same time the fifth transistor T5 is turned off, and the first power supply signal cannot be transmitted through the sixth transistor T6 and the fifth transistor T5 to the first control terminal CTRL1. The low level of the first control terminal CTRL1 controls the tenth transistor T10 to turn on. The second clock signal is transmitted through the third transistor T3 to the first pole of the tenth transistor T10, and then transmitted through the tenth transistor T10 to the output terminal VOUT. The low level of the second control terminal CTRL2 controls the eleventh transistor T11 to turn on, and the first power supply signal is transmitted through the eleventh transistor T11 to the output terminal VOUT. At this time, the second clock signal is at a high level, so the gate drive signal of the gate drive circuit is at a high level.

[0083] In the second stage t12, the input signal is at a high level, the first clock signal is at a high level, the second clock signal is at a low level, the first frequency control signal is at a low level, and the second frequency control signal is at a low level. The first transistor T1, the second transistor T2, the third transistor T3, and the seventh transistor T7 are turned on. The second clock signal is transmitted to the gate of the fifth transistor T5 through the second transistor T2. At the same time, the second frequency control signal is transmitted to the gate of the fifth transistor T5 through the seventh transistor T7, making the gate of the fifth transistor T5 at a low level and turning on the fifth transistor T5. The first clock signal is transmitted to the gates of the fourth transistor T4 and the ninth transistor T9 through the first transistor T1, controlling the fourth transistor T4 and the ninth transistor T9 to be turned off. The first control terminal CTRL1 maintains a low level and controls the eighth transistor T8 and the tenth transistor T10 to be turned on. The first clock signal is transmitted to the first pole of the eighth transistor T8 through the first transistor T1 and then transmitted to the second control terminal CTRL2 through the eighth transistor T8, making the potential of the second control terminal CTRL2 at a high level. At the same time, it is controlled that the second clock signal is output to the output terminal VOUT through the tenth transistor T10, and the gate drive signal output by the gate drive circuit is at a low level. At this time, the second control signal controls the sixth transistor T6 and the eleventh transistor T11 to be turned off, and the gate drive circuit stops outputting the first power signal. At the same time, the first power signal cannot be transmitted to the first control terminal CTRL1 through the fifth transistor T5 and the sixth transistor T6.

[0084] In the third stage t13, the input signal is at a high level, the first clock signal is at a low level, the second clock signal is at a high level, the first frequency control signal is at a low level, and the second frequency control signal is at a low level. The first transistor T1, the second transistor T2, the third transistor T3, and the seventh transistor T7 are turned on. The first clock signal is transmitted through the first transistor T1 to the gates of the fourth transistor T4 and the ninth transistor T9, controlling the fourth transistor T4 and the ninth transistor T9 to turn on. The fourth transistor T4 transmits the input signal to the first control terminal CTRL1, making the potential of the first control terminal CTRL1 at a high level, and controlling the eighth transistor T8 and the tenth transistor T10 to turn off. The second clock signal cannot be transmitted through the tenth transistor T10 to the output terminal VOUT. At the same time, the ninth transistor T9 transmits the second power supply signal to the second control terminal CTRL2, making the potential of the second control terminal CTRL2 at a low level, controlling the sixth transistor T6 and the eleventh transistor T11 to turn on. The first power supply signal is transmitted through the eleventh transistor T11 to the output terminal VOUT. At this time, the gate drive signal of the gate drive circuit is at a high level. At the same time, the second clock signal is transmitted through the second transistor T2 to the gate of the fifth transistor T5, and the second frequency control signal is transmitted through the seventh transistor T7 to the gate of the fifth transistor T5, making the gate of the fifth transistor T5 at a low level, and the fifth transistor T5 turns on. The first power supply signal is transmitted through the fifth transistor T5 and the sixth transistor T6 to the first control terminal CTRL1, maintaining the high level of the first control terminal CTRL1.

[0085] Figure 9 For Figure 7 a timing schematic diagram corresponding to the gate drive circuit in the second operating mode. Refer to Figure 7 and Figure 9 , taking the first power supply signal as a high level, the second power supply signal as a low level, and the frequencies of the first clock signal and the second clock signal being twice the frequencies of the first frequency control signal and the second frequency control signal as an example for illustration. Among them, sin is the timing of the input signal provided by the input signal terminal SIN, clk1 is the timing of the first clock signal provided by the first clock signal input terminal CLK1, clk2 is the timing of the second clock signal provided by the second clock signal input terminal CLK2, cka is the timing of the first frequency control signal provided by the first frequency control signal input terminal CKA, ckb is the timing of the first frequency control signal provided by the first frequency control signal input terminal CKB, and vout is the timing of the gate drive signal output by the output terminal VOUT of the gate drive circuit in the second operating mode. The working principle of the gate drive circuit is described below through Figure 7 and Figure 9 the following.

[0086] In the second operating mode of the gate driving circuit, during the first stage t21, the input signal is at a low level, the first clock signal is at a low level, the second clock signal is at a high level, the first frequency control signal is at a low level, and the second frequency control signal is at a high level. The first transistor T1 and the seventh transistor T7 are turned on, and the second transistor T2 and the third transistor T3 are turned off. The first clock signal is transmitted through the first transistor T1 to the gates of the fourth transistor T4 and the ninth transistor T9, controlling the fourth transistor T4 and the ninth transistor T9 to turn on. The fourth transistor T4 transmits the input signal to the first control terminal CTRL1, making the potential of the first control terminal CTRL1 at a low level, and controlling the eighth transistor T8 to turn on. The first clock signal is transmitted through the first transistor T1 to the first pole of the eighth transistor T8, and then transmitted through the eighth transistor T8 to the second control terminal CTRL2. At the same time, the ninth transistor T9 transmits the second power supply signal to the second control terminal CTRL2, making the potential of the second control terminal CTRL2 at a low level. The second clock signal cannot be transmitted through the second transistor T2 to the gate of the fifth transistor T5, and the second frequency control signal is transmitted through the seventh transistor T7 to the gate of the fifth transistor T5, making the gate of the fifth transistor T5 at a high level, and the fifth transistor T5 is turned off. At the same time, the second clock signal cannot be transmitted through the third transistor T3 to the tenth transistor T10, so that the tenth transistor T10 cannot output the second clock signal. The low level of the second control terminal CTRL2 controls the sixth transistor T6 and the eleventh transistor T11 to turn on. At this time, the first power supply signal cannot be transmitted through the sixth transistor T6 and the fifth transistor T5 to the first control terminal CTRL1, ensuring that the potential of the first control terminal CTRL1 is at a low level. At the same time, the first power supply signal is transmitted through the eleventh transistor T11 to the output terminal VOUT, making the gate driving signal of the gate driving circuit at a high level.

[0087] In the second stage t22, the input signal is at a low level, the first clock signal is at a high level, the second clock signal is at a high level, the first frequency control signal is at a low level, and the second frequency control signal is at a high level. The first transistor T1 and the seventh transistor T7 are turned on, and the second transistor T2 and the third transistor T3 are turned off. The first clock signal is transmitted through the first transistor T1 to the gates of the fourth transistor T4 and the ninth transistor T9, controlling the fourth transistor T4 and the ninth transistor T9 to turn off. The input signal cannot be output through the fourth transistor T4 to the first control terminal CTRL1, and the potential of the first control terminal CTRL1 is maintained at a low level, controlling the eighth transistor T8 to turn on. At the same time, the first clock signal is transmitted through the first transistor T1 to the first pole of the eighth transistor T8, and then transmitted through the eighth transistor T8 to the second control terminal CTRL2, making the potential of the second control terminal CTRL2 high, and controlling the sixth transistor T6 and the eleventh transistor T11 to turn off, so that the eleventh transistor T11 stops outputting the first power signal. At the same time, the second clock signal cannot be transmitted through the third transistor T3 to the tenth transistor T10, so that the tenth transistor T10 cannot output the second clock signal. At this time, the gate drive signal of the gate drive circuit remains high.

[0088] In the third stage t23, the input signal is at a high level, one of the first clock signal and the second clock signal is at a high level and the other is at a low level, the first frequency control signal is at a high level, and the second frequency control signal is at a high level. The first transistor T1, the second transistor T2, the third transistor T3 and the seventh transistor T7 are turned off. The first clock signal cannot be output through the first transistor T1, and the second clock signal cannot be output through the second transistor T2 and the third transistor T3. The first control terminal CTRL1 and the second control terminal CTRL2 are in a floating state, and the maintaining effect of the first capacitor C1 and the second capacitor C2 makes the potentials of the first control terminal CTRL1 and the second control terminal CTRL2 maintained at the potentials of the previous stage, that is, the potential of the first control terminal CTRL1 is low and the potential of the second control terminal CTRL2 is high, and controls the sixth transistor T6 and the eleventh transistor T11 to turn off, so that the eleventh transistor T11 stops outputting the first power signal. At the same time, the second clock signal cannot be transmitted through the third transistor T3 to the tenth transistor T10, so that the tenth transistor T10 cannot output the second clock signal. At this time, the gate drive signal of the gate drive circuit remains high.

[0089] It should be noted that Figure 9Exemplarily shown in the figure is that the duration of the third stage t23 includes one period of the first clock signal and the second clock signal. In other embodiments, the frequencies of the first frequency control signal and the second frequency control signal can also be adjusted according to requirements, such that the third stage t23 can also include multiple periods of the first clock signal and the second clock signal, which is not limited herein. Among them, the smaller the frequencies of the first frequency control signal and the second frequency control signal are, the more periods of the first clock signal and the second clock signal the third stage t23 includes.

[0090] In the fourth stage t24, the input signal is at a high level, the first clock signal is at a high level, the second clock signal is at a low level, the first frequency control signal is at a high level, and the second frequency control signal is at a low level. The first transistor T1 and the seventh transistor T7 are cut off, and the second transistor T2 and the third transistor T3 are turned on. The first clock signal cannot be output through the first transistor T1, such that the gate potentials of the fourth transistor T4 and the ninth transistor T9 are in a floating state, and the fourth transistor T4 and the ninth transistor T9 maintain the cut-off state of the previous stage. The input signal cannot be output to the first control terminal CTRL1 through the fourth transistor T4, and the potential of the first control terminal CTRL1 is maintained at a low level, and controls the eighth transistor T8 and the tenth transistor T10 to be turned on. At the same time, it is output to the tenth transistor T10 through the third transistor T3, such that the tenth transistor T10 outputs the second clock signal to the output terminal VOUT. The first pole of the eighth transistor T8 is in a floating state, and at the same time the ninth transistor T9 is cut off, such that the potential of the second control terminal CTRL2 maintains the potential of the previous stage, which is at a high level, and controls the sixth transistor T6 and the eleventh transistor T11 to be cut off, such that the eleventh transistor T11 stops outputting the first power signal. The second clock signal is output to the gate of the fifth transistor T5 through the second transistor T2, controlling the fifth transistor T5 to be turned on. At this time, the sixth transistor T6 is cut off, and the first power signal cannot be transmitted to the first control terminal CTRL1 through the fifth transistor T5 and the sixth transistor T6, ensuring that the potential of the first control terminal CTRL1 is at a low level. At this time, the gate drive signal of the gate drive circuit is at a low level, realizing a shift output.

[0091] In the fifth stage t25, the input signal is at a high level, the first clock signal is at a low level, the second clock signal is at a high level, the first frequency control signal is at a low level, and the second frequency control signal is at a high level. The first transistor T1 and the seventh transistor T7 are turned on, and the second transistor T2 and the third transistor T3 are turned off. The first clock signal is transmitted through the first transistor T1 to the gates of the fourth transistor T4 and the ninth transistor T9, controlling the fourth transistor T4 and the ninth transistor T9 to be turned on. The fourth transistor T4 transmits the input signal to the first control terminal CTRL1, making the potential of the first control terminal CTRL1 at a high level, and controlling the eighth transistor T8 and the tenth transistor T10 to be turned off. At the same time, the ninth transistor T9 transmits the second power supply signal to the second control terminal CTRL2, making the potential of the second control terminal CTRL2 at a low level, and controlling the sixth transistor T6 and the eleventh transistor T11 to be turned on. The first power supply signal is output to the output terminal VOUT through the eleventh transistor T11. The second frequency control signal is transmitted through the seventh transistor T7 to the gate of the fifth transistor T5, making the gate of the fifth transistor T5 at a high level, and the fifth transistor T5 is turned off. At the same time, the second clock signal cannot be transmitted through the third transistor T3 to the tenth transistor T10, so that the tenth transistor T10 cannot output the second clock signal. At this time, the gate driving signal of the gate driving circuit is at a high level.

[0092] Based on the above technical solutions, when the working modes of the gate driving circuit include a first working mode and a second working mode, in the first working mode, the first frequency control signal and the second frequency control signal are the third power supply signal; in the second working mode, the frequency of the clock signal is greater than the frequencies of the first frequency control signal and the second frequency control signal.

[0093] Specifically, the clock signal may include a first clock signal and a second clock signal. In the first working mode, the first frequency control signal and the second frequency control signal can be set as the third power supply signal, and the third power supply signal is continuously at an effective level to control the frequency control module 110 to be able to continuously output clock signals, namely the first clock signal and the second clock signal. Exemplarily, when the frequency control module 110 includes a P-type first transistor, second transistor, and third transistor, the third power supply signal is continuously at a low level. In the second working mode, the frequencies of the first frequency control signal and the second frequency control signal can be set to be less than the frequencies of the first clock signal and the second clock signal according to the frequency requirement of the gate driving signal output by the gate driving circuit, so as to adjust the frequencies of the first clock signal and the second clock signal, thereby controlling the frequency of the gate driving signal output by the gate driving circuit.

[0094] It should be noted that when the low levels of the first frequency control signal and the second frequency control signal are valid levels, and the low levels of the first clock signal and the second clock signal are valid levels, the low levels of the first frequency control signal and the second frequency control signal can be less than the low levels of the first clock signal and the second clock signal, so that when the first clock signal and the second clock signal are at low levels, the first frequency control signal can ensure the effective conduction of the first transistor. Exemplarily, the low levels of the first frequency control signal and the second frequency control signal can be less than or equal to the sum of the second power supply signal and the threshold voltage of the transistor.

[0095] Based on the above technical solutions, in the second operating mode, the frequency of the clock signal is n times the frequencies of the first frequency control signal and the second frequency control signal; where n is an integer greater than 1.

[0096] Specifically, in the second operating mode, by setting the frequency of the clock signal to be n times the frequencies of the first frequency control signal and the second frequency control signal, at this time, the frequency adjustment module can control the frequencies of the first clock signal and the second clock signal output to the first control module, the second control module, and the output module according to the frequencies of the first frequency control signal and the second frequency control signal, so that the gate drive circuit can output a gate drive signal according to the frequencies of the first frequency control signal and the second frequency control signal, that is, the frequency of the gate drive signal output by the gate drive circuit is 1 / (2n - 1) times the frequencies of the first clock signal and the second clock signal. Exemplarily, the clock signal includes the first clock signal and the second clock signal. Figure 9 This is a timing simulation diagram when n = 2 provided by an embodiment of the present invention. Among them, sin is the timing of the input signal provided by the input signal terminal SIN, clk1 is the timing of the first clock signal provided by the first clock signal input terminal CLK1, clk2 is the timing of the second clock signal provided by the second clock signal input terminal CLK2, vout1 is the timing of the gate drive signal output by the output terminal VOUT of the gate drive circuit in the first operating mode, and vout2 is the timing of the gate drive signal output by the output terminal VOUT of the gate drive circuit in the second operating mode. As Figure 9 shown, when n = 2, in the first operating mode, the gate drive signal is output by shifting one clock cycle with respect to the input signal. At this time, the frequency of the gate drive signal is the same as the frequency of the clock signal. In the second operating mode, the gate drive signal is output by shifting three clock cycles with respect to the input signal. At this time, the frequency of the gate drive signal is 1 / 3 of the frequency of the clock signal.

[0097] An embodiment of the present invention also provides a gate driver. Figure 10 This is a schematic structural diagram of a gate driver provided by an embodiment of the present invention. As Figure 10As shown, the clock signal includes a first clock signal and a second clock signal; the gate driver includes multiple levels of gate driving circuits provided by any embodiment of the present invention; the first clock signal input terminal of the (2m + 1)-th level of the gate driving circuit is used to access the first clock signal, and the second clock signal input terminal of the (2m + 1)-th level of the gate driving circuit is used to access the second clock signal; the first clock signal input terminal of the 2(m + 1)-th level of the gate driving circuit is used to access the second clock signal, and the second clock signal input terminal of the 2(m + 1)-th level of the gate driving circuit is used to access the first clock signal; the first frequency control signal input terminal of the 2n-level gate driving circuit is used to sequentially input the first frequency control signal to the 2n-th frequency control signal; the second frequency control signal input terminal of the 2n-level gate driving circuit is used to sequentially input the second frequency control signal to the (2n + 1)-th frequency control signal; wherein, the first frequency control signal is multiplexed as the (2n + 1)-th frequency control signal; m is an integer greater than or equal to 0; the frequencies of the first clock signal and the second clock signal are n times the frequencies of the first frequency control signal and the second frequency control signal, and n is an integer greater than or equal to 1.

[0098] Specifically, Figure 10 FIG. shows a cascade schematic diagram of a multi-level gate driving circuit when n = 2. Among them, the first clock signal input terminal CLK1 of the odd levels accesses the first clock signal clk1, the second clock signal input terminal CLK2 of the odd levels accesses the second clock signal clk2, the first clock signal input terminal CLK1 of the even levels accesses the second clock signal clk2, and the second clock signal input terminal CLK2 of the even levels accesses the first clock signal clk1. The first frequency control signal input terminal CKA of the first level accesses the first frequency control signal ck1, the first frequency control signal input terminal CKA of the second level accesses the second frequency control signal ck2, the first frequency control signal input terminal CKA of the third level accesses the third frequency control signal ck3, the first frequency control signal input terminal CKA of the fourth level accesses the fourth frequency control signal ck4, the second frequency control signal input terminal CKB of the first level accesses the second frequency control signal ck2, the second frequency control signal input terminal CKB of the second level accesses the third frequency control signal ck3, the second frequency control signal input terminal CKB of the third level accesses the fourth frequency control signal ck4, and the second frequency control signal input terminal CKB of the fourth level accesses the first frequency control signal ck1. Thus, during the operation of the gate driving circuit, the cascade of the multi-level gate driving circuit can be realized according to the multiple relationship between the frequencies of the first frequency control signal and the second frequency control signal and the frequencies of the first clock signal clk1 and the second clock signal clk2, so that the gate driving circuit can output the gate driving signal according to the frequencies of the first frequency control signal and the second frequency control signal.

[0099] An embodiment of the present invention also provides a display panel,Figure 11 A structural schematic diagram of a display panel provided by an embodiment of the present invention. As Figure 11 shown, the display panel includes a pixel driving circuit 10 and a gate driver 20 provided by any embodiment of the present invention; the gate driver 20 is connected to the pixel driving circuit 10, and the gate driver 20 is used to provide a gate driving signal for the pixel driving circuit 10.

[0100] Specifically, the display panel may be, for example, an organic light emitting diode display panel, a liquid crystal display panel, or an electronic paper display panel, etc. The display panel may include multiple rows of pixel driving circuits 10 and gate drivers 20. The multiple-stage gate driving circuits in the gate driver 20 are respectively connected to at least one row of pixel driving circuits 10, and are used to provide gate driving signals for at least one row of pixel driving circuits 10.

[0101] An embodiment of the present invention also provides a display device. Figure 12 A structural schematic diagram of a display device provided by an embodiment of the present invention. As Figure 12 shown, the display device includes a display panel 1 provided by any embodiment of the present invention. The display device may be, for example, a mobile phone, a tablet computer, a smart wearable device, an information inquiry machine in a public place hall, etc. The display device includes a display panel 1 provided by any embodiment of the present invention, and its technical principle and technical effects are similar, which will not be elaborated here.

[0102] Note that the above is only a preferred embodiment of the present invention and the applied technical principle. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments may be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A gate driving circuit, characterized in that The operating modes of the gate driving circuit include at least two operating modes, and the gate driving circuit includes a frequency adjustment module, a first control module, a second control module, and an output module; The first control module is connected to the first control end of the output module and the second control module. The first control module is configured to output a first control signal according to an input signal, a clock signal, a first frequency control signal, a second frequency control signal, a first power supply signal, and a second control signal; The second control module is connected to the first control module and the second control end of the output module. The second control module is configured to output the second control signal according to the first control signal, the clock signal, and a second power supply signal; The frequency adjustment module is connected to the first control module, the second control module, and the output module. The frequency adjustment module is configured to control the frequency of the clock signal according to the first frequency control signal and the second frequency control signal; The output module is configured to output the first power supply signal or the clock signal according to the first control signal and the second control signal; wherein, the effective duration of the first frequency control signal and the second frequency control signal is greater than the pulse width of the clock signal, and the frequencies of the first frequency control signal and the second frequency control signal are different in different operating modes; The clock signal includes a first clock signal and a second clock signal; the frequency adjustment module includes a first adjustment unit and a second adjustment unit; The input end of the first adjustment unit is connected to the first clock signal input end. The output end of the first adjustment unit is connected to the first control module and the second control module. The control end of the first adjustment unit is connected to the first frequency control signal output end. The first adjustment unit is configured to control the frequency of the first clock signal provided by the first clock signal input end output to the first control module and the second control module according to the first frequency control signal provided by the first frequency control signal output end; The input end of the second adjustment unit is connected to the second clock signal input end. The output end of the second adjustment unit is connected to the first control module and the output module. The control end of the second adjustment unit is connected to the second frequency control signal output end. The second adjustment unit is configured to control the frequency of the second clock signal provided by the second clock signal input end output to the first control module and the output module according to the second frequency control signal provided by the second frequency control signal output end.

2. The gate driving circuit according to claim 1, wherein The first adjustment unit includes a first transistor, and the second adjustment unit includes a second transistor and a third transistor; The gate of the first transistor is connected to the first frequency control signal output end. The first pole of the first transistor is connected to the first clock signal input end. The second pole of the first transistor is connected to the first control module and the second control module; The gate of the second transistor and the gate of the third transistor are connected to the second frequency control signal output end, the first electrode of the second transistor and the first electrode of the third transistor are connected to the second clock signal input end, the second electrode of the second transistor is connected to the first control module, and the second electrode of the third transistor is connected to the output module.

3. The gate driving circuit according to claim 2, wherein A channel width-to-length ratio of the third transistor is greater than 1.

4. The gate driving circuit according to claim 2 or 3, characterized in that, The first control module includes an input unit, a node control unit and an error output control unit; The input unit is used to output the first control signal according to the input signal and the first clock signal, the node control unit is used to output the first control signal according to the second clock signal, the first power supply signal and the second control signal, and the error output control unit is used to control the node control unit and the input unit to output the first control signal in a time-sharing manner according to the first frequency control signal and the second frequency control signal.

5. The gate driving circuit according to claim 4, wherein The input unit includes a fourth transistor, the node control unit includes a fifth transistor and a sixth transistor, and the erroneous output control unit includes a seventh transistor; The gate of the fourth transistor is connected to the second electrode of the first transistor, the first electrode of the fourth transistor is connected to the input signal terminal, the second electrode of the fourth transistor is connected to the second electrode of the fifth transistor, the first control terminal and the second control module, the gate of the fifth transistor is connected to the second electrode of the second transistor, the first electrode of the fifth transistor is connected to the second electrode of the sixth transistor, the first electrode of the sixth transistor is connected to the first power supply signal input terminal, and the gate of the sixth transistor is connected to the second control terminal; the gate of the seventh transistor is connected to the first frequency control signal output terminal, the first electrode of the seventh transistor is connected to the second frequency control signal output terminal, and the second electrode of the seventh transistor is connected to the gate of the fifth transistor.

6. The gate driving circuit according to claim 5, wherein The second control module includes an eighth transistor and a ninth transistor; The gate of the eighth transistor is connected to the first control end, the first electrode of the eighth transistor and the gate of the ninth transistor are connected to the second electrode of the first transistor, the second electrode of the eighth transistor and the second electrode of the ninth transistor are connected to the second control end, and the first electrode of the ninth transistor is connected to the second power supply signal input end.

7. The gate driving circuit according to claim 6, wherein The output module includes a first output unit and a second output unit; The control end of the first output unit serves as the first control end, the input end of the first output unit is connected to the second electrode of the third transistor, the output end of the first output unit is connected to the output end of the second output unit, and serves as the output end of the gate drive circuit; the control end of the second output unit serves as the second control end, and the input end of the second output unit is connected to the first power signal input end.

8. The gate driving circuit according to claim 7, wherein The first output unit includes a tenth transistor and a first capacitor; a gate of the tenth transistor is connected to a first pole of the first capacitor and serves as the first control terminal, a first pole of the tenth transistor is connected to a second pole of the third transistor, and a second pole of the tenth transistor is connected to a second pole of the first capacitor and serves as an output terminal of the gate driving circuit; The second output unit includes an eleventh transistor and a second capacitor; a gate of the eleventh transistor is connected to a first pole of the second capacitor and serves as the second control terminal, a first pole of the eleventh transistor and a first pole of the second capacitor are connected to the first power signal input terminal, and a second pole of the eleventh transistor serves as an output terminal of the gate driving circuit.

9. The gate driving circuit according to claim 7, wherein The gate driving circuit further includes a twelfth transistor; a gate of the twelfth transistor is connected to the second power signal input terminal, and the first control module and the second control module are connected to the first control terminal through the twelfth transistor.

10. The gate driving circuit according to claim 1, wherein The working modes of the gate driving circuit include a first working mode and a second working mode. In the first working mode, the first frequency control signal and the second frequency control signal are the third power signal; in the second working mode, the frequency of the clock signal is greater than the frequencies of the first frequency control signal and the second frequency control signal.

11. The gate driving circuit according to claim 10, wherein In the second working mode, the frequency of the clock signal is n times the frequencies of the first frequency control signal and the second frequency control signal; where n is an integer greater than 1.

12. A gate driver, characterized in that, The clock signal includes a first clock signal and a second clock signal; the gate driver includes a plurality of gate driving circuits according to any one of claims 1-11; a first clock signal input terminal of the (2m + 1)-th stage gate driving circuit is used to access the first clock signal, and a second clock signal input terminal of the (2m + 1)-th stage gate driving circuit is used to access the second clock signal; a first clock signal input terminal of the 2(m + 1)-th stage gate driving circuit is used to access the second clock signal, and a second clock signal input terminal of the 2(m + 1)-th stage gate driving circuit is used to access the first clock signal; a first frequency control signal input terminal of the 2n-stage gate driving circuit is used to sequentially input the first frequency control signal to the 2n-th frequency control signal; a second frequency control signal input terminal of the 2n-stage gate driving circuit is used to sequentially input the second frequency control signal to the (2n + 1)-th frequency control signal; where the first frequency control signal is multiplexed as the (2n + 1)-th frequency control signal; m is an integer greater than or equal to 0; the frequencies of the first clock signal and the second clock signal are n times the frequencies of the first frequency control signal and the second frequency control signal, and n is an integer greater than or equal to 1.

13. A display panel, characterized in that, It includes a pixel driving circuit and the gate driver according to claim 12; the gate driver is connected to the pixel driving circuit, and the gate driver is used to provide a gate driving signal for the pixel driving circuit.

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