Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display panels, and specifically discloses a display panel and a display device. The display panel comprises a display area and a non-display area which at least partially surrounds the display area; the non-display area comprises a plurality of cascaded shift register units; the display area comprises a plurality of pixel units arranged in an array; each shift register unit comprises a first output end and a second output end; a first output signal output by the first output end is opposite in polarity to a second output signal output by the second output end; each pixel unit comprises a driving thin film transistor, an auxiliary thin film transistor and a pixel electrode; the driving thin film transistor and the auxiliary thin film transistor are connected to the pixel electrode respectively; the driving thin film transistor is controlled to be turned on or turned off by the first output signal of the corresponding shift register unit; and the auxiliary thin film transistor is controlled to be turned on or turned off by the second output signal of the corresponding shift register unit. The technical scheme provided by the application can improve the flicker problem of a liquid crystal display caused by a coupling voltage.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In a thin-film transistor liquid crystal display (TFT-LCD), the pixel circuit contains thin-film transistors (TFTs) connected to the pixel electrodes. The gate signal is connected to the gate of the TFT to control its on / off state; the data signal is connected to the drain of the TFT to write the desired data voltage to the TFT. When the TFT is on, the data voltage is transmitted through the drain to the source of the TFT and then through the pixel electrodes to the liquid crystal capacitor, adjusting the transmittance of the liquid crystal.

[0003] Because TFTs have parasitic capacitance Cgs, when the gate signal drops from high to low, a downward coupling voltage (feedthrough) is generated on the pixel electrode, causing flicker in the liquid crystal display. Existing technology compensates for feedthrough by adjusting the common voltage Vcom of the common electrode to improve flicker. However, this compensation method only compensates for a portion of the pixel units in the central display area and cannot compensate for the pixel units of the entire display panel. Summary of the Invention

[0004] This invention provides a display panel and display device to improve the flickering problem of liquid crystal displays caused by coupling voltage.

[0005] In a first aspect, embodiments of the present invention provide a display panel, comprising: a display area and a non-display area at least partially surrounding the display area; the non-display area includes cascaded shift register units; the display area includes pixel units arranged in an array;

[0006] The shift register unit includes a first output terminal and a second output terminal; the first output signal output from the first output terminal has the opposite polarity to the second output signal output from the second output terminal.

[0007] The pixel unit includes a driving thin-film transistor, an auxiliary thin-film transistor, and a pixel electrode; the driving thin-film transistor and the auxiliary thin-film transistor are respectively connected to the pixel electrode; the driving thin-film transistor is controlled to be turned on or off by a first output signal of the corresponding shift register unit; the auxiliary thin-film transistor is controlled to be turned on or off by a second output signal of the corresponding shift register unit.

[0008] Secondly, embodiments of the present invention provide a display device, the display device including a display panel provided in any embodiment of the present invention.

[0009] In this invention, the display panel shift register unit includes two output terminals, which output a first output signal and a second output signal with opposite polarities, respectively. Simultaneously, the pixel unit of the display panel is equipped with a driving thin-film transistor (TFT) and an auxiliary TFT, both connected to the pixel electrode. The driving TFT is controlled to turn on or off by the first output signal of its corresponding shift register unit, and the auxiliary TFT is controlled to turn on or off by the second output signal of its corresponding shift register unit. Therefore, when the driving TFT generates a coupling voltage to the pixel electrode, the auxiliary TFT generates a coupling voltage with opposite polarity between itself and the pixel electrode. This opposite-polarity coupling voltage compensates for the coupling voltage generated by the driving TFT, preventing display panel flicker caused by the coupling voltage and improving the uniformity of the panel display. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the structure of a pixel circuit in the prior art;

[0011] Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0012] Figure 3 This is a schematic diagram of the structure of a pixel unit provided in an embodiment of the present invention;

[0013] Figure 4 Timing diagrams of the first and second output signals provided for embodiments of the present invention;

[0014] Figure 5 This is a schematic diagram of the structure of a shift register unit provided in an embodiment of the present invention;

[0015] Figure 6 Another timing diagram of the first output signal and the second output signal provided in an embodiment of the present invention;

[0016] Figure 7 This is a schematic diagram of the structure of an inverter unit provided in an embodiment of the present invention;

[0017] Figure 8 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention;

[0018] Figure 9 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0019] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0020] Figure 1 This is a schematic diagram of the pixel circuit structure in the prior art. For example... Figure 1 As shown, the pixel circuit includes a driving transistor TFT', a liquid crystal capacitor CLc, and a storage capacitor Cst. The liquid crystal capacitor CLc consists of a pixel electrode and a common electrode. After the scan signal Gate is turned on, the data signal Source charges the pixel electrode. Because TFT' has a registered capacitance, when the scan signal Gate drops from a high level to a low level, it generates a downward coupling voltage (feedthrough) on the pixel electrode. Existing technology compensates for feedthrough by adjusting the common electrode voltage Vcom, thereby improving flicker. However, Vcom can mainly compensate for the central display area and cannot compensate for the entire panel. In the process of implementing the present invention, the inventors discovered that because there is a voltage drop (RC-loading) on ​​the scan lines of the display panel, the feedthrough of the pixel circuits connected to the near end of the scan line is different from that of the pixel circuits connected to the far end. In addition, the liquid crystal capacitance in different areas also varies. Therefore, adjusting Vcom to a fixed value to compensate for the entire panel individually will result in inconsistent compensation voltages in different areas of the display panel, and flicker will still exist, making the panel uniformity poor. Especially when the display panel size is large, the flicker is more obvious and seriously affects the image quality.

[0021] To address the aforementioned flickering problem, embodiments of the present invention provide a display panel, comprising: a display area and a non-display area at least partially surrounding the display area; the non-display area includes cascaded shift register units; the display area includes pixel units arranged in an array.

[0022] The shift register unit includes a first output terminal and a second output terminal; the first output signal output from the first output terminal has the opposite polarity to the second output signal output from the second output terminal;

[0023] The pixel unit includes a driving thin-film transistor, an auxiliary thin-film transistor, and a pixel electrode; the driving thin-film transistor and the auxiliary thin-film transistor are respectively connected to the pixel electrode; the driving thin-film transistor is controlled to be turned on or off by a first output signal of the corresponding shift register unit; the auxiliary thin-film transistor is controlled to be turned on or off by a second output signal of the corresponding shift register unit.

[0024] In this embodiment of the invention, the display panel shift register unit includes two output terminals, which output a first output signal and a second output signal with opposite polarities, respectively. Simultaneously, the pixel unit of the display panel is provided with a driving thin-film transistor and an auxiliary thin-film transistor, both connected to the pixel electrode. The driving thin-film transistor is controlled to be turned on or off by the first output signal of the corresponding shift register unit, and the auxiliary thin-film transistor is controlled to be turned on or off by the second output signal of the corresponding shift register unit. Therefore, when the driving thin-film transistor generates a coupling voltage to the pixel electrode, the auxiliary thin-film transistor generates a coupling voltage with opposite polarity between itself and the pixel electrode. This opposite-polarity coupling voltage can compensate for the coupling voltage generated by the driving thin-film transistor, avoiding display panel flicker caused by the coupling voltage and improving the uniformity of the panel display. The above is the core idea of ​​this invention. The technical solutions in this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0025] Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of a pixel unit structure provided in an embodiment of the present invention. Figure 2 and Figure 3As shown, the display panel includes a display area AA and a non-display area NA that at least partially surrounds the display area AA. The non-display area NA forms a multi-level cascaded shift register unit 11. The display area AA includes pixel units 12 arranged in an array. The shift register unit 11 includes two output terminals: a first output terminal Gout1 and a second output terminal Gout2. The first output terminal Gout1 outputs a first output signal U1, and the second output terminal Gout2 outputs a second output signal U2. The first output signal U1 and the second output signal U2 have opposite polarities. The pixel unit 12 includes a driving thin-film transistor T1, an auxiliary thin-film transistor T2, and a pixel electrode 121 (one of the electrodes of a liquid crystal capacitor CLc). The driving thin-film transistor T1 is controlled to switch by the first output signal U1, and the auxiliary thin-film transistor T2 is controlled to switch by the second output signal U2. Because the first output signal U1 and the second output signal U2 have opposite polarities, when the control terminal of the driving thin-film transistor T1 generates a downward coupling voltage D1 (the coupling voltage points from the control terminal of the driving thin-film transistor T1 to the pixel electrode), the control terminal of the auxiliary thin-film transistor T2 generates an upward coupling voltage D2 (the coupling voltage points from the pixel electrode to the control terminal of the driving thin-film transistor T1) on the pixel electrode. The coupling voltages D1 and D2, due to their different polarities, cancel each other out, effectively preventing voltage jumps in the pixel electrode during operation, improving the flicker problem of the pixel unit 12 and even the entire display panel, and enhancing the display uniformity of the entire display panel. It should be noted that in this embodiment, each pixel unit 12 individually compensates and corrects the coupling voltage of its own pixel electrode, ensuring that each pixel unit 12 does not flicker, thus preventing flickering of the entire display panel. Compensation is not required by adjusting the common electrode voltage Vcom, thus eliminating the need to consider the inconsistency in coupling voltage between far and near pixel units caused by the voltage drop (RC-loading) of the scan line, nor the inconsistency in compensation voltage caused by differences in liquid crystal capacitance in different areas. It effectively improves the problem of poor panel uniformity and enhances panel image quality.

[0026] like Figure 3As shown, optionally, the display panel may further include: a common electrode 122; the common electrode 122 is connected to a common voltage Vcom; the common electrode 122 and the pixel electrode 121 have a facing area, thus the common electrode 122 and the pixel electrode 121 form a capacitor, namely, the aforementioned liquid crystal capacitor CLc. The liquid crystal capacitor CLc can control the liquid crystal flipping of the liquid crystal layer of the display panel, thereby controlling the light emission of the display panel. Feedthrough is the coupling voltage generated by the control terminal of the driving thin film transistor T1 to the pixel electrode 121. In this embodiment, an auxiliary thin film transistor T2 generates a coupling voltage in the opposite direction to the pixel electrode 121, thereby avoiding the flickering problem caused by the parasitic capacitance between the control terminal and the source of the driving thin film transistor T1.

[0027] Optionally, the gate layers of driving thin-film transistor T1 and auxiliary thin-film transistor T2 are arranged in the same layer; the active layers of driving thin-film transistor T1 and auxiliary thin-film transistor T2 are arranged in the same layer; and the source and drain layers of driving thin-film transistor T1 and auxiliary thin-film transistor T2 are arranged in the same layer. In the panel structure, the thin-film transistor includes a gate layer, an active layer, and a source and drain layer. In this embodiment, the gate layers of driving thin-film transistor T1 and auxiliary thin-film transistor T2 are fabricated in the same layer using the same process, the active layers are fabricated in the same layer using the same process, and the source and drain layers are fabricated in the same layer using the same process. Therefore, the entire device of driving thin-film transistor T1 and auxiliary thin-film transistor T2 is fabricated using the same process, so the register capacitance between their control terminals and pixel electrodes 121 is the same. This makes the downward coupling voltage D1 generated by driving thin-film transistor T1 the same in magnitude but opposite in direction as the upward coupling voltage D2 generated by auxiliary thin-film transistor T2. Thus, the coupling voltage D2 and the coupling voltage D1 cancel each other out. This embodiment can completely compensate for the coupling voltage generated by driving thin-film transistor T1, improving the uniformity of the display panel.

[0028] Optional, continue to refer to Figure 2 The display panel may further include: a first scan line 131 and a second scan line 132 extending along a first direction X; the first scan line 131 is connected to the first output terminal Gout1 of the corresponding shift register unit 11, and is used to transmit the first output signal U1 to the control terminal of the driving thin film transistor T1 of the corresponding pixel unit 12; the second scan line 132 is connected to the second output terminal Gout2 of the corresponding shift register unit 11, and is used to transmit the second output signal U2 to the control terminal of the auxiliary thin film transistor T2 of the corresponding pixel unit 12.

[0029] Because the shift register unit 11 in this embodiment includes two output terminals, each shift register unit 11 can be configured with two scan lines. The first scan line 131 is used to transmit the first output signal U1 output from the first output terminal Gout1 to the corresponding pixel unit 12, and the second scan line 132 is used to transmit the second output signal U2 output from the second output terminal Gout2 to the corresponding pixel unit 12. The first output signal U1 is used to control the on and off states of the driving thin-film transistor T1 of the pixel unit 12, and the second output signal U2 is used to control the on and off states of the auxiliary thin-film transistor T2 of the pixel unit 12. The polarities of the first output signal U1 and the second output signal U2 are opposite, causing the coupling voltage D1 generated by the control terminal of the driving thin-film transistor T1 to the pixel electrode to cancel each other out with the coupling voltage D2 generated by the control terminal of the auxiliary thin-film transistor T2 to the pixel electrode, effectively avoiding the flickering problem of the display panel.

[0030] Optional, continue to refer to Figure 2 and Figure 3 The display panel may further include: a data line 14 extending along a second direction Y; the second direction Y intersects with the first direction X; the data line 14 is connected to the first end of the driving thin film transistor T1 of the corresponding pixel unit 12 for transmitting data signals to the driving thin film transistor T1; the second end of the driving thin film transistor T1 is connected to the pixel electrode 121; the first end and the second end of the auxiliary thin film transistor T2 are both connected to the pixel electrode 121.

[0031] In this embodiment, the first terminal of the driving thin-film transistor T1 is connected to the data line 14 to transmit data signals to the pixel electrode 121. The auxiliary thin-film transistor T2 does not need to transmit signals in the pixel unit 12, so its first and second terminals are simply connected. When the scan line 13 outputs a first output signal U1 and a second output signal U2 with opposite polarities, if the first output signal U1 changes from high to low, the second output signal U2 changes from low to high. The pixel electrode 121 will then receive a coupling voltage D1 generated by the control terminal of the driving thin-film transistor T1, and a coupling voltage D2 generated by the control terminal of the auxiliary thin-film transistor T2, which is opposite in direction to the coupling voltage D1. Since the coupling voltages D1 and D2 are of the same magnitude, they can completely cancel each other out, thereby compensating for feedthrough and improving panel uniformity.

[0032] Specifically, Figure 4 Timing diagrams of the first and second output signals provided for embodiments of the present invention. (See diagram below.) Figure 3 and Figure 4As shown, the first output signal U1 is used to turn on the driving thin-film transistor T1 of the pixel electrode 121. After the first output signal U1 turns on the driving thin-film transistor T1, the data signal charges the pixel electrode 121 through the driving thin-film transistor T1. When the first output signal U1 is pulled down from the high level VGH to the low level VGL, a downward coupling voltage D1 is generated on the pixel electrode 121. At the same time, the second output signal U2 of the auxiliary thin-film transistor T2 control terminal is pulled up from the low level VGL to the high level VGH, generating an upward coupling voltage.

[0033] D1 = (VGH - VGL) * Cgs_A / (Cgs_A + Clc + Cst), D2 = |VGL - VGH| * Cgs_B / (Cgs_B + Clc + Cst). In this embodiment, the driving thin-film transistor T1 and the auxiliary thin-film transistor T2 can be fabricated using the same process. The parasitic capacitance Cgs_A = Cgs_B, which is offset by D2 to compensate for D1 and the feedthrough voltage. This ensures a better display regardless of whether the scan line is near, far, or in other areas, avoiding flickering and improving the uniformity of the entire panel.

[0034] Continue to refer to Figure 3 Optionally, pixel unit 12 may further include: a storage capacitor Cst; the first terminal of the storage capacitor Cst is connected to the second terminal of the driving thin-film transistor T1 and the second terminal of the auxiliary thin-film transistor T2 respectively; the second terminal of the storage capacitor Cst is connected to a common voltage Vcom. The coupling voltage D2 generated by the auxiliary thin-film transistor T2, which is opposite to the coupling voltage D1, can also compensate for the feedthrough generated by the storage capacitor Cst, avoiding fluctuations in the data signal stored in the storage capacitor Cst, thereby preventing flickering of the display panel during the data holding period of a frame, and improving the image quality of the display panel, especially large-size display panels.

[0035] Optionally, the polarity of the conduction signals of the driving thin-film transistor T1 and the auxiliary thin-film transistor T2 is the same. In this embodiment, the driving thin-film transistor T1 and the auxiliary thin-film transistor T2 are the same type of switching transistor. For example, both the driving thin-film transistor T1 and the auxiliary thin-film transistor T2 are N-type transistors, or both are P-type transistors. This embodiment illustrates the example where both the driving thin-film transistor T1 and the auxiliary thin-film transistor T2 are P-type transistors. When the driving thin-film transistor T1 and the auxiliary thin-film transistor T2 are the same type of switching transistor, their conduction signal polarity is the same; for example, if they are both P-type transistors, then their conduction signal is low. When the control signal of the driving thin-film transistor T1 is low, the control signal of the auxiliary thin-film transistor T2 is high, so the auxiliary thin-film transistor T2 is turned off and will not affect the charging of the pixel electrode 121 by the driving thin-film transistor T1. When the control signal of the driving thin-film transistor T1 is high, the control signal of the auxiliary thin-film transistor T2 is low, so the auxiliary thin-film transistor T2 is turned on. However, because the first and second terminals of the auxiliary thin-film transistor T2 are connected, the auxiliary thin-film transistor T2 will not charge the pixel electrode 121. Therefore, the auxiliary thin-film transistor T2 will not affect the charging and discharging process of the pixel unit 12. Furthermore, the coupling voltage generated by the thin-film transistor on the pixel electrode occurs at the transition time of the first output signal U1 and the second output signal U2. In this embodiment, the transition time of the first output signal U1 and the second output signal U2 is set to coincide, thereby eliminating the coupling voltage and effectively avoiding the panel flicker problem.

[0036] Figure 5 This is a schematic diagram of a shift register unit provided in an embodiment of the present invention. Optionally, the shift register unit 11 may include: an inverter unit 111; the input terminal of the inverter unit 111 is connected to the first output terminal Gout1 of the shift register unit 11, and is used to invert the first output signal U1 into a second output signal U2.

[0037] In this embodiment, there are many ways to provide a first output signal U1 and a second output signal U2 with opposite polarities. For example, the shift register unit 11 can simultaneously form a first output signal U1 and a second output signal U2 with opposite polarities. Specifically, the shift register unit 11 forms the first output signal U1 by passing the input signal through N devices, and the shift register unit 11 also forms the second output signal U2 by passing the input signal through N devices. Since both the first output signal U1 and the second output signal U2 are formed by passing the input signal through the same devices, the transition times of the first output signal U1 and the second output signal U2 are the same, with no time delay. Figure 4As shown, the transition times t11 of the first output signal U1 and the second output signal U2 coincide, with no time difference. For example, if an inverter unit 111 is connected after the first output terminal Gout1 of the shift register unit 11, then the first output signal U1 is inverted to form the second output signal U2, resulting in... Figure 6 The timing diagram shown is as follows. Figure 6 This is another timing diagram of the first output signal and the second output signal provided in an embodiment of the present invention. Because the second output signal U2 is formed by the first output signal U1 through the inverter unit 111, the transition time t13 of the second output signal U2 is delayed after the transition time t12 of the first output signal U1.

[0038] Figure 7 This is a schematic diagram of an inverter unit provided in an embodiment of the present invention. Optionally, the inverter unit may include: a first pull-up subunit 112 and a first pull-down subunit 113; the control terminals of the first pull-up subunit 112 and the first pull-down subunit 113 are both connected to the first output terminal Gout1 of the shift register unit 11; the first terminal of the first pull-up subunit 112 is connected to a first power signal VGH; the second terminal of the first pull-up subunit 112 is connected to the second output terminal Gout2 of the shift register unit 11; the first terminal of the first pull-down subunit 113 is connected to a second power signal VGL; the second terminal of the first pull-down subunit 113 is connected to the second output terminal Gout2 of the shift register unit 11.

[0039] The first output signal U1 output at the first output terminal Gout1 is used to control the first pull-up sub-unit 112 and the first pull-down sub-unit 113. When the first output signal U1 is high, the first pull-down sub-unit 113 outputs the second power signal VGL to the second output terminal Gout2 to form the second output signal U2. When the first output signal U1 is low, the first pull-up sub-unit 112 outputs the first power signal VGH to the second output terminal Gout2 to form the second output signal U2. Optionally, in this embodiment, the high level of the first output signal U1 can be the same as the first power signal VGH, and the low level of the first output signal U1 can be the same as the second power signal VGL, so that the polarities of the first output signal U1 and the second output signal U2 are opposite, further compensating for feedthrough and eliminating panel flicker problems.

[0040] Continue to refer to Figure 7Optionally, the first pull-up subunit 112 may include a first thin-film transistor T3; the first pull-down subunit 113 may include a second thin-film transistor T4; the control terminal of the first thin-film transistor T3 is the control terminal of the first pull-up subunit; the first terminal of the first thin-film transistor T3 is the first terminal of the first pull-up subunit 112; the second terminal of the first thin-film transistor T3 is the second terminal of the first pull-up subunit 112; the control terminal of the second thin-film transistor T4 is the control terminal of the first pull-down subunit 113; the first terminal of the second thin-film transistor T4 is the first terminal of the first pull-down subunit 113; the second terminal of the second thin-film transistor T4 is the second terminal of the first pull-down subunit 113; the polarity of the conduction signal of the first thin-film transistor T3 is opposite to that of the conduction signal of the second thin-film transistor T4. To ensure that only one of the first thin-film transistors (TFTs) T3 and T4 is turned on when the first output signal U1 at the first output terminal Gout1 is high or low, the polarity of the turn-on signal of the first TFT T3 is opposite to that of the second TFT T4. That is, the first TFT T3 and the second TFT T4 are different types of switching transistors. For example, the first TFT T3 is an N-type transistor and the second TFT T4 is a P-type transistor; or, the first TFT T3 is a P-type transistor and the second TFT T4 is an N-type transistor.

[0041] Figure 8 This is a schematic diagram of another shift register unit provided in an embodiment of the present invention. Optionally, the shift register unit 11 may further include: a trigger write unit 116, a power supply unit 114, and a first output adjustment unit 115; the trigger write unit 116 is used to write a trigger signal SIN to a first node N1 according to a first clock signal SCK1; the power supply unit 114 is used to write a second power signal VGL to a second node N2 according to the first clock signal SCK1; the first output adjustment unit 115 is used to adjust the first output signal U1 of the first output terminal Gout1 of the shift register unit 11 according to the first power signal VGH, the second clock signal SCK2, the trigger signal SIN of the first node N1, and the second power signal VGL of the second node N2.

[0042] The shift register unit can output the trigger signal SIN after a set delay. That is, the first output signal U1 of the first output terminal Gout1 of the shift register unit is the shift signal of the trigger signal SIN. Specifically, the trigger writing module 116 can write the trigger signal SIN to the first node N1 according to the first clock signal SCK1. The second node N2 is controlled by the power supply unit 114. Under the control of the first clock signal SCK1, the power supply unit 114 writes the second power signal VGL to the second node N2. The first clock signal SCK1 and the second clock signal SCK2 can be inverted signals. That is, when the first clock signal SCK1 is low, the second clock signal SCK2 is high, and when the first clock signal SCK1 is high, the second clock signal SCK2 is low. The first power signal VGH and the second power signal VGL are opposite signals. For example, when the second power signal VGL is low, the first power signal VGH is high. GH is high level; the first output adjustment unit 115 can output a first power signal VGH or a second clock signal SCK2. For example, when the potential of the first node N1 enables the first output adjustment unit 115, the first output terminal of the shift register unit outputs the second clock signal SCK2; when the potential of the second node N2 enables the first output adjustment unit 115, the first output terminal of the shift register unit outputs the first power signal VGH; through the coordinated control of the first clock signal SCK1 and the second clock signal SCK2, the first output signal U1 of the first output terminal Gout1 of the shift register unit is equivalent to the trigger signal SIN to generate a shift; the first output signal U1 of the first output terminal of the shift register unit can be used as the scanning signal of the pixel unit in the display panel. The second output terminal Gout2 of the shift register unit outputs a second output signal U2. The polarity of the second output signal U2 is opposite to that of the first output signal U1, so that the coupling voltage D2 generated by the control terminal of the auxiliary thin film transistor T2 to the pixel electrode cancels out the coupling voltage D1 generated by the control terminal of the driving thin film transistor T1 to the pixel electrode, effectively avoiding the flickering problem of the display panel and improving the uniformity of the entire panel.

[0043] This invention also provides a display device. Figure 9 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 9 As shown, the display device provided in this embodiment of the invention includes the display panel 100 described in any embodiment of the invention. The display device can be as follows: Figure 9 The mobile phone shown can also be a computer, television, smart wearable device, etc., and this embodiment does not make any special limitation on it.

[0044] The display device provided in the embodiments of the present invention includes the technical features of the display panel provided in any embodiment of the present invention, and has the beneficial effects of the corresponding technical features, which will not be repeated here.

[0045] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized by, The display panel comprises: a display area and a non-display area at least partially surrounding the display area; the non-display area comprises a plurality of cascaded shift register units; the display area comprises an array of pixel units; the shift register unit comprises a first output end and a second output end; a first output signal output by the first output end is opposite in polarity to a second output signal output by the second output end; the pixel unit comprises a driving thin film transistor, an auxiliary thin film transistor and a pixel electrode; the driving thin film transistor and the auxiliary thin film transistor are respectively connected to the pixel electrode; the driving thin film transistor is controlled to be turned on or turned off by the first output signal of the corresponding shift register unit; the auxiliary thin film transistor is controlled to be turned on or turned off by the second output signal of the corresponding shift register unit; the driving thin film transistor and the auxiliary thin film transistor are the same type of switch; the first end and the second end of the auxiliary thin film transistor are electrically connected and electrically connected to the pixel electrode.

2. The display panel of claim 1, wherein, Further comprising: a first scan line and a second scan line extending in a first direction; the first scan line is connected to the first output end of the corresponding shift register unit, for transmitting the first output signal to the control end of the driving thin film transistor of the corresponding pixel unit; the second scan line is connected to the second output end of the corresponding shift register unit, for transmitting the second output signal to the control end of the auxiliary thin film transistor of the corresponding pixel unit.

3. The display panel of claim 1, wherein, Further comprising: a data line extending in a second direction; the second direction intersects the first direction; the data line is connected to the first end of the driving thin film transistor of the corresponding pixel unit, for transmitting a data signal to the driving thin film transistor; the second end of the driving thin film transistor is connected to the pixel electrode; the first end and the second end of the auxiliary thin film transistor are both connected to the pixel electrode.

4. The display panel of claim 3, wherein, Further comprising: a common electrode; the common electrode is connected to a common voltage; the common electrode and the pixel electrode have a facing area.

5. The display panel of claim 4, wherein, The pixel unit further comprises a storage capacitor; the first end of the storage capacitor is connected to the second end of the driving thin film transistor and the second end of the auxiliary thin film transistor respectively; the second end of the storage capacitor is connected to the common voltage.

6. The display panel of claim 1, wherein, The driving thin film transistor and the auxiliary thin film transistor have the same polarity of the conduction signal.

7. The display panel of claim 1, wherein: the gate layers of the driving thin film transistor and the auxiliary thin film transistor are provided in the same layer; the active layers of the driving thin film transistor and the auxiliary thin film transistor are provided in the same layer; the source / drain layers of the driving thin film transistor and the auxiliary thin film transistor are provided in the same layer.

8. The display panel of claim 1, wherein, The shift register unit comprises an inverter unit; the input end of the inverter unit is connected to the first output end of the shift register unit, for inverting the first output signal into the second output signal.

9. The display panel of claim 8, wherein, The inverter unit comprises a first pull-up sub-unit and a first pull-down sub-unit; the control ends of the first pull-up sub-unit and the first pull-down sub-unit are both connected to the first output end of the shift register unit; The first end of the first pull-up sub-unit is connected to a first power supply signal; the second end of the first pull-up sub-unit is connected to the second output end of the shift register unit; the first end of the first pull-down sub-unit is connected to a second power supply signal; and the second end of the first pull-down sub-unit is connected to the second output end of the shift register unit.

10. The display panel of claim 9, wherein, The first pull-up sub-unit comprises a first thin film transistor; and the first pull-down sub-unit comprises a second thin film transistor. The control end of the first thin film transistor is the control end of the first pull-up sub-unit; the first end of the first thin film transistor is the first end of the first pull-up sub-unit; the second end of the first thin film transistor is the second end of the first pull-up sub-unit; the control end of the second thin film transistor is the control end of the first pull-down sub-unit; the first end of the second thin film transistor is the first end of the first pull-down sub-unit; and the second end of the second thin film transistor is the second end of the first pull-down sub-unit. The conduction signal of the first thin film transistor is opposite in polarity to the conduction signal of the second thin film transistor.

11. The display panel of claim 8, wherein, The shift register unit further comprises a trigger writing unit, a power supply introduction unit and a first output adjusting unit. The trigger writing unit is configured to write a trigger signal to a first node according to a first clock signal; and the power supply introduction unit is configured to write a second power supply signal to a second node according to the first clock signal. The first output adjusting unit is configured to adjust a first output signal of a first output end of the shift register unit according to a first power supply signal, a second clock signal, the trigger signal of the first node and the second power supply signal of the second node.

12. A display device, characterized by comprising: The display panel comprises any one of the display panels of claims 1-11.

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