Method of forming a semiconductor structure
By modifying the height of the semiconductor structure, the problem of device height uniformity in different regions is solved, and the performance of the semiconductor structure is improved, especially the height uniformity and top surface flatness of the device gate structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2022-05-10
- Publication Date
- 2026-07-24
Smart Images
Figure CN117080166B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology
[0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance towards smaller process nodes, enabling integrated circuits to develop in the direction of smaller size, higher circuit precision, and higher circuit complexity.
[0003] In the development of integrated circuits, the functional density (i.e. the number of interconnects in each chip) usually increases gradually while the geometric size (i.e. the smallest component size that can be produced by process steps) gradually decreases, which correspondingly increases the difficulty and complexity of integrated circuit manufacturing.
[0004] Currently, with the technology nodes constantly shrinking, improving the high consistency of devices in different regions of a wafer has become a challenge. Summary of the Invention
[0005] The problem addressed by the embodiments of the present invention is to provide a method for forming a semiconductor structure, thereby improving the performance of the semiconductor structure.
[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region, a gate structure formed on the top of the substrate, an interlayer dielectric material layer formed on the exposed portion of the gate structure, the interlayer dielectric material layer covering the top and sidewalls of the gate structure, the width of the gate structure in the first region being smaller than the width of the gate structure in the second region; using the top of the gate structure as a stop position, performing a first planarization process on the interlayer dielectric material layer above the top of the gate structure, the remaining interlayer dielectric material layer serving as an interlayer dielectric layer, the top of the interlayer dielectric layer being flush with the top of the gate structure; and performing the following steps: After the first planarization process, a height correction process is performed on the gate structure and the interlayer dielectric layer, so that the height of the gate structure and the interlayer dielectric layer in the second region is greater than the height of the gate structure and the interlayer dielectric layer in the first region. After the height correction process, the gate structure is removed, and a gate opening is formed in the interlayer dielectric layer. A device gate material layer is formed in the gate opening, and the device gate material layer also covers the top of the interlayer dielectric layer. A second planarization process is performed on the device gate material layer and the interlayer dielectric layer, so that the remaining device gate material layers in the first region and the second region both reach the same target height. The remaining device gate material layer after the second planarization process serves as the device gate structure.
[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0008] This invention provides a method for forming a semiconductor structure. The method involves performing a height correction process on the gate structure and interlayer dielectric layer, making the height of the gate structure and interlayer dielectric layer in the second region greater than the height of the gate structure and interlayer dielectric layer in the first region. Specifically, before forming the device gate structure, a height correction process is performed on the gate structure and interlayer dielectric layer in both the first and second regions, creating a height difference between them. Since the width of the gate structure in the first region is smaller than the width of the gate structure in the second region, this difference is mitigated during the subsequent second planarization process of the device gate material layer and interlayer dielectric layer. The contact area between the device gate material layer in the first region and the planarization device is smaller than that in the second region. This results in a lower removal rate of the device gate material layer in the first region compared to the second region. Therefore, the height difference obtained through the height correction process can compensate for the difference in removal rates between the two regions. This facilitates making the height of the device gate material layer in the second region equal to that in the first region within the same time frame during the second planarization process. This improves the height uniformity and top surface flatness of the device gate structure in both regions, thereby enhancing the performance of the semiconductor structure. Attached Figure Description
[0009] Figures 1 to 7 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0010] Figures 8 to 17 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure fabrication method of the present invention. Detailed Implementation
[0011] Currently, the performance of semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using one method for forming a semiconductor structure as an example. Figures 1 to 7 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0012] refer to Figure 1A substrate 10 is provided, the substrate 10 including a first region 100a and a second region 100b, a gate structure 11 is formed on the top of the substrate 10, and the width of the gate structure 11 in the first region 100a is smaller than the width of the gate structure 11 in the second region 100b in a direction perpendicular to the extension direction of the gate structure 11. An etch stop layer 12 is formed on the top and sidewalls of the gate structure 11 and on the substrate 10 where the gate structure 11 is exposed.
[0013] refer to Figure 2 A sacrificial layer 13 is formed between adjacent gate structures 11, the sacrificial layer 13 covering a portion of the sidewall of the etch stop layer 12.
[0014] refer to Figure 3 Remove the sacrificial layer 13 to expose the etch stop layer 12.
[0015] refer to Figure 4 After removing the etch stop layer 12 exposed by the sacrificial layer 13, the sacrificial layer 13 is removed, and an interlayer dielectric layer 15 is formed between adjacent gate structures 11. The top of the interlayer dielectric layer 15 is flush with the top of the etch stop layer 12 in the first region 100a.
[0016] refer to Figure 5 Remove the gate structure 11 and form a gate opening 16 in the interlayer dielectric layer 15.
[0017] refer to Figure 6 A device gate structure 17 is formed in the gate opening 16.
[0018] refer to Figure 7 After forming the device gate structure 17, the device gate structure 17 and the interlayer dielectric layer 15 are planarized.
[0019] Research revealed that before planarizing the device gate structure 17 and the interlayer dielectric layer 15, since the heights of the device gate structure 17 and the interlayer dielectric layer 15 in the first region 100a are the same as those in the second region 100b, correspondingly, during the planarization process, the contact surface between the device gate structure 17 in the first region 100a and the planarization device... The area is smaller than the contact area between the device gate structure 17 in the second region 100b and the planarization device, causing the removal rate of the device gate structure 17 in the first region 100a to be less than the removal rate of the device gate structure 17 in the second region 100b. This results in a height difference between the device gate structure 17 in the first region 100a and the device gate structure 17 in the second region 100b, reducing the height consistency between the device gate structure 17 in the first region 100a and the device gate structure 17 in the second region 100b, thereby affecting the performance of the semiconductor structure.
[0020] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region, a gate structure formed on the top of the substrate, an interlayer dielectric material layer formed on the exposed portion of the gate structure, the interlayer dielectric material layer covering the top and sidewalls of the gate structure, the width of the gate structure in the first region being smaller than the width of the gate structure in the second region; using the top of the gate structure as a stop position, performing a first planarization process on the interlayer dielectric material layer above the top of the gate structure, the remaining interlayer dielectric material layer serving as an interlayer dielectric layer, the top of the interlayer dielectric layer being flush with the top of the gate structure; and performing... After the first planarization process, the gate structure and interlayer dielectric layer are height-corrected to make the height of the gate structure and interlayer dielectric layer in the second region greater than the height of the gate structure and interlayer dielectric layer in the first region. After the height correction process, the gate structure is removed, and a gate opening is formed in the interlayer dielectric layer. A device gate material layer is formed in the gate opening, and the device gate material layer also covers the top of the interlayer dielectric layer. The device gate material layer and interlayer dielectric layer are then subjected to a second planarization process, so that the remaining device gate material layers in both the first and second regions reach the same target height. The remaining device gate material layer after the second planarization process serves as the device gate structure.
[0021] In the scheme disclosed in this embodiment of the invention, the gate structure and interlayer dielectric layer are height-corrected to make the height of the gate structure and interlayer dielectric layer in the second region greater than the height of the gate structure and interlayer dielectric layer in the first region. That is, before forming the device gate structure, the gate structure and interlayer dielectric layer in the first region, as well as the gate structure and interlayer dielectric layer in the second region, are height-corrected to create a height difference between the gate structure in the first region and the gate structure in the second region. Since the width of the gate structure in the first region is smaller than the width of the gate structure in the second region, during the subsequent second planarization process of the device gate material layer and interlayer dielectric layer, the first region... The contact area between the device gate material layer in the first region and the planarization device is smaller than that in the second region, causing the removal rate of the device gate material layer in the first region to be lower than that in the second region. Therefore, the height difference obtained by the height correction process can compensate for the difference in removal rates between the two regions. This is beneficial because during the second planarization process, the height of the device gate material layer in the second region can be made equal to that in the first region within the same time frame. This improves the height uniformity and top surface flatness of the device gate structure in the first and second regions, thereby enhancing the performance of the semiconductor structure.
[0022] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0023] Figures 8 to 17 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure fabrication method of the present invention.
[0024] refer to Figure 8 A substrate is provided, the substrate including a first region 100a and a second region 100b, a gate structure 105 is formed on the top of the substrate, and an interlayer dielectric material layer 107 is formed on the exposed part of the gate structure 105 on the substrate, the interlayer dielectric material layer 107 covering the top and sidewalls of the gate structure 105, and the width of the gate structure 105 in the first region 100a is smaller than the width of the gate structure 105 in the second region 100b.
[0025] The substrate is used to provide a process platform for subsequent process manufacturing.
[0026] In this embodiment, the substrate is used to form a fin field-effect transistor (FinFET). The substrate includes a substrate 100 and fins 101 protruding from the substrate 100.
[0027] In this embodiment, the substrate 100 is a silicon substrate 100. In other embodiments, the material of the substrate 100 may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, etc. The substrate 100 may also be a silicon substrate on an insulator 100 or a germanium substrate on an insulator, etc., other types of substrate 100.
[0028] In this embodiment, the material of the fin 101 is the same as the material of the substrate 100, and the material of the fin 101 is silicon. In other embodiments, the material of the fin 101 may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.
[0029] In this embodiment, the sidewalls of the gate structure 105 are also formed with sidewalls.
[0030] The sidewall is used to protect the sidewalls of the subsequently formed device gate structure. The sidewall can be a single-layer structure or a multi-layer structure, and the material of the sidewall includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxycarbonate, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall is a single-layer structure, and the material of the sidewall is silicon nitride.
[0031] In this embodiment, the substrate includes a first region 100a and a second region 100b, wherein the width of the gate structure 105 of the first region 100a is smaller than the width of the gate structure 105 of the second region 100b.
[0032] It should be noted that after the gate structure 105 is removed to form a gate opening, the exposed substrate area of the gate opening is the channel region. Therefore, the width of the gate opening is equal to the width of the gate structure of the device to be formed (i.e., the gate width), and correspondingly, the width of the gate opening is equal to the channel length of the device to be formed.
[0033] It should also be noted that the width refers to the dimension in the direction perpendicular to the extension direction of the gate structure 105.
[0034] In this embodiment, the first region 100a is a first core device region, and the second region 100b includes a second core device region c and an input / output device region d. The width of the gate structure 105 of the input / output device region d is the same as the width of the gate structure 105 of the second core device region c, and the operating voltage of the gate structure 105 of the input / output device region d is greater than the operating voltage of the gate structure 105 of the second core device region c.
[0035] It should be noted that the first region 100a is used to form a short channel device, and the second region 100b is used to form a long channel device. The gate width of the short channel device is smaller than the gate width of the long channel device, meaning the channel length of the short channel device is smaller than the channel length of the long channel device.
[0036] It should also be noted that the second region 100b includes a second core device region c and an input / output device region d. The second core device region c is the device operating region, and the input / output device region d is used to provide operating voltage for the devices in the second region 100b. For this purpose, the operating voltage of the gate structure 105 of the input / output device region d is greater than the operating voltage of the gate structure 105 of the second core device region c.
[0037] In this embodiment, the metal gate structure 105 is formed by forming a high k last metal gatelast after forming a high k last gate dielectric layer. Therefore, the gate structure 105 is a pseudo gate structure.
[0038] The gate structure 105 occupies space for the subsequent formation of the device gate structure.
[0039] In this embodiment, the gate structure 105 is made of amorphous silicon. In other embodiments, the gate structure 105 is made of polycrystalline silicon. In other embodiments, the gate structure 105 may also be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, or amorphous carbon.
[0040] In this embodiment, a gate oxide layer 106 is also formed between the gate structure 105 and the substrate.
[0041] The gate oxide layer 106 is a tunnel oxide layer, which is used to achieve electrical isolation between the gate structure 105 and the substrate 100, thereby utilizing the tunneling effect to allow electrons to enter the gate structure 105 through the gate oxide layer 106.
[0042] Therefore, the material of the gate oxide layer 106 is silicon oxide.
[0043] The interlayer dielectric material layer 107 is used to electrically isolate adjacent devices in the first region 100a and the second region 100b. The material of the interlayer dielectric material layer 107 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric material layer 107 is silicon oxide.
[0044] In this embodiment, during the step of providing the substrate, an etch stop layer 103 is formed on the top and sidewalls of the gate structure 105, and the etch stop layer 103 is located between the gate structure 105 and the interlayer dielectric material layer 107.
[0045] In the subsequent second sub-planarization process of the device gate material layer above the top of the etch stop layer 103, the etch stop layer 103 is used as the etch stop position for the planarization process, which reduces the probability of over-etching of the device gate material layer and thus improves the performance of the semiconductor structure.
[0046] In this embodiment, the material of the etching stop layer 103 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon oxynitride.
[0047] Specifically, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon oxynitride have high hardness, resulting in a large polishing selectivity between them and the device gate material layer and the interlayer dielectric material layer 107 during the subsequent planarization process. This increases the probability of removing the device gate material layer and the interlayer dielectric material layer 107. Therefore, as an example, the etch stop layer 103 is made of silicon nitride.
[0048] It should be noted that, in this embodiment, after forming the gate structure 105 and before forming the interlayer dielectric material layer 107, the method further includes: forming source / drain doped layers 102 in the fins 101 on both sides of the gate structure 105.
[0049] When the formed semiconductor device is a PMOS transistor, the material of the source / drain doped layer 102 is silicon germanide doped with P-type ions, wherein the P-type ions include B, Ga, or In. When the formed semiconductor device is an NMOS transistor, the material of the source / drain doped layer 102 is silicon carbide or silicon doped with N-type ions, wherein the N-type ions include P, As, or Sb.
[0050] refer to Figure 9 Using the etch stop layer 103 located at the top of the gate structure 105 as the stop position, the interlayer dielectric material layer 107 above the top surface of the etch stop layer 103 is subjected to a fourth planarization process.
[0051] Specifically, a fourth planarization process is performed on the interlayer dielectric material layer 107 above the top surface of the etch stop layer 103, resulting in a higher flatness of the top surface of the remaining interlayer dielectric material layer 107. This facilitates the subsequent planarization process of the interlayer dielectric material layer 107 above the top of the gate structure 105, ensuring that the top of the gate structure 105 is flush with the top of the remaining interlayer dielectric material layer 107. This improves the flatness of the top surfaces of the gate structure 105 and the interlayer dielectric material layer 107, thereby enhancing the performance of the semiconductor structure.
[0052] In this embodiment, the process for performing the fourth planarization treatment on the interlayer dielectric material layer 107 above the top surface of the etching stop layer 103 is a chemical mechanical polishing process.
[0053] refer to Figure 10 Using the top of the gate structure 105 as the stop position, the interlayer dielectric material layer 107 above the top of the gate structure 105 is subjected to a first planarization process, and the remaining interlayer dielectric material layer 107 is used as the interlayer dielectric layer 108, the top of the interlayer dielectric layer 108 being flush with the top of the gate structure 105.
[0054] It should be noted that the interlayer dielectric material layer 107 above the top of the gate structure 105 undergoes a first planarization process, making the top of the interlayer dielectric layer 108 flush with the top of the gate structure 105. This improves the flatness of the top surfaces of the interlayer dielectric layer 108 and the gate structure 105. At the same time, it also facilitates the subsequent height correction process of the gate structure 105 and the interlayer dielectric layer 108, so that the height of the gate structure 105 and the interlayer dielectric layer 108 in the second region 100b is greater than the height of the gate structure 105 and the interlayer dielectric layer 108 in the first region 100a.
[0055] In this embodiment, during the first planarization process of the interlayer dielectric material layer 107 above the top of the gate structure 105, the etch stop layer 103 above the top of the gate structure 105 is also subjected to a first planarization process. The top of the remaining etch stop layer 103 is flush with the top of the gate structure 105, that is, the height of the etch stop layer 103 in the first region 100a is equal to that in the second region 100b. Accordingly, after the subsequent formation of the device gate structure, the etch stop layer 103 can protect the sidewalls of the device gate structure, reduce the probability of oxygen ions in the interlayer dielectric layer 108 entering the device gate structure, thereby improving the performance of the semiconductor structure.
[0056] In this embodiment, the first planarization process includes a chemical mechanical polishing process.
[0057] The described chemical mechanical polishing process combines the advantages of chemical polishing and mechanical polishing. It can achieve a relatively flat surface while ensuring material removal efficiency, featuring high surface precision, good integrity, and high polishing efficiency. This is beneficial during the first planarization process of the interlayer dielectric material layer 107 above the top of the gate structure 105, ensuring that the remaining interlayer dielectric material layer 107 is flush with the top of the gate structure 105, thus improving the top surface flatness of the first region 100a and the second region 100b.
[0058] refer to Figure 11 After the first planarization process, the gate structure 105 and the interlayer dielectric layer 108 are height-corrected so that the height of the gate structure 105 and the interlayer dielectric layer 108 in the second region 100b is greater than the height of the gate structure 105 and the interlayer dielectric layer 108 in the first region 100a.
[0059] Specifically, the gate structure 105 and the interlayer dielectric layer 108 are height-corrected to make the height of the gate structure 105 and the interlayer dielectric layer 108 in the second region 100b greater than the height of the gate structure 105 and the interlayer dielectric layer 108 in the first region 100a. That is, before forming the device gate structure, the gate structure 105 and the interlayer dielectric layer 108 in the first region 100a, and the gate structure 105 and the interlayer dielectric layer 108 in the second region 100b, are height-corrected to create a height difference between them. Since the width of the gate structure 105 in the first region 100a is smaller than the width of the gate structure 105 in the second region 100b, the height difference between the gate structure 105 in the first region 100a and the gate structure 105 in the second region 100b is reduced before forming the device gate material layer and the interlayer dielectric layer 108. 8. During the second planarization process, the contact area between the device gate material layer in the first region 100a and the planarization device is smaller than the contact area between the device gate material layer in the second region 100b and the planarization device. This results in a lower removal rate of the device gate material layer in the first region 100a than that in the second region 100b. Therefore, the height difference obtained by the height correction process can compensate for the difference in removal rates between the two regions. This is beneficial because during the second planarization process, the height of the device gate material layer in the second region 100b can be made equal to the height of the device gate material layer in the first region 100a within the same time frame. This improves the height uniformity and top surface flatness of the device gate structure in the first region 100a and the second region 100b, thereby improving the performance of the semiconductor structure.
[0060] In this embodiment, the height correction process for the gate structure 105 and the interlayer dielectric layer 108 includes: performing a third planarization process on the gate structure 105 and the interlayer dielectric layer 108, wherein the removal rate of the gate structure 105 and the interlayer dielectric layer 108 in the first region 100a is greater than the removal rate of the gate structure 105 and the interlayer dielectric layer 108 in the second region 100b.
[0061] Specifically, by making the removal rate of the gate structure 105 and the interlayer dielectric layer 108 in the first region 100a greater than the removal rate of the gate structure 105 and the interlayer dielectric layer 108 in the second region 100b, the removal height of the gate structure 105 and the interlayer dielectric layer 108 in the first region 100a is made greater than the removal height of the gate structure 105 and the interlayer dielectric layer 108 in the second region 100b. Accordingly, a height difference is generated between the gate structure 105 and the interlayer dielectric layer 108 in the second region 100b and the gate structure 105 and the interlayer dielectric layer 108 in the first region 100a.
[0062] In this embodiment, the third planarization process is a chemical mechanical polishing process.
[0063] The described chemical mechanical polishing process combines the advantages of chemical polishing and mechanical polishing. It can achieve a relatively flat surface while ensuring material removal efficiency, exhibiting high surface precision, good integrity, and high polishing efficiency. By controlling the removal rates of the gate structure 105 and interlayer dielectric layer 108 in the first region 100a and the second region 100b, a height difference that meets process requirements is created between the gate structure 105 and interlayer dielectric layer 108 in the second region 100b and the gate structure 105 and interlayer dielectric layer 108 in the first region 100a.
[0064] It should be noted that the ratio of the removal rate of the gate structure 105 and the interlayer dielectric layer 108 in the first region 100a to the removal rate of the gate structure 105 and the interlayer dielectric layer 108 in the second region 100b should not be too large or too small. If the ratio is too large, it can easily lead to excessively large removal thicknesses of the gate structure 105 and interlayer dielectric layer 108 in the first region 100a, and excessively small removal thicknesses of the gate structure 105 and interlayer dielectric layer 108 in the second region 100b. Consequently, the height difference between the gate structure 105 and interlayer dielectric layer 108 in the second region 100b and the gate structure 105 and interlayer dielectric layer 108 in the first region 100a cannot meet the process requirements. Consequently, during the subsequent second planarization process of the device gate material layer and interlayer dielectric layer 108, the effectiveness of the height difference in compensating for the difference in removal rates between the two regions decreases, causing the tops of the gate structure 105 and interlayer dielectric layer 108 in the first region 100a to be non-flush with the tops of the gate structure 105 and interlayer dielectric layer 108 in the second region 100b, thereby affecting the semiconductor structure. Performance; if the ratio is too small, it is easy for the thickness of the gate structure 105 and interlayer dielectric layer 108 removed in the first region 100a to be close to the thickness of the gate structure 105 and interlayer dielectric layer 108 removed in the first region 100a. This makes the height difference between the gate structure 105 and interlayer dielectric layer 108 in the second region 100b and the gate structure 105 and interlayer dielectric layer 108 in the first region 100a not meet the process requirements. Accordingly, during the subsequent second planarization process of the device gate material layer and interlayer dielectric layer 108, the effect of the height difference in compensating for the difference in removal rate between the two regions decreases, causing the top of the gate structure 105 and interlayer dielectric layer 108 in the first region 100a to be non-flush with the top of the gate structure 105 and interlayer dielectric layer 108 in the second region 100b, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the ratio of the removal rate of the gate structure 105 and the interlayer dielectric layer 108 in the first region 100a to the removal rate of the gate structure 105 and the interlayer dielectric layer 108 in the second region 100b is 5:1 to 2:1.
[0065] In this embodiment, the height correction process for the gate structure 105 and the interlayer dielectric layer 108 is further performed on the etch stop layer 103, so that the height of the etch stop layer 103 in the second region 100b is greater than the height of the etch stop layer 103 in the first region 100a.
[0066] Specifically, the height correction process is performed on the etch stop layer 103 to create a height difference between the etch stop layer 103 in the first region 100a and the etch stop layer 103 in the second region 100b. During the subsequent second sub-planarization process on the device gate material layer above the top of the etch stop layer 103, using the etch stop layer 103 as the stop position, a height difference is also created between the device gate material layer in the first region 100a and the device gate material layer in the second region 100b. Correspondingly, during the subsequent third sub-planarization process on the remaining device gate material layer and the interlayer dielectric layer 108, the height difference can compensate for the difference in removal rates between the two regions, improving the height uniformity and top surface flatness of the device gate structure in the first region 100a and the second region 100b, thereby improving the performance of the semiconductor structure.
[0067] It should be noted that the range H between the height of the gate structure 105 in the second region 100b and the height of the gate structure 105 in the first region 100a should not be too large or too small. If the range H between the height of the gate structure 105 in the second region 100b and the height of the gate structure 105 in the first region 100a is too large, the height difference between the gate structure 105 and the interlayer dielectric layer 108 in the second region 100b and the gate structure 105 and the interlayer dielectric layer 108 in the first region 100a may not meet the process requirements. Consequently, during the subsequent second planarization process of the device gate material layer and the interlayer dielectric layer 108, the effect of the height difference in compensating for the difference in removal rates between the two regions decreases, causing the tops of the gate structure 105 and the interlayer dielectric layer 108 in the first region 100a to be non-flush with the tops of the gate structure 105 and the interlayer dielectric layer 108 in the second region 100b, thereby affecting the performance of the semiconductor structure. If the range H between the height of the gate structure 105 in the second region 100b and the height of the gate structure 105 in the first region 100a is too small, the heights of the gate structure 105 and the interlayer dielectric layer 108 in the second region 100b and the first region 100a will be similar. Consequently, during the subsequent second planarization process of the device gate material layer and the interlayer dielectric layer 108, the effect of the height difference between the two regions in compensating for the difference in removal rates between the two regions will decrease. This will cause the tops of the gate structure 105 and the interlayer dielectric layer 108 in the first region 100a to be non-flush with the tops of the gate structure 105 and the interlayer dielectric layer 108 in the second region 100b, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the range H between the height of the gate structure 105 in the second region 100b and the height of the gate structure 105 in the first region 100a is 80 angstroms to 120 angstroms. As an example, the height of the gate structure 105 in the second region 100b is greater than the height of the gate structure 105 in the first region 100a by a range H of 90 angstroms, 100 angstroms, or 110 angstroms.
[0068] refer to Figure 12 After the height correction process is performed, the gate structure 105 is removed, and a gate opening 110 is formed in the interlayer dielectric layer 108.
[0069] The gate opening 110 provides space for the subsequent formation of the device gate material layer.
[0070] In this embodiment, the process of removing the gate structure 105 and forming the gate opening 110 in the interlayer dielectric layer 108 includes a dry etching process.
[0071] Specifically, the dry etching process is a plasma dry etching process. That is, in the process of removing the gate structure 105, plasma is directly used to physically react with the gate structure 105, thereby achieving the purpose of removing the gate structure 105.
[0072] refer to Figure 13 After removing the gate structure 105, the method further includes: removing the gate oxide layer 106 located in the first core device region and the second core device region c through the gate opening 110.
[0073] It should be noted that the operating voltage of the first region 100a and the second region 100b is proportional to the thickness of the gate oxide layer 106. Since the operating voltage of the input / output device region d is greater than the operating voltage of the second core device region c and the operating voltage of the first core device region, the total thickness of the gate oxide layer 106 in the input / output device region d is greater than the total thickness of the gate oxide layers 106 in the second core device region c and the first core device region. Accordingly, after removing the gate structure 105, the gate oxide layer 106 located in the input / output device region d is retained, while the gate oxide layers 106 in the first core device region and the second core device region c are removed.
[0074] It should also be noted that during the process of removing the gate oxide layer 106 located in the first core device region and the second core device region c through the gate opening 110, a portion of the thickness of the interlayer dielectric layer 108 (such as...) will also be consumed. Figure 13 (As shown).
[0075] refer to Figure 14 A device gate material layer 112 is formed in the gate opening 110, and the device gate material layer 112 also covers the top of the interlayer dielectric layer 108.
[0076] Specifically, the device gate material layer 112 provides a process basis for the subsequent formation of the device gate structure.
[0077] In this embodiment, the step of forming a device gate material layer 112 in the gate opening 110 includes: forming a gate dielectric layer at the bottom and sidewalls of the gate opening 110 and at the top of the interlayer dielectric layer 108; after forming the gate dielectric layer, forming a gate electrode layer in the gate opening 110 and at the top of the gate dielectric layer, wherein the gate electrode layer and the gate dielectric layer constitute the device gate material layer 112.
[0078] In this embodiment, the gate dielectric layer 160 is made of a high-k dielectric material. A high-k dielectric material refers to a dielectric material whose relative permittivity is greater than that of silicon oxide. As an example, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.
[0079] The gate electrode layer is used for subsequent electrical connection with external interconnect structures. The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.
[0080] As an example, the gate electrode layer may include a work function layer and an electrode layer located on the work function layer, wherein the work function layer is used to regulate the threshold voltage of the transistor. In other embodiments, the gate electrode layer may also consist only of a work function layer.
[0081] refer to Figures 15 to 17 A second planarization process is performed on the device gate material layer 112 and the interlayer dielectric layer 108 so that the remaining device gate material layers 112 in the first region and the second region 100b both reach the same target height. The remaining device gate material layers 112 after the second planarization process serve as the device gate structure 116.
[0082] It should be noted that, during the second planarization process of the device gate material layer 112 and the interlayer dielectric layer 108, the contact area between the device gate material layer 112 in the first region 100a and the planarization device is smaller than that in the second region 100b. This results in a lower removal rate of the device gate material layer 112 in the first region 100a compared to the second region 100b. Therefore, the height difference obtained by the height correction process can compensate for the difference in removal rates between the two regions. Consequently, the height uniformity and top surface flatness of the device gate structure 116 in the first region 100a and the second region 100b can be improved within the same time frame, thereby improving the performance of the semiconductor structure.
[0083] Reference Figures 15 to 17 The steps for performing a second planarization process on the gate material layer 112 and the interlayer dielectric layer 108 of the device are described in detail.
[0084] refer to Figure 15 A first sub-planarization process is performed on a portion of the thickness of the device gate material layer 112.
[0085] Specifically, the first sub-planarization process is a pre-grinding process, which makes the top surface of the gate material layer 112 of the device have a high degree of flatness, providing a good flat surface for the subsequent second sub-planarization process.
[0086] It should be noted that the thickness of the removed gate material layer 112 should not be too large or too small. If the removed thickness of the gate material layer 112 is too large, it is easy to damage the top surface of the etch stop layer 103. Consequently, during the subsequent second sub-planarization process of the gate material layer 112 above the top of the etch stop layer 103, the etch stop layer 103 will not be able to stop the etching, thereby reducing the performance of the semiconductor structure. If the removed thickness of the gate material layer 112 is too small, it is easy to cause a decrease in the process efficiency of removing the gate material layer 112 during the subsequent second sub-planarization process, and an increase in process cost. Therefore, in this embodiment, the thickness of the removed gate material layer 112 is 100 Å to 200 Å. As an example, the thickness of the removed gate material layer 112 is approximately 120 Å, 150 Å, or 180 Å.
[0087] refer to Figure 16 After the first sub-planarization process is performed, the top of the etch stop layer 103 is used as the stop layer position, and the device gate material layer 112 above the top of the etch stop layer 103 is subjected to the second sub-planarization process.
[0088] Specifically, by using the top of the etch stop layer 103 as the stop layer position, the probability of over-etching of the device gate material layer 112 is reduced, creating a height difference between the device gate material layer 112 in the first region 100a and the device gate material layer 112 in the second region 100b. Correspondingly, during the subsequent third sub-planarization process of the remaining device gate material layer 112 and the interlayer dielectric layer 108, the height difference is used to compensate for the difference in removal rate between the two regions, thereby improving the height uniformity and top surface flatness of the device gate structure 116 in the first region 100a and the second region 100b, and thus improving the performance of the semiconductor structure.
[0089] refer to Figure 17 After the second sub-planarization process, the remaining device gate material layer 112 and interlayer dielectric layer 108 are subjected to a third sub-planarization process, so that the remaining device gate material layers 112 in the first region 100a and the second region 100b reach the same target height.
[0090] During the third sub-planarization process on the remaining device gate material layer 112 and interlayer dielectric layer 108, since the contact area between the device gate material layer 112 in the first region 100a and the planarization device is smaller than that in the second region 100b, the removal rate of the device gate material layer 112 in the first region 100a is smaller than that in the second region 100b. By utilizing the height difference generated between the two regions in the aforementioned second sub-planarization process, the difference in removal rate between the first region 100a and the second region 100b is compensated, so that the remaining device gate material layers 112 in the first region 100a and the second region 100b both reach the same target height.
[0091] In this embodiment, the second planarization process includes a chemical mechanical polishing (CMP) process. The CMP process combines the advantages of chemical polishing and mechanical polishing, and can obtain a relatively flat surface while ensuring material removal efficiency. It has the characteristics of high surface precision, good integrity and high polishing efficiency, which is beneficial for performing the second planarization process on the device gate material layer 112 and the interlayer dielectric layer 108, so that the remaining device gate material layers 112 in the first region and the second region 100b both reach the same target height.
[0092] In this embodiment, the device gate structure 116 is a metal gate structure.
[0093] The metal gate structure is used to control the opening or closing of the conductive channel.
[0094] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region and a second region, a gate structure is formed on the top of the substrate, an interlayer dielectric material layer is formed on the exposed part of the gate structure, the interlayer dielectric material layer covers the top and sidewalls of the gate structure, and the width of the gate structure in the first region is smaller than the width of the gate structure in the second region. Using the top of the gate structure as the stop position, the interlayer dielectric material layer above the top of the gate structure is subjected to a first planarization process, and the remaining interlayer dielectric material layer is used as the interlayer dielectric layer. The gate structure and interlayer dielectric layer are height-corrected to make the height of the gate structure and interlayer dielectric layer in the second region greater than the height of the gate structure and interlayer dielectric layer in the first region. Remove the gate structure and form a gate opening in the interlayer dielectric layer; A device gate material layer is formed in the gate opening, and the device gate material layer also covers the top of the interlayer dielectric layer; The device gate material layer and interlayer dielectric layer are subjected to a second planarization process so that the remaining device gate material layers in the first region and the second region both reach the same target height. The remaining device gate material layers after the second planarization process serve as the device gate structure.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The modification step of highly correcting the gate structure and interlayer dielectric layer includes: performing a third planarization process on the gate structure and interlayer dielectric layer, wherein the removal rate of the gate structure and interlayer dielectric layer in the first region is greater than the removal rate of the gate structure and interlayer dielectric layer in the second region.
3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The third planarization process is a chemical mechanical polishing process.
4. The method for forming a semiconductor structure as described in claim 2, characterized in that, In the step of performing a third planarization process on the gate structure and interlayer dielectric layer, the ratio of the removal rate of the gate structure and interlayer dielectric layer in the first region to the removal rate of the gate structure and interlayer dielectric layer in the second region is 5:1 to 2:
1.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, an etch stop layer is formed on the top and sidewalls of the gate structure, and the etch stop layer is located between the gate structure and the interlayer dielectric layer. In the step of performing a first planarization process on the interlayer dielectric material layer above the top of the gate structure, a first planarization process is also performed on the etch stop layer above the top of the gate structure, and the top of the remaining etch stop layer is flush with the top of the gate structure. In the step of performing height correction processing on the gate structure and the interlayer dielectric layer, the height correction processing is also performed on the etch stop layer, so that the height of the etch stop layer in the second region is greater than the height of the etch stop layer in the first region.
6. The method for forming a semiconductor structure as described in claim 5, characterized in that, Before performing the first planarization process on the interlayer dielectric material layer above the top of the gate structure, the method further includes: using the etch stop layer located at the top of the gate structure as the stop position, performing a fourth planarization process on the interlayer dielectric material layer above the top surface of the etch stop layer.
7. The method for forming a semiconductor structure as described in claim 5, characterized in that, The material of the etching stop layer includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, and silicon oxynitride.
8. The method for forming a semiconductor structure as described in claim 5, characterized in that, The step of performing a second planarization process on the device gate material layer and the interlayer dielectric layer includes: performing a first sub-planarization process on a portion of the thickness of the device gate material layer; After the first sub-planarization process is performed, the top of the etch stop layer is used as the stop layer position, and the device gate material layer above the top of the etch stop layer is subjected to the second sub-planarization process. After the second sub-planarization process, the remaining device gate material layer and interlayer dielectric layer are subjected to a third sub-planarization process, so that the remaining device gate material layers in the first region and the second region both reach the same target height.
9. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the first sub-planarization step, the thickness of the device gate material layer removed is 100 angstroms to 200 angstroms.
10. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, the first region is a first core device region, the second region includes a second core device region and an input / output device region, the width of the gate structure of the input / output device region is the same as the width of the gate structure of the second core device region, and the operating voltage of the gate structure of the input / output device region is greater than the operating voltage of the gate structure of the second core device region.
11. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of providing the substrate, a gate oxide layer is further formed between the gate structure and the substrate; After removing the gate structure, the process further includes: removing the gate oxide layer located in the first core device region and the second core device region through the gate opening.
12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a device gate material layer in the gate opening includes: forming a gate dielectric layer at the bottom and sidewalls of the gate opening and at the top of the interlayer dielectric layer; and after forming the gate dielectric layer, forming a gate electrode layer in the gate opening and at the top of the gate dielectric layer, wherein the gate electrode layer and the gate dielectric layer constitute the device gate material layer.
13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.
14. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of performing height correction processing on the gate structure and the interlayer dielectric layer, the height of the gate structure in the second region is greater than the height of the gate structure in the first region by a range of 80 angstroms to 120 angstroms.
15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process of removing the gate structure and forming a gate opening in the interlayer dielectric layer includes a dry etching process.
16. The method for forming a semiconductor structure as described in claim 1, characterized in that, Both the first planarization process and the second planarization process include chemical mechanical polishing.