An anti-interference device and method for a rotary transformer circuit

Abstract

The application relates to an anti-interference device and method for a rotary transformer circuit, and belongs to the technical field of rotary transformer circuits. The device solves the problems that the existing anti-interference method has large hardware changes, high cost, cannot process the faults caused by the interference in time, and has poor reliability. The device comprises a first anti-interference circuit used for performing front-stage filtering on sine excitation signals and cosine excitation signals output by a rotary transformer decoding chip; a second anti-interference circuit used for performing resistance-capacitance filtering on sine differential signals and cosine differential signals output by the rotary transformer circuit based on received front-stage filtered sine wave excitation signals and cosine excitation signals; the rotary transformer decoding chip is used for generating digital signals and a first fault signal based on received filtered sine differential signals and cosine differential signals; a master control chip generates a second fault signal according to the received digital signals; and the device is also used for judging whether the rotary transformer circuit has a fault based on the first fault signal and the second fault signal, and eliminating the fault if the fault occurs.

Description

Technical Field

[0001] This invention relates to the field of resolver circuit technology, and in particular to an anti-interference device and method for resolver circuits. Background Technology

[0002] There are various control methods in the controller of permanent magnet synchronous motors, including SSI control, resolver control, incremental encoder control, and sine / cosine encoder control. Among them, resolver control is composed of high-performance silicon steel laminations and enameled wire with special electromagnetic design. Compared with encoders using photoelectric technology, it has the ability to adapt to harsh environments such as heat resistance, vibration resistance, shock resistance, and oil resistance.

[0003] Currently, the most widely used type of resolver in many fields of industrial production is the single-pole resolver, a single-turn absolute feedback system. The resolver typically has six signal lines, divided into three groups, corresponding to one excitation coil and two orthogonal induction coils. The excitation coil receives a sinusoidal excitation signal, while the induction coils, based on the relative angular positions of the resolver rotor and stator, induce detection signals with SIN and COS envelopes. The resolver circuit requires a resolver decoding chip to provide a sinusoidal oscillator, supplying sinusoidal excitation to the resolver circuit and converting the sine and cosine input information into digital quantities corresponding to the input angle and speed, which are then transmitted to the processor. The processor obtains the angle and speed information and controls the motor accordingly. During the decoding process, the resolver decoding chip determines whether a fault has occurred based on the received sine and cosine signals and outputs a fault signal; the processor, based on the received angle and speed information, also outputs a fault signal.

[0004] However, the signal during the interaction between the resolver circuit and the resolver decoding chip is highly susceptible to interference, leading to false alarms. Furthermore, during high-voltage, high-power drive control, the resolver circuit experiences electromagnetic interference at the moment of high-voltage power-on, causing the resolver decoding chip to output a fault signal. This fault is a short-lived pulse that generates a false alarm. Current anti-interference methods require significant modifications to the hardware and products, resulting in high costs. Moreover, they cannot quickly determine whether a fault is caused by interference, hindering timely processing and leading to long processing times and poor reliability. Summary of the Invention

[0005] Based on the above analysis, the present invention aims to provide an anti-interference device and method for resolver circuits, in order to solve the problems that existing anti-interference methods require significant hardware modifications, have high costs, and cannot promptly handle faults caused by interference, resulting in poor reliability.

[0006] On one hand, embodiments of the present invention provide an anti-interference device for a resolver circuit, including a resolver decoding chip, a first anti-interference circuit, a second anti-interference circuit, a resolver circuit, and a main control chip;

[0007] The first anti-interference circuit is used to perform pre-stage filtering on the sine excitation signal and cosine excitation signal output by the resolver decoding chip;

[0008] The second anti-interference circuit is used to perform RC filtering on the sinusoidal differential signal and cosine differential signal output by the resolver circuit based on the received pre-filtered sinusoidal excitation signal and cosine excitation signal.

[0009] The resolver decoding chip is also used to generate a digital signal and a first fault signal based on the received filtered sine differential signal and cosine differential signal;

[0010] The main control chip is used to generate a second fault signal based on the digital signal output by the received resolver decoding chip; it is also used to determine whether the resolver circuit has malfunctioned based on the first fault signal and the second fault signal, and if a fault has occurred, to perform fault elimination.

[0011] Furthermore, the main control chip eliminates faults in the following ways:

[0012] When either the first fault signal or the second fault signal is low, a fault is determined to have occurred in the resolver circuit, and the following fault clearing process is executed every clock cycle:

[0013] If the fault clearance execution time is less than or equal to the preset fault clearance time threshold, then

[0014] Set the sampling pin of the resolver decoder chip to low level. After a set time interval, set the input enable pin of the resolver decoder chip to low level, input the configuration data 0xFF on the serial data input pin, and then set the input enable pin of the resolver decoder chip to high level. Determine whether the first fault signal and the second fault signal are both not low level. If so, determine that the fault is cleared and stop the fault clearing process.

[0015] If the fault elimination execution time exceeds the preset fault elimination time threshold, the fault elimination process will be stopped and the results will be reported.

[0016] Furthermore, the fault elimination process of the main control chip also includes:

[0017] After setting the input enable pin of the resolver decoder chip to high level, set the sampling pin of the resolver decoder chip to low level, high level, and low level in sequence to ensure that the fault is eliminated.

[0018] Furthermore, the main control chip generates a second fault signal including:

[0019] Based on the set number of samples, high-speed sampling is used to sample the digital signal output by the received resolver decoder chip, thereby obtaining the average value of each sampled data. The main control chip generates a second fault signal based on this average value.

[0020] Furthermore, the resolver decoding chip uses the AD2S1210 chip.

[0021] Furthermore, the fault clearance time threshold is set to 50ms.

[0022] Furthermore, the first anti-interference circuit includes a sinusoidal excitation signal anti-interference circuit and a cosine excitation signal anti-interference circuit;

[0023] The sinusoidal excitation signal anti-interference circuit includes operational amplifiers P1 and P2, resistors R1 to R6, and capacitors C1 to C4. The inverting input terminal of operational amplifier P1 is connected to one end of resistor R1 and one end of capacitor C1 via resistor R2. The other end of resistor R1 receives the sinusoidal excitation signal, and the other end of capacitor C1 is grounded. The inverting input terminal of operational amplifier P1 is also connected to the output terminal of operational amplifier P2 via capacitor C2. The inverting input terminal of operational amplifier P1 is also connected to the output terminal of operational amplifier P1 via resistors R2 and R3. The non-inverting input of operational amplifier P1 is connected to a reference voltage; the inverting input of operational amplifier P2 is grounded via resistor R5; the inverting input of operational amplifier P2 is also connected to one end of resistor R6 and one end of capacitor C4, and the other end of resistor R6 and the other end of C4 are connected to the output of operational amplifier P2; the non-inverting input of operational amplifier P2 is connected to one end of resistor R4 and one end of capacitor C3, the other end of resistor R4 is connected to the output of operational amplifier P1, and the other end of capacitor C3 is grounded; the output of operational amplifier P2 outputs the pre-filtered sinusoidal excitation signal.

[0024] The cosine excitation signal anti-interference circuit has the same structure as the sine excitation signal anti-interference circuit. The cosine excitation signal anti-interference circuit receives the cosine excitation signal and outputs the cosine excitation signal after pre-stage filtering.

[0025] Furthermore, the second anti-interference circuit includes a sinusoidal differential signal anti-interference circuit and a cosine differential signal anti-interference circuit;

[0026] The sinusoidal differential signal anti-interference circuit includes resistors R7 to R10 and capacitors C5 to C7. One end of resistor R7 receives the negative analog input signal of the sinusoidal differential signal, and the other end is connected to one end of capacitor C5, and is also used to output the negative analog input signal of the filtered sinusoidal differential signal. One end of capacitor C5 is also connected to one end of resistor R9, and the other end is connected to one end of capacitor C6. The other end of capacitor C6 is connected to one end of resistor R8, and is also used to output the positive analog input signal of the filtered sinusoidal differential signal. The other end of capacitor C6 is also connected to one end of resistor R10, and the other end of resistor R8 receives the positive analog input signal of the sinusoidal differential signal. The other ends of resistors R9 and R10 are connected and connected to the reference voltage via capacitor C7.

[0027] The cosine differential signal anti-interference circuit has the same structure as the sine differential signal anti-interference circuit. The cosine differential signal anti-interference circuit receives the negative analog input signal and the positive analog input signal of the cosine differential signal, and outputs the filtered negative analog input signal and the positive analog input signal of the cosine differential signal.

[0028] On the other hand, embodiments of the present invention provide an anti-interference method for resolver circuits, comprising the following steps:

[0029] The sine and cosine excitation signals output by the resolver decoding chip are obtained and filtered in the pre-stage.

[0030] The resolver circuit obtains sinusoidal differential signals and cosine differential signals generated from the received pre-filtered sinusoidal excitation signals and performs RC filtering.

[0031] Acquire the digital signal and the first fault signal generated based on the received filtered sinusoidal differential signal and cosine differential signal;

[0032] A second fault signal is generated based on the digital signal, and the resolver circuit is judged to have a fault based on the first fault signal and the second fault signal. If a fault occurs, the fault is eliminated.

[0033] Furthermore, the fault can be eliminated in the following ways:

[0034] When either the first fault signal or the second fault signal is low, a fault is determined to have occurred in the resolver circuit, and the following fault clearing process is executed every clock cycle:

[0035] If the fault clearance execution time is less than or equal to the preset fault clearance time threshold, then

[0036] Set the sampling pin of the resolver decoder chip to low level. After a set time interval, set the input enable pin of the resolver decoder chip to low level, input the configuration data 0xFF on the serial data input pin, and then set the input enable pin of the resolver decoder chip to high level. Determine whether the first fault signal and the second fault signal are both not low level. If so, determine that the fault is cleared and stop the fault clearing process.

[0037] If the fault elimination execution time exceeds the preset fault elimination time threshold, the fault elimination process will be stopped and the results will be reported.

[0038] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0039] This invention provides an anti-interference device and method for resolver circuits.

[0040] 1. By setting up a first interference circuit and a second anti-interference circuit, the sinusoidal excitation signal, cosine excitation signal, sinusoidal differential signal and cosine differential signal interacting between the resolver decoding chip and the resolver circuit are filtered, eliminating the faults caused by environmental interference in the interaction signal, making the output signal more accurate.

[0041] 2. Through the set fault elimination process, faults caused by interference can be eliminated in a short time, making the handling more timely and reliable, and avoiding the need to stop work due to faults caused by interference, which would affect the work process;

[0042] 3. By setting up interference circuits and fault elimination processes, interference and faults can be eliminated without adding too much hardware, saving time and reducing costs.

[0043] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0044] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0045] Figure 1 This is a schematic diagram of the anti-interference device for a resolver circuit provided in Embodiment 1 of the present invention;

[0046] Figure 2The circuit connection diagram of the sinusoidal excitation signal anti-interference circuit in the first anti-interference circuit provided in Embodiment 1 of the present invention is shown.

[0047] Figure 3 The circuit connection diagram of the sinusoidal differential signal anti-interference circuit in the second anti-interference circuit provided in Embodiment 1 of the present invention is shown.

[0048] Figure 4 This is a flowchart illustrating the anti-interference method for a resolver circuit provided in Embodiment 2 of the present invention. Detailed Implementation

[0049] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0050] Example 1

[0051] One specific embodiment of the present invention discloses an anti-interference device for a resolver circuit, such as... Figure 1 As shown, it includes a resolver decoding chip, a first anti-interference circuit, a second anti-interference circuit, a resolver circuit, and a main control chip;

[0052] The first anti-interference circuit is used to perform pre-stage filtering on the sine excitation signal and cosine excitation signal output by the resolver decoding chip;

[0053] The second anti-interference circuit is used to perform RC filtering on the sinusoidal differential signal and cosine differential signal output by the resolver circuit based on the received pre-filtered sinusoidal excitation signal and cosine excitation signal.

[0054] The resolver decoding chip is also used to generate a digital signal and a first fault signal based on the received filtered sine differential signal and cosine differential signal;

[0055] Specifically, the resolver decoding chip is based on the Type II tracking loop. Through its internal phase-sensitive demodulator, integrator, and compensation filter, it converts the filtered sinusoidal and cosine differential signals into digital quantities corresponding to angle and velocity, thus obtaining digital signals.

[0056] Specifically, the resolver decoding chip compares the filtered sine differential signal and cosine differential signal with the reference value set inside the chip to determine whether the resolver circuit has a fault. If a fault occurs, the first fault signal output is a low-level signal.

[0057] The main control chip is used to generate a second fault signal based on the digital signal output by the received resolver decoding chip; it is also used to determine whether the resolver circuit has malfunctioned based on the first fault signal and the second fault signal, and if a fault has occurred, to perform fault elimination.

[0058] It should be noted that the main control chip generates a second fault signal based on the received digital signal. This is an existing internal setting of the main control chip. When a fault is detected, the output second fault signal is a low-level signal.

[0059] In practice, the resolver decoding chip is the AD2S1210 chip.

[0060] Compared with existing technologies, this invention provides an anti-interference device for resolver circuits. By setting up a first interference circuit and a second anti-interference circuit, the sinusoidal excitation signal, cosine excitation signal, sinusoidal differential signal, and cosine differential signal interacting between the resolver decoding chip and the resolver circuit are filtered, eliminating faults caused by environmental interference in the interactive signals. This makes the output signal more accurate and reduces fault reports caused by interference. Through the set fault elimination process, faults caused by interference can be eliminated in a short time, making the processing more timely and reliable, avoiding the need to stop operations due to interference faults and affecting the operation process. By setting up the interference circuit and the fault elimination process, interference and faults can be eliminated without adding too much hardware, saving time and reducing costs.

[0061] During implementation, the main control chip eliminates faults in the following ways:

[0062] When either the first fault signal or the second fault signal is low, a fault is determined to have occurred in the resolver circuit, and the following fault clearing process is executed every clock cycle:

[0063] If the fault clearance execution time is less than or equal to the preset fault clearance time threshold, then

[0064] The sampling pin of the resolver decoder chip is set to low level. After a set time interval, the input enable pin of the resolver decoder chip is set to low level in sequence, configuration data 0xFF is input on the serial data input pin, and then the input enable pin of the resolver decoder chip is set to high level. In other words, the main control chip clears the data by controlling the register of the resolver decoder chip to clear the corresponding fault. It is determined whether the first fault signal and the second fault signal are both not low level. If so, the fault is determined to be cleared and the fault clearing process is stopped.

[0065] If the fault elimination execution time exceeds the preset fault elimination time threshold, the fault elimination process will be stopped and the results will be reported.

[0066] It is understood that the fault elimination process in this embodiment first eliminates the fault when it occurs. If the fault is eliminated within the set fault elimination time threshold, it can be determined that the fault is a false alarm caused by interference. At this time, the fault has been eliminated and does not affect the normal operation of the device. If the fault is not eliminated within the set fault elimination time threshold, it can be determined that it is due to a problem with the device itself. At this time, the fault result is reported for inspection and fault handling. The fault has been preliminarily diagnosed, which helps with subsequent fault handling.

[0067] Specifically, the fault clearance time threshold is set to 50ms, which is based on the duration of the fault caused by the actual interference.

[0068] Preferably, the fault clearing process of the main control chip further includes:

[0069] After setting the input enable pin of the resolver decoder chip to high level, the sampling pin of the resolver decoder chip is then set to low level, high level, and low level sequentially to ensure fault clearance. This setting further preserves the integrity of the fault clearing process, ensuring its completeness and effectiveness.

[0070] During implementation, the main control chip generates a second fault signal including:

[0071] Based on the set number of samples, high-speed sampling is used to sample the digital signal output by the received resolver decoder chip, thereby obtaining the average value of each sampled data. The main control chip generates a second fault signal based on this average value. The number of samples can be set according to requirements; for example, the number of samples is 5.

[0072] Specifically, the main control chip generates a second fault signal based on the average value of the digital signal. This is achieved by sampling within a set number of times within the sampling time window. If the average value is 1 or 0, it indicates no interference, and the second fault signal is output as a high-level signal. Otherwise, it indicates interference, and the second fault signal is output as a low-level signal. Understandably, if there is no interference, each sample result of the digital signal should be the same data, and its average value should be 1 or 0. If there is interference, the digital signal is affected by the interference and has errors. In this case, the average value of the digital signal is other data.

[0073] Understandably, by applying mean filtering to the digital signal output by the resolver decoder chip, data errors caused by interference are further eliminated, data accuracy is improved, the obtained second fault signal is more accurate, and fault reporting caused by interference is reduced.

[0074] In implementation, the first anti-interference circuit includes a sinusoidal excitation signal anti-interference circuit and a cosine excitation signal anti-interference circuit;

[0075] The sinusoidal excitation signal anti-interference circuit, such as Figure 2 As shown, the system includes operational amplifiers P1 and P2, resistors R1 to R6, and capacitors C1 to C4. The inverting input of operational amplifier P1 is connected to one end of resistor R1 and one end of capacitor C1 via resistor R2. The other end of resistor R1 receives a sinusoidal excitation signal, and the other end of capacitor C1 is grounded. The inverting input of operational amplifier P1 is also connected to the output of operational amplifier P2 via capacitor C2. The inverting input of operational amplifier P1 is also connected to the output of operational amplifier P1 via resistors R2 and R3. The non-inverting input of operational amplifier P1... The inverting input of operational amplifier P2 is connected to a reference voltage; the inverting input of operational amplifier P2 is grounded via resistor R5; the inverting input of operational amplifier P2 is also connected to one end of resistor R6 and one end of capacitor C4, and the other end of resistor R6 and the other end of C4 are connected to the output of operational amplifier P2; the non-inverting input of operational amplifier P2 is connected to one end of resistor R4 and one end of capacitor C3, the other end of resistor R4 is connected to the output of operational amplifier P1, and the other end of capacitor C3 is grounded; the output of operational amplifier P2 outputs the pre-filtered sinusoidal excitation signal.

[0076] The cosine excitation signal anti-interference circuit has the same structure as the sine excitation signal anti-interference circuit. The cosine excitation signal anti-interference circuit receives the cosine excitation signal and outputs the cosine excitation signal after pre-stage filtering. That is, the input terminal of the cosine excitation signal anti-interference circuit is connected to the analog output terminal EXCN of the cosine excitation signal generated by the resolver decoding chip, and the output terminal is connected to the excitation input terminal EXC- of the resolver circuit that receives the cosine excitation signal.

[0077] It should be noted that the resolver decoding chip generates a sine excitation signal and a cosine excitation signal that is 90 degrees out of phase with the sine signal. These are used as excitation signals for the two stators on the resolver circuit, respectively, to generate sine differential signals and cosine differential signals on the rotor in the resolver circuit.

[0078] In implementation, the second anti-interference circuit includes a sinusoidal differential signal anti-interference circuit and a cosine differential signal anti-interference circuit;

[0079] The sinusoidal differential signal anti-interference circuit, such as Figure 3As shown, the circuit includes resistors R7 to R10 and capacitors C5 to C7. One end of resistor R7 receives the negative analog input signal of the sinusoidal differential signal, i.e., this end serves as the negative analog input terminal of the sinusoidal differential signal anti-interference circuit and is connected to the sinusoidal negative analog output terminal SIN- of the sinusoidal differential signal output by the resolver circuit. The other end is connected to one end of capacitor C5 and is also used to output the filtered negative analog input signal of the sinusoidal differential signal. That is, this end serves as the negative analog output terminal of the sinusoidal differential signal anti-interference circuit and is connected to the sinusoidal negative analog input terminal SINLo of the resolver decoding chip. One end of capacitor C5 is also connected to one end of resistor R9, and the other end is connected to one end of capacitor C6. The other end of capacitor C6 is connected to one end of resistor R8 and is also used to output the positive analog input signal of the filtered sinusoidal differential signal. That is, this end is connected to the positive analog output terminal of the sinusoidal differential signal anti-interference circuit and the sinusoidal positive analog input terminal SIN of the resolver decoding chip. The other end of capacitor C6 is also connected to one end of resistor 10. The other end of resistor R8 receives the positive analog input signal of the sinusoidal differential signal. That is, this end is connected to the positive analog input terminal of the sinusoidal differential signal anti-interference circuit and the sinusoidal positive analog output terminal SIN+ of the positive analog input signal of the sinusoidal differential signal output by the resolver circuit. The other ends of resistor R9 and resistor R10 are connected and connected to the reference voltage through capacitor C7.

[0080] The cosine differential signal anti-interference circuit has the same structure as the sine differential signal anti-interference circuit. The cosine differential signal anti-interference circuit receives the negative analog input signal and the positive analog input signal of the cosine differential signal, and outputs the filtered negative analog input signal and the positive analog input signal of the cosine differential signal. That is, the negative analog input terminal and the positive analog input terminal of the cosine differential signal anti-interference circuit are respectively connected to the cosine negative analog output terminal COS- and the cosine positive analog output terminal COS+ of the negative analog input signal and the positive analog input signal of the cosine differential signal output by the resolver circuit. The positive analog output terminal and the negative analog output terminal of the cosine differential signal anti-interference circuit are respectively connected to the cosine positive analog input terminal COS and the cosine negative analog input terminal COSLo of the resolver decoding chip.

[0081] Preferably, twisted-pair shielded cables are used to connect the differential pairs of signals in pairs to increase signal reliability.

[0082] Understandably, by setting up the first and second anti-interference circuits, the interaction signal errors caused by interference are eliminated in the hardware, improving the accuracy of interaction, greatly reducing the fault reporting caused by environmental interference, and improving the operating efficiency of the device.

[0083] Example 2

[0084] A specific embodiment 2 of the present invention provides an anti-interference method for resolver circuits, such as... Figure 4As shown, it includes the following steps:

[0085] The sine and cosine excitation signals output by the resolver decoding chip are obtained and filtered in the pre-stage.

[0086] The resolver circuit obtains sinusoidal differential signals and cosine differential signals generated from the received pre-filtered sinusoidal excitation signals and performs RC filtering.

[0087] Acquire the digital signal and the first fault signal generated based on the received filtered sinusoidal differential signal and cosine differential signal;

[0088] A second fault signal is generated based on the digital signal, and the resolver circuit is judged to have a fault based on the first fault signal and the second fault signal. If a fault occurs, the fault is eliminated.

[0089] During implementation, the fault should be eliminated in the following ways:

[0090] When either the first fault signal or the second fault signal is low, a fault is determined to have occurred in the resolver circuit, and the following fault clearing process is executed every clock cycle:

[0091] If the fault clearance execution time is less than or equal to the preset fault clearance time threshold, then

[0092] Set the sampling pin of the resolver decoder chip to low level. After a set time interval, set the input enable pin of the resolver decoder chip to low level, input the configuration data 0xFF on the serial data input pin, and then set the input enable pin of the resolver decoder chip to high level. Determine whether the first fault signal and the second fault signal are both not low level. If so, determine that the fault is cleared and stop the fault clearing process.

[0093] If the fault elimination execution time exceeds the preset fault elimination time threshold, the fault elimination process will be stopped and the results will be reported.

[0094] The specific implementation process of this invention can be found in the above-described device embodiments, and will not be repeated here.

[0095] Since this embodiment is based on the same principle as the above-described device embodiment, this method also has the corresponding technical effects of the above-described method embodiment.

[0096] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.

[0097] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. An anti-interference device for a resolver circuit, characterized in that, It includes a resolver decoding chip, a first anti-interference circuit, a second anti-interference circuit, a resolver circuit, and a main control chip; The first anti-interference circuit is used to perform pre-stage filtering on the sine excitation signal and cosine excitation signal output by the resolver decoding chip; The second anti-interference circuit is used to perform RC filtering on the sinusoidal differential signal and cosine differential signal output by the resolver circuit based on the received pre-filtered sinusoidal excitation signal and cosine excitation signal. The resolver decoding chip is also used to generate a digital signal and a first fault signal based on the received filtered sine differential signal and cosine differential signal; The main control chip is used to generate a second fault signal based on the digital signal output by the received resolver decoding chip; it is also used to determine whether the resolver circuit has malfunctioned based on the first fault signal and the second fault signal, and if a fault has occurred, to perform fault elimination. The main control chip eliminates faults in the following ways: When either the first fault signal or the second fault signal is low, a fault is determined to have occurred in the resolver circuit, and the following fault clearing process is executed every clock cycle: If the fault clearance execution time is less than or equal to the preset fault clearance time threshold, then Set the sampling pin of the resolver decoder chip to low level. After a set time interval, set the input enable pin of the resolver decoder chip to low level, input the configuration data 0xFF on the serial data input pin, and then set the input enable pin of the resolver decoder chip to high level. Determine whether the first fault signal and the second fault signal are both not low level. If so, determine that the fault is cleared and stop the fault clearing process. If the fault elimination execution time exceeds the preset fault elimination time threshold, the fault elimination process will be stopped and the results will be reported.

2. The anti-interference device for a resolver circuit according to claim 1, characterized in that, The fault clearing process of the main control chip also includes: After setting the input enable pin of the resolver decoder chip to high level, set the sampling pin of the resolver decoder chip to low level, high level, and low level in sequence to ensure that the fault is eliminated.

3. The anti-interference device for a resolver circuit according to claim 1, characterized in that, The main control chip generates the second fault signal including: Based on the set number of samples, high-speed sampling is used to sample the digital signal output by the received resolver decoder chip, thereby obtaining the average value of each sampled data. The main control chip generates a second fault signal based on this average value.

4. The anti-interference device for a resolver circuit according to claim 1, characterized in that, The resolver decoding chip uses the AD2S1210 chip.

5. The anti-interference device for a resolver circuit according to claim 2, characterized in that, The fault clearance time threshold is set to 50ms.

6. The anti-interference device for a resolver circuit according to claim 1, characterized in that, The first anti-interference circuit includes a sinusoidal excitation signal anti-interference circuit and a cosine excitation signal anti-interference circuit. The sinusoidal excitation signal anti-interference circuit includes operational amplifiers P1 and P2, resistors R1~R6, and capacitors C1~C4. The inverting input terminal of operational amplifier P1 is connected to one end of resistor R1 and one end of capacitor C1 via resistor R2. The other end of resistor R1 receives the sinusoidal excitation signal, and the other end of capacitor C1 is grounded. The inverting input terminal of operational amplifier P1 is also connected to the output terminal of operational amplifier P2 via capacitor C2. The inverting input terminal of operational amplifier P1 is also connected to the output terminal of operational amplifier P1 via resistors R2 and R3. The non-inverting input of operational amplifier P1 is connected to a reference voltage; the inverting input of operational amplifier P2 is grounded via resistor R5; the inverting input of operational amplifier P2 is also connected to one end of resistor R6 and one end of capacitor C4, and the other end of resistor R6 and the other end of C4 are connected to the output of operational amplifier P2; the non-inverting input of operational amplifier P2 is connected to one end of resistor R4 and one end of capacitor C3, the other end of resistor R4 is connected to the output of operational amplifier P1, and the other end of capacitor C3 is grounded; the output of operational amplifier P2 outputs the pre-filtered sinusoidal excitation signal. The cosine excitation signal anti-interference circuit has the same structure as the sine excitation signal anti-interference circuit. The cosine excitation signal anti-interference circuit receives the cosine excitation signal and outputs the cosine excitation signal after pre-stage filtering.

7. The anti-interference device for a resolver circuit according to claim 1, characterized in that, The second anti-interference circuit includes a sinusoidal differential signal anti-interference circuit and a cosine differential signal anti-interference circuit; The sinusoidal differential signal anti-interference circuit includes resistors R7~R10 and capacitors C5~C7. One end of resistor R7 receives the negative analog input signal of the sinusoidal differential signal, and the other end is connected to one end of capacitor C5, and is also used to output the negative analog input signal of the filtered sinusoidal differential signal. One end of capacitor C5 is also connected to one end of resistor R9, and the other end is connected to one end of capacitor C6. The other end of capacitor C6 is connected to one end of resistor R8, and is also used to output the positive analog input signal of the filtered sinusoidal differential signal. The other end of capacitor C6 is also connected to one end of resistor R10, and the other end of resistor R8 receives the positive analog input signal of the sinusoidal differential signal. The other ends of resistors R9 and R10 are connected and connected to the reference voltage via capacitor C7. The cosine differential signal anti-interference circuit has the same structure as the sine differential signal anti-interference circuit. The cosine differential signal anti-interference circuit receives the negative analog input signal and the positive analog input signal of the cosine differential signal, and outputs the filtered negative analog input signal and the positive analog input signal of the cosine differential signal.

8. An anti-interference method for resolver circuits, characterized in that, Includes the following steps: The sine and cosine excitation signals output by the resolver decoding chip are obtained and filtered in the pre-stage. The resolver circuit obtains sinusoidal differential signals and cosine differential signals generated from the received pre-filtered sinusoidal excitation signals and performs RC filtering. Acquire the digital signal and the first fault signal generated based on the received filtered sinusoidal differential signal and cosine differential signal; A second fault signal is generated based on the digital signal, and the resolver circuit is judged to have a fault based on the first fault signal and the second fault signal. If a fault occurs, the fault is eliminated. The following methods can be used to eliminate the fault: When either the first fault signal or the second fault signal is low, a fault is determined to have occurred in the resolver circuit, and the following fault clearing process is executed every clock cycle: If the fault clearance execution time is less than or equal to the preset fault clearance time threshold, then Set the sampling pin of the resolver decoder chip to low level. After a set time interval, set the input enable pin of the resolver decoder chip to low level, input the configuration data 0xFF on the serial data input pin, and then set the input enable pin of the resolver decoder chip to high level. Determine whether the first fault signal and the second fault signal are both not low level. If so, determine that the fault is cleared and stop the fault clearing process. If the fault elimination execution time exceeds the preset fault elimination time threshold, the fault elimination process will be stopped and the results will be reported.

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