Timing path repair method and apparatus, electronic device, and storage medium

Abstract

The application provides a timing path repair method and device, electronic equipment and storage medium, and relates to the field of integrated circuit design. The timing path repair method comprises the following steps: determining the layout margin and the wiring margin of each region in a chip based on a chip design file and a preset margin calculation rule; judging whether the layout margin and the wiring margin of each region meet a preset threshold condition; adding a constraint to each target region that does not meet the preset threshold condition; the added constraint is used to limit the adjustment mode of the circuit unit in the target region to which the constraint belongs during timing violation path repair; and repairing the timing violation path in the chip based on the constraint of each region. By adding a constraint to the region in the chip whose layout margin and wiring margin do not meet the preset threshold condition, the adjustment mode of the region during timing path repair is limited, so as to reduce new problems caused by the adjustment of the region, thereby improving the repair efficiency.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design, and more specifically, to a timing path repair method, apparatus, electronic device, and storage medium. Background Technology

[0002] After the chip layout and routing are completed, the timing of the chip will be verified. If the timing does not meet the requirements, i.e. there is a timing violation, the circuit path involved in the timing violation needs to be adjusted and repaired so that the timing of the chip meets the requirements.

[0003] Currently, during timing optimization, new circuit cells are inserted or adjusted in areas of the layout where no circuit cells were originally intended. Inserting new circuit cells occupies available space on the chip, and adjusting circuit cells may change the original area of ​​the circuit cells, thus requiring more chip area. The occupied space may be used for routing, and this area may contain a lot of routing. If occupied, it may cause short circuits in the routing and circuit cells in that area, or violate physical design rules, requiring manual time to resolve, thus affecting the efficiency of timing violation repair. Summary of the Invention

[0004] In view of this, this application aims to provide a timing path repair method, apparatus, electronic device and storage medium to improve the repair efficiency of timing violation paths.

[0005] In a first aspect, embodiments of this application provide a timing path repair method, comprising: determining the layout margin and routing margin of each region in a chip based on a chip design file and a preset margin calculation rule; the chip is divided into multiple regions; for each region: the layout margin of the region represents the free layout space of the region, and the routing margin of the region represents the free routing space of the region; the chip design file includes circuit unit information and routing information of the chip; the preset margin calculation rule includes: the calculation relationship between circuit unit information and layout margin, and the calculation relationship between routing information and routing margin; determining whether the layout margin and routing margin of each region meet a preset threshold condition; adding constraints to each target region in each region that does not meet the preset threshold condition; the added constraints are used to restrict the adjustment method of the circuit units in the target region to which the constraints belong during timing violation path repair; and repairing the timing violation path in the chip based on the constraints of each region.

[0006] In this embodiment, before repairing timing violation paths, layout margin and routing margin are considered. Constraints are added to areas where the layout margin and routing margin do not meet the preset threshold conditions, restricting their participation in the adjustment method when repairing timing violation paths. This reduces new problems caused by insufficient space during repair, thereby reducing the number of iterations required for timing violation path repair, improving repair efficiency, and ultimately improving chip design efficiency.

[0007] In one embodiment, adding constraints to each target region that does not meet the preset threshold condition in each of the regions includes: adding a first constraint to each target region; the first constraint prohibits timing repair by increasing the area of ​​circuit units within the target region.

[0008] In this embodiment, a first constraint is added to the target region so that it will not cause new problems due to changes in the area of ​​the circuit unit when participating in the timing violation path repair. As a result, the number of iterations required for timing violation path repair can be reduced and the repair efficiency can be improved.

[0009] In one embodiment, adding constraints to each target region that does not meet the preset threshold condition in each of the regions includes: adding a second constraint to each target region; the second constraint prohibits timing repair by inserting new circuit units in the winding of the timing violation path in the target region.

[0010] In this embodiment, a second constraint is added to the target area, which prohibits the insertion of new circuit units in the middle of the winding in the area during repair. This avoids the impact of the new circuit units on the existing circuit units and windings in the area, thereby effectively reducing new problems caused by repairing timing violation paths, reducing the number of iterations required for repairing timing violation paths, and improving repair efficiency.

[0011] In one embodiment, the preset threshold conditions include a first threshold, a second threshold, a third threshold, and a fourth threshold, wherein the third threshold is less than or equal to the first threshold, and the fourth threshold is less than the second threshold; the addition of constraints to each target region that does not meet the preset threshold conditions in each of the regions includes: for any target region, if the layout margin of the target region is between the first threshold and the third threshold, and / or the routing margin of the target region is between the second threshold and the fourth threshold, then a first constraint is added to the target region; the first constraint prohibits timing repair by increasing the area of ​​the circuit units within the target region; if the layout margin of the target region is less than the third threshold, and / or the routing margin of the target region is less than the fourth threshold, then a second constraint is added to the target region; the second constraint prohibits timing repair by inserting new circuit units in the routing of the timing violation path in the target region.

[0012] In this embodiment, different constraints are set for target regions with different margins. For target regions with larger margins, a first constraint is set to allow for more types of repair methods to be used in these regions, thereby improving repair efficiency. For target regions with smaller margins, a second constraint is set to strictly prohibit the addition of circuit units in the windings within these target regions, so as to avoid affecting the existing circuit units and windings in these regions, thereby effectively reducing the possibility of new problems occurring and improving the repair efficiency of timing violation paths.

[0013] In one embodiment, after repairing the timing violation paths within the chip based on the constraints of each region, the method further includes: if there are timing violation paths within the chip that cannot be repaired, then relaxing the preset threshold conditions.

[0014] In this embodiment, if the timing violation path clock cannot be repaired, it may be because the current preset threshold condition is set too small, making it impossible to adjust some areas with large margins. Repairing timing violation paths in such areas is more complicated and may require adjusting too many areas, which can easily cause new problems. Therefore, the preset threshold condition can be relaxed to reduce the areas that do not meet the preset threshold condition, so as to reduce new problems caused during repair.

[0015] In one embodiment, determining the layout margin and routing margin of each region in the chip based on the chip design file and preset margin calculation rules includes: for each region: extracting the circuit unit information of the region from the chip design file; the circuit unit information includes the circuit unit type in the region, the number of each circuit unit type, and the area of ​​the chip occupied by each circuit unit type; calculating the layout margin of the region based on the calculation relationship between the circuit unit information and the layout margin, the circuit unit type, the number, and the area; and extracting the routing information of the region from the chip design file, the routing information includes the number of routing lines passing through the region, the routing line width, the line spacing, and the side length of the region; calculating the routing margin of the region based on the calculation relationship between the routing information and the routing margin, the number of routing lines, the routing line width, the line spacing, and the side length of the region.

[0016] In this embodiment, the routing margin is related to the number of wires, wire width, wire spacing, and area. Therefore, the routing margin of a region can be calculated based on the calculation relationship between routing information and routing margin, the number of wires, wire width, wire spacing, and the side length of the region. By calculating both layout margin and routing margin, both are considered when setting constraints. Compared to considering only layout margin, this effectively reduces changes to areas with limited routing resources, thereby reducing new problems caused by timing violation path repair in areas with limited routing resources.

[0017] In one embodiment, the plurality of regions are divided according to a preset target size; wherein the target size is obtained based on the following method: the chip is divided into a plurality of regions using a plurality of preset sizes; the layout margin and wiring margin of each region of the chip under each preset size are calculated; based on the layout margin and wiring margin of each region of the chip under each preset size, a division evaluation value corresponding to each preset size is determined; the preset size with the highest division evaluation value is the target size.

[0018] There are various ways to divide a chip, and the layout margin and routing margin are different under different division methods. If there are too many constrained areas after division, the options for repair are small and the utilization rate of each area is low. In this embodiment, the preset size with the highest division evaluation value is selected as the target size, so that the layout margin and routing margin of each area after division are large, thereby reducing the proportion of constrained areas, which facilitates the selection of areas during repair and improves the utilization rate of areas.

[0019] In one embodiment, the method further includes: performing static timing analysis on the chip to determine all timing violation paths in the chip and the circuit units and windings with timing violations in each timing violation path; marking the regions involved in each timing violation path; and marking the circuit units and windings with timing violations.

[0020] In one embodiment, the areas involved in timing violation paths, the circuit units with timing violations, and the windings are marked so that users can quickly identify the problems in the timing violation paths. This makes it easier for users to confirm whether the current timing violation path repair method is reasonable, so that unreasonable repair methods can be adjusted in a timely manner, thereby improving the repair efficiency of timing violation paths.

[0021] Secondly, embodiments of this application also provide a timing path repair apparatus, comprising: a margin analysis module, used to determine the layout margin and routing margin of each region in the chip based on a chip design file and a preset margin calculation rule; the chip is divided into multiple regions; for each region: the layout margin of the region represents the free layout space of the region, and the routing margin of the region represents the free routing space of the region; the chip design file includes circuit unit information and routing information of the chip; the preset margin calculation rule includes: the calculation relationship between circuit unit information and layout margin, and the calculation relationship between routing information and routing margin; a judgment module, used to determine whether the layout margin and routing margin of each region meet a preset threshold condition; a constraint module, used to add constraints to each target region in each region that does not meet the preset threshold condition; the added constraints are used to restrict the adjustment method of the circuit units in the target region to which the constraint belongs during timing violation path repair; and a repair module, used to repair the timing violation path in the chip based on the constraints of each region.

[0022] Thirdly, embodiments of this application provide an electronic device, including a memory and a processor, wherein the memory stores computer-readable instructions, which are executed by the processor to perform the method as described in the first aspect.

[0023] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to perform the method described in the first aspect. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A flowchart of a timing path repair method provided in an embodiment of this application;

[0026] Figure 2 This is a schematic diagram of the region division provided for an embodiment of this application;

[0027] Figure 3 A constraint diagram provided for an embodiment of this application;

[0028] Figure 4 A schematic diagram of a repair provided in an embodiment of this application;

[0029] Figure 5 A schematic diagram of a timing path repair device provided in an embodiment of this application;

[0030] Figure 6 This is a schematic diagram of an electronic device provided in an embodiment of this application.

[0031] Icons: Timing path repair device 200; Margin analysis module 210; Judgment module 220; Constraint module 230; Repair module 240; Electronic device 300; Processor 310; Memory 320. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0033] Please see Figure 1 , Figure 1 A flowchart illustrating a timing path repair method provided in one embodiment of this application. The timing path repair method includes:

[0034] S110 determines the layout margin and routing margin of each region in the chip based on the chip design file and preset margin calculation rules.

[0035] In this embodiment, the chip is divided into multiple regions. For each region: the layout margin of the region represents the free layout space of the region, which can be calculated by the area occupied by the circuit units in the region and the total area of ​​the region. Correspondingly, the wiring margin of the region represents the free wiring space of the region, which can be calculated by the actual number of wires passing through the circuit units in the region and the total number of wires that can pass through the region.

[0036] In the back-end design of a chip, timing path repair is performed after the circuit design and placement and routing are completed. At this point, the chip has a complete structure. Therefore, a complete chip can be divided into multiple regions.

[0037] like Figure 2 As shown, a chip can be divided according to a preset size, such as... Figure 2 A 40µm × 40µm chip can be divided into 16 10µm × 10µm regions. Different types of chips may have different sizes; the above is just an example. The specific dimensions of the chip are fully recorded in the chip design file and will not be elaborated here.

[0038] In this embodiment, the chip design file records various parameters of the chip, including circuit unit information such as the location, quantity, type, and area occupied by each circuit unit in the chip, as well as winding information such as the location, quantity, line width, and line spacing of the wires. For example, the chip design file may include DEF (Design Exchange Format) files and LEF (Library Exchange Format) files, or the chip design file may include GDS (Graphic Data System) files. The chip design file may also be other files that include circuit unit information and winding information, which will not be elaborated here.

[0039] In one embodiment, for any region, the process of calculating the layout margin of that region may include: extracting circuit cell information of that region from the chip design file; and calculating the layout margin of that region based on the calculation relationship between the circuit cell information and the layout margin, and the circuit cell type, number, and area in the circuit cell information.

[0040] As mentioned earlier, the circuit unit information in the chip design file can include the location information of the circuit unit. Based on the location information, the region to which the circuit unit belongs can be determined. Thus, the content, quantity, and other information of all circuit units in each region of the chip can be determined.

[0041] Meanwhile, during chip design, the area of ​​each circuit unit is defined. For example, in one chip, the cache circuit unit occupies an area of ​​8.78 square micrometers. The chip area occupied by each circuit unit is defined in the chip design file. Therefore, through the chip design file, various circuit unit information, including the type of circuit unit in that area, the number of each circuit unit type, and the chip area occupied by each circuit unit type, can be extracted.

[0042] Accordingly, the layout margin is equal to the difference between the total area of ​​the region and the total area occupied by each circuit unit, minus the total area of ​​the region, i.e.:

[0043]

[0044] The total area of ​​a region can be calculated based on the dimensions of the divided regions. The area occupied by a certain circuit unit in a region is equal to the number of that circuit unit in that region multiplied by the chip area occupied by that type of circuit unit. The total area occupied by all circuit units is equal to the sum of the areas occupied by all circuit units in that region.

[0045] Similarly, in one embodiment, for any region, the process of calculating the routing margin of that region includes: extracting the routing information of that region from the chip design file; and calculating the routing margin of that region based on the calculation relationship between the routing information and the routing margin, the number of routing lines, the routing line width, the line spacing, and the side length of that region.

[0046] As mentioned earlier, chip design files can also include routing information, such as the location, number, line width, and spacing of the routing wires. The location of the routing wires determines the areas they pass through, and thus the number of routing wires passing through each area. For each area, the actual number of routing wires passing through it can be determined. Similarly, chip design files also include information such as the line width and spacing of the routing wires, which can be directly extracted from the chip design file. The total number of routing wires that can pass through an area is equal to the area's side length divided by the sum of the line width and the line spacing.

[0047] After obtaining the routing information, the routing margin for that area can be calculated. The routing margin is equal to the ratio of the difference between the total number of routes that can pass through the area and the actual number of routes that pass through the area, to the total number of routes that can pass through the area.

[0048]

[0049] The layout margin and routing margin can be calculated using the above method.

[0050] In some embodiments, after obtaining the routing margin and layout margin of each region, the layout margin and routing margin can be marked on the corresponding region to facilitate the user's access to the layout margin and routing margin information, thereby helping the user to identify potential problems during the timing violation repair process. Figure 3 As shown, layout margins and wiring margins can be marked in each area.

[0051] Layout and routing margins are related to the area of ​​the partitioned region. In real-world scenarios, the circuit units and wiring of different parts of a chip design vary, resulting in differences in the layout and routing margins calculated when partitioning the chip to different sizes. Therefore, during actual partitioning, a target size needs to be determined so that the partitioned region can maintain a relatively large layout and routing margin between each region, thus facilitating the selection of repair locations when fixing timing violation paths.

[0052] In some embodiments, the multiple regions of the chip can be divided according to a preset target size. The target size can be obtained by: dividing the chip into multiple regions using multiple preset sizes; calculating the layout margin and routing margin of each region of the chip under each preset size; determining the division evaluation value corresponding to each preset size based on the layout margin and routing margin of each region of the chip under each preset size; and determining the preset size with the highest division evaluation value as the target size.

[0053] For example, a 40um×40um chip can be divided into sizes such as 4um×4um, 5um×5um, and 10um×10um.

[0054] In this embodiment, different sizes can be used as preset sizes to divide the same chip, and the layout margin and routing margin corresponding to each region after division by different preset sizes are calculated. Then, the layout margin and routing margin of each region are used to calculate the division evaluation value, and the preset size corresponding to the highest division evaluation value is selected as the target size. Among them, the division evaluation value corresponding to a preset size can be calculated by using the square root, average value, weighted average, covariance, etc. of the layout margin or routing margin of all regions obtained by dividing by that size.

[0055] There are various ways to partition a chip, and the layout and routing margins differ depending on the partitioning method. If too many regions are constrained after partitioning, the options for repair are limited, resulting in low utilization of each region. Therefore, in this embodiment, the partitioning evaluation values ​​of layout and routing margins are calculated, and the preset size with the highest partitioning evaluation value is selected as the target size. This ensures that the layout and routing margins of each region are large after partitioning, reducing the proportion of constrained regions and facilitating region selection during repair, thereby improving region utilization. Note that the layout and routing margins are proportions relative to the free space in the region, rather than specific dimensions.

[0056] In some embodiments, after dividing the region, static timing analysis can be performed on the chip to determine all timing violation paths in the chip, as well as the circuit units and windings with timing violations in each timing violation path; the regions involved in each timing violation path are marked, as well as the circuit units and windings with timing violations are marked.

[0057] Static timing analysis is used to determine the path of timing violations and the circuit unit and winding of the timing violation. For details, please refer to existing technologies, which will not be elaborated here.

[0058] After identifying the timing violation paths, the areas involved in each path can be marked. Marking methods include, but are not limited to, numbers, symbols, and lines. Different colored lines and symbols can be used to distinguish different timing violation paths. For example... Figure 3 As shown, the timing violation path includes five regions: top left, bottom left, bottom center, bottom right, and top right, which are connected by lines. The small rectangles can represent the circuit units where timing violations occur.

[0059] In some embodiments, the names of the timing violation circuit cells or windings may also be recorded in this area.

[0060] By marking timing violation circuits, users can analyze the circuits during timing violation repair to obtain information about the timing violation circuits, identify the problem, and thus improve the repair efficiency of timing violation circuits.

[0061] S120, determine whether the layout margin and wiring margin of each area meet the preset threshold conditions.

[0062] In this embodiment, the preset threshold condition is a pre-set margin value that allows the insertion of new circuit units without affecting the original circuit units, the winding operation, and the timing.

[0063] In this embodiment, if the layout margin or wiring margin of a region does not meet the preset threshold condition, it indicates that there is insufficient space to lay out circuit units or lay out windings in that region. Therefore, when repairing timing violation paths, the adjustment method used for repair in that region needs to be restricted.

[0064] In one embodiment, the layout margin and routing margin can each be set with corresponding thresholds. For example, the threshold corresponding to the layout margin is a first threshold, and the margin corresponding to the routing margin is a second threshold. For example, the first threshold can be 15%, and the second threshold can be 10%.

[0065] In some embodiments, a stepped threshold can be set, with different limiting methods for different threshold steps. For example, a first threshold and a third threshold can be set for layout margin, with the third threshold being less than or equal to the first threshold; a second threshold and a fourth threshold can be set for routing margin, with the fourth threshold being less than the third threshold. For example, the first threshold could be 15%, the second threshold could be 10%, the third threshold could be 12%, and the fourth threshold could be 8%. These are merely examples and should not be considered limitations of this application. Different chips have different setting methods, which will not be described in detail here.

[0066] S130, add constraints to each target region that does not meet the preset threshold conditions in each region.

[0067] In this embodiment, the added constraint is used to restrict the adjustment method of circuit units within the target area to which the constraint belongs during timing violation path repair.

[0068] When repairing timing violation paths, the circuit cells along those paths are typically adjusted, including inserting or deleting some cells and modifying their structure. These adjustments can affect the area occupied by the circuit cells on the chip, thus reducing the layout margin in the area where the circuit cells are located. Simultaneously, due to the adjustment of the circuit cells, the routing may also be adjusted, such as adding routing or increasing the length of routing depending on the position, thus changing the routing margin. Insufficient layout and routing margins can lead to short circuits, non-compliance with design rules, and other issues.

[0069] Therefore, when repairing timing violation paths, adjustments should be restricted to areas with insufficient margin. This could include limiting the addition of circuit units in those areas, or limiting the area occupied by those circuit units.

[0070] In the embodiments of this application, if there is a target area that does not meet the preset threshold conditions, for example, if the layout margin of a certain area is less than the first threshold or the wiring margin is less than the second threshold, then constraints can be imposed on that area.

[0071] In one embodiment, a first constraint may be added to each target region; the first constraint prohibits timing repair by increasing the area of ​​circuit cells within the target region.

[0072] Since the first constraint prohibits increasing the area of ​​circuit units within the target region, during repair, the area of ​​the circuit units can only be reduced, or the newly added circuit units can be connected to other regions. Reducing the circuit area and connecting the circuit units to other regions do not affect the winding of the target region, which can effectively reduce the changes in winding caused by timing violation repair, thereby reducing new timing violations caused by changes in winding, thus reducing the iteration process during repair and improving repair efficiency.

[0073] In one embodiment, a second constraint may be added to each target region; the second constraint prohibits timing from being repaired by inserting new circuit units into the routing of the timing violation path in the target region.

[0074] In this embodiment, the second constraint can also be referred to as locking, meaning that inserting circuit units in the middle of any routing is prohibited within this area. It is understood that inserting circuit units occupies a certain amount of chip area, further reducing layout and routing margins. If the area itself has limited free space, the routing must be adjusted after a new circuit unit occupies some area, or may even be unable to be adjusted, causing new timing violations or short circuits. Therefore, for areas with insufficient margin, a second constraint can be added to prohibit the insertion of new circuit units.

[0075] In some embodiments of this application, the preset threshold conditions include a first threshold, a second threshold, a third threshold, and a fourth threshold. The third threshold is less than the first threshold, and the fourth threshold is less than the second threshold. For any target area, if the layout margin of the target area is between the first threshold and the third threshold, and / or the wiring margin of the target area is between the second threshold and the fourth threshold, then a first constraint is added to the target area. If the layout margin of the target area is less than the third threshold, and / or the wiring margin of the target area is less than the fourth threshold, then a second constraint is added to the target area.

[0076] For example, such as Figure 3 As shown, for all areas in the first row and the bottom right corner area, the layout margin is greater than the first threshold, and the routing margin is greater than the second threshold, satisfying the preset threshold conditions. For the bottom left area, the layout margin is less than the first threshold, so a first constraint can be set for this area. For the bottom middle area, the routing margin is less than the fourth threshold, so a second constraint can be set.

[0077] Different constraints are set for different layout and routing margins. When the margin allows, a wider first constraint is set to reduce the requirements and difficulty of repairing timing violation paths. When the margin is insufficient, a stricter second constraint is set to reduce the possibility of new problems caused by repairing timing violation paths.

[0078] S140, repairs timing violation paths within the chip based on constraints in each region.

[0079] In this embodiment, repairing a timing violation path can involve adjusting existing circuit units along the timing violation path or adding new circuit units to the timing violation path. For example, ... Figure 4 As shown, for a timing violation path ABCD, circuit unit E can be inserted between any two adjacent circuit units A, B, C, and D to achieve timing adjustment and repair. For example, inserting E between C and D will change the path to ABCED.

[0080] In this embodiment of the application, the repair process must be carried out according to the constraints of each region. If a first constraint exists in the target region, then expanding the area of ​​the circuit units within that target region is prohibited. For example, as Figure 3 As shown, the area in the lower left corner is marked first, and the circuit units in this area adjust their timing by increasing the occupied chip area.

[0081] Similarly, Figure 3 If the middle area of ​​the second row is subject to the second constraint, then no new circuit units can be added along the path representing the lower left and lower right areas. New circuit units can only be added from the position between the lower right and upper right corners, or between the lower left and upper left corners.

[0082] In some embodiments, if there is an unrecoverable timing violation path in the chip memory, the preset threshold condition is relaxed.

[0083] For example, if the first threshold for layout margin is 20%, then a layout margin greater than 20% is considered to meet the preset threshold condition, requiring no additional constraints. A margin less than or equal to 20% is considered to fail to meet the preset threshold condition, requiring additional constraints. However, excessive margins less than or equal to 20% necessitate placing the inserted circuit units at relatively far locations during timing violation path repair, potentially leading to significant changes in the routing and affecting the traversed areas, causing problems in some intermediate regions. Therefore, the preset threshold condition can be relaxed to allow more margin to support the adjustment areas participating in the timing path repair process, reducing the possibility of new problems and improving repair efficiency.

[0084] In this embodiment, relaxing the preset threshold condition means reducing the threshold. For example, the values ​​of the first threshold and the second threshold can be reduced. For instance, if the first threshold is changed from 15% to 10%, the range that originally met the preset condition is relaxed from 15% to 100% to 10% to 10% to 100%. And for those who do not meet the preset threshold condition, the range is reduced from 0 to 15% to 0 to 10%.

[0085] In addition, the repair of timing violation paths may be iterated multiple times. Each time the repair is performed, if the size and method of the divided area remain unchanged, and the circuit units and windings in the area have not changed, the layout margin and routing margin obtained from the previous calculation can be used, or they can be recalculated. Users can set this according to their needs.

[0086] In this embodiment, before performing timing violation path repair, layout margin and routing margin are considered. Constraints are added to areas where the layout margin and routing margin do not meet the preset threshold conditions to restrict their participation in timing violation path repair. This reduces new problems caused by insufficient space during repair, thereby reducing the number of iterations required for timing violation path repair, improving repair efficiency, and thus improving chip design efficiency.

[0087] Based on the same inventive concept, embodiments of this application also provide a timing path repair device. Please refer to... Figure 5 , Figure 5 This is a schematic diagram of a timing path repair device provided in an embodiment of this application. The timing path repair device 200 includes: a margin analysis module 210, a judgment module 220, a constraint module 230, and a repair module 240.

[0088] The margin analysis module 210 is used to determine the layout margin and routing margin of each region in the chip based on the chip design file and preset margin calculation rules. The chip is divided into multiple regions. For each region: the layout margin of the region represents the free layout space of the region, and the routing margin of the region represents the free routing space of the region. The chip design file includes the circuit unit information and routing information of the chip. The preset margin calculation rules include: the calculation relationship between the circuit unit information and the layout margin, and the calculation relationship between the routing information and the routing margin.

[0089] The judgment module 220 is used to determine whether the layout margin and the wiring margin of each region meet the preset threshold conditions.

[0090] The constraint module 230 is used to add constraints to each target region that does not meet the preset threshold conditions in each region; the added constraints are used to restrict the adjustment method of the circuit units in the target region to which the constraint belongs during the timing violation path repair.

[0091] Repair module 240 is used to repair timing violation paths within the chip based on constraints of each region.

[0092] The constraint module 230 is also used to add a first constraint to each target region; the first constraint prohibits timing repair by increasing the area of ​​the circuit unit in the target region.

[0093] The constraint module 230 is also used to add a second constraint to each target region; the second constraint prohibits timing from being repaired by inserting new circuit units into the winding of the timing violation path in the target region.

[0094] The judgment module 220 is preset with a first threshold, a second threshold, a third threshold and a fourth threshold. The third threshold is less than or equal to the first threshold and the fourth threshold is less than the second threshold. The judgment module 220 is also used to judge the relationship between the layout margin of the area and the first threshold and the third threshold, as well as the relationship between the wiring margin of the area and the second threshold and the fourth threshold.

[0095] For any of the target regions, the constraint module 230 is further configured to add a first constraint to the target region if the layout margin of the target region is between a first threshold and a third threshold, and / or the routing margin of the target region is between a second threshold and a fourth threshold; the first constraint prohibits timing repair by increasing the area of ​​the circuit cells in the target region; if the layout margin of the target region is less than the third threshold, and / or the routing margin of the target region is less than the fourth threshold, a second constraint is added to the target region; the second constraint prohibits timing repair by inserting new circuit cells in the routing of the timing violation path in the target region.

[0096] In one embodiment, the determination module 220 is further configured to relax the preset threshold condition if there is a timing violation path in the chip memory that cannot be repaired.

[0097] In one embodiment, for each region, the margin analysis module 210 is further configured to extract circuit unit information of that region from the chip design file; the circuit unit information includes the type of circuit unit in that region, the number of each type of circuit unit, and the area of ​​the chip occupied by each type of circuit unit; calculate the layout margin of that region based on the calculation relationship between the circuit unit information and the layout margin, the type of circuit unit, the number of circuit units, and the area; and extract the routing information of that region from the chip design file, the routing information including the number of routing lines passing through that region, the routing line width, the line spacing, and the side length of that region; calculate the routing margin of that region based on the calculation relationship between the routing information and the routing margin, the number of routing lines, the routing line width, the line spacing, and the side length of that region.

[0098] In one embodiment, multiple regions are divided according to a preset target size; the margin analysis module 210 can obtain the target size based on the following method: dividing the chip into multiple regions using multiple preset sizes; calculating the layout margin and wiring margin of each region of the chip under each preset size; determining the division evaluation value corresponding to each preset size based on the layout margin and wiring margin of each region of the chip under each preset size; the preset size with the highest division evaluation value is the target size.

[0099] In one embodiment, the determination module 220 is further configured to perform static timing analysis on the chip, determine all timing violation paths in the chip and the circuit units and windings with timing violations in each timing violation path; mark the areas involved in each timing violation path; and mark the circuit units and windings with timing violations.

[0100] It is understood that the function implemented by the timing path repair device 200 is similar to the aforementioned timing path repair method. For details, please refer to the aforementioned timing path repair method, which will not be elaborated here.

[0101] Please refer to Figure 6 Based on the same inventive concept, this application also provides an electronic device 300, which can serve as the execution subject of the aforementioned timing path repair method. That is, it can be a server device, including a processor 310 and a memory 320 that is communicatively connected to the processor 310, and can utilize the resources including the processor 310 and the memory 320 to deploy multiple virtual systems.

[0102] In this embodiment, the memory 320 may store computer-readable instructions that can be executed by the processor 310. The computer-readable instructions are executed by the processor 310 so that the processor 310 can perform the timing path repair method in the foregoing embodiment.

[0103] The processor 310 and the memory 320 can be connected via a communication bus.

[0104] Processor 310 can be an integrated circuit chip with signal processing capabilities. Processor 310 can be a general-purpose processor, including a CPU, NP (Network Processor), etc.; it can also be a digital signal processor, application-specific integrated circuit, off-the-shelf programmable gate array, or other programmable logic device or transistor logic device, or discrete hardware component. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor.

[0105] The memory 320 may include, but is not limited to, RAM (Random Access Memory), ROM (Read Only Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electric Erasable Programmable Read-Only Memory), etc.

[0106] It is understood that the electronic device 300 may also include more general modules required by itself, which will not be described one by one in the embodiments of this application.

[0107] Based on the same inventive concept, embodiments of this application also provide a computer-readable storage medium storing a computer program thereon, which executes the methods provided in the above embodiments when the computer program is run.

[0108] The storage medium can be any available medium that a computer can access, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., SSDs (Solid State Disks)).

[0109] In the embodiments provided in this application, it should be understood that the disclosed methods and apparatus can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. The functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0110] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, external hard drives, ROM, RAM, magnetic disks, or optical disks.

[0111] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0112] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A time-series path repair method, characterized in that, include: The layout margin and routing margin of each region in the chip are determined based on the chip design documents and preset margin calculation rules. The chip is divided into multiple regions; For each of the regions: the layout margin of the region represents the free layout space of the region, and the wiring margin of the region represents the free wiring space of the region; The chip design file includes the chip's circuit unit information and winding information; The preset margin calculation rules include: the calculation relationship between circuit unit information and layout margin, and the calculation relationship between winding information and wiring margin; Determine whether the layout margin and wiring margin of each region meet the preset threshold conditions; Constraints are added to each target region that does not meet the preset threshold condition in each of the aforementioned regions; the added constraints are used to limit the adjustment method of the circuit units in the target region to which the constraint belongs during timing violation path repair; Repairing timing violation paths within the chip based on constraints of each of the aforementioned regions; The method of determining the layout margin and routing margin of each region in the chip based on the chip design file and preset margin calculation rules includes: for each region: extracting the circuit unit information of the region from the chip design file; the circuit unit information includes the circuit unit type in the region, the number of each circuit unit type, and the area of ​​the chip occupied by each circuit unit type; calculating the layout margin of the region based on the calculation relationship between the circuit unit information and the layout margin, the circuit unit type, the number, and the area; and extracting the routing information of the region from the chip design file, the routing information includes the number of routing lines passing through the region, the routing line width, the line spacing, and the side length of the region; calculating the routing margin of the region based on the calculation relationship between the routing information and the routing margin, the number of routing lines, the routing line width, the line spacing, and the side length of the region.

2. The timing path repair method according to claim 1, characterized in that, The addition of constraints to target regions that do not meet the preset threshold conditions in each of the aforementioned regions includes: A first constraint is added to each of the target regions; the first constraint prohibits timing repair by increasing the area of ​​the circuit units within the target region.

3. The timing path repair method according to claim 1, characterized in that, The addition of constraints to target regions that do not meet the preset threshold conditions in each of the aforementioned regions includes: A second constraint is added to each of the target regions; the second constraint prohibits timing repair by inserting new circuit units in the winding of the timing violation path in the target region.

4. The timing path repair method according to claim 1, characterized in that, The preset threshold conditions include a first threshold, a second threshold, a third threshold, and a fourth threshold, wherein the third threshold is less than or equal to the first threshold, and the fourth threshold is less than the second threshold; The addition of constraints to target regions that do not meet the preset threshold conditions in each of the aforementioned regions includes: For any one of the target regions If the layout margin of the target area is between the first threshold and the third threshold, and / or the wiring margin of the target area is between the second threshold and the fourth threshold, then a first constraint is added to the target area; the first constraint prohibits timing from being repaired by increasing the area of ​​the circuit cells in the target area; If the layout margin of the target area is less than the third threshold, and / or the routing margin of the target area is less than the fourth threshold, then a second constraint is added to the target area; the second constraint prohibits timing repair by inserting new circuit units in the routing of the target area on the timing violation path.

5. The timing path repair method according to claim 1, characterized in that, After repairing the timing violation paths within the chip based on the constraints of each of the aforementioned regions, the method further includes: If there is an unrecoverable timing violation path in the chip memory, the preset threshold condition is relaxed.

6. The timing path repair method according to claim 1, characterized in that, The multiple regions are divided according to a preset target size; wherein, the target size is obtained based on the following method: The chip is divided into multiple regions using multiple preset sizes; Calculate the layout margin and wiring margin of each region of the chip under each preset size; Based on the layout margin and wiring margin of each region of the chip under each preset size, the partitioning evaluation value corresponding to each preset size is determined; the preset size with the highest partitioning evaluation value is the target size.

7. The timing path repair method according to any one of claims 1-6, characterized in that, The method further includes: Static timing analysis is performed on the chip to determine all timing violation paths in the chip, as well as the circuit units and windings with timing violations in each timing violation path. The regions involved in each of the aforementioned timing violation paths are marked; The circuit cells with timing violations and the windings with timing violations are marked.

8. A timing path repair device, characterized in that, include: The margin analysis module is used to determine the layout margin and routing margin of each region in the chip based on the chip design file and preset margin calculation rules; The chip is divided into multiple regions; for each region: the layout margin of the region represents the free layout space of the region, and the wiring margin of the region represents the free wiring space of the region; The chip design file includes the chip's circuit unit information and winding information; The preset margin calculation rules include: the calculation relationship between circuit unit information and layout margin, and the calculation relationship between winding information and wiring margin; The judgment module is used to determine whether the layout margin and the wiring margin of each region meet the preset threshold conditions; The constraint module is used to add constraints to each target region that does not meet the preset threshold condition in each of the regions; the added constraints are used to restrict the adjustment method of the circuit units in the target region to which the constraint belongs during timing violation path repair. The repair module is used to repair timing violation paths within the chip based on the constraints of each of the regions. For each of the aforementioned regions, the margin analysis module is further configured to: extract the circuit unit information of the region from the chip design file; the circuit unit information includes the circuit unit type in the region, the number of each circuit unit type, and the chip area occupied by each circuit unit type; calculate the layout margin of the region based on the calculation relationship between the circuit unit information and the layout margin, the circuit unit type, the number, and the area; and extract the routing information of the region from the chip design file, the routing information including the number of routings passing through the region, the routing line width, the line spacing, and the side length of the region; calculate the routing margin of the region based on the calculation relationship between the routing information and the routing margin, the number of routings, the routing line width, the line spacing, and the side length of the region.

9. An electronic device, characterized in that, The device includes a memory and a processor, wherein the memory stores computer-readable instructions that, when executed by the processor, cause the processor to perform the timing path repair method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The readable storage medium stores a computer program that, when run on a computer, causes the computer to perform the timing path repair method as described in any one of claims 1-7.

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