Driving circuit and driving method thereof, memory

Abstract

The application provides a driving circuit, a driving method thereof and a memory. The driving circuit comprises a word line driving circuit and a first control circuit. The word line driving circuit comprises an input end, an output end and at least one N-type transistor. The word line driving circuit is configured to provide an output signal to the output end according to an input signal received by the input end. The first control circuit is configured to lower a substrate end voltage of the at least one N-type transistor in the word line driving circuit when the input signal is a first control signal, so as to reduce a leakage current of the at least one N-type transistor. The driving circuit can improve the leakage problem of the N-type transistor in the word line driving circuit, and further improve the performance of the memory.

Description

Technical Field

[0001] This application relates to, but is not limited to, a driving circuit and its driving method, and a memory. Background Technology

[0002] The memory includes a word line driver circuit (SWD), which outputs a high-level signal or a low-level signal to the memory cell through the word line, thereby realizing the read and write operation of the memory cell.

[0003] If the word line is in a high-level state for a long time, and the leakage current of the N-type transistor in the word line driving circuit is too large, the high-level signal output by the word line driving circuit may not be able to effectively reach the word line, which may result in the inability to effectively drive the memory cell to perform read and write operations, thereby affecting the performance of the memory. Summary of the Invention

[0004] This application provides a driving circuit and driving method thereof, as well as a memory, which can reduce the leakage current of N-type transistors in word line driving circuits and improve memory performance.

[0005] In a first aspect, this application provides a driving circuit, comprising:

[0006] A word line driving circuit includes an input terminal and an output terminal, the word line driving circuit being configured to provide an output signal to the output terminal according to an input signal received at the input terminal, the word line driving circuit including at least one N-type transistor;

[0007] A first control circuit is configured to reduce the substrate voltage of the at least one N-type transistor when the input signal is a first control signal, so as to reduce the leakage current of the at least one N-type transistor.

[0008] In some embodiments, the first control circuit includes a second P-type transistor, whose gate is connected to the input terminal of the word line driving circuit, whose first terminal is connected to the substrate terminal of the at least one N-type transistor, and whose second terminal is connected to a third signal terminal.

[0009] The third signal terminal is configured to provide a third voltage when the second P-type transistor is turned on.

[0010] In some embodiments, the third voltage is below zero.

[0011] In some embodiments, the word line driving circuit includes a first P-type transistor and a first N-type transistor;

[0012] The gate of the first P-type transistor and the gate of the first N-type transistor are interconnected and serve as the input terminal of the word line driving circuit.

[0013] The first terminal of the first P-type transistor and the first terminal of the first N-type transistor are connected to each other and serve as the output terminal of the word line driving circuit.

[0014] The substrate of the first N-type transistor is connected to the first terminal of the second P-type transistor.

[0015] In some embodiments, the second terminal of the first P-type transistor is connected to the first signal terminal, and the second terminal of the first N-type transistor is connected to the second signal terminal;

[0016] The first signal terminal is configured to provide a first voltage when the first P-type transistor is turned on, and the second signal terminal is configured to provide a second voltage when the first N-type transistor is turned on;

[0017] Wherein, the first voltage is greater than the second voltage.

[0018] In some embodiments, the word line driving circuit further includes:

[0019] The second N-type transistor has its first terminal connected to the output terminal of the word line driving circuit, its second terminal connected to the second terminal of the first N-type transistor, and its gate connected to the input terminal or control signal terminal of the word line driving circuit.

[0020] The control signal terminal is configured to provide a control signal that is in phase with the input signal.

[0021] In some embodiments, the substrate of the second N-type transistor is connected to the first electrode of the second P-type transistor.

[0022] In some embodiments, it also includes:

[0023] The second control circuit is configured to increase the substrate voltage of the at least one N-type transistor when the input signal is the second control signal, so as to reduce the threshold voltage of the at least one N-type transistor.

[0024] The level of the second control signal is different from the level of the first control signal.

[0025] In some embodiments, the level of the first control signal is lower than the level of the second control signal.

[0026] In some embodiments, the second control circuit includes a third N-type transistor, whose gate is connected to the input terminal of the word line driving circuit, whose first terminal is connected to the substrate terminal of the at least one N-type transistor, and whose second terminal is connected to a fourth signal terminal.

[0027] The fourth signal terminal is configured to provide a fourth voltage when the third N-type transistor is turned on.

[0028] In some embodiments, the fourth voltage is greater than the third voltage.

[0029] In some embodiments, the first terminal of the third N-type transistor is connected to the substrate terminal of the first N-type transistor and the substrate terminal of the second N-type transistor.

[0030] In some embodiments, the input of the word line driving circuit is configured to connect to the main word line, and the output of the word line driving circuit is connected to the word line.

[0031] Secondly, this application provides a memory including the driving circuitry of the first aspect and any possible implementation thereof.

[0032] Thirdly, this application provides a driving method for the driving circuit according to the first aspect and any possible implementation of the first aspect, comprising:

[0033] Provide an input signal to the input terminal of the word line driving circuit so that the output terminal of the word line driving circuit provides an output signal; and

[0034] When the input signal is the first control signal, the substrate voltage of the at least one N-type transistor is reduced to decrease the leakage current of the at least one N-type transistor.

[0035] In some embodiments, the driving circuit further includes: a second control circuit configured to increase the substrate voltage of the at least one N-type transistor to decrease the threshold voltage of the at least one N-type transistor when the input signal is a second control signal, wherein the level of the second control signal is different from the level of the first control signal;

[0036] The driving method further includes:

[0037] When the input signal is the second control signal, the substrate voltage of the at least one N-type transistor is increased to reduce the threshold voltage of the at least one N-type transistor.

[0038] In some embodiments, the word line driving circuit includes a first P-type transistor and a first N-type transistor, the gates of the first P-type transistor and the first N-type transistor are connected to each other as the input terminal of the word line driving circuit, and the first terminals of the first P-type transistor and the first terminals of the first N-type transistor are connected to each other as the output terminal of the word line driving circuit.

[0039] The first control circuit includes a second P-type transistor, whose gate is connected to the input terminal of the word line driving circuit, whose first terminal is connected to the substrate terminal of the first N-type transistor, and whose second terminal is connected to the third signal terminal, the third signal terminal being configured to provide a third voltage when the second P-type transistor is turned on;

[0040] When the input signal is a first control signal, lowering the substrate voltage of the at least one N-type transistor to reduce the leakage current of the at least one N-type transistor includes:

[0041] When the input signal is the first control signal, the second P-type transistor is turned on, so that the substrate terminal of the first N-type transistor is connected to the third signal terminal, and the substrate terminal voltage of the first N-type transistor is reduced to reduce the leakage current of the first N-type transistor.

[0042] In some embodiments, the word line driving circuit includes a first P-type transistor and a first N-type transistor, the gates of the first P-type transistor and the first N-type transistor are connected to each other and serve as the input terminal of the word line driving circuit, and the first terminals of the first P-type transistor and the first terminals of the first N-type transistor are connected to each other and serve as the output terminal of the word line driving circuit.

[0043] The second control circuit includes a third N-type transistor, whose gate is connected to the input terminal of the word line driving circuit, whose first terminal is connected to the substrate terminal of the first N-type transistor, and whose second terminal is connected to a fourth signal terminal, the fourth signal terminal being configured to provide a fourth voltage when the third N-type transistor is turned on;

[0044] When the input signal is the second control signal, increasing the substrate voltage of the at least one N-type transistor to reduce the threshold voltage of the at least one N-type transistor includes:

[0045] When the input signal is the second control signal, the third N-type transistor is turned on, so that the substrate terminal of the first N-type transistor is connected to the fourth signal terminal, thereby reducing the threshold voltage of the first N-type transistor.

[0046] In some embodiments, the word line driving circuit includes a first P-type transistor, a first N-type transistor, and a second N-type transistor. The gates of the first P-type transistor and the first N-type transistor are interconnected and serve as the input terminal of the word line driving circuit. The first terminals of the first P-type transistor and the first terminals of the first N-type transistor are interconnected and serve as the output terminal of the word line driving circuit. The gate of the second N-type transistor is connected to either the input terminal or a control signal terminal of the word line driving circuit. The first terminal of the second N-type transistor is connected to the output terminal of the word line driving circuit. The second terminal of the second N-type transistor is connected to the second terminal of the first N-type transistor. The control signal terminal is configured to provide a control signal in phase with the input signal.

[0047] The first control circuit includes a second P-type transistor, whose gate is connected to the input terminal of the word line driving circuit, whose first terminal is connected to at least one of the substrate terminal of the first N-type transistor and the substrate terminal of the second N-type transistor, and whose second terminal is connected to a third signal terminal, the third signal terminal being configured to provide a third voltage when the second P-type transistor is turned on;

[0048] When the input signal is a first control signal, lowering the substrate voltage of the at least one N-type transistor to reduce the leakage current of the at least one N-type transistor includes:

[0049] Under the action of the first control signal as the input signal, the second P-type transistor is controlled to turn on, so that at least one of the substrate terminals of the first N-type transistor and the second N-type transistor is connected to the third signal terminal, and the substrate terminal voltage of at least one of the first N-type transistor and the second N-type transistor is reduced, so as to reduce the leakage current of at least one of the first N-type transistor and the second N-type transistor.

[0050] In some embodiments, the word line driving circuit includes a first P-type transistor, a first N-type transistor, and a second N-type transistor. The gates of the first P-type transistor and the first N-type transistor are interconnected and serve as the input terminal of the word line driving circuit. The first terminals of the first P-type transistor and the first terminals of the first N-type transistor are interconnected and serve as the output terminal of the word line driving circuit. The gate of the second N-type transistor is connected to either the input terminal or a control signal terminal of the word line driving circuit. The first terminal of the second N-type transistor is connected to the output terminal of the word line driving circuit. The second terminal of the second N-type transistor is connected to the second terminal of the first N-type transistor. The control signal terminal is configured to provide a control signal in phase with the input signal.

[0051] The second control circuit includes a third N-type transistor whose gate is connected to the input terminal of the word line driving circuit, whose first terminal is connected to at least one of the substrate terminal of the first N-type transistor and the substrate terminal of the second N-type transistor, and whose second terminal is connected to a fourth signal terminal, the fourth signal terminal being configured to provide a fourth voltage when the third N-type transistor is turned on.

[0052] When the input signal is a second control signal, increasing the substrate voltage of the at least one N-type transistor to decrease the threshold voltage of the at least one N-type transistor includes:

[0053] When the input signal is the second control signal, the third N-type transistor is controlled to turn on, so that at least one of the substrate terminals of the first N-type transistor and the second N-type transistor is connected to the fourth signal terminal, and the substrate terminal voltage of at least one of the first N-type transistor and the second N-type transistor is increased, so as to reduce the threshold voltage of at least one of the first N-type transistor and the second N-type transistor.

[0054] This application provides a driving circuit including a word line driving circuit and a first control circuit. The word line driving circuit includes an input terminal, an output terminal, and at least one N-type transistor. The word line driving circuit is configured to provide an output signal to the output terminal based on an input signal received at the input terminal. The first control circuit is configured to lower the substrate voltage of at least one N-type transistor in the word line driving circuit when the input signal is a first control signal, so as to reduce the leakage current of at least one N-type transistor, improve the leakage current problem of the N-type transistor in the word line driving circuit, and enable the high-level signal output by the word line driving circuit to effectively reach the word line, thereby improving the performance of the memory. Attached Figure Description

[0055] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0056] Figure 1-2 Circuit diagrams of two word line driving circuits provided in embodiments of this application;

[0057] Figure 3-6 A circuit diagram of a driving circuit provided in one embodiment of this application;

[0058] Figure 7-10 A circuit diagram of another driving circuit provided in one embodiment of this application;

[0059] Figure 11-14 A circuit diagram of another driving circuit provided in one embodiment of this application;

[0060] Figure 15This is a flowchart of a driving method provided in an embodiment of this application.

[0061] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0062] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0063] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the foregoing claims.

[0064] Figure 1 This is a circuit diagram of a word line driving circuit provided in one embodiment of this application. Figure 1 As shown, the word line driving circuit 101 includes an NMOS transistor and a PMOS transistor. The gates of the first N-type transistor N1 and the first P-type transistor P1 are interconnected as the input terminal IN of the word line driving circuit 101. The input terminal IN of the word line driving circuit 101 is connected to the main word line MWL and is used to receive the input signal provided by the main word line MWL. The first terminal of the first P-type transistor P1 and the first terminal of the first N-type transistor N1 are interconnected as the output terminal OUT of the word line driving circuit 101. The output terminal OUT of the word line driving circuit 101 is connected to the word line WL. Under the action of the input signal, the word line driving circuit 101 outputs a high-level signal or a low-level signal to the word line WL.

[0065] The second terminal of the first P-type transistor P1 is connected to the first signal terminal LWL. When the input signal is a first control signal (e.g., a low-level signal), the first N-type transistor N1 is turned off, the first P-type transistor P1 is turned on, and the first signal terminal LWL provides a first voltage (e.g., the first voltage is high-level). Then, the word line driving circuit 101 outputs a high-level signal to the word line WL. The second terminal of the first N-type transistor N1 is connected to the second signal terminal NBS. When the input signal is a second control signal (e.g., a high-level signal), the first P-type transistor P1 is turned off, the first N-type transistor N1 is turned on, and the second signal terminal NBS provides a second voltage (e.g., the second voltage is low-level). Then, the word line driving circuit 101 outputs a low-level signal to the word line WL. Thus, read and write operations can be performed on the memory cell via the word line WL. For example, in this application, the first terminal can be the drain, and the second terminal can be the source; or, the first terminal can be the source, and the second terminal can be the drain.

[0066] Figure 2 This is a circuit diagram of another word line driving circuit provided in one embodiment of this application. (See diagram below.) Figure 2 As shown, the word line driving circuit 101 includes two NMOS transistors and one PMOS transistor. The gates of the first N-type transistor N1 and the first P-type transistor P1 are connected to each other as the input terminal IN of the word line driving circuit 101. The first terminal of the first P-type transistor P1, the first terminal of the first N-type transistor N1, and the first terminal of the second N-type transistor N2 are connected to each other as the output terminal OUT of the word line driving circuit 101. The gate of the second N-type transistor N2 is connected to either the input terminal IN or the control signal terminal LWLB of the word line driving circuit 101. When the gate of the second N-type transistor N2 is connected to the control signal terminal LWLB, the control signal terminal LWLB can improve the turn-on speed of the second N-type transistor N2.

[0067] When the second terminal of the first P-type transistor P1 is connected to the first signal terminal LWL, and the gate of the second N-type transistor N2 is connected to the input terminal IN of the word line driving circuit 101, when the input signal is the first control signal, the first N-type transistor N1 and the second N-type transistor N2 are turned off, the first P-type transistor P1 is turned on, and the first signal terminal LWL provides the first voltage. When the gate of the second N-type transistor N2 is connected to the control signal terminal LWLB, and the input signal is the first control signal, the first N-type transistor N1 is turned off, the first P-type transistor P1 is turned on, and the control signal terminal LWLB provides a third control signal (e.g., a low-level signal). The third control signal is in phase with the input signal at this time (e.g., the duty cycle of the third control signal is the same as or slightly different from that of the first control signal). The second N-type transistor N2 is turned off under the action of the third control signal, and the first signal terminal LWL provides the first voltage.

[0068] The second terminals of the first N-type transistor N1 and the second terminals of the second N-type transistor N2 are connected and connected to the second signal terminal NBS. If the gate of the second N-type transistor N2 is connected to the input terminal IN of the word line driving circuit 101, and the input signal is the second control signal, the first P-type transistor P1 is turned off, and the first N-type transistor N1 and the second N-type transistor N2 are turned on, and the first signal terminal LWL provides the first voltage. If the gate of the second N-type transistor N2 is connected to the control signal terminal LWLB, and the input signal is the second control signal, the first P-type transistor P1 is turned off, and the first N-type transistor N1 is turned on. At the same time, the control signal terminal LWLB provides a fourth control signal (e.g., a high-level signal). The fourth control signal is in phase with the input signal at this time (e.g., the fourth control signal has the same or slightly different duty cycle as the second control signal). Then, the second N-type transistor N2 is turned on under the action of the fourth control signal, and the first N-type transistor N1 and the second N-type transistor N2 are turned on, which can pull down the voltage of the word line WL more quickly and effectively turn off the word line.

[0069] Figure 3-6 This is a circuit diagram of a driving circuit provided in one embodiment of this application. Figure 3-6 As shown, one embodiment of this application provides a driving circuit, including a word line driving circuit 101 and a first control circuit 102. The word line driving circuit 101 includes an input terminal IN, an output terminal OUT, and at least one N-type transistor. The word line driving circuit 101 is configured to provide an output signal to the output terminal OUT based on an input signal received at the input terminal IN. The first control circuit 102 is configured to lower the substrate voltage of at least one N-type transistor when the input signal is a first control signal, thereby reducing the leakage current of at least one N-type transistor. This improves the electrical performance of the N-type transistor, enabling the high-level signal output by the word line driving circuit to effectively reach the word line, improving leakage current during the burn-in test stage in chip probing (CP), enhancing the effectiveness of the burn-in test, and more effectively eliminating dead cells in the memory. Referring to Table 1, generally, the smaller the substrate voltage VB of an N-type transistor, the smaller the leakage current Ioff of that N-type transistor.

[0070] Table 1

[0071]

[0072]

[0073] In some embodiments, the first control circuit 102 includes a second P-type transistor P2. The gate of the second P-type transistor P2 is connected to the input terminal IN of the word line driving circuit 101. Its first terminal is connected to the substrate of at least one N-type transistor, and its second terminal is connected to a third signal terminal VNB. The third signal terminal VNB is configured to provide a third voltage when the second P-type transistor P2 is turned on. When the input signal received by the input terminal of the word line driving circuit 101 is a first control signal, the second P-type transistor P2 is turned on, and the third signal terminal VNB provides a third voltage to the substrate of at least one N-type transistor. This third voltage is low, thereby pulling down the substrate voltage of at least one N-type transistor and reducing its leakage current. For example, the third voltage can be below zero, thereby quickly pulling down the substrate voltage of at least one N-type transistor.

[0074] like Figure 3 As shown, the word line driving circuit 101 includes a first P-type transistor P1 and a first N-type transistor N1, and the first control circuit 102 includes a second P-type transistor P2. The gates of the first P-type transistor P1 and the first N-type transistor N1 are interconnected and serve as the input terminal IN of the word line driving circuit 101. The first terminals of the first P-type transistor P1 and the first terminals of the first N-type transistor N1 are interconnected and serve as the output terminal OUT of the word line driving circuit 101. The first terminal of the second P-type transistor P2 is connected to the substrate terminal of the first N-type transistor N1, thereby reducing the substrate terminal voltage of the first N-type transistor N1 and reducing the leakage current of the first N-type transistor N1. The second terminal of the first P-type transistor P1 is connected to the first signal terminal LWL, and the second terminal of the first N-type transistor N1 is connected to the second signal terminal NBS. The first signal terminal LWL is configured to provide a first voltage when the first P-type transistor P1 is turned on, thereby providing a high-level signal to the output terminal OUT. The second signal terminal NBS is configured to provide a second voltage when the first N-type transistor N1 is turned on, thereby providing a low-level signal to the output terminal OUT. In other words, the first voltage is greater than the second voltage.

[0075] When the input signal received by the input terminal IN of the word line driving circuit 101 is the first control signal, the first N-type transistor N1 is turned off, and the first P-type transistor P1 and the second P-type transistor P2 are turned on. The first signal terminal LWL provides the first voltage to the output terminal OUT of the word line driving circuit 101, and at the same time, the third signal terminal VNB provides the third voltage to the substrate terminal of the first N-type transistor N1, thereby pulling down the substrate terminal voltage of the first N-type transistor N1, reducing the leakage current of the first N-type transistor, so that the first voltage provided by the first signal terminal LWL can effectively reach the word line WL connected to the output terminal OUT.

[0076] like Figures 4-6As shown, the word line driving circuit 101 includes a first P-type transistor P1, a first N-type transistor N1, and a second N-type transistor N2. The first terminal of the second N-type transistor N2 is connected to the output terminal OUT of the word line driving circuit 101, and the second terminal of the second N-type transistor N2 is connected to the second terminal of the first N-type transistor N1. The gate of the second N-type transistor N2 is connected to the input terminal IN or the control signal terminal LWLB of the word line driving circuit 101. The first control circuit 102 includes a second P-type transistor P2, and the first terminal of the second P-type transistor P2 is connected to the substrate terminal of the first N-type transistor N1 and / or the substrate terminal of the second N-type transistor N2. When the input signal is the first control signal, the second P-type transistor P2 is turned on, reducing the substrate terminal voltage of the first N-type transistor N1 and / or the second N-type transistor N2, thereby reducing the leakage current of the first N-type transistor N1 and / or the second N-type transistor N2.

[0077] like Figure 4 As shown, the first terminal of the second P-type transistor P2 is connected to the substrate terminal of the first N-type transistor N1. When the input signal is the first control signal, the first N-type transistor N1 is turned off, and the first P-type transistor P1 and the second P-type transistor P2 are turned on. The first signal terminal LWL provides a first voltage to the output terminal OUT of the word line driving circuit 101, and the third signal terminal VNB provides a third voltage to the substrate terminal of the first N-type transistor N1, thereby pulling down the substrate terminal voltage of the first N-type transistor N1 and reducing the leakage current of the first N-type transistor N1, so that the first voltage provided by the first signal terminal LWL can effectively reach the word line WL connected to the output terminal OUT.

[0078] like Figure 5As shown, the first terminal of the second P-type transistor P2 is connected to the substrate of the second N-type transistor N2. If the gate of the second N-type transistor N2 is connected to the input terminal IN of the word line driving circuit 101, and the input signal is the first control signal, the first N-type transistor N1 and the second N-type transistor N2 are turned off, and the first P-type transistor P1 and the second P-type transistor P2 are turned on. The first signal terminal LWL provides a first voltage to the output terminal OUT of the word line driving circuit 101, and the third signal terminal VNB provides a third voltage to the substrate of the second N-type transistor N2, thereby pulling down the substrate voltage of the second N-type transistor N2 and reducing the leakage current of the second N-type transistor N2, so that the first voltage provided by the first signal terminal LWL can effectively reach the word line WL connected to the output terminal OUT. If the gate of the second N-type transistor N2 is connected to the control signal terminal LWLB, and the control signal terminal LWLB is configured to provide a control signal in phase with the input signal (for example, the control signal includes the third control signal and the fourth control signal described in this application), when the input signal is the first control signal, the first N-type transistor N1 is turned off, the first P-type transistor P1 and the second P-type transistor P2 are turned on, and the second N-type transistor N2 is turned off under the action of the third control signal provided by the control signal terminal LWLB. The first signal terminal LWL provides a first voltage to the output terminal OUT, and the third signal terminal VNB provides a third voltage to the substrate terminal of the second N-type transistor N2, thereby pulling down the substrate terminal voltage of the second N-type transistor N2, reducing the leakage current of the second N-type transistor N2, so that the first voltage provided by the first signal terminal LWL can effectively reach the word line WL connected to the output terminal OUT.

[0079] like Figure 6 As shown, the first terminal of the second P-type transistor P2 is connected to the substrate of the first N-type transistor N1 and the substrate of the second N-type transistor N2. If the gate of the second N-type transistor N2 is connected to the input terminal IN of the word line driving circuit 101, when the input signal is the first control signal, the first N-type transistor N1 and the second N-type transistor N2 are turned off, and the first P-type transistor P1 and the second P-type transistor P2 are turned on. The first signal terminal LWL provides a first voltage to the output terminal OUT, and the third signal terminal VNB provides a third voltage to the substrate of the first N-type transistor N1 and the second N-type transistor N2, thereby pulling down the substrate voltage of the first N-type transistor N1 and the second N-type transistor N2, reducing the leakage current of the first N-type transistor N1 and the second N-type transistor N2, so that the first voltage provided by the first signal terminal LWL can effectively reach the word line WL connected to the output terminal OUT.

[0080] If the gate of the second N-type transistor N2 is connected to the control signal terminal LWLB, when the input signal is the first control signal, the first N-type transistor N1 is turned off, and the first P-type transistor P1 and the second P-type transistor P2 are turned on. The control signal terminal LWLB provides a third control signal to turn off the second N-type transistor N2. The first signal terminal LWL provides a first voltage to the output terminal OUT, and the third signal terminal VNB provides a third voltage to the substrate terminals of the first N-type transistor N1 and the second N-type transistor N2, thereby pulling down the substrate terminal voltages of the first N-type transistor N1 and the second N-type transistor N2, reducing the leakage current of the first N-type transistor N1 and the second N-type transistor N2, so that the first voltage provided by the first signal terminal LWL can effectively reach the word line WL connected to the output terminal OUT.

[0081] Figure 7-10 This is a circuit diagram of a driving circuit provided in one embodiment of this application. Figure 7-10 As shown, the driving circuit includes a word line driving circuit 101, a first control circuit 102, and a second control circuit 103. The first control circuit 102 is configured to lower the substrate voltage of at least one N-type transistor when the input signal is a first control signal, thereby reducing the leakage current of the at least one N-type transistor. The second control circuit 103 is configured to raise the substrate voltage of at least one N-type transistor when the input signal is a second control signal, thereby lowering the threshold voltage of the at least one N-type transistor. The level of the second control signal is different from the level of the first control signal, so that the input terminal IN drives the first control circuit 102 or the second control circuit 103 to operate respectively when it receives signals of different levels. The level of the first control signal is lower than the level of the second control signal, so that the first control circuit 102 can be driven to operate when the input signal received by the input terminal IN is the first control signal, and the second control circuit 103 can be driven to operate when the input signal received by the input terminal IN is the second control signal.

[0082] In some embodiments, the second control circuit 103 includes a third N-type transistor N3. The gate of the third N-type transistor N3 is connected to the input terminal IN of the word line driving circuit 101. Its first terminal is connected to the substrate of at least one N-type transistor, and its second terminal is connected to a fourth signal terminal VG. The fourth signal terminal VG is configured to provide a fourth voltage when the third N-type transistor N3 is turned on. When the input signal is the second control signal, the third N-type transistor N3 is turned on, and the fourth signal terminal VG provides the fourth voltage to the substrate of at least one N-type transistor, thereby raising the substrate voltage of at least one N-type transistor and lowering the threshold voltage of at least one N-type transistor. Referring to Table 1, the larger the substrate voltage VB of the N-type transistor, the smaller the threshold voltage Vt of the N-type transistor. The fourth voltage can be greater than the third voltage to raise the substrate voltage of at least one N-type transistor. For example, the fourth voltage can be zero voltage, but it is not limited to this.

[0083] like Figure 7 As shown, the word line driving circuit 101 includes a first P-type transistor P1 and a first N-type transistor N1. When the input signal is a first control signal, the first control circuit 102 lowers the substrate voltage of the first N-type transistor N1 to reduce the leakage current of the first N-type transistor N1. When the input signal is a second control signal, the second control circuit 103 raises the substrate voltage of the first N-type transistor N1 to lower the threshold voltage of the first N-type transistor N1.

[0084] The first control circuit 102 includes a second P-type transistor P2, and the second control circuit 103 includes a third N-type transistor N3. The first terminals of both the second P-type transistor P2 and the third N-type transistor N3 are connected to the substrate of the first N-type transistor N1. When the input signal is the first control signal, the first N-type transistor N1 and the third N-type transistor N3 are turned off, while the first P-type transistor P1 and the second P-type transistor are turned on. The third signal terminal VNB provides a third voltage to the substrate of the first N-type transistor N1, thereby lowering the substrate voltage of the first N-type transistor N1 and reducing its leakage current. When the input signal is the second control signal, the first P-type transistor P1 and the second P-type transistor are turned off, while the first N-type transistor N1 and the third N-type transistor N3 are turned on. The fourth signal terminal VG provides a fourth voltage to the substrate of the first N-type transistor N1, thereby raising the substrate voltage of the first N-type transistor N1 and lowering its threshold voltage.

[0085] like Figure 8-10 As shown, the word line driving circuit 101 includes a first P-type transistor P1, a first N-type transistor N1, and a second N-type transistor N2. The first terminal of the second P-type transistor P2 is connected to the substrate terminal of the first N-type transistor N1 and / or the substrate terminal of the second N-type transistor N2. When the input signal is a first control signal, the first control circuit 102 lowers the substrate terminal voltage of the first N-type transistor N1 and / or the second N-type transistor N2 to reduce the leakage current of the first N-type transistor N1 and / or the second N-type transistor. The third N-type transistor N3 is connected to the substrate terminal of the first N-type transistor N1 and / or the substrate terminal of the second N-type transistor N2. When the input signal is a second control signal, the second control circuit 103 raises the substrate terminal voltage of the first N-type transistor N1 and / or the second N-type transistor N2 to lower the threshold voltage of the first N-type transistor N1 and / or the second N-type transistor N2.

[0086] like Figure 8As shown, the first control circuit 102 includes a second P-type transistor P2, and the second control circuit 103 includes a third N-type transistor N3. The first terminal of the second P-type transistor P2 is connected to the substrate of the first N-type transistor N1, and the first terminal of the third N-type transistor N3 is connected to the substrate of the first N-type transistor N1. When the input signal is the first control signal, the first N-type transistor N1 and the third N-type transistor N3 are turned off, while the first P-type transistor P1 and the second P-type transistor P2 are turned on. The third signal terminal VNB provides a third voltage to the substrate of the first N-type transistor N1, thereby lowering the substrate voltage of the first N-type transistor N1 and reducing its leakage current. When the input signal is the second control signal, the first P-type transistor P1 and the second P-type transistor P2 are turned off, while the first N-type transistor N1 and the third N-type transistor N3 are turned on. The fourth signal terminal VG provides a fourth voltage to the substrate of the first N-type transistor N1, thereby raising the substrate voltage of the first N-type transistor N1 and lowering its threshold voltage.

[0087] like Figure 9 As shown, the first terminal of the second P-type transistor P2 is connected to the substrate of the second N-type transistor N2, and the first terminal of the third N-type transistor N3 is connected to the substrate of the second N-type transistor N2. When the input signal is the first control signal, the third N-type transistor N3 is turned off, the first P-type transistor P1 and the second P-type transistor P2 are turned on, and the second N-type transistor N2 is turned off under the action of the first or third control signal. The third signal terminal VNB provides a third voltage to the substrate of the second N-type transistor N2, thereby pulling down the substrate voltage of the second N-type transistor N2 and reducing the leakage current of the second N-type transistor N2. When the input signal is the second control signal, the first P-type transistor P1 and the second P-type transistor are turned off, the third N-type transistor N3 is turned on, and the second N-type transistor N2 is turned on under the action of the second or fourth control signal. The fourth signal terminal VG provides a fourth voltage to the substrate of the second N-type transistor N2, thereby raising the substrate voltage of the second N-type transistor N2 and lowering the threshold voltage of the second N-type transistor N2.

[0088] like Figure 10As shown, the first terminal of the second P-type transistor P2 is connected to the substrate of the first N-type transistor N1 and the substrate of the second N-type transistor N2, and the first terminal of the third N-type transistor N3 is connected to the substrate of the first N-type transistor N1 and the substrate of the second N-type transistor N2. When the input signal is the first control signal, the first N-type transistor N1 and the third N-type transistor N3 are turned off, the first P-type transistor P1 and the second P-type transistor P2 are turned on, and the second N-type transistor N2 is turned off under the action of the first control signal or the third control signal. The third signal terminal VNB provides a third voltage to the substrate of the first N-type transistor N1 and the substrate of the second N-type transistor N2, thereby pulling down the substrate voltage of the first N-type transistor N1 and the second N-type transistor N2 and reducing the leakage current of the first N-type transistor N1 and the second N-type transistor N2. When the input signal is the second control signal, the first P-type transistor P1 and the second P-type transistor are turned off, the first N-type transistor N1 and the third N-type transistor N3 are turned on, and the second N-type transistor N2 is turned on under the action of the second control signal or the fourth control signal. The fourth signal terminal VG provides a fourth voltage to the substrate terminal of the first N-type transistor N1 and the substrate terminal of the second N-type transistor N2, thereby raising the substrate terminal voltage of the first N-type transistor N1 and the second N-type transistor N2 and lowering the threshold voltage of the first N-type transistor N1 and the second N-type transistor N2.

[0089] Figure 11-14 This is a circuit diagram of a driving circuit provided in one embodiment of this application. Figure 11-14 As shown, the driving circuit includes a word line driving circuit 101 and a second control circuit 103. The second control circuit 103 is configured to increase the substrate voltage of at least one N-type transistor when the input signal is a second control signal, so as to decrease the threshold voltage of at least one N-type transistor.

[0090] like Figure 11 As shown, the word line driving circuit 101 includes a first P-type transistor P1 and a first N-type transistor N1, and the second control circuit 103 includes a third N-type transistor N3. The gate of the third N-type transistor N3 is connected to the input terminal IN of the word line driving circuit 101, and the first terminal of the third N-type transistor N3 is connected to the substrate terminal of the first N-type transistor N1. When the input signal is the second control signal, the first P-type transistor P1 is turned off, and the first N-type transistor N1 and the third N-type transistor N3 are turned on. The fourth signal terminal VG provides a fourth voltage to the substrate terminal of the first N-type transistor N1, thereby raising the substrate terminal voltage of the first N-type transistor N1 and lowering the threshold voltage of the first N-type transistor N1.

[0091] like Figure 12-14As shown, the word line driving circuit 101 includes a first P-type transistor P1, a first N-type transistor N1, and a second N-type transistor N2. The second control circuit 103 includes a third N-type transistor N3. The first terminal of the third N-type transistor N3 is connected to the substrate terminal of the first N-type transistor N1 and / or the substrate terminal of the second N-type transistor N2. When the input signal is the second control signal, the third N-type transistor N3 is turned on, increasing the substrate terminal voltage of the first N-type transistor N1 and / or the substrate terminal voltage of the second N-type transistor N2, and decreasing the threshold voltage of the first N-type transistor N1 and / or the second N-type transistor N2.

[0092] like Figure 12 As shown, the first terminal of the third N-type transistor N3 is connected to the substrate terminal of the first N-type transistor N1. When the input signal is the second control signal, the first P-type transistor P1 is turned off, and the first N-type transistor N1 and the third N-type transistor N3 are turned on. The fourth signal terminal VG provides a fourth voltage to the substrate terminal of the first N-type transistor N1, thereby raising the substrate terminal voltage of the first N-type transistor N1 and reducing the threshold voltage of the first N-type transistor N1.

[0093] like Figure 13 As shown, the first terminal of the third N-type transistor N3 is connected to the substrate terminal of the second N-type transistor N2. When the input signal is the second control signal, the first P-type transistor P1 is turned off, the third N-type transistor N3 is turned on, and the second N-type transistor N2 is turned on under the action of the second control signal or the fourth control signal. The fourth signal terminal VG provides a fourth voltage to the substrate terminal of the second N-type transistor N2, thereby raising the substrate terminal voltage of the second N-type transistor N2 and reducing the threshold voltage of the second N-type transistor N2.

[0094] like Figure 14 As shown, the first terminal of the third N-type transistor N3 is connected to the substrate terminal of the first N-type transistor N1 and the substrate terminal of the second N-type transistor N2. When the input signal is the second control signal, the first P-type transistor P1 is turned off, and the first N-type transistor N1 and the third N-type transistor N3 are turned on. The second N-type transistor N2 is turned on under the action of the second control signal or the fourth control signal. The fourth signal terminal VG provides a fourth voltage to the substrate terminal of the first N-type transistor N1 and the substrate terminal of the second N-type transistor N2, thereby raising the substrate terminal voltage of the first N-type transistor N1 and the second N-type transistor N2 and reducing the threshold voltage of the first N-type transistor N1 and the second N-type transistor N2.

[0095] It should be noted that the substrate of a transistor can also be referred to as its back gate; unless the connection method of the transistor's substrate is specified, the substrate can be grounded (e.g., zero voltage), but is not limited to this. Furthermore, it is understood that the word line driving circuit in this application is not limited to... Figure 1-2 The situation shown.

[0096] One embodiment of this application provides a memory including the driving circuit described above.

[0097] The memory includes one or more memory banks, and each memory bank includes one or more memory cells. The operating states of a memory bank include an active state and a quiet state, and may also include other states. For example, when the memory bank is in the active state, a first control circuit lowers the substrate voltage of at least one N-type transistor in the word line drive circuit, reducing the leakage current of at least one N-type transistor and improving leakage current issues during aging tests or operation. When the memory is in the quiet state, a second control circuit raises the substrate voltage of at least one N-type transistor in the word line drive circuit, lowering the threshold voltage of at least one N-type transistor, thereby quickly reducing the word line voltage and shutting down the word line.

[0098] Figure 15 A flowchart illustrating a driving method for a driving circuit provided in an embodiment of this application. Figure 15 As shown, an embodiment of this application provides a driving method for a driving circuit, including:

[0099] S101. Provide an input signal to the input terminal of the word line driving circuit so that the output terminal of the word line driving circuit provides an output signal.

[0100] The driving circuit includes a word line driving circuit and a first control circuit. An input signal is provided to the input terminal of the word line driving circuit, so that when the input signal is the first control signal, the first control circuit lowers the substrate voltage of at least one N-type transistor in the word line driving circuit, reduces the leakage current of at least one N-type transistor, and thus enables the output signal provided by the output terminal of the word line driving circuit to effectively reach the word line.

[0101] S102. When the input signal is the first control signal, the substrate voltage of at least one N-type transistor is reduced to reduce the leakage current of at least one N-type transistor.

[0102] In some embodiments, the word line driving circuit includes a first P-type transistor and a first N-type transistor. The gates of the first P-type transistor and the first N-type transistor are interconnected as the input terminal of the word line driving circuit, and the first terminals of the first P-type transistor and the first terminals of the first N-type transistor are interconnected as the output terminal of the word line driving circuit. The first control circuit includes a second P-type transistor. The gate of the second P-type transistor is connected to the input terminal of the word line driving circuit, the first terminal of the second P-type transistor is connected to the substrate terminal of the first N-type transistor, and the second terminal of the second P-type transistor is connected to a third signal terminal. The third signal terminal is configured to provide a third voltage when the second P-type transistor is turned on.

[0103] When the input signal is the first control signal, the first N-type transistor is turned off and the second P-type transistor is turned on, so that the substrate end of the first N-type transistor is connected to the third signal end, so that the third signal end provides a third voltage to the substrate end of the first N-type transistor. The third voltage is a low voltage, thereby reducing the substrate end voltage of the first N-type transistor and reducing the leakage current of the first N-type transistor.

[0104] In some embodiments, the word line driving circuit includes a first P-type transistor, a first N-type transistor, and a second N-type transistor. The gate of the second N-type transistor is connected to the input terminal or control signal terminal of the word line driving circuit. The control signal terminal provides a third control signal that is in phase with the input signal. The first terminal of the second N-type transistor is connected to the output terminal of the word line driving circuit, and the second terminal is connected to the second terminal of the first N-type transistor. The first terminal of the second P-type transistor can be connected to the substrate terminal of the first N-type transistor. When the input signal is the first control signal, the first N-type transistor is controlled to be turned off, and the second P-type transistor is turned on, so that the substrate terminal of the first N-type transistor is connected to the third signal terminal. The third signal terminal provides a third voltage to lower the substrate terminal voltage of the first N-type transistor and reduce the leakage current of the first N-type transistor. The first terminal of the second P-type transistor can be connected to the substrate terminal of the second N-type transistor. When the input signal is the first control signal, the second N-type transistor is controlled to be turned off, and the second P-type transistor is turned on, so that the substrate terminal of the second N-type transistor is connected to the third signal terminal. The third signal terminal provides a third voltage to lower the substrate terminal voltage of the second N-type transistor and reduce the leakage current of the second N-type transistor. The first terminal of the second P-type transistor can also be connected to the substrate terminals of the first N-type transistor and the second N-type transistor. When the input signal is the first control signal, the first N-type transistor and the second N-type transistor are controlled to be turned off, and the second P-type transistor is turned on, so that the substrate terminals of the first N-type transistor and the second N-type transistor are connected to the third signal terminal. The third signal terminal provides a third voltage to reduce the substrate terminal voltage of the first N-type transistor and the second N-type transistor, thereby reducing the leakage current of the first N-type transistor and the second N-type transistor.

[0105] In some embodiments, the driving circuit includes a word line driving circuit, a first control circuit, and a second control circuit. The second control circuit is configured to increase the substrate voltage of at least one N-type transistor to decrease the threshold voltage of at least one N-type transistor when the input signal is a second control signal. The level of the second control signal is different from the level of the first control signal. Accordingly, the driving method may further include: increasing the substrate voltage of at least one N-type transistor to decrease the threshold voltage of at least one N-type transistor when the input signal is the second control signal.

[0106] For example, the word line driving circuit includes a first N-type transistor and a first P-type transistor, and the second control circuit includes a third N-type transistor. The gate of the third N-type transistor is connected to the input terminal of the word line driving circuit, and the first terminal of the third N-type transistor is connected to the substrate terminal of the first N-type transistor. When the input signal is the second control signal, the third N-type transistor is controlled to turn on, so that the substrate terminal of the first N-type transistor is connected to the fourth signal terminal. The fourth signal terminal provides a fourth voltage to increase the substrate terminal voltage of the first N-type transistor and decrease the threshold voltage of the first N-type transistor.

[0107] For example, the word line driving circuit includes a first P-type transistor, a first N-type transistor, and a second N-type transistor, and the second control circuit includes a third N-type transistor. The first terminal of the third N-type transistor can be connected to the substrate of the first N-type transistor. When the input signal is a second control signal, it controls the first and third N-type transistors to conduct, causing the substrate of the first N-type transistor to connect to a fourth signal terminal. The fourth signal terminal provides a fourth voltage to reduce the threshold voltage of the first N-type transistor. The first terminal of the third N-type transistor can also be connected to the substrate of the second N-type transistor. When the input signal is the second control signal, it controls the third N-type transistor to conduct, and simultaneously controls the second N-type transistor to conduct under the action of either the second or fourth control signal, causing the substrate of the second N-type transistor to connect to the fourth signal terminal. The fourth signal terminal provides a fourth voltage to reduce the threshold voltage of the second N-type transistor. The first terminal of the third N-type transistor can be connected to the substrate terminals of the first N-type transistor and the second N-type transistor. When the input signal is the second control signal, the first N-type transistor and the third N-type transistor are controlled to conduct. At the same time, the second N-type transistor is controlled to conduct under the action of the second control signal or the fourth control signal, so that the substrate terminals of the first N-type transistor and the second N-type transistor are connected to the fourth signal terminal. The fourth signal terminal provides a fourth voltage to reduce the threshold voltage of the first N-type transistor and the second N-type transistor.

[0108] In the above technical solution, the driving circuit includes a word line driving circuit and a first control circuit. The word line driving circuit provides an output signal to the output terminal according to the input signal received at the input terminal. When the input signal is the first control signal, the first control circuit lowers the substrate voltage of at least one N-type transistor in the word line driving circuit to reduce the leakage current of at least one N-type transistor, so that the high-level signal output by the word line driving circuit can effectively reach the word line, improve the leakage current problem of the N-type transistor in the word line driving circuit, and thus improve the performance of the memory.

[0109] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A driving circuit, characterized in that, include: A word line driving circuit includes an input terminal and an output terminal. The word line driving circuit is configured to provide an output signal to the output terminal according to an input signal received at the input terminal. The word line driving circuit includes a first P-type transistor and at least one N-type transistor. A first control circuit is configured to reduce the substrate voltage of the at least one N-type transistor when the input signal is a first control signal, so as to reduce the leakage current of the at least one N-type transistor. The first control circuit includes a second P-type transistor, whose gate is connected to the input terminal of the word line driving circuit, whose first terminal is connected to the substrate terminal of the at least one N-type transistor, and whose second terminal is connected to the third signal terminal. The third signal terminal is configured to provide a third voltage when the second P-type transistor is turned on.

2. The driving circuit according to claim 1, characterized in that, The third voltage is below zero.

3. The driving circuit according to claim 1, characterized in that, The word line driving circuit includes a first N-type transistor; The gate of the first P-type transistor and the gate of the first N-type transistor are interconnected and serve as the input terminal of the word line driving circuit. The first terminal of the first P-type transistor and the first terminal of the first N-type transistor are connected to each other and serve as the output terminal of the word line driving circuit. The substrate of the first N-type transistor is connected to the first terminal of the second P-type transistor.

4. The driving circuit according to claim 3, characterized in that, The second terminal of the first P-type transistor is connected to the first signal terminal, and the second terminal of the first N-type transistor is connected to the second signal terminal. The first signal terminal is configured to provide a first voltage when the first P-type transistor is turned on, and the second signal terminal is configured to provide a second voltage when the first N-type transistor is turned on; Wherein, the first voltage is greater than the second voltage.

5. The driving circuit according to claim 4, characterized in that, The word line driving circuit also includes: The second N-type transistor has its first terminal connected to the output terminal of the word line driving circuit, its second terminal connected to the second terminal of the first N-type transistor, and its gate connected to the input terminal or control signal terminal of the word line driving circuit. The control signal terminal is configured to provide a control signal that is in phase with the input signal.

6. The driving circuit according to claim 5, characterized in that, The substrate of the second N-type transistor is connected to the first terminal of the second P-type transistor.

7. The driving circuit according to claim 5, characterized in that, Also includes: The second control circuit is configured to increase the substrate voltage of the at least one N-type transistor when the input signal is the second control signal, so as to reduce the threshold voltage of the at least one N-type transistor. The level of the second control signal is different from the level of the first control signal.

8. The driving circuit according to claim 7, characterized in that, The level of the first control signal is lower than the level of the second control signal.

9. The driving circuit according to claim 7, characterized in that, The second control circuit includes a third N-type transistor, whose gate is connected to the input terminal of the word line driving circuit, whose first terminal is connected to the substrate terminal of the at least one N-type transistor, and whose second terminal is connected to the fourth signal terminal. The fourth signal terminal is configured to provide a fourth voltage when the third N-type transistor is turned on.

10. The driving circuit according to claim 9, characterized in that, The fourth voltage is greater than the third voltage.

11. The driving circuit according to claim 9, characterized in that, The first terminal of the third N-type transistor is connected to the substrate terminal of the first N-type transistor and the substrate terminal of the second N-type transistor.

12. The driving circuit according to any one of claims 1-11, characterized in that, The input terminal of the word line driving circuit is configured to connect to the main word line, and the output terminal of the word line driving circuit is configured to connect to the word line.

13. A memory comprising a drive circuit according to any one of claims 1-12.

14. A driving method for a driving circuit according to any one of claims 1-12, comprising: An input signal is provided to the input terminal of the word line driving circuit so that the output terminal of the word line driving circuit provides an output signal; as well as When the input signal is the first control signal, the substrate voltage of the at least one N-type transistor is reduced by the first control circuit to reduce the leakage current of the at least one N-type transistor.

15. The method according to claim 14, characterized in that, The driving circuit further includes: a second control circuit configured to increase the substrate voltage of the at least one N-type transistor to decrease the threshold voltage of the at least one N-type transistor when the input signal is a second control signal, wherein the level of the second control signal is different from the level of the first control signal; The driving method further includes: When the input signal is the second control signal, the substrate voltage of the at least one N-type transistor is increased by the second control circuit to reduce the threshold voltage of the at least one N-type transistor.

16. The method according to claim 14, characterized in that, The word line driving circuit includes a first N-type transistor, the gate of the first P-type transistor and the gate of the first N-type transistor are connected to each other and serve as the input terminal of the word line driving circuit, and the first terminal of the first P-type transistor and the first terminal of the first N-type transistor are connected to each other and serve as the output terminal of the word line driving circuit. The first control circuit includes a second P-type transistor, whose gate is connected to the input terminal of the word line driving circuit, whose first terminal is connected to the substrate terminal of the first N-type transistor, and whose second terminal is connected to a third signal terminal, the third signal terminal being configured to provide a third voltage when the second P-type transistor is turned on; When the input signal is a first control signal, the step of lowering the substrate voltage of the at least one N-type transistor via the first control circuit to reduce the leakage current of the at least one N-type transistor includes: When the input signal is the first control signal, the second P-type transistor is turned on, so that the substrate terminal of the first N-type transistor is connected to the third signal terminal, and the substrate terminal voltage of the first N-type transistor is reduced to reduce the leakage current of the first N-type transistor.

17. The method according to claim 15, characterized in that, The word line driving circuit includes a first N-type transistor, the gate of the first P-type transistor and the gate of the first N-type transistor are connected to each other and serve as the input terminal of the word line driving circuit, and the first terminal of the first P-type transistor and the first terminal of the first N-type transistor are connected to each other and serve as the output terminal of the word line driving circuit. The second control circuit includes a third N-type transistor, whose gate is connected to the input terminal of the word line driving circuit, whose first terminal is connected to the substrate terminal of the first N-type transistor, and whose second terminal is connected to a fourth signal terminal, the fourth signal terminal being configured to provide a fourth voltage when the third N-type transistor is turned on; When the input signal is a second control signal, adjusting the substrate voltage of the at least one N-type transistor by the second control circuit to reduce the threshold voltage of the at least one N-type transistor includes: When the input signal is the second control signal, the third N-type transistor is turned on, so that the substrate terminal of the first N-type transistor is connected to the fourth signal terminal, thereby reducing the threshold voltage of the first N-type transistor.

18. The method according to claim 14, characterized in that, The word line driving circuit includes a first N-type transistor and a second N-type transistor. The gates of the first P-type transistor and the first N-type transistor are interconnected and serve as the input terminal of the word line driving circuit. The first terminals of the first P-type transistor and the first terminals of the first N-type transistor are interconnected and serve as the output terminal of the word line driving circuit. The gate of the second N-type transistor is connected to either the input terminal or the control signal terminal of the word line driving circuit. The first terminal of the second N-type transistor is connected to the output terminal of the word line driving circuit. The second terminal of the second N-type transistor is connected to the second terminal of the first N-type transistor. The control signal terminal is configured to provide a control signal in phase with the input signal. The first control circuit includes a second P-type transistor, whose gate is connected to the input terminal of the word line driving circuit, whose first terminal is connected to at least one of the substrate terminal of the first N-type transistor and the substrate terminal of the second N-type transistor, and whose second terminal is connected to a third signal terminal, the third signal terminal being configured to provide a third voltage when the second P-type transistor is turned on; When the input signal is a first control signal, the step of lowering the substrate voltage of the at least one N-type transistor via the first control circuit to reduce the leakage current of the at least one N-type transistor includes: When the input signal is the first control signal, the second P-type transistor is controlled to turn on, so that at least one of the substrate terminals of the first N-type transistor and the second N-type transistor is connected to the third signal terminal, and the substrate terminal voltage of at least one of the first N-type transistor and the second N-type transistor is reduced, so as to reduce the leakage current of at least one of the first N-type transistor and the second N-type transistor.

19. The method according to claim 15, characterized in that, The word line driving circuit includes a first N-type transistor and a second N-type transistor. The gates of the first P-type transistor and the first N-type transistor are interconnected and serve as the input terminal of the word line driving circuit. The first terminals of the first P-type transistor and the first terminals of the first N-type transistor are interconnected and serve as the output terminal of the word line driving circuit. The gate of the second N-type transistor is connected to either the input terminal or the control signal terminal of the word line driving circuit. The first terminal of the second N-type transistor is connected to the output terminal of the word line driving circuit. The second terminal of the second N-type transistor is connected to the second terminal of the first N-type transistor. The control signal terminal is configured to provide a control signal in phase with the input signal. The second control circuit includes a third N-type transistor whose gate is connected to the input terminal of the word line driving circuit, whose first terminal is connected to at least one of the substrate terminal of the first N-type transistor and the substrate terminal of the second N-type transistor, and whose second terminal is connected to a fourth signal terminal, the fourth signal terminal being configured to provide a fourth voltage when the third N-type transistor is turned on. When the input signal is a second control signal, the substrate voltage of the at least one N-type transistor is increased by the second control circuit to reduce the threshold voltage of the at least one N-type transistor, including: When the input signal is the second control signal, the third N-type transistor is controlled to turn on, so that at least one of the substrate terminals of the first N-type transistor and the second N-type transistor is connected to the fourth signal terminal, and the substrate terminal voltage of at least one of the first N-type transistor and the second N-type transistor is increased, so as to reduce the threshold voltage of at least one of the first N-type transistor and the second N-type transistor.

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