Multi-screen data processing method, electronic device and readable storage medium

Abstract

The present application provides a multi-screen data processing method, an electronic device and a readable storage medium, belonging to the technical field of electronic devices, wherein the electronic device comprises: a control chip comprises a first display serial interface DSI and a second display serial interface DSI, the first DSI and the second DSI are respectively connected to the input end of the display chip, and are used to provide a first data signal to the display chip; the output end of the display chip is connected to the first display screen among multiple display screens, and the control chip is used to control the display chip to output the first data signal or the second data signal to the first display screen, wherein the second data signal comprises image data obtained by processing the first data signal by the display chip; and / or, the control chip is used to control the output end of the display chip to output the first data or the second data to the second display screen other than the first display screen. The electronic device can realize that one display chip corresponds to multiple display screens, and the demand for the effect of multi-screen enhanced display is improved, thereby improving the user experience.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a multi-screen data processing method, an electronic device and a readable storage medium. Background Art

[0002] With the continuous development of electronic products, more and more electronic products are welcomed by consumers. Along with this, people's requirements for high performance and low cost of electronic products are constantly improving. Among them, display function has become a major indicator. For example, in order to improve the display effect, a post-processing dedicated integrated circuit (ASIC) will be added. It can also be called a post-processing independent display chip. The ASIC chip is used to optimize and enhance the image data of a single screen. However, with the increase in the number of display screens, the current method can no longer meet people's needs for multi-screen enhanced image data processing. Summary of the invention

[0003] In view of this, the present invention provides a multi-screen data processing method, an electronic device, and a computer-readable storage medium, which can realize that one ASIC chip provides image data processing for multiple display screens, with low cost and meet customers' requirements for display effects.

[0004] Some embodiments of the present application provide a multi-screen data processing method. The present application is introduced from multiple aspects below, and the embodiments and beneficial effects of the following aspects can be referenced to each other.

[0005] In a first aspect, the present invention provides an electronic device comprising: a control chip, a display chip, multiple display screens and a switching switch; the control chip is connected to the display chip, the switching switch and the multiple display screens, and the control chip is used to control the interface of the control chip and / or the connection relationship between the display chip and the corresponding display screens among the multiple display screens through the switching switch, so that a control chip directly provides first data to the multiple display screens, or a display chip provides second data to the display screens respectively connected to the display chip, wherein the second data is image data that is different from the first data and is processed by the display chip.

[0006] According to the electronic device of the embodiment of the present application, when the electronic device is provided with more than two display screens, it is possible to realize that one display chip corresponds to multiple display screens without increasing the number of display chips, so that the multiple display screens of the electronic device can display enhanced and optimized visual effects, thereby meeting the user's low cost and demand for multi-screen enhanced display effects, and improving the user experience.

[0007] As an embodiment of the first aspect of the present application, the control chip includes a first camera serial interface CSI, a first display serial interface DSI, and a second display serial interface DSI, wherein the control chip receives an output signal from a first output terminal of the display chip through the CSI, and outputs a signal to the display chip through the first DSI;

[0008] The second output terminal of the display chip outputs a signal to a first display screen among the multiple display screens;

[0009] The switch includes a first switch, the first switch includes an input terminal connected to the second DSI, and includes a first output terminal connected to the display chip and a second output terminal that outputs a signal to a second display screen other than the first display screen;

[0010] The control chip controls the first switch to switch between the signal transmission channel between the second DSI and the display chip and the signal transmission channel between the second DSI and the second display screen. By adding a switch, dual-screen display can be achieved simultaneously, and each screen can obtain the image data processed by the display chip.

[0011] As an embodiment of the first aspect of the present application, the second output end of the display chip is directly connected to the first display screen, and the second output end of the first switch is directly connected to the second display screen.

[0012] As an embodiment of the first aspect of the present application, the switch further includes a second switch and a third switch.

[0013] The second switch includes an input end connected to the second output end of the display chip, and includes a first output end connected to the third switch and a second output end connected to the first display screen, so that the second output end of the display chip outputs a signal to the first display screen via the second switch.

[0014] The third switch includes a first input end connected to the first switch and a second input end connected to the second switch, and an output end of the third switch is connected to the second display screen. This method can realize that the display chip is directly connected to multiple screens and directly sends processed image data without returning it to the control chip, which has more advantages in power consumption, data delay and system software implementation.

[0015] As an embodiment of the first aspect of the present application, the first switching switch, the second switching switch and the third switching switch are independent switches, or integrated switches integrated together.

[0016] As an embodiment of the first aspect of the present application, the switch is integrated in a display chip, the display chip includes a data processing unit, wherein the data processing unit is used to optimize the image data; the control chip includes a first camera serial interface CSI and a first display serial interface DSI and a second display serial interface DSI;

[0017] The switching switches include: a fourth switching switch, a fifth switching switch, a sixth switching switch and a seventh switching switch;

[0018] The input end of the fourth switch is connected to the first DSI, the first output end is connected to the first input end of the data processing unit in the display chip, and the second output end is connected to the first input end of the sixth switch.

[0019] The second input end of the sixth switch is connected to the second output end of the data processing unit, and the output end of the sixth switch is connected to the third display screen among the multiple display screens;

[0020] The input end of the fifth switch is connected to the second DSI, the first output end is connected to the second input end of the data processing unit, and the second output end is connected to the first input end of the seventh switch.

[0021] The second input end of the seventh switch is connected to the second output end of the data processing unit, and the output end is connected to the fourth display screen except the third display screen;

[0022] The third output terminal of the data processing unit is connected to the CSI of the control chip and is used to return data to the control chip.

[0023] This structure integrates the control switch into the display chip, which reduces the occupied area of ​​the circuit and saves space for the hardware structure.

[0024] As an embodiment of the first aspect of the present application, the control chip includes a first camera serial interface CSI and a first display serial interface DSI, a second display serial interface DSI and a third display serial interface DSI, wherein the CSI is connected to a first output end of the display chip, the first DSI and the second DSI are respectively connected to a first input end and a second input end of the display chip, the control chip receives a first output from the display chip through the CSI, and outputs a signal to the display chip via the first DSI and the second DSI; the switching switch includes an eighth switching switch and a ninth switching switch;

[0025] The input end of the eighth switch is connected to the second output end of the display chip, the first output end is connected to the first input end of the ninth switch, and the second output end is connected to the fifth display screen among the multiple display screens;

[0026] The second input end of the ninth switch is connected to the third DSI, and the output end is connected to the sixth display screen except the fifth display screen. By adding the DSI interface, the number of switches can be reduced as much as possible, and the display chip can be directly connected to multiple display screens without the need to be transmitted back to the control chip, thereby reducing the power consumption of the control chip.

[0027] As an embodiment of the first aspect of the present application, the input end of the switching switch is connected to the display chip, and the output end is connected to multiple display screens respectively.

[0028] A second aspect. A multi-screen data processing method, characterized in that it is applied to an electronic device, the electronic device comprising: a control chip, a dedicated integrated circuit display chip and a plurality of display screens, the control chip is connected to the display chip and the plurality of display screens, the method comprising:

[0029] The control chip controls the interface of the control chip and / or the display chip to be connected to multiple display screens respectively, so that the control chip directly provides first data to the multiple display screens, or enables a display chip to provide second data to the display screens respectively connected to the display chip, wherein the second data is image data that is different from the first data and is processed by the display chip.

[0030] According to the multi-screen data processing method of the embodiment of the present application, when an electronic device is provided with more than two display screens, it is possible to realize that one display chip corresponds to multiple display screens without increasing the number of display chips, so that multiple display screens of the electronic device can display enhanced and optimized visual effects, meeting the user's low cost and the demand for multi-screen enhanced display effects, and improving the user experience.

[0031] As an embodiment of the second aspect of the present application, the control chip controls the display chip to be connected to multiple display screens respectively, so that one display chip is respectively connected to the display screens connected to the display chip to provide second data, including:

[0032] The control chip receives a first request for image processing from a first display screen among the multiple display screens, controls the display chip to be directly connected to the first display screen, and sends the first request to the display chip;

[0033] The display chip processes the image data based on the first request to obtain second data, and sends the second data to the first display screen;

[0034] The control chip receives a second request for image processing from a second display screen other than the first display screen, disconnects the display chip from the first display screen, and connects the display chip to the second display screen;

[0035] The control chip sends the second request to the display chip, and the display chip processes the image data based on the second request to obtain second data, and sends the second data to the second display screen. The method can realize dual-screen simultaneous display, and each screen can obtain the image data processed by the display chip.

[0036] As an embodiment of the second aspect of the present application, the control chip includes a first camera serial interface CSI and a first display serial interface DSI1 and a second display serial interface DSI2, wherein CSI and DSI1 are connected to the display chip respectively;

[0037] The control chip receives a first request for image processing from a first display screen among multiple display screens, controls the display chip to be directly connected to the first display screen, and sends the first request to the display chip, including:

[0038] The control chip receives a first request for image processing from the first display screen, controls DSI2 to be connected to the input end of the display chip, and connects the output end of the display chip to the first display screen, so that the display chip processes the image data based on the first request to obtain second data, and sends the second data to the first display screen, thereby achieving that one of the display screens obtains the processed data from the display chip.

[0039] As an embodiment of the second aspect of the present application, the control chip receives a second request for image processing from a second display screen other than the first display screen, disconnects the display chip from the first display screen, and connects the display chip to the second display screen, including:

[0040] The control chip receives a second request for image processing from the second display screen, disconnects the display chip from the first display screen, and connects DSI2 to the second display screen;

[0041] The display chip processes the image data based on the second request to obtain second data, and sends the second data to the second display screen, including:

[0042] Based on the second request, the display chip processes the image data to obtain second data, and sends the second data to the control chip, which then sends the second data to the second display screen, thereby enabling another display screen to obtain the data processed by the display chip.

[0043] As an embodiment of the second aspect of the present application, the control chip receives a second request for image processing from a second display screen other than the first display screen, disconnects the display chip from the first display screen, and connects the display chip to the second display screen, including:

[0044] The control chip receives a second request for image processing from the second display screen, disconnects the display chip from the first display screen, disconnects DSI2 from the display chip, and connects the display chip and DSI2 to the second display screen.

[0045] As an embodiment of the second aspect of the present application, the display chip includes a data processing unit;

[0046] The control chip controls the display chip to be connected to the plurality of display screens respectively, so that the display chip provides second data to the display screens respectively connected to the display chip, including:

[0047] The control chip controls the data processing unit to be connected to the plurality of display screens respectively, so that the display chip provides the second data to the display screens directly connected to the data processing unit.

[0048] As an embodiment of the second aspect of the present application, the control chip includes a first camera serial interface CSI and a first display serial interface DSI1, a second display serial interface DSI2 and a third display serial interface DSI3, wherein CSI, DSI1 and DSI2 are respectively connected to the display chip;

[0049] The control chip receives a first request for image processing from the first display screen, and controls the display chip to be directly connected to the first display screen, including:

[0050] The control chip receives a first request for image processing from the first display screen, and controls the display chip to be directly connected to the first display screen, and DSI3 is disconnected from the second display screen.

[0051] As an embodiment of the second aspect of the present application, the control chip receives a second request for image processing from a second display screen other than the first display screen, disconnects the display chip from the first display screen, and connects the display chip to the second display screen, including:

[0052] The control chip receives the second request for image processing from the second display screen, disconnects the display chip from the first display screen, disconnects DSI3 from the second display screen, and disconnects the display chip from the second display screen.

[0053] In a third aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by an electronic device, the electronic device executes the method in the above-mentioned first aspect embodiment.

[0054] In a fourth aspect, the present application discloses a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method in the embodiment of the first aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1a The schematic diagram of the structure of the electronic device is shown as an example;

[0056] Figure 1b It is a schematic diagram of the dual-screen structure of a mobile phone;

[0057] Figure 2 A schematic diagram of the structure of an electronic device according to an embodiment of the present application;

[0058] Figure 3 A schematic diagram of the software architecture of an electronic device according to an embodiment of the present application;

[0059] Figure 4a This is a schematic diagram of the structure of a single switch in a dual-screen mobile phone according to an embodiment of the present application;

[0060] Figure 4b This is a schematic diagram of the connection structure of scenario 1 in Table 1 of an embodiment of the present application;

[0061] Figure 4c This is a schematic diagram of the connection structure of scenario 2 in Table 1 of an embodiment of the present application;

[0062] Figure 4d This is a schematic diagram of the connection structure of scenario 3 in Table 1 of an embodiment of the present application;

[0063] Figure 5a This is a schematic diagram of the structure of multiple switching switches in a dual-screen mobile phone according to another embodiment of the present application;

[0064] Figure 5b This is a schematic diagram of the connection structure corresponding to scenario 1 in Table 2 of another embodiment of the present application;

[0065] Figure 5c This is a schematic diagram of a connection structure corresponding to scenario 2 in Table 2 of another embodiment of the present application;

[0066] Figure 5d This is a schematic diagram of a connection structure corresponding to scenario 3 in Table 2 of another embodiment of the present application;

[0067] Figure 6a This is a schematic diagram of a structure in which a switch in a dual-screen mobile phone according to an embodiment of the present application is integrated into a chip;

[0068] Figure 6b This is a schematic diagram of the internal structure of an ASIC chip according to an embodiment of the present application;

[0069] Figure 7 This is a schematic diagram of the structure of a dual-screen mobile phone according to an embodiment of the present application when the dual-screen display is not provided;

[0070] Figure 8This is a schematic diagram of the structure of a dual-screen mobile phone with three DSI interfaces according to an embodiment of the present application;

[0071] Fig. 9 This is a schematic diagram of the structure of a dual-screen mobile phone with three DSI interfaces in another embodiment of the present application;

[0072] Fig.10 A flowchart of a multi-screen data processing method according to another embodiment of the present application;

[0073] Fig.11 A block diagram of a system on a chip according to some embodiments of the present application. DETAILED DESCRIPTION

[0074] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application.

[0075] In order to facilitate the understanding of the technical solution of the present application, the key terms appearing in the present application are first explained below.

[0076] System-on-chip, also known as system on chip, is abbreviated as SoC. It is an integrated circuit with a dedicated purpose, which contains all the contents of a complete system and embedded software, and is used to implement the entire process from determining the system function to software / hardware division and completing the design. In this application, it is used to control the connection relationship between the interface of SoC, ASIC chip and multiple display screens, so as to realize the control of the display of a display screen alone, or to control the display in collaboration with display chips, etc. SoC is an example of a control chip used in this application.

[0077] Application-specific integrated circuits, i.e. display chips used for post-processing, are referred to as ASIC chips. The full name in English is Application Specific Integrated Circuit, or ASIC for short. It is an integrated circuit made for a specific user or a specific electronic system. For example, in this application, it is used to optimize and enhance the display backend image data, such as color enhancement, MEMC interpolation, HDR data processing, etc. ASIC is an example of a display chip used in this application.

[0078] The technical solution of the present application is explained below in conjunction with a scene diagram.

[0079] In some special scenarios, such as game scenarios, page browsing, etc., current electronic devices need to optimize and enhance image data to improve display effects and user experience, such as color enhancement, motion estimation and motion compensation (MEMC) (i.e., MEMC interpolation), high dynamic range (HDR) data processing, etc., to better reflect the visual effects in the real environment, thereby improving the user's visual experience. These special processes are usually processed separately by adding an ASIC chip to the electronic device. In the following embodiments, the internal structure of the electronic device will be described in conjunction with specific drawings.

[0080] refer to Figure 1a , Figure 1a The schematic diagram of the structure of the electronic device is shown as an example. Figure 1a As shown, the electronic device includes a system-level chip "SoC", an ASIC chip connected to the SoC, and a display screen connected to the ASIC chip. The SoC includes a camera serial interface (Camera Serial Interface, CSI), namely "CSI", and two display serial interfaces (DisplaySerial Interface Specification, DSI), namely "DSI1" and "DSI2", wherein the SoC is connected to the ASIC chip through these interfaces, and the image data to be processed is sent to the ASIC chip through DSI1 and DSI2, and the ASIC chip optimizes and enhances the image data, and the ASIC chip sends the processed image data to the display screen, and the display screen displays the optimized and enhanced image.

[0081] However, since the ASIC chip is only connected to one display screen, when there are multiple display screens, enhanced display of the multiple display screens cannot be achieved.

[0082] refer to Figure 1b , Figure 1b The figure shows a schematic diagram of the structure of a mobile phone with inner and outer screens. Figure 1b As shown in (i), the mobile phone 10 has a "first display screen", also called an inner screen. Figure 1b As shown in (ii), the mobile phone 10 also has a "second display screen" also called an external screen. Figure 1aIn the structure shown, since the ASIC chip is only connected to one display screen, for example, the ASIC chip is connected to the first display screen, the optimized and enhanced image can only be displayed on the first display screen, while the second display screen cannot achieve such a visual effect. Therefore, this connection method cannot be used for dual or multiple screens, which reduces the user experience. If multiple ASIC chips are added, the manufacturing cost will increase greatly, which cannot meet the user's demand for low cost.

[0083] Therefore, in order to realize the use of a display ASIC chip for dual screens or multiple screens, the present application provides an electronic device. The electronic device includes at least two display screens, a system-on-chip SOC, an application-specific integrated circuit ASIC chip, and a switch. Among them, the connection between the SOC, the ASIC chip, the switch and the at least two display screens may include a direct connection by wire or wireless, or an indirect connection via other components. The SOC is used to control one or more of the connection relationship between the interface of the SOC and the ASIC chip, the connection relationship between the interface of the SOC and multiple display screens, and the connection relationship between the ASIC chip and multiple display screens through the switch. Thereby, under the condition of setting only one ASIC chip, one or more switching switches are added, and the data transmission relationship between the SOC, the ASIC chip and the display screen is modified, so that image data after image quality processing can be provided to multiple display screens through one ASIC chip.

[0084] In one embodiment of the present application, the function of the switch may be implemented by hardware or software, and the present application does not make any specific limitation.

[0085] In the embodiments of the present application, an electronic device having two screens (display screens) is used as an example for description. In some embodiments, there may also be multiple display screens, and the present application does not limit the shape and other features of the display screens.

[0086] In some embodiments of the present application, the electronic device may also be a mobile phone, a desktop computer, a tablet computer, a laptop computer, a super mobile personal computer, a personal digital assistant (PDA), or a wearable electronic device such as a watch, a bracelet, or other electronic device with multiple screens. The present application does not limit the specific form of the electronic device.

[0087] In the following embodiments, the structure of the electronic device and the multi-screen data processing method of the present application will be described in conjunction with specific embodiments.

[0088] The present application scheme is described below in conjunction with the specific structure of the electronic device.

[0089] refer to Figure 2 , Figure 2 A schematic diagram of the structure of an electronic device according to an embodiment of the present application is shown. The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) connector 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, a subscriber identification module (SIM) card interface 195, an ASIC chip 196, etc. The sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0090] It is to be understood that the structure illustrated in the embodiment of the present invention does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown in the figure, or combine some components, or separate some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0091] The processor 110 may include one or more processing units, for example, the processor 110 may include an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0092] The processor 110 can generate an operation control signal according to the instruction operation code and the timing signal to complete the control of fetching and executing instructions.

[0093] The processor 110 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may store instructions or data that the processor 110 has just used or cyclically used. If the processor 110 needs to use the instruction or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0094] In one embodiment of the present application, the processor 110 controls the interface of the SoC and the ASIC chip to be connected to multiple display screens respectively, so that the SoC provides data to multiple screens and displays them on multiple screens, or an ASIC chip provides image data processed by the ASIC chip to the display screens connected to the ASIC chip respectively, so that one ASIC chip corresponds to multiple display screens.

[0095] In some embodiments, the processor 110 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, and a subscriber identity module (SIM) interface.

[0096] The MIPI interface can be used to connect the processor 110 with peripheral devices such as the display screen 194 and the camera 193. The MIPI interface includes a camera serial interface (CSI), a display serial interface (DSI), etc. In some embodiments, the processor 110 and the camera 193 communicate via the CSI interface to implement the shooting function of the electronic device 100. The processor 110 and the display screen 194 communicate via the DSI interface to implement the display function of the electronic device 100.

[0097] In some embodiments, an ASIC chip is provided between the processor 110 and the display screen 194. After receiving an image display request from the display screen, the processor 110 sends some image data that needs to be optimized and enhanced to the ASIC chip, and the ASIC chip further optimizes and processes the image data, such as color enhancement, MEMC interpolation, HDR data processing, etc. The ASIC chip then sends the processed data to the display screen that issued the request for enhanced display to achieve a better visual effect.

[0098] In some embodiments, the processor 110 can connect the ASIC chip to multiple display screens through a switching switch, so that one ASIC chip can provide processed image data for multiple display screens, so as to ensure that each display screen can achieve optimized and enhanced visual effects at a low cost. Among them, the function of the switching switch can be implemented by hardware or software. These switching switches can be one or more. When multiple switching switches are hardware, they can be independently set or integrated together. The number and structural form of the switching switches are not limited in this application.

[0099] The DSI interface in the present application can be set to two or more, and these DSI interfaces can be directly connected to the ASIC chip 196 to ensure that the processor 110 can quickly send the image data to the ASIC chip.

[0100] In addition, in some embodiments, when there are multiple display screens, to ensure that each display screen can display simultaneously, the processor 110 can control some DSI interfaces to be connected to the ASIC chip through a switching switch, and some DSI interfaces to be used to connect to other display screens, thereby realizing multiple display screens to display simultaneously. And when the ASIC chip needs to be connected to another display screen, the processor 110 can also change the connection relationship between the DSI interface and the ASIC chip, and the connection relationship between the ASIC chip and the display screen, so that the ASIC chip provides enhanced and optimized image data to another display screen.

[0101] It is understandable that the interface connection relationship between the modules illustrated in the embodiment of the present invention is only a schematic illustration and does not constitute a structural limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.

[0102] The electronic device 100 implements the display function through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, which connects the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

[0103] The display screen 194 is used to display images, videos, etc. The display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode or an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), Miniled, MicroLed, Micro-oLed, a quantum dot light-emitting diode (QLED), etc.

[0104] In some embodiments, the electronic device 100 may include 1 or N display screens 194, where N is a positive integer greater than 1. When the number of display screens is greater than 1, the processor 110 may control the connection relationship between the ASIC chip and these display screens by controlling the switch, thereby ensuring that each display screen can be connected to the ASIC chip and obtain enhanced and optimized image data, thereby improving the user experience.

[0105] The electronic device 100 can realize the shooting function through ISP, camera 193, video codec, GPU, display screen 194 and application processor.

[0106] The camera 193 is used to capture still images or videos. The object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, and then passes the electrical signal to the ISP to be converted into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard RGB, YUV or other format. In some embodiments, the electronic device 100 may include 1 or N cameras 193, where N is a positive integer greater than 1.

[0107] In some embodiments, the processor 110 is connected to the camera 193 via the camera serial interface CSI and obtains image data collected by the camera 193. After the processor 110 further optimizes and enhances the image data through the ASIC chip, the ASIC chip displays the processed image data on the display screen to which it is connected, so that the scene seen by the user through the display screen is closer to the real scene in front of the camera and more realistic, thereby improving the user experience.

[0108] The internal memory 121 can be used to store computer executable program codes, and the executable program codes include instructions. The internal memory 121 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area may store data created during the use of the electronic device 100 (such as audio data, a phone book, etc.), etc. In addition, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The processor 110 executes various functional applications and data processing of the electronic device 100 by running instructions stored in the internal memory 121, and / or instructions stored in a memory provided in the processor.

[0109] In some embodiments, the internal memory 121 stores logic instructions for controlling the switching switch. The processor 110 connects each DSI interface, ASIC chip and multiple display screens according to these instructions, so that one ASIC chip corresponds to multiple display screens, so that the multiple display screens of the electronic device can achieve a better visual effect.

[0110] The touch sensor 180K is also called a "touch control device". The touch sensor 180K can be set on the display screen 194. The touch sensor 180K and the display screen 194 form a touch screen, also called a "touch control screen". The touch sensor 180K is used to detect touch operations acting on or near it. The touch sensor can pass the detected touch operation to the application processor to determine the type of touch event. Visual output related to the touch operation can be provided through the display screen 194. In other embodiments, the touch sensor 180K can also be set on the surface of the electronic device 100, which is different from the position of the display screen 194.

[0111] In some embodiments, a user can perform operations such as clicking on the display screen 194, and the touch sensor obtains the click and other operations, encapsulates the touch event and sends it to the processor 110. The processor 110 determines the user's request based on the touch event. When the data requested by the user includes image data that needs to be enhanced and optimized, the processor 110 sends the image data to the ASIC chip for post-processing so that the enhanced and optimized image data is displayed on the display screen clicked by the user.

[0112] Above Figure 2 The software system of the electronic device 100 shown may adopt a layered architecture, an event-driven architecture, a micro-core architecture, a micro-service architecture, or a cloud architecture, etc. The embodiment of the present invention takes the Android system of the layered architecture as an example to exemplify the software system architecture of the electronic device 100.

[0113] Figure 3 1 is a software structure block diagram of the electronic device 100 according to an embodiment of the present invention.

[0114] like Figure 3 As shown, the layered architecture divides the software into several layers, each with clear roles and division of labor. The layers communicate with each other through software interfaces. In some embodiments, the Android system is divided into four layers, from top to bottom, namely, the application layer, the application framework layer, the Android runtime (Android runtime) and the system library, and the kernel layer.

[0115] The application layer can include a series of application packages.

[0116] like Figure 3 As shown, the application package may include applications such as camera, gallery, calendar, call, map, navigation, WLAN, Bluetooth, music, video, short message, game, etc.

[0117] like Figure 3 As shown, the application framework layer may include a window manager, a content provider, a view system, a phone manager, a resource manager, a notification manager, and the like.

[0118] Content providers are used to store and retrieve data and make it accessible to applications. The data can include videos, images, audio, calls made and received, browsing history and bookmarks, phone books, etc.

[0119] In some embodiments, the content provider may store the image data processed by the ASIC chip and provide it for use by applications in the application layer, such as game applications.

[0120] The kernel layer is the layer between hardware and software. The kernel layer contains at least display driver, camera driver, audio driver, and sensor driver.

[0121] The structure of the electronic device and the multi-screen data processing method of the present application are described in detail below in conjunction with specific embodiments.

[0122] In the following embodiments, a mobile phone (as an example of an electronic device) is used as an example for description. The mobile phone has multiple screens. In the following embodiments, a dual-screen mobile phone is used as an example, and part of the structure of the dual-screen mobile phone is described. Other specific structures of the mobile phone can be referred to as follows. Figure 2 , Figure 3 Hardware structure and software structure.

[0123] The electronic device of the embodiment of the present application includes a system-on-chip (SOC), an ASIC chip, multiple display screens, and a switch. The SOC is used to control one or more of the connection relationship between the SOC interface and the ASIC chip, the connection relationship between the SOC interface and the multiple display screens, and the connection relationship between the ASIC chip and the multiple display screens through the switch, so as to realize the addition of one or more switch and modify the data transmission relationship between the SOC, the ASIC chip and the display screen under the condition of only setting one ASIC chip, so as to provide image data after image quality processing for multiple display screens through one ASIC chip.

[0124] The following describes the connection relationship between the various components and the process of realizing a single display screen display (the ASIC chip provides post-processed image data to one of the display screens) and a multi-screen display in conjunction with specific embodiments.

[0125] In the following embodiments, dual screens are used as an example for explanation. In some embodiments, there may also be three screens, four screens, etc., and the present application does not limit the number of the display screens. Example

[0126] refer to Figure 4a , Figure 4a A schematic diagram of the structure of a single switch in a dual-screen mobile phone according to an embodiment of the present application is shown. Figure 4a As shown, the mobile phone includes SoC410 (equivalent to Figure 2 The processor 110 or including the processor 110), the ASIC chip 420, a switch 430 and two display screens, such as Figure 4a The display screen PNL1 (corresponding to the first display screen) and the display screen PNL2 (corresponding to the second display screen) in FIG. Figure 4a As shown, SoC410 includes a camera serial interface CSI and two display serial interfaces DSI. Figure 4aDSI1 and DSI2 are shown in FIG. Among them, the camera serial interface CSI is used to transmit the data processed by the ASIC chip 420 back to the SoC410, and at least one of the two display serial interfaces is used by the SoC410 to transmit the data to be processed to the ASIC chip 420. The ASIC chip 420 includes an output terminal 421, an output terminal 422, an input terminal 423 and an input terminal 424. The switch includes an input terminal 431, an output terminal 432 and an output terminal 433.

[0127] The corresponding channels between the ports are described below.

[0128] like Figure 4a As shown, CSI is connected to the output terminal 421 of the ASIC chip to form a transmission channel E. DSI1 is connected to the input terminal 413 of the ASIC chip to form a transmission channel C. The output terminal 422 of the ASIC chip is connected to PNL1 to form a transmission channel D for outputting signals to the display screen PNL1. The input terminal 431 of the switch is connected to DSI2, the output terminal 432 is connected to the ASIC chip to form a transmission channel A, and the output terminal 433 is connected to the display screen PNL2 to form a transmission channel B.

[0129] The following is a description of the data flow between channels in conjunction with the accompanying drawings. Figure 4a As shown, in an embodiment of the present application, channel E is used to return the image data processed by the ASIC chip to the SoC. Transmission channel C is used to output a signal from the SoC to the ASIC chip, for example, to output the image data to be processed. Transmission channel D is used to output a signal to PNL1, for example, the signal can be a signal generated by enhancing the image transmitted through channel C or channel A via the ASIC chip, or it can be a signal generated by the image transmitted through channel C via the SoC. Transmission channel A is used to transmit the signal output by DSI2 of the SoC, for example, the image signal before processing, to the ASIC chip. Transmission channel B is used to transmit the signal output by DSI2 of the SoC, which can be the image data processed by the ASIC chip output via DSI2, or the signal corresponding to the data output by the SoC that does not need to be processed via DSI2, to the display screen PNL2. It should be noted that the signal output by DSI2 can be a different type of signal from DSI1, for example, DSI1 can output an image signal, and DSI1 can output a barrage or text image signal. In some embodiments, the image signal to be processed can also be output by DSI1, which is not limited here. The following embodiments are described as herein.

[0130] Combined with the data flow between the above channels, and combined with the specific figures and Table 1, the following describes how SoC adjusts the connection relationship between DSI2, ASIC chip and display screen by controlling the switching switch to achieve single-screen and dual-screen display, as well as the flow direction of data flow in different display scenarios. Specifically, the following scenarios may be included, refer to Table 1.

[0131] Table 1

[0132] Scenario plan Implementation Scenario 1 Dual screen display (1) ASIC chip on / off; (2) A off, B on; (3) C, D on; Scenario 2 PNL1+ ASIC chip (1) ASIC chip on / off; (2) A on, B off; (3) C, D on; Scene 3 PNL2 + ASIC chip (1) ASIC chip on / off; (2) A off, B on (3) C on, D off, E on

[0133] It should be noted that the ASIC chip on in the table indicates that the ASIC chip is in the on state and can enhance and optimize the unprocessed image signal. The ASIC chip off indicates that the ASIC chip is in the off state. At this time, the ASIC chip only serves as an ordinary transmission channel and does not enhance and optimize the image signal. In the present application, the SoC can turn on or off the ASIC chip according to whether the request received is to enhance and optimize the image. In the following embodiments, the ASIC chip on / off is the same as here and will not be repeated.

[0134] refer to Figure 4b , Figure 4b The schematic diagram of the connection structure of scene 1 in Table 1 is shown. Scene 1 is a dual-screen display scene, that is, PNL1 and PNL2 are displayed simultaneously. Figure 4b As shown, the switch control and data flow in this scenario are as follows: when the SoC receives the dual-screen display instruction, it executes the instruction and controls the switching switch 430 to connect DSI2 with PNL2, that is, channel A is closed and channel B is opened, so that DSI2 is connected to PNL2. Channel C and channel D are opened to connect DSI1 with PNL1. If the dual-screen display instruction does not include a request for image signal optimization processing, the data flow for PNL1 is as follows: the SoC outputs the unprocessed image signal through DSI1, and transmits it to PNL1 via channel C, the ASIC chip in the closed state, and channel D, so as to realize the display of PNL1. The data flow for PNL2 is as follows: the SoC outputs the unprocessed image signal through DSI2, and transmits it to PNL2 via channel B, so as to realize the display of PNL2.

[0135] In the above process, if the dual-screen display instruction includes a request for optimizing the image signal corresponding to PNL1, the SoC turns on the ASIC chip, outputs the unprocessed image signal through DSI1, and transmits it to the ASIC chip through channel C. The ASIC chip processes the unprocessed image signal and transmits the processed image signal to PNL1 through channel D. This allows PNL1 to display conventionally (the displayed image is not processed by the ASIC chip) or to enhance and optimize the display (the displayed image is enhanced and optimized by the ASIC chip).

[0136] refer to Figure 4c , Figure 4c The connection structure diagram of scene 2 in Table 1 is shown. Scene 2 is a scene in which PNL1 is displayed alone and image enhancement and optimized display can be achieved. Figure 4c As shown, in this scenario, the situation and data flow of SoC controlling the switching switch are as follows: when SoC receives the instruction displayed by PNL1, SoC executes the instruction and controls the switching switch 430 to connect DSI2 with the ASIC chip, and the ASIC chip with PNL1. If the instruction requires enhancement and optimization processing, SoC controls the ASIC chip to turn on, close channel B, turn on channel A, channel C and channel D, and realize the connection between the two interfaces of SoC and the ASIC chip, and the ASIC chip with PNL1. SoC sends the image signal to be processed to the ASIC chip through at least one of channel A and channel C. The ASIC chip processes the image signal to obtain the processed image signal. The ASIC chip sends the processed image signal to PNL1 via channel D, thereby realizing the enhancement and optimization display of the image by PNL1.

[0137] In scenario 2, if there is no enhancement and optimization request in the instruction, the SoC does not need to turn on the ASIC chip, that is, the ASIC chip does not process the image signal, and the SoC directly outputs the unprocessed image signal to PNL1.

[0138] refer to Figure 4d , Figure 4d The connection structure diagram of scene 3 in Table 1 is shown. Scene 3 is a scene in which PNL2 is displayed alone and image enhancement and optimized display can be achieved. Figure 4dAs shown, in this scenario, the situation and data flow of SoC controlling the switching switch are as follows: when SoC receives the instruction displayed by PNL2, SoC executes the instruction and controls the switching switch 430 to connect DSI2 with PNL2. If the instruction includes a request for enhancement and optimization processing, SoC turns on the ASIC chip, turns off channels A and D, turns on channels B, C and E, and realizes that SoC is connected to the ASIC chip through interface CSI and interface DSI1, and interface DSI2 is connected to PNL2. When transmitting data, SoC sends the image signal to be processed, such as "videoX", to the ASIC chip via channel C. The ASIC chip processes the image signal to obtain a processed image signal, such as "videoY". The ASIC chip transmits it back to the SoC through channel E, and then the SoC sends the processed image signal to PNL2 through channel B, thereby realizing the enhancement and optimization display of the image by PNL2.

[0139] In scenario 3, if there is no enhancement and optimization requirement in the instruction, the SoC does not need to turn on the ASIC chip, that is, the ASIC chip does not process the image signal, and the SoC directly outputs the unprocessed image signal to PNL2.

[0140] It should be noted that the channel D can be closed by controlling the ASIC chip through the software module not to provide data to PNL1. Or by setting a one-way switch, the SoC disconnects the channel D by controlling the switch. The present application does not limit the closing method.

[0141] According to the electronic device of the embodiment of the present application, it is possible to realize multi-screen display simultaneously, and it is also possible to realize that one ASIC chip is connected to multiple display screens respectively, so that each display screen can obtain an enhanced image effect, thereby improving the user experience. Example

[0142] refer to Figure 5a , Figure 5a A schematic diagram of the structure of multiple switches in a dual-screen mobile phone according to another embodiment of the present application is shown. Figure 4a Two switching switches are added to the structure to increase the data processing speed.

[0143] like Figure 5a As shown, the mobile phone includes SoC510, ASIC chip 520, switch 530, switch 540 and switch 550, and two display screens, such as Figure 5a Display screen PNL1 and display screen PNL2 in the.

[0144] like Figure 5a As shown, the SoC includes two display serial interfaces, such as Figure 5aASIC chip 520 includes output terminal 521, output terminal 522, input terminal 523 and input terminal 524. Switch 530 includes input terminal 531, output terminal 532 and output terminal 533. Switch 540 includes input terminal 541, input terminal 542 and output terminal 543. Switch 550 includes input terminal 551, output terminal 552 and output terminal 553.

[0145] The corresponding channels between the ports are described below.

[0146] like Figure 5a As shown, DSI1 is connected to the input terminal 523 of the ASIC chip to form a transmission channel C. The input terminal 531 of the switching switch 530 is connected to DSI2, the output terminal 532 is connected to the input terminal 524 of the ASIC chip to form a transmission channel A, and the output terminal 533 is connected to the input terminal 542 of the switching switch 540 to form a transmission channel B. The input terminal 541 of the switching switch 540 is connected to the output terminal 553 of the switching switch 550 to form a channel G, and the output terminal 552 is connected to the display screen PNL2 to form a transmission channel H. The input terminal 551 of the switching switch 550 is connected to the output terminal 522 of the ASIC chip to form a transmission channel D, and the output terminal 552 of the switching switch 550 is connected to the display screen PNL1 to form a transmission channel F.

[0147] The data flow between the channels is described below with reference to the accompanying drawings.

[0148] like Figure 5a As shown, in an embodiment of the present application, transmission channel C can output a signal from DSI1 of SoC to ASIC chip, for example, output an unprocessed image signal, which can be processed by ASIC chip to obtain a processed image signal, or directly transmitted to PNL1 or PNL2 without being processed by ASIC chip. Transmission channel A can output a signal from DSI2 of SoC to ASIC chip, which signal can be the same as the signal type transmitted by transmission channel C (data is not repeated), or it can be different, for example, output an unprocessed image signal, or a data signal such as barrage, text, etc. Transmission channel B and transmission channel H are used to output a signal from DSI2 of SoC to display screen PNL2, which signal can be an unprocessed image signal. Transmission channel D and transmission channel F are used to output a signal from ASIC chip to display screen PNL1, which signal can be an image signal processed by ASIC chip or an unprocessed image signal. Transmission channel D, transmission channel G and transmission channel H are used to output a signal from ASIC chip to display screen PNL1, which signal can be an image signal processed by ASIC chip or an unprocessed image signal.

[0149] Combined with the data flow between the above channels, and combined with the specific drawings, the SoC controls three switches to adjust the connection relationship between DSI1, DSI2, ASIC chip and display screen to achieve single-screen and dual-screen display of the mobile phone, as well as the flow direction of data flow in different display scenarios. Specifically, the following scenarios can be included, refer to Table 2.

[0150] Table 2

[0151] Scenario plan Implementation Scenario 1 Dual screen display (1) ASIC chip on / off; (2) A / G off; (3) C / D / F / B / H on Scenario 2 PNL1 + ASIC chip (1) ASIC chip on / off; (2) B / G / H off; (3) A / C / D / F on Scene 3 PNL2 + ASIC chip (1) ASIC chip on / off; (2) B / F off; (3) A / C / D / G / H on

[0152] refer to Figure 5b , Figure 5b The schematic diagram of the connection structure corresponding to the scenario 1 in Table 2 is shown. Among them, scenario 1 is a dual-screen display scenario, that is, PNL1 and PNL2 are displayed at the same time. Figure 5b As shown, the switch control and data flow in this scenario are as follows: when the SoC receives the dual-screen display instruction, it executes the instruction, and the SoC controls the switching switch 530, the switching switch 540 and the switching switch 550 to turn off the channels A and G, and turn on the channels C, D, F, B and H, so that DSI2 is connected to PNL2, and DSI1 is connected to PNL1. If the dual-screen display instruction does not include a request for image signal optimization processing, the data flow for PNL1 is as follows: the SoC outputs the unprocessed image signal through DSI1, and transmits it to PNL1 via channel C, the ASIC chip in the closed state, channel D and channel F, so as to realize the display of PNL1. The data flow for PNL2 is as follows: the SoC outputs the unprocessed image signal through DSI2, and transmits it to PNL2 via channels B and H, so as to realize the display of PNL2. In the above process, if the dual-screen display instruction includes a request for optimizing the image signal corresponding to PNL1, the SoC turns on the ASIC chip, outputs the unprocessed image signal through DSI1, and transmits it to the ASIC chip through channel C. The ASIC chip processes the unprocessed image signal and transmits the processed image signal to PNL1 through channels D and F. This allows PNL1 to display conventionally (the displayed image is not processed by the ASIC chip) or to enhance and optimize the display (the displayed image is enhanced and optimized by the ASIC chip).

[0153] refer to Figure 5c , Figure 5c The schematic diagram of the connection structure corresponding to the scene 2 in Table 2 is shown. Among them, the scene 2 is a scene in which PNL1 is displayed alone and image enhancement and optimized display can be achieved. Figure 5cAs shown, in this scenario, the situation and data flow of SoC controlling the switch are as follows: when SoC receives the instruction displayed by PNL1, if the instruction includes a request for image enhancement and optimization processing, SoC executes the instruction, turns on the ASIC chip, and SoC controls the switch 530, switch 540 and switch 550 to turn off channels B, G and H, and turn off channels A, C, D and F, so as to connect the interfaces DSI1 and DSI2 of SoC to the ASIC chip and connect the ASIC chip to PNL1. The data processing process is as follows: SoC sends the unprocessed image signal to the ASIC chip via any one or both of channels A and C, and the ASIC chip processes the image signal to obtain the processed image signal, and sends the processed image signal to PNL1 via channels D and F, so as to realize the enhancement and optimization display of the image by PNL1. If there is no request for enhancement and optimization in the instruction, SoC can directly send it to PNL1 via channel C, the ASIC chip in the closed state, channel D and channel F, so as to realize that PNL1 can enhance and optimize the display, or can also display normally.

[0154] refer to Figure 5d , Figure 5d The schematic diagram of the connection structure corresponding to the scenario 3 in Table 2 is shown. Among them, scenario 3 is a scenario in which PNL2 is displayed alone and image enhancement and optimized display can be achieved. Figure 5d As shown, in this scenario, the situation and data flow of SoC controlling the switching switch are as follows: when SoC receives the instruction displayed by PNL2, if the instruction includes a request for image enhancement and optimization processing, SoC executes the instruction, turns on the ASIC chip, and SoC controls the switching switch 530, the switching switch 540 and the switch 550, turns off channel B and channel F, turns on channel A, channel C, channel D, channel G and channel H, and connects the ASIC chip to the display screen PNL2. When transmitting data, SoC sends the image signal to be processed to the ASIC chip through one or two of the transmission channels A and C, and the ASIC chip performs post-processing on the image signal to obtain the processed image signal, and sends the processed image signal to PNL2 through the transmission channels D, G and H, thereby realizing the enhancement and optimization display of the image signal by PNL2. Compared with the first embodiment, the ASIC chip does not need to transmit the data back to the SoC, and can directly transmit it to PNL2, which has more advantages in power consumption, data delay and system software implementation. Example

[0155] refer to Figure 6a , Figure 6aThe schematic diagram of the structure of the switch integrated into the chip in a dual-screen mobile phone of an embodiment of the present application is shown. From the appearance structure, the line connection method outside the ASIC chip is simple. Figure 6a As shown, the mobile phone includes a SoC 610 , an ASIC chip 620 , and two display screens (eg, PNL1 and PNL2 ).

[0156] like Figure 6a As shown, the SoC includes two display serial interfaces, such as Figure 6a ASIC chip 620 includes two input terminals and two output terminals, and the specific ports are as follows: Figure 6b As shown, the ASIC chip 620 includes an input terminal DSI1-RX1 and an input terminal DSI2-RX2, an output terminal DSI1-TX1, and an output terminal DSI2-TX2.

[0157] The corresponding channels between the ports are described below.

[0158] like Figure 6a As shown, the interface DSI1 of the SOC is connected to the input terminal DSI1-RX1 of the ASIC chip to form a transmission channel A. The interface DSI2 of the SOC is connected to the input terminal DSI2-RX2 of the ASIC chip to form a transmission channel B. The output terminal DSI1-TX1 of the ASIC chip is connected to the display screen PNL1 to form a transmission channel C. The output terminal DSI2-TX2 of the ASIC chip is connected to the display screen PNL2 to form a transmission channel D.

[0159] Among them, transmission channel A and transmission channel B are used to output signals from SoC to ASIC chip, for example, output image data to be processed, and the output signal can be processed by ASIC chip, and the processed image signal is output to PNL1 or PNL2. Among them, transmission channel C is used to output signals to display screen PNL1. Transmission channel D is used to output signals to display screen PNL2.

[0160] The internal structure of the ASIC chip is described below.

[0161] refer to Figure 6b , Figure 6b The figure shows the internal structure of an ASIC chip according to an embodiment of the present application. Figure 4a and Figure 5a Compared with the structure that integrates the control switch into the ASIC chip, the circuit occupancy area is reduced and space is saved for the hardware structure. Figure 6b As shown, the ASIC chip includes a data processing unit, a switch 621, a switch 622, a switch 623, a switch 624, and a plurality of interfaces (with Figure 6aThe data processing unit is a core component for post-processing image data. When the image data processed by the data processing unit is displayed on the display screen, an enhanced and optimized visual effect can be achieved.

[0162] like Figure 6b As shown, the multiple interfaces of the ASIC chip are respectively an input terminal DSI1-RX1 for connecting to DSI1, an input terminal DSI1-RX2 for connecting to DSI2, an output terminal DSI1-TX1 for connecting to PNL1, and an output terminal DSI2-RX2 for connecting to PNL2. The data processing unit includes an input terminal a, an input terminal b, an output terminal c, and an output terminal d. The switching switch 621 includes an input terminal a1, an output terminal b1, and an output terminal c1. The switching switch 622 includes an input terminal a2, an output terminal b2, and an output terminal c2. The switching switch 623 includes an input terminal a3, an input terminal b3, and an output terminal c3. The switching switch 624 includes an input terminal a4, an input terminal b4, and an output terminal c4.

[0163] The following describes the corresponding channels between the ports in the ASIC chip.

[0164] like Figure 6b As shown, the input interface DSI1-RX1 of the ASIC chip is connected to the input terminal a1 of the switching switch 621 to form a transmission channel X1. The output terminal b1 of the switching switch 621 is connected to the input terminal a3 of the switching switch 623 to form a transmission channel X2, and the output terminal c1 is connected to the input terminal b of the data processing unit to form a transmission channel X4. The input terminal b3 of the switching switch 623 is connected to the output terminal c of the data processing unit to form a transmission channel X5, and the output terminal c3 is connected to the output interface DSI1-TX1 of the ASIC chip to form a transmission channel X3.

[0165] The input interface DSI2-RX2 of the ASIC chip is connected to the input terminal a2 of the switching switch 622 to form a transmission channel Y1. The output terminal b2 of the switching switch 622 is connected to the input terminal a4 of the switching switch 624 to form a transmission channel Y2, and the output terminal c2 is connected to the input terminal a of the data processing unit to form a transmission channel Y4. The input terminal b4 of the switching switch 624 is connected to the output terminal d of the data processing unit to form a transmission channel Y5, and the output terminal c4 is connected to the output interface DSI2-TX2 of the ASIC chip to form a transmission channel Y3.

[0166] The transmission line composed of transmission channels X1, X2 and X3 is used to transmit the signal input through DSI1-RX1. Figure 6aThe transmission channel C in is connected to realize the connection with the display screen PNL1, and outputs a signal to PNL1. The signal does not pass through the data processing unit and is a signal that has not been processed by the ASIC chip.

[0167] The transmission line composed of transmission channels X1, X4, X5 and X3 is used to transmit the image signal to be processed input through DSI1-RX1 to the data processing unit for processing. The data processing unit then transmits the processed image signal to DSI1-TX1, and the transmission channel C transmits the processed image signal to the display screen PNL1.

[0168] The transmission line composed of transmission channels Y1, Y2 and Y3 is used to transmit the signal input through DSI2-RX2. Figure 6a The transmission channel D in is connected to realize the connection with the display screen PNL2, and outputs a signal to PNL1. The signal does not pass through the data processing unit and is a signal that has not been processed by the ASIC chip.

[0169] The transmission line composed of transmission channels Y1, Y4, Y5 and Y3 is used to transmit the image signal to be processed input through DSI2-RX2 to the data processing unit for processing, and then transmit the processed image signal to DSI2-TX2, and the transmission channel D transmits the processed image signal to the display screen PNL2.

[0170] Combine the following Figure 6a , Figure 6b Table 3 shows that SoC adjusts the connection relationship between DSI1, DSI2, ASIC chip and display screen by controlling four switching switches to realize single-screen and dual-screen display of mobile phones, as well as the flow direction of data flow in different display scenarios. The following scenarios can be included, refer to Table 3.

[0171] Table 3

[0172] Scenario plan Implementation Scenario 1 Dual screen display (1) ASIC chip on / off, transmitted to PNL1 via AC (2) ASIC chip on / off, transmitted to PNL2 via BD Scenario 2 PNL1 + ASIC chip (1) ASIC chip on / off; (2) A / B / C on, or A / C on (3) D off, or B / D off (4) The internal structure of the ASIC chip is: X1 / X4 / X5 / X3 on, the rest of the channels off, or X1 / X4 / Y1 / Y4 / X5 / X3 on, X2 / Y2 / Y5 / Y3 off Scene 3 PNL2 + ASIC chip (1) ASIC chip on / off; (2) A / B / D on, or B / D on (3) C off, or A / C off (4) The internal structure of the ASIC chip is: Y1 / Y4 / Y5 / Y3 on, the rest of the channels off, or X1 / X4 / Y1 / Y4 / X5 / X3 on, X2 / Y2 / X5 / X3 off

[0173] refer to Figure 6a and 6bCombined with Table 3, scenario 1 is a dual-screen display scenario, that is, PNL1 and PNL2 are displayed simultaneously. In this scenario, when the SoC receives a dual-screen display instruction from PNL1 and PNL2, if there is no enhancement and optimization request in the instruction, the SoC executes the instruction and controls the switching switch 621 and the switching switch 623 to connect channels X1, X2 and X3, so that DSI1 is directly connected to PNL1. The SoC controls the switching switch 622 and the switching switch 624 to connect channels Y1, Y2 and Y3, so that DSI2 is directly connected to PNL2. The data flow for PNL1 is: the SoC outputs the unprocessed image signal through DSI1, reaches the input end DSI1-RX1 of the ASIC chip through channel A, reaches the output end DSI1-TX1 through channels X1, X2 and X3, and then transmits it to PNL1 through channel C to realize the display of PNL1. The data flow for PNL2 is as follows: SoC outputs the unprocessed image signal through DSI2, reaches the input end DSI2-RX2 of the ASIC chip through channel B, reaches the output end DSI2-TX2 through channels Y1, Y2 and Y3, and is then transmitted to PNL2 through channel D to realize the display of PNL2.

[0174] If there is a request for PNL1 enhancement and optimization in the instruction, the SoC executes the instruction, turns on the ASIC chip, and controls the switching switch 621 and the switching switch 623 to connect the channels X1, X4, X5 and X3, so that DSI1 is connected to the data processing unit, and the data processing unit is directly connected to PNL1. The data flow is as follows: the SoC outputs the unprocessed image signal through DSI1, reaches the input end DSI1-RX1 of the ASIC chip through channel A, and transmits it to the data processing unit through channels X1 and X4. The data processing unit processes the image signal and transmits the processed image signal to the output end DSI1-TX1 through channels X5 and X3, and then transmits it to PNL1 through channel C, so as to realize the image enhancement and optimized display of PNL1.

[0175] If there is a request for PNL2 enhancement and optimization in the instruction, the SoC executes the instruction, turns on the ASIC chip, and controls the switching switch 622 and the switching switch 624 to connect channels Y1, Y4, Y5 and Y3, so that DSI2 and PNL2 are directly connected. The data flow is as follows: the SoC outputs the unprocessed image signal through DSI2, reaches the input terminal DSI2-RX2 of the ASIC chip through channel B, and transmits it to the data processing unit through channels Y1 and Y4. The data processing unit processes the image signal and transmits the processed image signal to the output terminal DSI2-TX2 through channels Y5 and Y3, and then transmits it to PNL2 through channel D, so as to realize the image enhancement and optimized display of PNL2.

[0176] In the present application, scenario 2 is a scenario where PNL1 is displayed alone, and the scenario further includes a scenario where PNL1 is connected to the SoC and ASIC chip in a single channel, and a scenario where PNL1 is connected to the SoC and ASIC chip in a dual channel. For the selection of single-channel connection and dual-channel connection, the SoC can make a selection according to preset rules. For example, under normal circumstances, a dual-channel connection can be selected by default, or when the SoC usage rate reaches a set value, such as a usage rate of more than 70%, a single-channel connection can be made. In the present application, the single-channel and dual-channel connection modes are not limited.

[0177] First, the scenario of single-channel connection between PNL1, SoC and ASIC chip in scenario 2 is described. When SoC receives the instruction displayed by PNL1, if the instruction includes a request for image enhancement and optimization, SoC executes the instruction, turns on the ASIC chip, turns on channels A and C, and turns off channels B and D. SoC controls the internal structure of the ASIC chip as follows: turns on channels X1, X4, X5 and X3, and turns off the remaining channels, so as to realize single-channel connection between DSI1 and ASIC chip, and the ASIC chip is connected to PNL1. The data flow direction is as follows: SoC sends the image signal to be processed to the data processing unit of the ASIC chip through channels X1 and X4, and the data processing unit of the ASIC chip obtains the image signal and processes the image signal to obtain the processed image signal, and the ASIC chip sends the processed image signal to PNL1 via channels X5 and X3. Thus, PNL1 can enhance and optimize the display of the image signal. If the instruction does not include a request for image enhancement and optimization, it reaches the output terminal DSI1-TX1 via channels X1, X2, and X3, and is then transmitted to PNL1 via channel C to achieve normal display of PNL1.

[0178] Let's describe the scenario 2, where PNL1 is connected to the SoC and ASIC chips in two ways. When the SoC receives the instruction displayed by PNL1, if the instruction includes a request for image enhancement and optimization, the SoC executes the instruction, turns on the ASIC chip, turns on channels A, B, and C, and turns off channel D. The SoC controls the internal structure of the ASIC chip as follows: channels X1, X4, Y1, Y4, X5, and X3 are turned on, and channels X2, Y2, Y5, and Y3 are turned off, so that DSI1 and DSI2 are connected to the ASIC chip in two ways, and the ASIC chip is connected to PNL1. The data flow is as follows: the SoC sends the unprocessed image signal to the data processing unit of the ASIC chip through channels X1 and X4, as well as channels Y1 and Y4, and the data processing unit of the ASIC chip obtains the image signal and processes the image to obtain the processed image signal. The data processing unit of the ASIC chip sends the processed image signal to PNL1 via channels X5 and X3, thereby realizing the enhancement and optimized display of the image signal by PNL1.

[0179] In one embodiment of the present application, if in scenario 2, when the instruction does not include a request for image enhancement and optimization, the SoC can control the switching switch to connect channels A, X1, X2, X3, and C, and the unprocessed image signal reaches the output terminal DSI1-TX1 via channels X1, X2, and X3, and is then transmitted to PNL1 by channel C to realize the normal display of PNL1. This process can refer to the switch control process and data flow for the display of PNL1 in scenario 1.

[0180] Scenario 3 is a scenario where PNL2 is displayed alone, and this scenario further includes a scenario where PNL2 is connected to the SoC and ASIC chips in a single channel, and a scenario where PNL2 is connected to the SoC and ASIC chips in a dual channel.

[0181] First, the scenario of single-channel connection between PNL2, SoC and ASIC chip in scenario 3 is described. When SoC receives the instruction displayed by PNL2, if the instruction includes a request for image enhancement and optimization, SoC executes the instruction, turns on the ASIC chip, turns on channel B and channel D, and turns off channel C. The internal structure of the ASIC chip is: channel Y1, channel Y4, channel Y5 and channel Y3 are turned on, and the remaining channels are turned off, so that DSI2 is connected to the ASIC chip in a single channel, and the ASIC chip is connected to PNL2. The data flow is as follows: SoC sends the image signal to be processed to the data processing unit of the ASIC chip through channels Y1 and Y4, and the data processing unit of the ASIC chip obtains the image signal and processes the image signal to obtain the processed image signal. The data processing unit of the ASIC chip sends the processed image signal to PNL2 via channels Y5 and Y3, thereby realizing the enhancement and optimization display of the image by PNL2.

[0182] Describe the scenario of dual-channel connection between PNL2 and SoC and ASIC chips in scenario 3. When SoC receives the instruction displayed by PNL2, if the instruction includes a request for image enhancement and optimization, SoC executes the instruction, turns on the ASIC chip, turns on channels A, B and D, and turns off channel C. The internal structure of the ASIC chip controlled by SoC is as follows: SoC turns on channels X1, X4, Y1, Y4, X5 and X3, and turns off channels X2, Y2, X5 and X3. DSI1 and DSI2 are dual-channel connected to the ASIC chip, and the ASIC chip is connected to PNL2. The data flow is as follows: SoC sends the image signal to be processed to the data processing unit of the ASIC chip through channels X1 and X4, and channels Y1 and Y4, and the data processing unit of the ASIC chip obtains the image signal and processes the image signal to obtain the processed image signal. The data processing unit of the ASIC chip sends the processed image signal to PNL2 via channels Y5 and Y3, thereby realizing the enhancement and optimization display of the image by PNL2.

[0183] In one embodiment of the present application, if in scenario 3, when the instruction does not include a request for image enhancement and optimization, the SoC can connect channel B, channel Y1, channel Y2, channel Y3 and channel D by controlling the switching switch, and the SoC outputs the unprocessed image signal through DSI2, reaches the input end DSI2-RX2 of the ASIC chip through channel B, reaches the output end DSI2-TX2 through channels Y1, Y2 and Y3, and then transmits it to PNL2 through channel D to realize the normal display of PNL2. This process can refer to the switch control process and data flow for the display of PNL2 in scenario 1.

[0184] According to the electronic device of the embodiment of the present application, it is possible to realize multi-screen display simultaneously, and it is also possible to realize that one ASIC chip is connected to multiple display screens respectively, so that each display screen can obtain an enhanced image effect, thereby improving the user experience.

[0185] In some embodiments, when dual-screen display is not required, a switching switch may be directly added between the ASIC chip and the multiple display screens to enable the ASIC chip to be directly connected to the multiple display screens respectively. Example

[0186] refer to Figure 7 As shown, Figure 7 The schematic diagram of the structure of a dual-screen mobile phone according to an embodiment of the present application when the dual-screen display is not provided is shown. Figure 7 As shown, the mobile phone includes SoC710, ASIC chip 720, a switching switch 730 and two display screens, such as PNL1 and PNL2.

[0187] like Figure 7 As shown, the SoC includes a display serial interface DSI1 and a display serial interface DSI2. The ASIC chip 720 includes an input terminal 721, an input terminal 722, an output terminal 723 and an output terminal 724. The switch 730 includes an input terminal 731, an output terminal 732 and an output terminal 733.

[0188] The corresponding channels between the ports are described below.

[0189] like Figure 7 As shown, the interface DSI1 of the SoC is connected to the input terminal 721 of the ASIC chip to form a transmission channel C. DSI2 is connected to the input terminal 722 of the ASIC chip to form a transmission channel A. The input terminal of the switching switch 730 is connected to the output terminal 724 of the ASIC chip to form a transmission channel D, the output terminal 732 is connected to PNL1 to form a transmission channel F, and the output terminal 733 is connected to PNL2 to form a transmission channel H.

[0190] The data flow between the channels is described below with reference to the accompanying drawings.

[0191] like Figure 7As shown, transmission channel C is used to output signals from DSI1 of SoC to ASIC chip, for example, output image signals to be processed, which can be processed by ASIC chip and delivered to PNL1 and PNL2. Transmission channel A is used to transmit the signal output by DSI2 of SoC to ASIC chip, which can also be processed by ASIC chip and delivered to PNL1 and PNL2. Transmission channel D is used to output signals, such as processed image signals, to two display screens. Transmission channel F is used to transmit the signal output by ASIC chip to PNL1, and transmission channel H is used to transmit the signal output by ASIC chip to PNL2.

[0192] Combined with the data flow between the above channels, combined with the specific figures and Table 4, the SoC is introduced to adjust the connection relationship between the ASIC chip and the display screen by controlling the switching switch to achieve enhanced display of a single screen, as well as the flow direction of data flow in different display scenarios. The following scenarios may be included, refer to Table 4.

[0193] Table 4

[0194] Scenario plan Implementation Scenario 1 PNL1 + ASIC chip (1) ASIC chip on / off; (2) A, C, D, F on; (3) H off Scenario 2 PNL2 + ASIC chip (1) ASIC chip on / off; (2) A, C, D, H on; (3) F off

[0195] refer to Figure 7 Combined with Table 4, scene 1 is the scene displayed by PNL1 alone, such as Figure 7 As shown, in this scenario, when SoC receives a display instruction from PNL1, if the instruction includes a request for image enhancement and optimization, SoC turns on the ASIC chip, and SoC controls the switch to turn on one or both of channels A and C, as well as channels D and F, and turns off channel H, so as to connect the ASIC chip with PNL1. The data processing process is as follows: SoC sends the image signal to be processed to the ASIC chip through channels A and C, the ASIC chip processes the image signal to obtain the processed image signal, and the ASIC chip directly sends the processed image signal to PNL1 through channel F, thereby realizing the enhancement and optimization display of the image data by PNL1. If the instruction does not include a request for image enhancement and optimization, SoC does not need to turn on the ASIC chip (the ASIC chip only serves as a channel for data transmission and does not process the image data), and transmits the unprocessed signal to PNL1 through one or both of channels A and C, as well as channels D and F, to realize the normal display of PNL1.

[0196] Scene 2 is the scene displayed by PNL2 alone. Figure 7As shown, when SoC receives a display instruction from PNL1, if the instruction includes a request for image enhancement and optimization, SoC turns on the ASIC chip, and SoC controls the switch to turn on one or both of channels A and C, as well as channels D and H, and turns off channel F, so as to connect the ASIC chip with PNL2. The data flow is as follows: SoC sends the image signal to be processed to the ASIC chip through channels A and C, the ASIC chip processes the image signal to obtain the processed image signal, and the ASIC chip directly sends the processed image signal to PNL2 through channel H, thereby realizing the enhancement and optimization display of the image by the display screen PNL2. If the instruction does not include a request for image enhancement and optimization, the SoC does not need to turn on the ASIC chip (the ASIC chip only serves as a channel for data transmission and does not process the image data), and transmits the unprocessed signal to PNL2 through one or both of channels A and C, as well as channels D and H, to realize the normal display of PNL2.

[0197] In the above embodiment, the description is made by taking the case where there are two DSI interfaces as an example. In some embodiments, when there are more DSI interfaces, the connection relationship between the SoC, the ASIC chip and the display screen may also include the following situations. Example

[0198] refer to Figure 8 , Figure 8 The schematic diagram of the structure of a dual-screen mobile phone with three DSI interfaces in one embodiment of the present application is shown. Figure 8 As shown, the mobile phone includes a SoC 810, an ASIC chip 820, a switching switch 830, a switching switch 840, and two display screens (eg, PNL1 and PNL2).

[0199] like Figure 8 As shown, the SoC includes a display serial interface DSI1, a display serial interface DSI2, and a display serial interface DSI3. The ASIC chip 820 includes an input terminal 821, an input terminal 822, an output terminal 823, and an output terminal 824. The switch 830 includes an input terminal 831, an input terminal 832, and an output terminal 833. The switch 840 includes an input terminal 841, an input terminal 842, and an output terminal 843.

[0200] The corresponding channels between the ports are described below.

[0201] like Figure 8As shown, DSI1 is connected to the input terminal 821 of the ASIC chip to form a transmission channel C, DSI2 is connected to the input terminal 822 of the ASIC chip to form a transmission channel A, and DSI3 is connected to the input terminal 842 of the switch to form a transmission channel B. The output terminal 824 of the ASIC chip is connected to the input terminal 831 of the switch 830 to form a transmission channel D. The output terminal 832 of the switch 830 is connected to PNL1 to form a transmission channel F, and the output terminal 833 is connected to the input terminal 841 of the switch 840 to form a transmission channel G. The input terminal 843 of the switch 840 is connected to PNL2 to form a transmission channel H.

[0202] Transmission channel C and transmission channel A are used to output signals from SoC to ASIC chip, for example, outputting the image signals "VideoX" and "VideoX'" to be processed. Transmission channel D is used to output signals to PNL1 and PNL2. Transmission channel F is used to transmit signals to PNL1. Transmission channel G and transmission channel H are used to transmit signals to PNL2. Transmission channel B is used to output the signal output by DSI3 of SoC. Transmission channel H is used to transmit signals to display screen PNL2.

[0203] Combined with the data flow between the above channels, Figure 8 Table 5 shows that SoC adjusts the connection relationship between DSI1, DSI2, DSI3, ASIC chip and display screen by controlling two switching switches to realize single-screen and dual-screen display of mobile phones, as well as the flow direction of data flow in different display scenarios. The following scenarios can be included, refer to Table 5.

[0204] Table 5

[0205] Scenario plan Implementation Scenario 1 Dual screen display (1) ASIC chip on / off (2) A, G off; (3) C, D, F, B, H on Scenario 2 PNL1 + ASIC chip (1) ASIC chip on / off; (2) G, B, H off; (3) A, C, D, F on Scene 3 PNL2 + ASIC chip (1) ASIC chip on / off; (2) A, C, D, G, H on; (3) F, B off

[0206] refer to Figure 8 As shown in Table 5, scene 1 is a dual-screen display scene, that is, a scene in which PNL1 and PNL2 are displayed simultaneously. Figure 8As shown, when the SoC receives the dual-screen display instruction and executes the instruction, the SoC controls the switching switch 820 and the switching switch 830 to turn off channel A and channel G, and turn on channel C, channel D, channel F, channel B and channel H, so that DSI1 is directly connected to PNL1. DSI3 is connected to PNL2. Data flow for PNL1: If the dual-screen display instruction does not include a request for image signal optimization processing, the SoC outputs the unprocessed image signal through any one or both of DSI1 and DSI2, and transmits the unprocessed image signal to PNL1 via channel C, the ASIC chip in the closed state, and channel D and channel F, so as to realize the display of PNL1. Data flow for PNL2: The SoC outputs the unprocessed image signal through DSI3, and transmits it to PNL2 via channel B and channel H, so as to realize the display of PNL2.

[0207] In the above process, if the dual-screen display instruction includes a request for optimizing the image signal corresponding to PNL1, the SoC turns on the ASIC chip, outputs the unprocessed image signal through either or both of DSI1 and DSI2, and transmits the unprocessed image signal to the ASIC chip via channel C and channel A, and the ASIC chip processes the unprocessed image signal and transmits the processed image signal to PNL1 via channel D and channel F. This allows PNL1 to display conventionally (the displayed image is not processed by the ASIC chip) or to enhance and optimize the display (the displayed image is enhanced and optimized by the ASIC chip).

[0208] Scenario 2 is a scenario where PNL1 is displayed independently, and image enhancement and optimized display can be achieved. The SoC controls the switching switch and the data flow is as follows: Figure 8 As shown, when SoC receives the instruction displayed by PNL1, if the instruction includes the request for image enhancement and optimized display, SoC executes the instruction, SoC turns on the ASIC chip, turns off channels G, B and H, and turns on channels A, C, D and F. DSI1 and DSI2 are connected to the ASIC chip, and the ASIC chip is connected to PNL1. The data flow is as follows: SoC810 sends the unprocessed image signals "VideoX" and "VideoX'" to ASIC chip 820 through channels C and A respectively, and ASIC chip 820 processes the image signals to obtain processed image signals, and ASIC chip 820 sends the processed image signals to PNL1 through channels D and F, thereby realizing the enhancement and optimized display of the image signals by PNL1.

[0209] Scenario 3 is a scenario where PNL2 is displayed independently and image enhancement and optimized display can be achieved. The SoC controls the switching switch and the data flow is as follows: Figure 8 As shown, when SoC receives the instruction of PNL2 display, if the instruction includes the request of image enhancement and optimized display, SoC executes the instruction, SoC turns on the ASIC chip, turns on channels A, C, D, G and H, and turns off channels F and B. DSI1 and DSI2 are connected to the ASIC chip, and the ASIC chip is connected to PNL2. The data flow is: SoC810 sends the unprocessed image signal to ASIC chip 820 through channels A and C, and ASIC chip 820 processes the image signal to obtain the processed image signal, and sends the processed image signal to PNL2 through channels D, G and H, so as to realize the enhancement and optimized display of image data by display screen PNL2.

[0210] In addition, in some embodiments, when there are more than two DSI interfaces, it is not necessary to set a switching switch. For details, please refer to Embodiment 5. Example

[0211] refer to Fig. 9 , Fig. 9 A schematic diagram of the structure of a dual-screen mobile phone with three DSI interfaces in another embodiment of the present application is shown. Fig. 9 As shown, the mobile phone includes a SoC 910, an ASIC chip 920, and two display screens (eg, PNL1 and PNL2).

[0212] like Fig. 9 As shown, the SoC includes a camera serial interface CSI and three display serial interfaces DSI1, DSI2 and DSI3. The ASIC chip 920 includes an input terminal 921, an input terminal 922, an output terminal 923 and an output terminal 924.

[0213] like Fig. 9 As shown, the CSI of the SoC is connected to the output terminal 923 of the ASIC chip 920 to form a transmission channel E. DSI1 is connected to the input terminal 921 of the ASIC chip to form a channel C, and DSI2 is connected to the input terminal 922 of the ASIC chip to form a channel A. The output terminal 924 of the ASIC chip is connected to PNL1 to form a transmission channel D. DSI3 is directly connected to the display screen PNL2 to form a transmission channel B.

[0214] The data flow between the channels is described below with reference to the accompanying drawings.

[0215] like Fig. 9As shown, channel E is used to return the image signal processed by the ASIC chip, such as "VideoY", to the SoC. Transmission channel C and transmission channel A are used to output signals from the SoC to the ASIC chip, for example, to output unprocessed image data "VideoX" and "VideoX'", which can be processed by the ASIC chip to obtain processed image signals, such as VideoY. The processed image data can be transmitted to PNL1 through transmission channel D. Or it can be transmitted back to the SoC through transmission channel E, and then transmitted to PNL2 by the SoC through transmission channel B.

[0216] Combine the following Fig. 9 Table 6 and SoC describe how to realize single-screen and dual-screen display of mobile phones by controlling the transmission status of each channel. Controlling the transmission status of each channel includes whether the transmission channel sends data or does not send data, where the channel that does not send data is considered to be off, and vice versa, the channel that sends data is on. The following scenarios may be included, refer to Table 6.

[0217] Table 6

[0218] Scenario plan Implementation Scenario 1 Dual screen display (1) ASIC chip / off, (2) A off; (3) B, C, D on Scenario 2 PNL1 + ASIC chip (1) ASIC chip on / off; (2) B off; (3) A, C, D on Scene 3 PNL2 + ASIC chip (1) ASIC chip on / off; (2) A, C, E, B on; (3) D off

[0219] refer to Fig. 9 Combined with Table 6, scene 1 is a dual-screen display scene, that is, PNL1 and PNL2 are displayed simultaneously. Fig. 9 As shown, the data flow in this scenario is: when the SoC receives the dual-screen display instruction, it executes the instruction, controls the closing of channel A, and opens channel B, channel C and channel D, so that DSI1 and DSI2 are directly connected to PNL1. If the dual-screen display instruction does not include a request for image signal optimization processing, the data flow for PNL1 is: the SoC transmits the unprocessed image signal to the closed state ASIC chip through at least one of DSI1 and DSI2, and then transmits it to PNL1 through the ASIC chip to realize the display of PNL1. The data flow for PNL2 is: the SoC outputs the unprocessed image signal through DSI3, and transmits it to PNL2 through channel B to realize the display of PNL2.

[0220] In the above process, if the dual-screen display instruction includes a request for optimizing the image signal processing for PNL1, the data flow for PNL1 is as follows: the SoC transmits the unprocessed image signal to the turned-on ASIC chip through at least one of DSI1 and DSI2, the ASIC chip processes the image signal, and transmits the processed image signal to PNL1 through transmission channel D, thereby realizing image enhancement and optimized display of PNL1.

[0221] Scene 2 is a scene where PNL1 is displayed alone and image enhancement and optimized display can be achieved, such as Fig. 9 As shown, in this scenario, the situation and data flow of SoC controlling the switch are as follows: when SoC receives the instruction displayed by PNL1, and the instruction includes a request for enhancement and optimization processing, SoC executes the instruction, turns on the ASIC chip, turns off channel B, turns on channels A, C and D, and realizes the connection between DSI1 and DSI2 and the ASIC chip, and the connection between the ASIC chip and PNL1. The data flow is as follows: SoC sends the image signal to be processed, such as "VideoX" and "VideoX'", to the ASIC chip, and the ASIC chip processes the image signal to obtain the processed image signal, and sends the processed image signal to PNL1 through channel D, thereby realizing the enhancement and optimization display of the image data by PNL1. In addition, if the instruction does not include a request for enhancement and optimization processing, SoC can transmit to the closed ASIC chip (without processing the image signal) through at least one of channels A and C, and then transmit the unprocessed image signal to PNL1 through channel D, so as to realize the normal display of PNL1.

[0222] Scene 3 is a scene where PNL2 is displayed alone and image enhancement and optimized display can be achieved, such as Fig. 9 As shown, in this scenario, the situation of SoC controlling the switching switch and the data flow are as follows: when SoC receives an instruction displayed by PNL2, and the instruction includes a request for enhancement and optimization processing, SoC executes the instruction, turns on the ASIC chip, turns off channel D, and turns on channel A, channel C, channel B, and channel E. PNL2 is connected to the ASIC chip through SoC. The data flow is that SoC sends the image signal to be processed, such as "VideoX" and "VideoX'", to ASIC chip 920, ASIC chip 920 processes the image signal to obtain a processed image signal, such as "videoY", and transmits videoY back to SoC through channel E, and then SoC sends the processed image signal videoY to PNL2, thereby achieving PNL2's enhancement and optimization display of the image data. In addition, if the instruction does not include a request for enhancement and optimization processing, SoC can transmit the unprocessed image signal to PNL2 through channel B to achieve PNL2's normal display. The following describes the multi-screen data processing method of an embodiment of the present application, which can be applied to the above Figure 2-Figure 8 In the structure of any one of the embodiments.

[0223] refer to Fig.10 , Fig.10 The flowchart of a multi-screen data processing method according to an embodiment of the present application is shown. Figure 1b The scene shown, such as Fig.10As shown, it includes S1010-S1060. The method is executed by a mobile phone. The specific structure can be referred to Figure 2-Figure 8 .

[0224] S1010, the SoC receives a request for image processing from the first display screen. The request for image processing may be an instruction issued by a user through an interface. For example, in a game interface, when a user opens the game interface on the first display screen, the touch sensor sends the user's opening operation event (request) to the SoC, and the SoC responds to the request and executes the following steps.

[0225] S1020, the SoC controls the switch so that the ASIC chip provides image data to the first display screen. The process of the SoC controlling the switch can refer to the above embodiment. Figure 2-Figure 8 The description of scene 2 in will not be repeated here.

[0226] S1030 , the SoC receives a request from display screen 2 for image processing.

[0227] S1040, the SoC controls the switch so that the ASIC chip no longer provides image data to the first display screen, but provides image data to display screen 2. The process of the SoC controlling the switch can refer to the above embodiment. Figure 2-Figure 8 The description of scene 3 in will not be repeated here.

[0228] It should be noted that there is no limitation on the order of requests S1010 and S1030. This application is only an exemplary description. In some embodiments, the second display screen may issue a request first, or a request for dual-screen display may be issued by other modules. This is not a limitation here.

[0229] S1050, the SoC receives a request for dual-screen display. The request may be sent by the user clicking the dual screen, or by a hardware button or software function key with a dual-screen display function on the mobile phone.

[0230] S1060, the SoC controls the switching switch so that the interface of the SoC is connected to the first display screen and the second display screen respectively, and the SoC provides data to the two display screens respectively. The process of the SoC controlling the switching switch can refer to the above embodiment. Figure 2-Figure 8 The description of scene 1 in FIG. 1 is not repeated here.

[0231] The method provides corresponding image signals processed by the ASIC chip or provides unprocessed image signals according to whether the display screen needs to enhance and optimize the image, so that one ASIC chip corresponds to multiple display screens and image processing can be automatically selected according to demand, thereby improving user experience.

[0232] It should be noted that in the above embodiments of the present application, two display screens are used as examples for explanation. In some embodiments, when the number of display screens is greater than 2, more display screens can be displayed by appropriately increasing the number of switching switches, and the present application does not limit the number of switching switches. According to the multi-screen data processing method of the embodiment of the present application, when an electronic device is provided with more than 2 display screens, one ASIC chip can correspond to multiple display screens without increasing the number of ASIC chips, so that multiple display screens of the electronic device can achieve enhanced and optimized visual effects, meet the user's low cost, and the demand for the effect of multi-screen enhanced display, and improve the user experience.

[0233] The components of the electronic device and the process of controlling the data flow of the embodiment of the present application are described in detail in the above embodiment. For details, please refer to the above embodiment. Fig.10 The multi-screen data processing method is not described in detail here.

[0234] The present application also provides an electronic device, including:

[0235] a memory for storing instructions to be executed by one or more processors of the device, and

[0236] A processor is used to execute the above embodiment in combination with Fig.10 The data processing method of multiple screens is explained.

[0237] The present application also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor executes the above-mentioned embodiment. Fig.10 The data processing method of multiple screens is explained.

[0238] The present application also provides a computer program product comprising instructions, which, when executed on an electronic device, enables a processor to execute the above-mentioned embodiments. Fig.10 The data processing method of multiple screens is explained.

[0239] Reference now Fig.11 , which is a block diagram of a SoC (System on Chip) 1300 according to an embodiment of the present application. Fig.11 In the FIG, similar components have the same reference numerals. In addition, the dashed boxes are optional features of more advanced SoCs. Fig.11In the embodiment, SoC 1300 includes: an interconnect unit 1350, which is coupled to an application processor 1310; a system agent unit 1380; a bus controller unit 1390; an integrated memory controller unit 1340; a group or one or more coprocessors 1320, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 1330; and a direct memory access (DMA) unit 1360. In one embodiment, the coprocessor 1320 includes a dedicated processor, such as, for example, a network or communication processor, a compression engine, a GPGPU, a high throughput MIC processor, or an embedded processor.

[0240] The static random access memory (SRAM) unit 1330 may include one or more computer-readable media for storing data and / or instructions. The computer-readable storage medium may store instructions, specifically, temporary and permanent copies of the instructions. The instructions may include: when executed by at least one unit in the processor, the Soc 1300 executes the shooting method according to the above embodiment, which may be specifically referred to in the above embodiment. Fig.10 The processing method explained will not be repeated here.

[0241] The various embodiments of the mechanism disclosed in the present application can be implemented in hardware, software, firmware or a combination of these implementation methods. The embodiments of the present application can be implemented as a computer program or program code executed on a programmable system, which includes at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device and at least one output device.

[0242] Program code can be applied to input instructions to perform each function described in the present application and generate output information. Output information can be applied to one or more output devices in a known manner. For the purpose of the present application, the processing system includes any system with a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC) or a microprocessor.

[0243] Program code can be implemented with high-level programming language or object-oriented programming language to communicate with the processing system. When necessary, program code can also be implemented with assembly language or machine language. In fact, the mechanism described in this application is not limited to the scope of any specific programming language. In either case, the language can be a compiled language or an interpreted language.

[0244] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed over a network or through other computer-readable media. Therefore, a machine-readable medium may include any mechanism for storing or transmitting information in a machine (e.g., computer) readable form, including but not limited to floppy disks, optical disks, optical disks, compact disc read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or tangible machine-readable memories for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in electrical, optical, acoustic, or other forms of propagation signals. Accordingly, machine-readable media include any type of machine-readable media suitable for storing or transmitting electronic instructions or information in a form readable by a machine (eg, a computer).

[0245] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the accompanying drawings of the specification. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0246] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation method of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0247] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0248] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. An electronic device, characterized in that: include: Control chip, display chip and multiple display screens; The control chip comprises a first display serial interface DSI, a second display serial interface DSI and a camera serial interface CSI, wherein the first display serial interface DSI and the second display serial interface DSI are respectively connected to the input end of the display chip, and are used to provide a first data signal to the display chip; The output end of the display chip is connected to a first display screen among the plurality of display screens; Another output terminal of the display chip is connected to the CSI, and is used to transmit the second data signal back to the control chip; The control chip is connected to a second display screen other than the first display screen; When the control chip receives an instruction displayed from the first display screen, the control chip executes the instruction, controls the second display serial interface DSI to be connected to the display chip, and controls the display chip to output the second data signal to the first display screen, wherein the instruction displayed by the first display screen includes image enhancement and optimization, and the second data signal includes image data obtained by processing the first data signal by the display chip; and, When the control chip receives an instruction from the second display screen, the control chip executes the instruction, controls the second display serial interface DSI to connect to the second display screen, and controls the display chip to transmit the second data signal back to the control chip through the CSI, and then sends the second data signal to the second display screen through the second display serial interface DSI, wherein the instruction displayed by the second display screen includes image enhancement and optimization.

2. The electronic device according to claim 1, characterized in that: When the control chip receives an instruction displayed from the first display screen, the control chip executes the instruction, controls the second display serial interface DSI to be connected to the display chip, and controls the display chip to output the first data signal to the first display screen, wherein the instruction displayed by the first display screen does not include image enhancement and optimization; and, When the control chip receives an instruction from the second display screen, the control chip executes the instruction, controls the second display serial interface DSI to connect to the second display screen, and outputs the first data signal to the second display screen. The instruction displayed by the second display screen does not include image enhancement and optimization.

3. The electronic device according to claim 1, characterized in that: Also includes: A first switch, comprising an input terminal connected to the second display serial interface DSI, and comprising a first output terminal connected to the display chip and a second output terminal connected to the second display screen; The control chip controls the first switch to switch between a signal transmission channel between the second display serial interface DSI and the display chip, and a signal transmission channel between the second display serial interface DSI and the second display screen.

4. An electronic device, characterized in that: include: Control chip, display chip and multiple display screens; The control chip includes a first display serial interface DSI, a second display serial interface DSI, a third display serial interface DSI and a camera serial interface CSI, wherein the first display serial interface DSI and the second display serial interface DSI are respectively connected to the input end of the display chip, and are used to provide a first data signal to the display chip; The output end of the display chip is connected to a first display screen among the plurality of display screens; Another output terminal of the display chip is connected to the CSI, and is used to transmit the second data signal back to the control chip; The third display serial interface DSI is connected to a second display screen other than the first display screen, and is used to output the first data signal or the second data signal to the second display screen; When the control chip receives an instruction from the first display screen, the control chip executes the instruction, outputs a first data signal to the display chip through the first display serial interface DSI and the second display serial interface DSI, and controls the display chip to output a second data signal to the first display screen, wherein the instruction for displaying the first display screen includes image enhancement and optimization, and the second data signal includes image data obtained by processing the first data signal by the display chip; and, When the control chip receives an instruction for display from the second display screen, the control chip executes the instruction, outputs a first data signal to the display chip through the first display serial interface DSI and the second display serial interface DSI, and controls the display chip to transmit the second data signal back to the control chip through the CSI, and then sends the second data signal to the second display screen through the third display serial interface DSI, wherein the instruction for display of the second display screen includes image enhancement and optimization, and the second data signal includes image data obtained by processing the first data signal by the display chip.

5. The electronic device according to claim 4, characterized in that: When the control chip receives an instruction displayed from the first display screen, the control chip executes the instruction and outputs the first data signal to the first display screen through the connection between the first display serial interface DSI and the second display serial interface DSI and the display chip, and the connection between the display chip and the first display screen, wherein the instruction displayed by the first display screen does not include image enhancement and optimization; and, When the control chip receives an instruction from the second display screen, the control chip executes the instruction and outputs the first data signal to the second display screen through the third display serial interface DSI, and the instruction displayed by the second display screen does not include image enhancement and optimization.

6. A multi-screen data processing method, characterized in that: Applied to an electronic device, the electronic device comprises: a control chip, a display chip and a plurality of display screens, the control chip further comprises a first camera serial interface CSI, the first camera serial interface CSI is connected to another output end of the display chip to form a first camera serial interface CSI transmission channel; the method comprises: When the control chip obtains a first request from a first display screen among the plurality of display screens, if the first request includes a request for image data processing; The control chip determines that there is at least one first transmission channel, and sends the first request and the first data signal to the display chip, wherein the first data signal is original image data that has not been processed; the display chip processes the first data signal based on the first request to obtain a second data signal, wherein the second data signal is used to represent image data obtained after the first data signal is processed by the display chip; The control chip controls the display chip to transmit a second data signal to the first display screen through a second transmission channel; When the control chip obtains a second request from a second display screen, the second display screen is a display screen other than the first display screen, and if the second request includes a request for image data processing; The control chip determines that there is at least one fourth transmission channel, and sends the second request and the third data signal to the display chip through the fourth transmission channel, wherein the third data signal is unprocessed image data; The display chip processes the third data signal based on the second request to obtain a fourth data signal, wherein the fourth data signal is used to represent image data obtained after the third data signal is processed by the display chip; The control chip controls the display chip to transmit the fourth data signal back to the control chip through the first camera serial interface CSI transmission channel, and the control chip outputs the fourth data signal to the second display screen through the third transmission channel.

7. The processing method according to claim 6, characterized in that: If the first request does not include a request for image data processing, The control chip determines to send the first request and the first data signal to the display chip through at least one of the first transmission channels; The control chip controls the display chip not to process the first data signal, and transmits the first data signal to the first display screen through the second transmission channel.

8. The processing method according to claim 6, characterized in that: The control chip includes a first display serial interface DSI, The control chip determines that there is at least one fourth transmission channel, including: The control chip controls the first display serial interface DSI to connect to the first input terminal of the display chip to establish a first display serial interface DSI transmission channel, and sends the second request and the third data signal to the display chip through the first display serial interface DSI transmission channel.

9. The processing method according to claim 8, characterized in that: The control chip also includes a second display serial interface DSI, The control chip outputs a fourth data signal to the second display screen through a third transmission channel, including: The control chip controls the second display serial interface DSI to connect with the second display screen to establish a second display serial interface DSI transmission channel; The control chip outputs the fourth data signal to the second display screen through the second display serial interface DSI transmission channel.

10. The processing method according to claim 7, characterized in that: The control chip includes a first display serial interface DSI and a second display serial interface DSI. The control chip determines that there is at least one fourth transmission channel, and further includes: The control chip controls the first display serial interface DSI to be connected to the first input end of the display chip to establish a first display serial interface DSI transmission channel, and the control chip controls the second display serial interface DSI to be connected to the second input end of the display chip to establish a second display serial interface DSI transmission channel, and sends the second request and the third data signal to the display chip through the first display serial interface DSI transmission channel and the second display serial interface DSI transmission channel.

11. The processing method according to claim 10, characterized in that: The control chip further includes a third display serial interface DSI, and the third display serial interface DSI is connected to the second display screen to form a third display serial interface DSI transmission channel. The control chip outputs a fourth data signal to the second display screen through a third transmission channel, including: The control chip outputs the fourth data signal to the second display screen through the third display serial interface DSI transmission channel.

12. The multi-screen data processing method according to claim 6, characterized in that: If the second request does not include a request for image data processing; The control chip transmits a third data signal to the second display screen through the third transmission channel, and the third transmission channel is a transmission channel formed by connecting the output end of the control chip and the second display screen.

13. An electronic device, characterized in that: include: Processors, display chips, multiple displays, and memory, The memory is used to store instructions executed by one or more processors of the device, and The processor is used to execute the instructions so that the electronic device executes the processing method described in any one of claims 6-12.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by an electronic device, the electronic device executes the processing method according to any one of claims 6 to 12.

15. A computer program product comprising instructions, characterized in that When the computer program product runs on an electronic device, the electronic device executes the processing method described in any one of claims 6 to 12.

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