SDC error detection method based on program heterogeneous relationship graph

Abstract

The present invention discloses a SDC error detection method based on a program heterogeneous relationship graph, comprising: secondary development of LLVM to obtain structural and non-structural information of the program; single-particle upset fault simulation at the register or memory level based on LLFI to mine the attributes of each program instruction and the SDC error rate; expanding instruction attributes and constructing a program heterogeneous relationship graph based on DGL; building a multi-relationship graph attention network HPRG to mine the spatial correlation between instructions, predict SDC vulnerable instructions, and explore the key relationships that affect the SDC error rate; designing a program fault tolerance mechanism, analyzing SDC vulnerable instructions and key relationships, identifying SDC key instructions, and performing targeted redundant reinforcement. The present invention uses a heterogeneous relationship graph to characterize the program, which can more accurately identify vulnerable instructions and key relationships, has a higher SDC error detection rate and lower time and space overhead, and can be flexibly applied to various programs.

Description

Technical Field

[0001] The present invention belongs to the technical field of SDC error detection and reinforcement, and in particular to an SDC error detection method based on a program heterogeneous relationship graph. Background Art

[0002] With the exponential growth in chip integration and complexity, system stability faces increasing challenges. In everyday life, computer system failures can be caused by electromagnetic or particle radiation, security attacks, hardware failures, and software errors. One of the most detrimental failures is erroneous output, known as silent data corruption (SDC). SDC has a complex propagation mechanism and can spread to various system components as programs run, ultimately leading to serious security incidents. Therefore, establishing an accurate and efficient SDC detection mechanism is crucial to ensuring system reliability and security.

[0003] Traditional SDC error detection methods based on redundancy incur significant performance overhead. Therefore, recent work has focused on identifying key instructions in programs prone to SDC errors and implementing targeted redundancy, thereby reducing overhead while ensuring detection rates. The most common approach is hardware fault injection, which simulates hardware faults to generate SDC errors, identifies vulnerable instructions through statistical analysis, and then implements redundancy. Schirmeier et al. proposed an intelligent framework for hardware fault injection (FAIL: An open and versatile fault-injection framework for the assessment of software-implemented hardware fault tolerance). To more effectively compress the fault space and improve the efficiency of hardware fault injection, it isolates hardware faults or identifies similar faults without fault simulation. Li et al. employed hardware fault result prediction technology (Smart Injector: Exploiting intelligent fault injection for SDC rate analysis) to reduce the time required for single hardware fault simulation. With the rise of artificial intelligence in recent years, machine learning-based SDC error detection techniques have emerged. By identifying vulnerable instructions, they maintain detection rates while reducing the overhead of hardware fault injection. Zheng et al. used classification and regression trees to predict SDC propensity (Vulnerability analysis of instructions for SDC-causing error detection); Ma et al.

[19] constructed an assembly-level heterogeneous graph of program instructions and used a graph attention network to predict instruction errors (GATPS: An attention-based graph neural network for predicting SDC-causing instructions).

[0004] While a significant amount of research has been conducted on SDC error detection, all efforts have limitations. Fault injection-based error detection methods face exponentially higher hardware fault injection costs as program size and the number of dynamic instructions increase. Artificial intelligence-based methods rarely explicitly consider program structure information, resulting in incomplete program representations and an inability to fully explore SDC damage mechanisms, making detection accuracy difficult to guarantee. Summary of the Invention

[0005] The present invention aims to address the aforementioned problems of the prior art by providing an SDC error detection method based on a program heterogeneous relational graph. This method achieves more complete program information mining, explicitly considers program structural information, and characterizes programs using a multi-relational heterogeneous graph. This method further explores the SDC error damage mechanism, thereby improving the accuracy of instruction vulnerability prediction, while maintaining detection rates and reducing time and space overhead. Furthermore, the present invention has good scalability and is suitable for detection and reinforcement of various programs.

[0006] The technical solution for achieving the purpose of the present invention is as follows: On the one hand, a SDC error detection method based on a program heterogeneous relationship graph is provided, the method comprising the following steps:

[0007] Step 1: Perform secondary development on the open source compiler LLVM to obtain the program's structural and non-structural information;

[0008] Step 2: Use the fault injection tool LLFI to simulate single-event upset faults at the register or memory level to mine the program's instruction attributes and SDC error rate.

[0009] Step 3: Mining instruction nodes and relationship edges from the program information obtained in steps 1 and 2, and then constructing the program heterogeneous relationship graph G based on the deep graph library DGL;

[0010] Step 4: Build a multi-relation graph attention network (HPRG) to predict SDC vulnerable instructions and mine the key relationships that affect the SDC error rate.

[0011] Step 5: Design a fault-tolerant mechanism to analyze the vulnerable SDC instructions and key relationships predicted in step 4, identify the key SDC instructions, perform targeted redundancy reinforcement, and implement SDC error detection.

[0012] Furthermore, the structural information of the program in step 1 includes program control flow, program data flow, instruction calls and data access; the non-structural information of the program includes instruction feature extraction, and the instruction features include instruction name, category, basic block, and function.

[0013] Furthermore, in step 2, single event upset fault simulation is performed based on LLFI, and the fault model FI constructed is expressed as:

[0014] FI=(I i ,W s ,W t ),i∈[1,N]

[0015] Where, I i represents the i-th program instruction, W s Indicates the source operand width of the program instruction, W tIndicates the destination operand width of the program instruction, and N indicates the total number of program instructions.

[0016] Furthermore, in step 3, instruction nodes and relationship edges are mined from the program information obtained from steps 1 and 2, and then a program heterogeneous relationship graph G is constructed based on the deep graph library DGL, which specifically includes:

[0017] Step 3-1: Based on the LLVM instruction set, extract the relationship between instructions from the program structure information and express it as a triple:

[0018] e ij =(I i ,r,I j ),i,j∈[1,N]

[0019] Where, e ij represents the relationship between instruction i and instruction j, and r represents the relationship between instructions;

[0020] Forming instruction relationship library E d ={e ij |i∈N,j∈N};

[0021] In step 3-2, based on the non-structural information of the program obtained in step 1 and the fault information obtained in step 2, the instruction feature set is extracted and represented as an 8-tuple:

[0022] F=(Bit,Pre,Suc,Nop,Type,BB,Fun,E_rate)

[0023] Where, Bit represents the instruction width, Pre represents the number of instruction predecessors, Suc represents the number of instruction successors, Type represents the instruction type, BB represents the basic block to which the instruction belongs, Fun represents the function to which the instruction belongs, and E_rate represents the instruction SDC error rate;

[0024] Encode and standardize each element in F to obtain the standard feature set f:

[0025]

[0026] Where L represents the total number of instruction features, Represents the i-th feature of instruction j, i∈[1,L],j∈[1,N];

[0027] Step 3-3, according to the instruction relationship library E d And the standard feature set f, based on DGL to build the program heterogeneous relationship graph G, specifically: the program instructions are the nodes of the program heterogeneous relationship graph G, the relationship between instructions is the edge of the program heterogeneous relationship graph G, the program heterogeneous relationship graph is expressed as G = (V, E), where V represents the instruction node set, E represents the relationship edge set.

[0028] Furthermore, the multi-relational graph attention network HPRG constructed in step 4 is specifically:

[0029] Step 4-1: The input is the heterogeneous relation graph G and the standard feature set f. Based on the multi-head graph attention mechanism, first, for the program instruction i∈[1,N], calculate its neighboring node j∈N (i) The attention weight of the k∈[1,K]th attention head under the relation r

[0030]

[0031] Among them, N (i) is the neighbor instruction of program instruction i, is the initialization node feature transformation matrix of the kth attention head under relation r, K is the total number of attention heads, f i is the characteristic of program instruction i, f j is the characteristic of program instruction j, is the weight parameter of the kth attention head under relation r, represented by MLP, LeakyReLU is the activation function, and T represents transpose;

[0032] Furthermore, the attention weight Normalize and get the weight coefficient

[0033]

[0034] Where, i∈[1,N],j∈[1,N],r∈[1,R], R is the total number of instruction relations, is the neighborhood node c∈N of program instruction i (i) The attention weight of the k∈[1,K]th attention head under the relation r;

[0035] Perform weighted summation on the weight coefficients to obtain the embedding of the kth attention head of program instruction i under relation r

[0036]

[0037] Where W (k) is the linear transformation weight matrix of the kth attention head;

[0038] Step 4-2, embedding of each attention head k under each relation r for program instruction i Perform aggregation to obtain the representation Q of program instruction i i :

[0039]

[0040] Get the SDC vulnerability y' of program instruction i through the classifier i :

[0041] y' i =W M (Relu(Q i ))+b M

[0042] Where W M is the weight parameter of the fully connected network, b M is the bias parameter;

[0043] For the program heterogeneous relation graph G, the loss function L of the multi-relation graph attention network is:

[0044]

[0045] Furthermore, the fault-tolerance mechanism described in step 5 is designed to analyze the vulnerable SDC instructions and key relationships predicted in step 4, identify key SDC instructions, perform targeted redundancy reinforcement, and implement SDC error detection. Specifically, the following steps are included:

[0046] Step 5-1, according to the instruction vulnerability Y obtained by the multi-relational graph attention network in step 4, i |i∈[1,N]}, sort the instructions in the target program in descending order, and get the descending table D T ; and according to the configurable redundancy granularity g∈(0,1), from D T Filter out the preliminary instruction set S;

[0047] Step 5-2: According to the multi-relation graph attention network in step 4, obtain the attention weights of each edge of each attention head under each relationship Sum and average the edge weights under each relationship to obtain the relationship with the maximum weight r max , expressed as:

[0048]

[0049] Where V r Represents the instruction set under relation r, Num r V r The total number of instructions;

[0050] For the instructions under the maximum weight relationship, the edge with a weight greater than the threshold TV is selected as the key edge, and the instructions at both ends of the key edge are used as key instructions to form the key instruction set E key , expressed as:

[0051]

[0052] Where, Represents the relationship r max Program instruction set under

[0053] Furthermore, for E key The final redundant instruction set RD is obtained by union with S, which is expressed as:

[0054] RD=E key ∪S

[0055] Step 5-3, redundantly reinforce the instructions in the redundant instruction set RD, and insert a comparison instruction cmp to compare the original instruction with the redundant instruction. If they are the same, it means that the program is running normally and the program continues to run; otherwise, jump to the error handling module and perform an exception interrupt.

[0056] Furthermore, in step 5-1, according to the configurable redundancy granularity g∈(0,1), T The preliminary instruction set S is initially screened out, specifically: from D T Select the first g*N program instructions to form a preliminary instruction set S.

[0057] On the other hand, a SDC error detection system based on a program heterogeneous relationship graph is provided, the system comprising:

[0058] The first module is used to perform secondary development of the open source compiler LLVM to obtain the program's structural and non-structural information;

[0059] The second module is used to simulate single-event upset faults at the register or memory level based on the fault injection tool LLFI, and to mine the program's instruction attributes and SDC error rate.

[0060] The third module is used to mine instruction nodes and relationship edges from the program information obtained from the first module and the second module, and then build a program heterogeneous relationship graph G based on the deep graph library DGL;

[0061] The fourth module is used to build a multi-relationship graph attention network (HPRG) to predict SDC vulnerable instructions and mine key relationships that affect SDC error rates.

[0062] The fifth module is used to design a fault-tolerant mechanism, analyze the predicted SDC vulnerable instructions and key relationships, identify SDC key instructions, perform targeted redundant reinforcement, and implement SDC error detection.

[0063] Compared with the existing technology, the present invention has the following significant advantages: 1) It explicitly considers program structure information, innovatively constructs a program heterogeneous relationship graph, and conducts a more comprehensive mining of program representation information; 2) It constructs a multi-relationship graph attention network to mine the spatial correlation between instructions, which can more accurately identify vulnerable instructions and key relationships, has a higher SDC error detection rate and lower time and space overhead, and can be flexibly applied to various programs; 3) It analyzes vulnerable instructions and key relationships, designs a program fault-tolerant mechanism, and performs granular configurable redundancy on the program, thereby achieving the purpose of effectively and accurately detecting SDC errors.

[0064] The present invention is further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 This is a flow chart of the SDC error detection method based on the program heterogeneous relationship graph of the present invention.

[0066] Figure 2 is a comparison diagram of algorithm errors in one embodiment, where Figure 2 (a) is the performance comparison of the present invention and four variants in terms of Precision. Figure 2 (b) in FIG1 is a performance comparison of the present invention and four variants on Recall.

[0067] Figure 3 is a graph comparing algorithm errors in one embodiment, where Figure 3 (a) is the performance comparison of the present invention and four variants on MAP, Figure 3 (b) is a performance comparison of the present invention and four variants on NDCG. DETAILED DESCRIPTION

[0068] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0069] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0070] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features specified as "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0071] In one embodiment, a method for detecting SDC errors based on a program heterogeneous relationship graph is provided, the method comprising the following steps:

[0072] Step 1: Perform secondary development on the open source compiler LLVM to obtain the program's structural and non-structural information;

[0073] Here, the structural information of the program includes program control flow, program data flow, instruction call and data access; the non-structural information of the program includes instruction feature extraction, and the instruction features include instruction name, category, basic block and function.

[0074] Step 2: Use the fault injection tool LLFI to simulate single-event upset faults at the register or memory level to mine the program's instruction attributes (opcode, instruction width) and SDC error rate.

[0075] Here, the constructed fault model FI is expressed as:

[0076] FI=(I i ,W s ,W t ),i∈[1,N]

[0077] Where, I i represents the i-th program instruction, W s Indicates the source operand width of the program instruction, W t Indicates the destination operand width of the program instruction, and N indicates the total number of program instructions.

[0078] Step 3: Mining instruction nodes and relationship edges from the program information obtained in steps 1 and 2, and then constructing the program heterogeneous relationship graph G based on the deep graph library DGL. This specifically includes:

[0079] Step 3-1: Based on the LLVM instruction set, extract the relationship between instructions from the program structure information and express it as a triple:

[0080] e ij =(Ii ,r,I j ),i,j∈[1,N]

[0081] Where, e ij represents the relationship between instruction i and instruction j, and r represents the relationship between instructions; preferably, there are four types of relationships, including control flow, data flow, call and access;

[0082] Forming instruction relationship library E d ={e ij |i∈N,j∈N};

[0083] In step 3-2, based on the non-structural information of the program obtained in step 1 and the fault information obtained in step 2, the instruction feature set is extracted and represented as an 8-tuple:

[0084] F=(Bit,Pre,Suc,Nop,Type,BB,Fun,E_rate)

[0085] Where, Bit represents the instruction width, Pre represents the number of instruction predecessors, Suc represents the number of instruction successors, Type represents the instruction type, BB represents the basic block to which the instruction belongs, Fun represents the function to which the instruction belongs, and E_rate represents the instruction SDC error rate;

[0086] Encode and standardize each element in f to obtain the standard feature set f:

[0087]

[0088] Where L represents the total number of instruction features, Represents the i-th feature of instruction j, i∈[1,L],j∈[1,N];

[0089] Step 3-3, according to the instruction relationship library E d And the standard feature set f, based on DGL to build the program heterogeneous relationship graph G, specifically: the program instructions are the nodes of the program heterogeneous relationship graph G, the relationship between instructions is the edge of the program heterogeneous relationship graph G, the program heterogeneous relationship graph is expressed as G = (V, E), where V represents the instruction node set, E represents the relationship edge set.

[0090] Step 4: Build a multi-relation graph attention network (HPRG) to predict SDC vulnerable instructions and mine the key relationships that affect the SDC error rate.

[0091] Here, the constructed multi-relational graph attention network HPRG is specifically as follows:

[0092] Step 4-1: The input is the heterogeneous relation graph G and the standard feature set f. Based on the multi-head graph attention mechanism, first, for the program instruction i∈[1,N], calculate its neighboring node j∈N(i) The attention weight of the k∈[1,K]th attention head under the relation r

[0093]

[0094] Among them, N (i) is the neighbor instruction of program instruction i, is the initialization node feature transformation matrix of the kth attention head under relation r, K is the total number of attention heads, f i is the characteristic of program instruction i, f j is the characteristic of program instruction j, is the weight parameter of the kth attention head under relation r, represented by MLP, LeakyReLU is the activation function, and T represents transpose;

[0095] Furthermore, the attention weight Normalize and get the weight coefficient

[0096]

[0097] Where, i∈[1,N],j∈[1,N],r∈[1,R], R is the total number of instruction relations, is the neighborhood node c∈N of program instruction i (i) The attention weight of the k∈[1,K]th attention head under the relation r;

[0098] Perform weighted summation on the weight coefficients to obtain the embedding of the kth attention head of program instruction i under relation r

[0099]

[0100] Where W (k) is the linear transformation weight matrix of the kth attention head;

[0101] Step 4-2, embedding of each attention head k under each relation r for program instruction i Perform aggregation to obtain the representation Q of program instruction i i :

[0102]

[0103] Get the SDC vulnerability y' of program instruction i through the classifier i :

[0104] y' i =W M (Relu(Q i ))+b M

[0105] Where W M is the weight parameter of the fully connected network, b M is the bias parameter;

[0106] For the program heterogeneous relation graph G, the loss function L of the multi-relation graph attention network is:

[0107]

[0108] Step 5: Design a fault-tolerant mechanism to analyze the vulnerable SDC instructions and key relationships predicted in step 4, identify key SDC instructions, and perform targeted redundancy reinforcement to implement SDC error detection. This includes:

[0109] Step 5-1, according to the instruction vulnerability Y obtained by the multi-relational graph attention network in step 4, i |i∈[1,N]}, sort the instructions in the target program in descending order, and get the descending table D T ; and according to the configurable redundancy granularity g∈(0,1), from D T Filter out the preliminary instruction set S;

[0110] Step 5-2: According to the multi-relation graph attention network in step 4, obtain the attention weights of each edge of each attention head under each relationship Sum and average the edge weights under each relationship to obtain the relationship with the maximum weight r max , expressed as:

[0111]

[0112] Where V r Represents the instruction set under relation r, Num r V r The total number of instructions;

[0113] For the instructions under the maximum weight relationship, the edge with a weight greater than the threshold TV is selected as the key edge, and the instructions at both ends of the key edge are used as key instructions to form the key instruction set E key , expressed as:

[0114]

[0115] Where, Represents the relationship r max Program instruction set under

[0116] Furthermore, for E key The final redundant instruction set RD is obtained by union with S, which is expressed as:

[0117] RD=E key ∪S

[0118] Step 5-3: Redundancy reinforcement is performed on the instructions in the redundant instruction set RD. A comparison instruction cmp is inserted to compare the original instruction with the redundant instruction. If they are identical, the program is running normally and execution continues. Otherwise, the program jumps to the error handling module and interrupts the program. Ultimately, a reinforced program with detection capabilities is obtained.

[0119] In one embodiment, a SDC error detection system based on a program heterogeneous relationship graph is provided, the system comprising:

[0120] The first module is used to perform secondary development of the open source compiler LLVM to obtain the program's structural and non-structural information;

[0121] The second module is used to simulate single-event upset faults at the register or memory level based on the fault injection tool LLFI, and to mine the program's instruction attributes and SDC error rate.

[0122] The third module is used to mine instruction nodes and relationship edges from the program information obtained from the first module and the second module, and then build a program heterogeneous relationship graph G based on the deep graph library DGL;

[0123] The fourth module is used to build a multi-relationship graph attention network (HPRG) to predict SDC vulnerable instructions and mine key relationships that affect SDC error rates.

[0124] The fifth module is used to design a fault-tolerant mechanism, analyze the predicted SDC vulnerable instructions and key relationships, identify SDC key instructions, perform targeted redundant reinforcement, and implement SDC error detection.

[0125] For the specific definition of the SDC error detection system based on the program heterogeneous relationship graph, please refer to the definition of the SDC error detection method based on the program heterogeneous relationship graph above, which will not be repeated here. The various modules in the above-mentioned SDC error detection system based on the program heterogeneous relationship graph can be implemented in whole or in part by software, hardware and their combination. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0126] As a specific example, the present invention is further verified and explained in one of the embodiments.

[0127] This embodiment uses the programs in the Mibench benchmark test set for experiments. The programs include quick sort (Qsort), shortest path algorithm (Dijkstra), integer square root solution (Isqrt), breadth-first search (BFS), radian to angle (Rad2deg) and data management system (Data). 70% of the instructions in the program are used as training sets, 10% of the instructions are used as validation sets, and the remaining instructions are used as test sets. The learning rate is set to 0.01, the hidden layer dimension of the multi-relational graph attention network is set to 3, the number of attention heads is set to 2, and the model is optimized using Adam and cross entropy loss, which is minimized by backpropagation. The prediction accuracy of the model is evaluated using accuracy, precision and F1-score. The performance of the method is evaluated using detection rate and time and space overhead.

[0128] This embodiment selects different currently popular SDC error detection methods as comparison methods to conduct comparative experiments: SDC error detection method based on support vector machine with radial basis function kernel (IPAS), SDC error prediction model based on improved SVM (PVInsiden), SDC error detection method based on improved LightGBM (SDIFI), instruction error prediction model based on assembly relationship graph (GATPS), high-frequency path instruction redundancy method (Hotpath), SDC error detection reinforcement method based on deep regression forest (DFRMR). The method of the present invention is denoted as RGED. The prediction results of different methods on the Mibench program are shown in Table 1 below, and the detection results of different methods on the Mibench program are shown in Table 2 below.

[0129] Table 1 Performance comparison of different methods on various programs (Accuracy, Precision, F1-score)

[0130]

[0131] Table 2 Detection results of different methods on Mibench program

[0132]

[0133] Table 1 shows that the method proposed in the present invention (RGED) performs better in predicting SDC vulnerabilities. As can be seen from the table: RGED's average accuracy is 0.845, 12.7% higher than PVInsiden; its average precision is 0.821, 10.2% higher than SDIFI; and its average F1-score is 0.843, 19.6% higher than SDIFI. Although GATPS achieved a higher accuracy on Dijkstra, its F1-score was the lowest, indicating that this method has a better fit for negative samples, which is meaningless and cannot predict instructions with high vulnerabilities. SDIFI achieved a higher F1-score on Qsort, but its accuracy and precision were lower than the method of the present invention. The present invention explicitly considers structural information and multiple relationships between instructions, and more fully characterizes the program, thereby better mining static and dynamic information, better fitting SDC errors, and improving the accuracy of model prediction.

[0134] Table 2 shows that the proposed method (RGED) also performs better in SDC error detection. As can be seen from the table, the average detection rates of Hotpath, DFRMR, SDIFI, and HPRG are 83.1%, 84.8%, 87.0%, and 87.4%, respectively, demonstrating that the proposed method exhibits superior performance. Hotpath, based on traditional program analysis methods, redundantly analyzes instructions on high-frequency execution paths and fails to consider SDC-vulnerable instructions outside these paths, resulting in the lowest detection capability. DFRMR and SDIFI, on the other hand, use artificial intelligence to identify SDC-vulnerable instructions within a program, enabling a more comprehensive exploration of key instructions within the program. The proposed method explicitly considers program structure information for the first time, constructing a heterogeneous graph of program multi-relationships. It also uses a graph attention mechanism to explore the spatial correlation of instructions, comprehensively considering key instructions and key relationships within the program. Consequently, it exhibits higher SDC error detection capabilities. For the Rad2deg and Qsort programs, the proposed method achieves comparable detection capabilities to SDIFI, likely because the vulnerable instructions within the key relationships are identical to those predicted by SDIFI.

[0135] In order to explore the impact of different relationships between instructions on SDC errors, an ablation experiment was conducted. In addition to the complete model considering the program heterogeneous relationship graph, four variants of the present invention were set: (1) HPRG_D means not considering the data flow relationship; (2) HPRG_C means not considering the control flow relationship; (3) HPRG_I means not considering the call relationship; (4) HPRG_A means not considering the access relationship. In addition, taking the Data program as an example, its edge attention weights were visualized to explore the key relationships that affect SDC errors. The final experimental results are shown in Figure 2. Figure 2 shown.

[0136] Depend on Figure 2 It can be seen that (1) the effect of HPRG_D is the most significantly reduced, which indicates that data flow has the greatest impact on SDC errors. This is because when an SDC error occurs, the result after the instruction operation is often propagated backward along the data flow, resulting in errors in the program operation results. At the same time, the impact of HPRG_A is also very large. This is because access instructions are highly related to memory or registers. When the error data is stored in registers or memory, or when an error occurs in memory or registers and is loaded into a certain instruction, it will more or less affect the subsequent operation of the program. Control flow and call relations are basic program flow relations. If any of them is missing, the structural information of the program is incomplete, which affects the error reasoning ability of the method and makes the prediction effect of the model worse. (2) The average weight coefficient of data flow is the largest, which indicates that data flow is the key relationship affecting SDC errors. This is similar to the results of the ablation experiment. Similarly, the access relationship is also the same. Since control flow is the basic program flow direction and contains some data relations, it has a certain impact on SDC errors. In addition, the edge weights in various relationships are quite different, which shows that the model of the present invention can learn the SDC error influencing factors of instructions under different relationships, thereby exploring the key relationships.

[0137] In order to verify the effectiveness of the present invention, it is necessary to consider not only the detection rate but also the performance overhead. Therefore, in the detection and reinforcement experiment, the size of the program after reinforcement by various methods was counted, so as to analyze the space overhead of each method and the program running time. The space overhead and running time of the source program are set to 1, and the space overhead and running time of the reinforcement program are defined as the ratio to the source program. The final experimental results are as follows: Figure 3 shown.

[0138] Depend on Figure 3 It can be seen that (1) the average space overhead of Hotpath, DFRMR, SDIFI and HPRG are 1.216, 1.192, 1.186 and 1.177 respectively, and the present invention has a lower space overhead. (2) The average time overhead of Hotpath, DFRMR, SDIFI and HPRG are 1.556, 1.532, 1.509 and 1.502 respectively, and the present invention has a lower time overhead. In summary, the present invention has a lower time and space overhead while ensuring the detection rate. This is because the SDC error detection method based on the program heterogeneous relationship graph can more fully explore the spatial correlation between instructions, explore the key relationships that affect SDC errors, more accurately identify SDC vulnerable instructions, analyze the key relationships, and reduce the number of redundant instructions and comparison instructions.

[0139] In summary, the SDC error detection method based on program heterogeneous relationship graph proposed in the present invention fully mines program information and represents it through program heterogeneous relationship graph, thereby improving the SDC error reasoning ability. At the same time, a multi-relationship graph attention network is constructed to learn more accurate instruction representations and explore the key relationships that affect SDC errors. Finally, a program fault tolerance mechanism based on instruction vulnerability and key relationships is used to achieve efficient SDC error detection and reinforcement. By comparing with other related algorithms, it is further verified that the present invention can more accurately predict instruction vulnerability and more efficiently detect and reinforce SDC errors.

[0140] The basic principles, main features, and advantages of the present invention are shown and described above. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely illustrative of the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention, and such changes and modifications fall within the scope of the invention as claimed.

Claims

1. A SDC error detection method based on program heterogeneous relationship graph, characterized in that: The method comprises the following steps: Step 1: Perform secondary development on the open source compiler LLVM to obtain the program's structural and non-structural information; Step 2: Use the fault injection tool LLFI to simulate single-event upset faults at the register or memory level to mine the program's instruction attributes and SDC error rate. Step 3: Mining instruction nodes and relationship edges from the program information obtained in steps 1 and 2, and then constructing the program heterogeneous relationship graph G based on the deep graph library DGL; Step 4: Build a multi-relation graph attention network (HPRG) to predict SDC vulnerable instructions and mine the key relationships that affect the SDC error rate. Step 5: Design a fault-tolerant mechanism to analyze the vulnerable SDC instructions and key relationships predicted in step 4, identify key SDC instructions, and perform targeted redundancy reinforcement to implement SDC error detection. In step 2, single event upset fault simulation is performed based on LLFI, and the fault model FI constructed is expressed as: FI=(I i ,W s ,W t ),i∈[1,N] Where, I i Represents program instruction i, W s Indicates the source operand width of the program instruction, W t Indicates the destination operand width of the program instruction, and N indicates the total number of program instructions; In step 3, we mine instruction nodes and relationship edges from the program information obtained in steps 1 and 2, and then build a program heterogeneous relationship graph G based on the deep graph library DGL. Specifically, we: Step 3-1: Based on the LLVM instruction set, extract the relationship between instructions from the program structure information and express it as a triple: e ij =(I i ,r,I j ),i,j∈[1,N] Where, e ij represents the relationship between program instruction i and program instruction j, and r represents the relationship between instructions; Forming instruction relationship library E d ={e ij |i∈[1,N],j∈[1,N]}; In step 3-2, based on the non-structural information of the program obtained in step 1 and the fault information obtained in step 2, the instruction feature set is extracted and represented as an 8-tuple: F=(Bit,Pre,Suc,Nop,Type,BB,Fun,E_rate) Where, Bit represents the instruction width, Pre represents the number of instruction predecessors, Suc represents the number of instruction successors, Type represents the instruction type, BB represents the basic block to which the instruction belongs, Fun represents the function to which the instruction belongs, and E_rate represents the instruction SDC error rate; Encode and standardize each element in F to obtain the standard feature set f: Where L represents the total number of instruction features, Represents the i'th feature of program instruction j, i'∈[1,L],j∈[1,N]; Step 3-3, according to the instruction relationship library E d And the standard feature set f, based on DGL to build the program heterogeneous relationship graph G, specifically: the program instructions are the nodes of the program heterogeneous relationship graph G, the relationship between instructions is the edge of the program heterogeneous relationship graph G, the program heterogeneous relationship graph is expressed as G = (V, E), where V represents the instruction node set, E represents the relationship edge set.

2. The SDC error detection method based on program heterogeneous relationship graph according to claim 1 is characterized in that: The structural information of the program in step 1 includes program control flow, program data flow, instruction calls and data access; the non-structural information of the program includes instruction feature extraction, and the instruction features include instruction name, category, basic block, and function.

3. The SDC error detection method based on program heterogeneous relationship graph according to claim 1 is characterized in that: The instruction attributes in step 2 include operation code and instruction width.

4. The SDC error detection method based on program heterogeneous relationship graph according to claim 1, characterized in that: The specific steps for building the multi-relationship graph attention network HPRG in step 4 are: Step 4-1: The input is the heterogeneous relation graph G and the standard feature set f. Based on the multi-head graph attention mechanism, first, for the program instruction i∈[1,N], calculate its neighboring node j∈N (i) The attention weight of the k∈[1,K]th attention head under the relation r Among them, N (i) is the neighbor instruction of program instruction i, is the initialization node feature transformation matrix of the kth attention head under relation r, K is the total number of attention heads, f i is the characteristic of program instruction i, f j is the characteristic of program instruction j, ω r(k) is the weight parameter of the kth attention head under relation r, represented by MLP, LeakyReLU is the activation function, and T represents transpose; Furthermore, the attention weight Normalize and get the weight coefficient Where, i∈[1,N],j∈[1,N],r∈[1,R], R is the total number of instruction relations, is the neighborhood node c∈N of program instruction i (i) The attention weight of the k∈[1,K]th attention head under the relation r; Perform weighted summation on the weight coefficients to obtain the embedding of the kth attention head of program instruction i under relation r Where w (k) is the linear transformation weight matrix of the kth attention head; Step 4-2, embedding of each attention head k under each relation r for program instruction i Perform aggregation to obtain the representation Q of program instruction i i : Get the SDC vulnerability y' of program instruction i through the classifier i : y′ i =In M (Relu(Q i ))+b M Where W M is the weight parameter of the fully connected network, b M is the bias parameter; For the program heterogeneous relation graph G, the loss function L of the multi-relation graph attention network is:

5. The SDC error detection method based on program heterogeneous relationship graph according to claim 4 is characterized in that: Step 5 describes the design of a fault-tolerance mechanism. This involves analyzing the vulnerable SDC instructions and key relationships predicted in step 4, identifying key SDC instructions, and implementing targeted redundancy reinforcement to implement SDC error detection. Specifically, this includes: Step 5-1, according to the instruction vulnerability Y obtained by the multi-relational graph attention network in step 4, i |i∈[1,N]}, sort the instructions in the target program in descending order, and get the descending table D T ; and according to the configurable redundancy granularity g∈(0,1), from D T Filter out the preliminary instruction set S; Step 5-2: According to the multi-relation graph attention network in step 4, obtain the attention weights of each edge of each attention head under each relationship Sum and average the edge weights under each relationship to obtain the relationship with the maximum weight r max , expressed as: Where V r Represents the instruction set under relation r, Num r V r The total number of instructions; For the instructions under the maximum weight relationship, the edge with a weight greater than the threshold TV is selected as the key edge, and the instructions at both ends of the key edge are used as key instructions to form the key instruction set E key , expressed as: Where, Represents the relationship r max Program instruction set under Furthermore, for E key The final redundant instruction set RD is obtained by union with S, which is expressed as: RD=E key ∪S Step 5-3, redundantly reinforce the instructions in the redundant instruction set RD, and insert a comparison instruction cmp to compare the original instruction with the redundant instruction. If they are the same, it means that the program is running normally and the program continues to run; otherwise, jump to the error handling module and perform an exception interrupt.

6. The SDC error detection method based on program heterogeneous relationship graph according to claim 5 is characterized in that: In step 5-1, according to the configurable redundancy granularity g∈(0,1), T The preliminary instruction set S is initially screened out, specifically: from D T Select the first g*N program instructions to form a preliminary instruction set S.

7. The SDC error detection system based on program heterogeneous relationship graph according to any one of claims 1 to 6, characterized in that: The system includes the following steps: The first module is used to perform secondary development of the open source compiler LLVM to obtain the program's structural and non-structural information; The second module is used to simulate single-event upset faults at the register or memory level based on the fault injection tool LLFI, and to mine the program's instruction attributes and SDC error rate. The third module is used to mine instruction nodes and relationship edges from the program information obtained from the first module and the second module, and then build a program heterogeneous relationship graph G based on the deep graph library DGL; The fourth module is used to build a multi-relationship graph attention network (HPRG) to predict SDC vulnerable instructions and mine key relationships that affect SDC error rates. The fifth module is used to design a fault-tolerant mechanism, analyze the predicted SDC vulnerable instructions and key relationships, identify SDC key instructions, perform targeted redundant reinforcement, and implement SDC error detection.

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