A method for constructing a radar emitter signal recognition model based on FPGA

Abstract

The application discloses a kind of based on FPGA's radar radiation source signal identification model construction method, comprising the following steps: S1, constructs data set;S2, designs original model;S3, model carries out sparse regularization training, and obtains the model of weight sparse;S4, pruning is carried out to model, according to the determination basis of preset filter importance, filter is sorted layer by layer, and sparse filter and corresponding channel are pruned;S5, fine-tuning training is carried out to model and is repeated iteration until model accuracy and compression ratio meet preset requirement;S6, parameter quantization is carried out to model, and optimization strategy of model parameter storage and reading is designed;S7, a kind of network layer module multiplexing architecture based on FPGA is designed and combined with acceleration strategy, and finally target model is obtained.The model obtained by the application has the characteristics of low structural complexity, less model parameters, high real-time identification and low power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of radar, in particular to a method for constructing a radar emitter signal recognition model based on FPGA. BACKGROUND

[0002] Radar emitter signal recognition is an important part of electronic reconnaissance and countermeasures. In traditional radar emitter recognition, the Pulse Description Word (PDW) feature parameter matching method is often used, or the signal is transformed in the time domain, frequency domain, and time-frequency domain, and then the intra-pulse features are manually extracted for classification and recognition. However, this method has the characteristics of low recognition rate under low signal-to-noise ratio, weak generalization ability, and poor robustness. In recent years, with the brilliant performance of deep learning in computer vision and natural language processing, various radar emitter recognition methods based on deep learning have been proposed and have made continuous breakthroughs. Based on deep learning, the end-to-end recognition can be completed without relying on manual feature extraction, and a very high recognition rate can be achieved. Its anti-interference ability and generalization ability are also stronger. Literature [1] uses the classic convolutional neural network (CNN) model AlexNet to classify and recognize the time-frequency diagram of the signal, converts the signal into a two-dimensional image for recognition, and obtains a high recognition accuracy. Literature [2] uses an improved one-dimensional convolutional long-short-term-memory deep neural network (1CLDNN) combined with a temporal convolutional neural network (TCN) model to classify the emitter signal, and the signal recognition accuracy is improved compared with the convolutional neural network model.

[0003] However, the feature extraction capability of the deep neural network model and its size are generally contradictory. In order to improve the recognition performance of the model, the network model usually adopts a more complex structure, which also leads to high computational complexity and time complexity of the model, causing difficulties for the limited computing and storage resources of edge computing devices, and also difficult to meet the real-time requirements in actual recognition scenarios. Therefore, few radar emitter recognition models are deployed in edge computing devices.

[0004] And the application number is 201811553980.2 of China invention discloses a kind of " based on VAE-ResNet network's radar radiation source identification method", its technical scheme is: to the aliasing signal received from receiver is separated, obtains radar radiation source signal, generates radar radiation source signal dataset, including 7 different radar radiation source signals, respectively as conventional pulse signal, linear frequency modulation signal, nonlinear body frequency modulation signal, two-phase encoding signal, four-phase encoding signal, two-frequency encoding signal and four-frequency encoding signal, then signal pre-processing is carried out, constructs VAE-ResNet network, and VAE-ResNet network is trained, obtains the VAE-ResNet network of well-trained to predict radar radiation source signal classification, i.e. output identification result. However, the feature extraction capability of deep neural network model and its size are generally contradictory, in order to improve the identification performance of model, network model usually adopts relatively complex structure, which also leads to high computational complexity and time complexity of model, which brings difficulties to the limited computing and storage resources of edge computing device, and it is also difficult to meet the real-time requirements in actual identification scene. Compared with the above, the light weight model for radar radiation source signal identification is designed, and the model is pruned, and the model parameters after pruning are statically quantized, which further reduces the model size and improves the real-time performance of radar radiation source identification. SUMMARY

[0005] The present application provides a method for constructing a radar radiation source signal identification model based on FPGA to solve the technical problems of high computational complexity and time complexity and low identification real-time performance in the prior art radar radiation source signal identification.

[0006] The present application provides a method for constructing a radar radiation source signal identification model based on FPGA, comprising the following steps:

[0007] S1, constructing a radar radiation source dataset;

[0008] S2, designing an original model based on deep separable convolution, denoted as 1D-LDS-CNN model;

[0009] S3, the model obtained in step S2 is trained using the radar radiation source dataset for sparse regularization, to obtain a 1D-LDS-CNN model with sparse weights;

[0010] S4, model pruning is performed on the model obtained in step S3, and the filters are sorted layer by layer according to the predetermined filter importance determination basis, and the sparse filters and the corresponding channels are pruned;

[0011] S5, fine-tuning training is performed on the model obtained in step S4 and iteration is repeated until the model precision and compression ratio both meet preset requirements;

[0012] S6, model parameter quantization is performed on the model obtained in step S5, and an optimization strategy for model parameter storage and reading is designed;

[0013] S7, a network layer module multiplexing architecture based on FPGA is constructed, and a preset acceleration strategy is combined to accelerate the inference process of the model obtained in step S6, and finally a target model is obtained.

[0014] Compared with the prior art, the method of the present application is designed for a lightweight model for radar emitter signal recognition, and the model is subjected to sparse training and pruning operation, and the model parameters after pruning are subjected to static quantization, which further reduces the model size, and finally a network layer module multiplexing architecture based on FPGA is constructed and combined with an acceleration strategy to improve the real-time performance of radar emitter recognition.

[0015] As a preferred scheme, in the step S1, the radar emitter data set includes CW signals, LFM signals, NLFM signals, BPSK signals, BFSK signals, QPSK signals, QFSK signals, P1 phase encoding signals, P2 phase encoding signals, P3 phase encoding signals and P4 phase encoding signals.

[0016] As a preferred scheme, in the step S2, the 1D-LDS-CNN model includes 1 ordinary convolution layer, 8 depth separable convolution layers, 1 global average pooling layer and 1 full connection layer connected in sequence; the ordinary convolution layer and the depth separable convolution layer both include a BN layer.

[0017] As a preferred scheme, in the step S3, the sparse regularization training specifically includes the following steps:

[0018] S31, in the 1D-LDS-CNN model, the BN layer includes a scaling coefficient , and the scaling coefficient indirectly reflects the importance of the corresponding filter; therefore, by applying L1 regularization to the scaling coefficient of the BN layer, the model becomes more sparse and a part of the values is distributed around 0, and the specific implementation is to increase a sparse penalty term for the scaling coefficient in the original defined loss function, so that the parameters in the filter are sparse, and the specific calculation formula is:

[0019] ​​ ;

[0020] wherein, is the classification network feedback loss, is the coefficient of the adjustment regularization penalty term, represents all channels of this training, is the L1 sparsity penalty of the scale factor;

[0021] S32, a sparsity measurement formula is designed to evaluate the sparsity of the filter, specifically:

[0022] ;

[0023] ;

[0024] ;

[0025] wherein, k is the convolution kernel weight, n, c, w, h are the dimension numbers of the 4-dimensional filter tensor, wherein n is the number of filters within the layer, c is the number of filter input channels; represents the sparsity value of the nth filter in the ith layer, the closer to 0, the more redundant the filter is compared with other filters within the layer; is the median of the L1 norm of all filter weights within the ith layer, and the median is selected as the step function of the threshold value of.

[0026] As a preferred scheme, in the step S4, the in step S3 is combined with as the basis for determining the importance of the filter, and the filter importance determination function within the layer is obtained, specifically:

[0027] ;

[0028] wherein, is the nth filter importance measurement value within the ith layer, is the BN layer scaling coefficient corresponding to the filter; represents the sparsity value of the nth filter in the ith layer.

[0029] As a preferred scheme, in the step S4, a prevention of over-pruning and pruning fault based on the prevention of pruning fault mechanism is constructed; the prevention of pruning fault mechanism is specifically:

[0030] All filters within the ith layer in the 1D-LDS-CNN model form a set , and the expected pruning number is ; first, according to the filter importance measurement value Sort all filters in the set , and determine the pruning threshold according to the set pruning number to obtain the set of filters to be pruned ; if , it indicates that the pruning threshold is equal to 0 at this time, that is , the importance measure values of all filters in the set are 0, at this time, the filter importance composite judgment mechanism is started, and all filters in the set are reordered according to the corresponding BN layer scaling coefficients , and the set of filters to be pruned is determined again ; if still appears, the filters with the same BN layer scaling coefficients in the set are randomly sorted, and the set of filters to be pruned is finally determined .

[0031] As a preferred scheme, in the step S6, the model parameter quantization is specifically:

[0032] The integer part and the decimal part of the quantization fixed-point number are set with bit widths according to the weight data and the feature data distribution range by using the static fixed-point quantization method, and the finally obtained quantization result is used to cover all model parameters and feature data generated in the inference process.

[0033] As a preferred scheme, in the step S6, the optimization strategy is specifically:

[0034] An optimization strategy of model parameter storage and reading is adopted, specifically, a method of splicing multiple channel data with one address is used to reasonably expand the convolution calculation in the input and output channels; according to the characteristics of the convolution calculation, the output channel parallelism of the previous layer convolution needs to be consistent with the parallelism of the input channel of the next layer, and the 18K BRAM space is configured as 512x36, then the relationship between the 18K BRAM resources consumed by the weight in each layer network and the parallelism of the input channel and the output channel is specifically:

[0035] ;

[0036] ;

[0037] ;

[0038] wherein, represents the data bit width of the weight data in each address in the BRAM, , represents the parallelism of the input channel and the output channel set in the convolution operation, represents the bit width of quantization, ​; Indicates the data depth of BRAM. , Here are the number of input and output channels for this layer of the network, and the size of the convolutional kernel is... Ultimately, it can be determined by and The value determines the number of 18K BRAM resources consumed by this layer of the network.

[0039] As a preferred embodiment, in step S7, the FPGA-based network layer module multiplexing architecture includes a convolution module, a normal / depth convolution module, a weight reading module, a bias reading module, an addition tree module, a ping-pong buffer module, a global pooling module, and a fully connected module.

[0040] The weight reading module is responsible for configuring weight parameters into the convolution calculation module, the ping-pong caching module is responsible for caching and reading intermediate feature data, and the addition tree module is responsible for adding the multi-channel convolution results of ordinary convolution and point convolution.

[0041] As a preferred embodiment, in step S7, the acceleration strategy includes a BN layer computation fusion strategy, an in-kernel pipeline strategy, and a channel parallelization and addition tree design strategy.

[0042] The BN layer computation fusion strategy specifically involves fusing the BN layer with the convolutional layer, and the output of the convolutional layer is as follows:

[0043]

[0044] in, The output value of a single convolutional layer. This is the average value across a single output channel. The variance over a single output channel. To prevent very small constant values ​​with a denominator of 0, This is the scaling factor. This is the offset factor; because the offset factor exists during the BN layer processing, the bias of the convolutional layer itself can be omitted, and the result after fusing the BN layer and the convolutional layer... and Specifically:

[0045] , ;

[0046] The channel parallel and addition tree strategy is specifically: built-in and external addition tree modules are arranged in the convolution module, the built-in addition tree is embedded in the convolution module and is responsible for adding all channel convolution calculation results in the convolution module, and the external addition tree is responsible for adding outputs of multiple convolution modules.

[0047] The channel parallel and addition tree strategy is specifically: built-in and external addition tree modules are arranged in the convolution module, the built-in addition tree is embedded in the convolution module and is responsible for adding all channel convolution calculation results in the convolution module, and the external addition tree is responsible for adding outputs of multiple convolution modules.

[0048] The beneficial effects of the present application are:

[0049] The present application designs a lightweight model for radar emitter signal recognition, and through sparse training and pruning operation on the model, the model parameters after pruning are statically quantized, the model size is further reduced, and high recognition accuracy is maintained; through the network layer module reuse architecture based on FPGA and combined with the acceleration strategy, the real-time of radar emitter recognition is further improved, and the low power consumption is also achieved. BRIEF DESCRIPTION OF DRAWINGS

[0050] Figure 1 A construction method flow chart of a radar emitter signal recognition model based on FPGA is provided for the embodiments of the present application.

[0051] Figure 2 A network layer module reuse architecture schematic diagram based on FPGA is provided for the embodiments of the present application.

[0052] Figure 3 A one-dimensional MAC array schematic diagram inside PE is provided for the embodiments of the present application.

[0053] Figure 4 Weight distribution diagrams before and after quantization are provided for the embodiments of the present application.

[0054] Figure 5 A simulation result diagram with input of single carrier signal (snr=-6dB) and output predicted label of 0 is provided for the embodiments of the present application.

[0055] Figure 6 A simulation result diagram with input of BFSK signal (snr=2dB) and output predicted label of 5 is provided for the embodiments of the present application.

[0056] Figure 7The simulation result diagram of inputting a polyphase code (P4 code) signal (SNR=10dB) provided by the embodiment of the present application and outputting a predicted label of 10;

[0057] Figure 8 The resource usage reporting diagram provided by the embodiment of the present application;

[0058] Figure 9 The power consumption reporting diagram provided by the embodiment of the present application. DETAILED DESCRIPTION

[0059] The accompanying drawings are only used for illustrative description and cannot be understood as a limitation to the present application;

[0060] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0061] The terms used in the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein means and includes any or all possible combinations of one or more associated listed items.

[0062] The following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims. In the description of the present application, it should be understood that the terms "first", "second", "third", etc. are only used to distinguish similar objects, and do not necessarily describe a specific order or sequence, nor can they be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0063] In addition, in the description of the present application, "multiple" means two or more, unless otherwise specified. The association between the associated objects is described as "and / or", which means that there can be three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone. The character " / " generally represents an "or" relationship between the associated objects before and after it. The present application is further described below in conjunction with the drawings and embodiments.

[0064] The application will be further described in conjunction with the accompanying drawings and examples.

[0065] Example 1

[0066] Please refer to Figures 1 to 3 A method for constructing a radar emitter signal recognition model based on an FPGA, comprising the following steps:

[0067] S1, constructing a radar emitter dataset;

[0068] In one specific embodiment, in the step S1, the radar emitter dataset comprises a CW signal, an LFM signal, an NLFM signal, a BPSK signal, a BFSK signal, a QPSK signal, a QFSK signal, a P1 phase encoding signal, a P2 phase encoding signal, a P3 phase encoding signal, and a P4 phase encoding signal.

[0069] It should be noted that the method of the application is based on the Matlab 2021b platform, simulates 11 common radar emitter signals of different modulation types, sets different signal parameters and signal-to-noise ratio conditions, and the main information of the dataset is shown in Table 1:

[0070] Table 1 Main parameters of the dataset

[0071]

[0072] S2, designing an original model based on deep separable convolution, denoted as a 1D-LDS-CNN model;

[0073] In one specific embodiment, in the step S2, the 1D-LDS-CNN model comprises, in sequence, 1 ordinary convolution layer, 8 deep separable convolution layers, 1 global average pooling layer, and 1 fully connected layer; the ordinary convolution layer and the deep separable convolution layer each comprises a BN layer.

[0074] It should be noted that the specific structure of the 1D-LDS-CNN model is shown in Table 2:

[0075] Table 2 Structure of 1D-LDS-CNN model

[0076]

[0077] S3, the model obtained in step S2 is trained by sparse regularization using the radar emitter dataset, to obtain a 1D-LDS-CNN model with sparse weights;

[0078] In one specific embodiment, in the step S3, the sparse regularization training specifically comprises the following steps:

[0079] S31, in the 1D-LDS-CNN model, the BN layer includes a scaling coefficient , due to the scaling coefficient of the BN layer , the scaling coefficient indirectly reflects the importance of the corresponding filter; therefore, by applying L1 regularization to the scaling coefficient of the BN layer , the parameters in the filter are sparsified, and the specific calculation formula is:

[0080]

[0081] , wherein, is the classification network feedback loss, is the coefficient for adjusting the regularization penalty term, represents all channels of this training, is the L1 sparsity penalty of the scale factor;

[0082] S32, a sparsity measurement formula is designed to evaluate the sparsity of the filter, specifically:

[0083]

[0084]

[0085]

[0086] , wherein k is the convolution kernel weight, n, c, w, and h are the dimension numbers of the 4-dimensional filter tensor, wherein n is the number of filters in the layer, and c is the number of filter input channels. , the closer to 0, the more redundant the filter is compared to other filters in the layer. is the median of the L1 norm of all filter weights in the i-th layer, and the median is selected as the threshold value of the step function .

[0087] Through the above improvements, the adverse effects of potential extreme parameters or uneven distribution in the filter sparsity measurement can be alleviated to some extent, thereby improving the sparsity measurement effect.

[0088] It should be noted that the operation process of the BN layer is specifically: ​​​​​​​

[0089]

[0090] S4, pruning the model obtained in step S3, according to the preset filter importance determination basis, sorting the filters layer by layer, and pruning the sparse filters and the corresponding channels;

[0091] In one specific embodiment, in the step S4, the filter importance determination method in step S3 is combined with the filter importance determination method in step S5, as the filter importance determination basis, to obtain a filter importance determination function in the layer, which is specifically:

[0092]

[0093] wherein, is the filter importance measurement value of the nth filter in the ith layer, is the BN layer scaling coefficient corresponding to the filter; represents the sparsity value of the nth filter in the ith layer.

[0094] It should be noted that if the filter weight values in a layer are generally sparse, the threshold value may be 0, thereby causing the filters in the layer to be over-pruned, and in severe cases, even causing the phenomenon of complete pruning of the filters in the layer. Therefore, on the basis of the above filter importance measurement method, a pruning fault prevention mechanism based on the filter importance measurement method is proposed.

[0095] In one specific embodiment, in the step S4, a pruning fault prevention mechanism based on the filter importance measurement method is constructed to prevent over-pruning and pruning faults; the pruning fault prevention mechanism based on the filter importance measurement method is specifically:

[0096] All filters in the ith layer in the 1D-LDS-CNN model form a set , and the expected pruning number is ; first, all filters in the set are sorted according to the filter importance measurement value , and the pruning threshold is determined according to the set pruning number to obtain the set of filters to be pruned ; if , it indicates that the pruning threshold is equal to 0 at this time, that is, all filter importance measurement values in the set are 0, at which time the filter importance composite determination mechanism is started, and all filters in the set are reordered according to the corresponding BN layer scaling coefficient , and the set of filters to be pruned is determined again ; if ​​​Inner BN layer scaling factor The same filter is randomly sorted, and the filter set to be pruned is finally determined .

[0097] It should be noted that in each pruning iteration, the filters are sorted layer by layer according to the determination basis of the filter importance The depth separable convolution layer composed of depth convolution and point convolution is regarded as a normal convolution layer during pruning, so pruning is only performed on the filters of the point convolution layer. For a model with an "N-2N-4N" channel combination, the filter combination pruned each iteration is "4-8-16", that is, the number of filters pruned each iteration for convolution layers with original output channels of N, 2N, and 4N is 4, 8, and 16, respectively. After each pruning, fine-tune training is performed to restore the accuracy of the pruned model.

[0098] S5, fine-tune training is performed on the model obtained in step S4, and iteration is repeated until the model accuracy and compression ratio meet the preset requirements;

[0099] S6, model parameter quantization is performed on the model obtained in step S5, and an optimization strategy for model parameter storage and reading is designed;

[0100] It should be noted that when quantizing parameters, both the accuracy of the operation and the speed of the operation should be ensured. From the quantization accuracy and quantization efficiency, the static fixed-point quantization method is appropriate. According to Table 3, the weight data is distributed between -9 and 8, and the feature data is distributed between -30 and 29.

[0101] Table 3 Weight data and feature data distribution range

[0102]

[0103] In one specific embodiment, the static fixed-point quantization method is used, the integer part and the decimal part of the quantization fixed-point number are set to have bit widths according to the weight data and feature data distribution range, and the final quantization result is used to cover all model parameters and feature data generated in the inference process.

[0104] Specifically, in order to balance the quantization range and accuracy, the integer part of the quantization fixed-point number is set to have a bit width of 5 bits, the decimal part is set to have a bit width of 10 bits, and an additional 1 bit sign bit is added. Finally, a 16-bit fixed-point quantization result can be obtained, and the 16-bit fixed-point number can cover all model parameters and feature data generated in the inference process.

[0105] In one specific embodiment, in the step S6, the optimization strategy is specifically:

[0106] An optimization strategy of model parameter storage and reading is adopted, specifically, a plurality of channel data is spliced by using an address to reasonably expand the convolution calculation in the input and output channels; according to the characteristics of the convolution calculation, the output channel parallelism of the previous layer convolution needs to be consistent with the parallelism of the input channel of the next layer, and the 18K BRAM space is configured in 512x36, then the relationship between the weight consumption of 18K BRAM resources and the parallelism of the input channel and the output channel in each network is specifically:

[0107] ;

[0108] ;

[0109] ;

[0110] wherein, represents the data bit width of the weight data at each address in the BRAM, 、 represents the parallelism of the input channel and the output channel of the convolution operation, represents the quantization bit width, ; represents the data depth of the BRAM, 、 is the input and output channel number of the current network, and the size of the convolution kernel is ; finally, the number of 18K BRAM resources consumed by the current network can be determined by the numerical size of and .

[0111] S7, constructing a network layer module multiplexing architecture based on FPGA and combining a preset acceleration strategy to accelerate the inference process of the model obtained in step S6, and finally obtaining a target model;

[0112] In one specific embodiment, in the step S7, the network layer module multiplexing architecture based on FPGA includes a convolution module, a general / depth convolution module, a weight reading module, a bias reading module, an addition tree module, a ping-pong cache module, a global pooling module, and a full connection module.

[0113] Among them, the weight reading module is responsible for configuring the weight parameters to the convolution calculation module, the ping-pong cache module is responsible for caching and reading the intermediate feature data, and the addition tree module is responsible for adding the multi-channel convolution results of the general convolution and the point convolution.

[0114] It should be noted that, as Figure 2As shown, the FPGA-based network layer module multiplexing architecture is composed of eight modules, including a point convolution module (Conv_pw), a normal / deep convolution module (Conv_dw), a weight reading module (Weight_loader), a bias reading module (Bias_loader), an addition tree module (Addition_tree), a ping-pong buffer module (Ping-pong Buffer), a global pooling module (Average Pool), and a full connection module (FC).

[0115] It should be noted that, for convolution calculation, since the normal convolution of the first layer uses a larger convolution kernel (1*9), which has high similarity with the deep convolution of the previous layers, the normal convolution and the deep convolution are combined into one module for implementation, which can save the use amount of DSP; the point convolution is implemented as a separate module. In the inference process of the model, the two modules alternately perform calculation in time, and finally all the forward inference calculations in the entire model can be completed.

[0116] It should be noted that the weight, bias reading module and ping-pong buffer module all use the optimization strategy, the ping-pong buffer module is composed of Ping RAM and Pong RAM units, Ping RAM and Pong RAM alternately write and read, that is, when Ping RAM is configured as a write state, Pong RAM is configured as a read state, and vice versa, this working mode masks the feature data transmission time and saves the non-computing time. The addition tree module internally uses a multi-tap multi-stage addition structure, which reduces the addition operation time through high water flow.

[0117] In one specific embodiment, in the step S7, the acceleration strategy includes a BN layer calculation fusion strategy, a convolution kernel internal pipeline strategy, and a channel parallelization and addition tree design strategy.

[0118] The BN layer calculation fusion strategy is specifically: the BN layer is fused with the convolution layer, and the output of the convolution layer is specifically:

[0119]

[0120] wherein, is the output value of a single convolution layer, is the average value on a single output channel, is the variance on a single output channel, is a very small constant value to prevent the denominator from being 0, is a scaling coefficient, is an offset factor; since there is an offset factor in the BN layer processing process, the bias in the convolution layer can be omitted, and the and Specifically,

[0121] , ;

[0122] The in-kernel pipelining strategy is specifically: if it is one-dimensional convolution, setting the convolution kernel size to 1*3, then three multiply-accumulate arrays MAC are needed to form a one-dimensional array in the internal calculation pipeline of a single convolution calculation unit PE; when the convolution calculation starts, the feature data enters the multiply-accumulate array in turn, and the output of the previous multiply-accumulate array will be used as the input of the next multiply-accumulate array; finally, a convolution calculation result can be obtained every clock cycle without repeated reading of weight and feature data.

[0123] The channel parallel and addition tree strategy is specifically: built-in and external addition tree modules are respectively arranged in the convolution module, the built-in addition tree is embedded in the convolution module and is responsible for adding all channel convolution calculation results in the convolution module, and the external addition tree is responsible for adding the outputs of multiple convolution modules.

[0124] It should be noted that BatchNorm (BN) is a basic processing in a network model, which can effectively solve the gradient disappearance and gradient explosion caused by a multi-layer network model, and improve the generalization ability of the network model. The 1D-LDS-CNN model contains BN operation processing in the convolution layer except the pooling layer and the fully connected layer, and the BN layer operation contains a large number of multiplication and division operations, which has a high demand for hardware resources. Therefore, the fusion processing of the BN layer and the convolution layer can reduce the model parameter quantity and reduce the hardware resource consumption.

[0125] It should be noted that pipelining calculation is one of the characteristics of FPGA, and pipelining calculation in the convolution kernel is a common convolution acceleration method. If it is one-dimensional convolution, setting the convolution kernel size to 1*3, then three MAC (Multiply-accumulate) are needed to form a one-dimensional array in the internal calculation pipeline of a single convolution calculation unit PE (Processing Unit). Figure 3

[0126] ​It should be noted that different channel parallel modes also have different characteristics in terms of resource usage. The input parallel mode has a low multiplexing rate for input feature map data, and more registers are needed to cache the input feature map data. In addition, the input parallel mode involves accumulating the processing results of multiple input channels, so more adders are also needed. The output parallel mode has a high multiplexing rate for input feature map data, but this mode needs to output the results of multiple channels at the same time, so more resources are needed to implement the operations such as bias addition and activation. In comparison, the input parallel mode is more LUT resource-saving, and the output parallel mode is more FF resource-saving.

[0127] Channel parallelization acceleration mainly focuses on two convolution modules and a fully connected module. For a single ordinary convolution / deep convolution module, the input parallel degree is equal to the output parallel degree. If the input channel parallel degree is set to N, the maximum total channel parallel degree that can be obtained at a certain deep convolution layer is also N. Therefore, as long as 1 such module is used, the depth convolution of each layer can achieve full input and output parallelism; for a single point convolution module, if the input channel parallel degree is set to N, using 64 such modules, the maximum total channel parallel degree that can be obtained at a certain point convolution layer is 64*N. The input and output channel parallel degrees of each layer are set as shown in Table 4:

[0128] Table 4 Channel parallel degree of each layer

[0129]

[0130] A large number of addition operations are needed after the convolution calculation of different input channels of ordinary convolution and point convolution. Using an addition tree can reduce the operation time. Since multiple point convolution modules are used in the design, the input and output channel parallel degrees of the point convolution modules of different network layers are different. In order to improve the utilization efficiency of computing resources, built-in addition trees and external addition tree modules are respectively set. The built-in addition tree is embedded in the convolution module and is responsible for adding all the channel convolution calculation results in the convolution module. The external addition tree is responsible for adding the outputs of multiple convolution modules. This design can flexibly adapt to the case where the channel parallel degree changes between different layers.

[0131] Embodiment 2

[0132] For reference Figures 4 to 9 The present embodiment verifies and analyzes the method, more specifically:

[0133] Verification and analysis of recognition accuracy of model 1D-LDS-CNN: On the radar emitter data set used in the application, the comparison of the parameter size and floating point operation amount of the 1D-LDS-CNN model proposed in the application and the 1D MobileNetv1 is shown in Table 5:

[0134] Table 5 Comparison of parameter size and operation amount of 1D-LDS-CNN and 1D MobileNetv1

[0135]

[0136] It can be seen that as a benchmark model, the size of 1D-LDS-CNN has been greatly reduced compared to 1D MobileNet, which is beneficial to improve the subsequent compression effect and reduce the compression time overhead.

[0137] The recognition accuracy and robustness of the 1D-LDS-CNN model on the simulation data set are verified, and the model recognition effect is experimentally verified. First, the 1D-LDS-CNN model is sparsely trained, and the training is set to use the Adam optimizer to optimize the network weight parameters, wherein the Batch Size is set to 256, the 1D-LDS-CNN model training period (epoch) is set to 100, the initial learning rate is set to 10-3, the weight decay is 10-4, the momentum is 0.9, the channel scaling factor is initialized to 0.5, and the L1 regularization weighting factor is set to 10-4. The experimental results are shown in Table 6:

[0138]

[0139] As can be seen from Table 6, the model can achieve an identification accuracy of more than 90% when the signal-to-noise ratio is greater than or equal to -6dB, and it shows good robustness to different signal-to-noise ratio signal samples.

[0140] Verification and analysis of the effect of the model compression method: The pruned 1D-LDS-CNN model after sparse training is used to carry out experiments using the pruning method proposed in the application, and the fine-tuning training period (epoch) is set to 20, and other settings are consistent with the sparse training. The experimental results are shown in Table 7:

[0141] Table 7 Experimental results of using layer-by-layer iterative pruning method on 1D-LDS-CNN model

[0142]

[0143] As can be seen from Table 7, the layered iterative pruning method proposed in the application can make the pruned model maintain good accuracy while greatly reducing the number of filters, and even slightly improve the accuracy, proving the effectiveness of the pruning method. After the 6th iteration pruning, the model pruning ratio is the largest under the condition that the model accuracy decreases by less than 0.5%, so the pruning model with the channel combination of "8-16-32" is selected as the final model for use, and the model structure is shown in Table 8:

[0144] Table 8 Model structure after pruning

[0145]

[0146] In order to illustrate the advantages of iterative pruning compared with static pruning, under the same experimental conditions, the 1D-LDS-CNN model is also subjected to static pruning and iterative pruning experiments, and the experimental results are shown in Table 9:

[0147] Table 9 Experimental results of static pruning and dynamic pruning

[0148]

[0149] The experimental results show that the accuracy of the pruning criterion proposed in this paper is better than that of other pruning criteria under the same pruning rate. The method proposed in this paper is more accurate in discriminating redundant filters, and higher accuracy and higher parameter compression rate are obtained.

[0150] The pruned model parameters are quantized to 16-bit fixed-point numbers using the static fixed-point quantization method described in Example 1, and the weight parameter frequency distribution before and after quantization is shown in Table 10. Figure 4 As can be seen, the weight frequency distribution before and after quantization is basically the same, and quantization does not have too much impact on accuracy, which can meet the accuracy requirements of the network.

[0151] The comparison of parameter storage space before and after quantization is shown in Table 10, which shows that the storage resources required for parameter storage are reduced by half, and the reduction of data bit width is beneficial to the improvement of data transmission bandwidth in the network operation process.

[0152] Table 10 Comparison of parameter storage space before and after quantization

[0153]

[0154] The comparison of model prediction accuracy before and after quantization is shown in Table 11, which shows that quantization only causes a 0.04% loss of accuracy, which can be ignored.

[0155] Table 11 Comparison of prediction accuracy

[0156]

[0157] Verification and analysis of FPGA acceleration effect: In order to verify the acceleration effect of the compressed 1D-LDS-CNN model, based on the Vivado 2018.3 development platform and the Xilinx ZCU111 development board, the acceleration design and actual test of the pruned model are completed. The post-synthesis simulation results are shown in Figures 5 to 7 .

[0158] According to Figures 5 to 7 , after using FPGA acceleration, only 3842 clock cycles are experienced from the first sampling time of the signal to the output time of the prediction result, and at a clock frequency of 100MHz, the prediction of a single sample only needs 38.42us.

[0159] The FPGA resource consumption of the module is shown in Figure 8 . It can be seen that the resource usage of the most used item (DSP) is only 13.01%, indicating that the design can adapt to other hardware platforms with more limited on-chip resources and has good portability.

[0160] The power consumption analysis of the module is shown in Figure 9 . The running power consumption is 1.794W, of which the dynamic power consumption is 0.703W and the static power consumption is 1.091W.

[0161] Using the test set described in the foregoing, the actual deployment test of the model is carried out on the Xilinx ZCU111 development kit. The on-board ARM (Cortex-A53) is compared with the FPGA acceleration performance, and the results are shown in Table 12:

[0162] Table 12 Comparison of results on different platforms

[0163]

[0164] The results show that the energy efficiency ratio of the network layer module reuse architecture based on FPGA of the application is much higher than that of the on-board ARM platform, about 124 times of the ARM platform, indicating the low power consumption and high speed characteristics of the design.

[0165] In summary, the network layer module reuse architecture based on FPGA provides good acceleration performance with lower resource consumption and power consumption, which not only meets the low power consumption requirement of the edge computing platform, but also basically meets the real-time requirement of radar emitter signal recognition.

[0166] Obviously, the above embodiments of the present application are merely exemplary but not intended to limit the embodiments of the present application. Based on the above description, any other variations or changes can be made by those skilled in the art without departing from the spirit and principles of the present application. It is not necessary to list all the embodiments here. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall fall within the scope of the claims of the present application.

Claims

1. A method for constructing a radar emitter signal recognition model based on FPGA, characterized in that, The method comprises the following steps: S1, constructing a radar emitter dataset; S2, designing a raw model based on a depth separable convolution, denoted as a 1D-LDS-CNN model; S3, performing sparse regularization training on the model obtained in step S2 using the radar emitter dataset to obtain a 1D-LDS-CNN model with sparse weights; S4, performing model pruning on the model obtained in step S3, sorting the filters layer by layer according to a preset filter importance determination basis, and pruning the sparse filters and the corresponding channels; S5, performing fine-tuning training on the model obtained in step S4 and repeating iterations until the model accuracy and compression ratio both meet preset requirements; S6, quantizing the model parameters of the model obtained in step S5, and designing an optimization strategy for model parameter storage and reading; S7, constructing a network layer module multiplexing architecture based on FPGA and combining a preset acceleration strategy to accelerate the inference process of the model obtained in step S6, and finally obtaining a target model; In the step S6, the model parameter quantization specifically comprises: using a static fixed-point quantization method, setting the integer part and the decimal part of the quantization fixed-point number according to the weight data and feature data distribution range, and finally obtaining a quantization result for covering all model parameters and feature data generated in the inference process; In the step S7, the acceleration strategy comprises a BN layer calculation fusion strategy, a convolution kernel internal pipeline strategy, and a channel parallelization and addition tree design strategy; The BN layer calculation fusion strategy specifically comprises: fusing the BN layer and the convolution layer, and the output of the convolution layer specifically comprises: wherein, is an output value of a single convolutional layer, is an average value on a single output channel, is a variance on a single output channel, is a very small constant value to prevent the denominator from being 0, is a scaling coefficient, is an offset factor; since there is an offset factor in the BN layer processing process, the bias in the convolutional layer itself can be omitted, and the and Specifically: ， ； The convolution kernel internal pipeline strategy specifically comprises: if it is one-dimensional convolution, setting the convolution kernel size to 1*3, then a one-dimensional array is formed by arranging three product accumulation arrays MAC inside a single convolution calculation unit PE internal calculation pipeline; when the convolution calculation starts, the feature data enters the product accumulation array in turn, and the output of the previous product accumulation array is used as the input of the next product accumulation array; finally, a convolution calculation result can be obtained every clock cycle without repeated reading of weight and feature data; The channel parallelization and addition tree strategy specifically comprises: setting an internal addition tree and an external addition tree module in the convolution module, the internal addition tree is embedded in the convolution module and is responsible for adding all channel convolution calculation results in the convolution module, and the external addition tree is responsible for adding the outputs of multiple convolution modules.

2. The method of claim 1, wherein the method is characterized by: In the step S1, the radar emitter dataset comprises a CW signal, an LFM signal, an NLFM signal, a BPSK signal, a BFSK signal, a QPSK signal, a QFSK signal, a P1 phase encoding signal, a P2 phase encoding signal, a P3 phase encoding signal, and a P4 phase encoding signal.

3. The method of claim 2, wherein the method further comprises: In the step S2, the 1D-LDS-CNN model comprises a normal convolution layer, eight depth separable convolution layers, a global average pooling layer, and a fully connected layer connected in sequence; the normal convolution layer and the depth separable convolution layer both comprise a BN layer.

4. The method of claim 3, wherein the method further comprises: In the step S3, the sparse regularization training specifically comprises the following steps: S31, in the 1D-LDS-CNN model, the BN layer includes scaling factors. Due to the scaling factor of the BN layer For each activation channel, the importance of that channel is indicated, and each activation channel corresponds to a filter in the previous layer; therefore, the scaling factor... This indirectly reflects the importance of the corresponding filter; therefore, by adjusting the scaling factor of the BN layer... Apply L1 regularization, so that To make the loss function sparser and distribute some values ​​near zero, a scaling factor is added to the original loss function. The sparsity penalty is applied to make the parameters in the filter sparsified. The specific calculation formula is as follows: ； wherein, is the classification network feedback loss, is the coefficient to adjust the regularization penalty term, represents all channels of this training, is the L1 sparsity penalty on the scale factor; S32, a sparsity measurement formula is designed to evaluate the sparsity of the filter, specifically: ； ； ； where k is the convolution kernel, i.e., filter weights, and n, c, w, h are the dimension numbers of the 4-dimensional filter tensor, where n is the number of filters within a layer, c is the number of filter input channels; denotes the sparsity value of the n-th filter in the i-th layer, The closer to 0, the more redundant the filter is compared with other filters within the layer. is the median of the L1-norm of all filter weights within the i-th layer, and the median is selected as the threshold value of the step function .

5. The method of claim 4, wherein the method further comprises: In the step S4, the step S3 is combined with and as a basis for determining the importance of the filter, to obtain an intra-layer filter importance determination function, which is specifically: ； wherein, is the importance measure value of the n-th filter in the i-th layer, is the BN layer scaling coefficient corresponding to the filter; denotes the sparsity value of the n-th filter in the i-th layer.

6. The method of claim 5, wherein the method further comprises: In the step S4, a mechanism for preventing pruning faults is constructed to prevent over-pruning and pruning faults; the mechanism for preventing pruning faults is specifically: In the 1D-LDS-CNN model, all filters within the i-th layer constitute a set. The expected number of pruning branches is First, based on the filter importance metric... For sets All filters within the set are sorted, and a pruning threshold is determined based on the set pruning quantity to obtain the set of filters to be pruned. ;like This indicates that the pruning threshold is equal to 0 at this time, that is... When all filter importance metrics are 0, the filter importance composite determination mechanism is activated, and the set is... All filters within the layer are scaled according to their corresponding BN layer scaling factor. Reorder and re-determine the set of filters to be pruned. If it still occurs Then for Inner BN scaling factor The same filters are randomly sorted to determine the final set of filters to be pruned. .

7. The method of claim 1, wherein the method further comprises: In the step S6, the optimization strategy is specifically: An optimization strategy for model parameter storage and reading is adopted, specifically, a method of splicing multiple channel data with an address is used to reasonably expand the convolution calculation in the input and output channels; according to the characteristics of the convolution calculation, the output channel parallelism of the previous layer needs to be consistent with the parallelism of the input channel of the next layer, and the 18K BRAM space is configured in 512*36, so the relationship between the 18K BRAM resources consumed by the weight in each network and the parallelism of the input channel and the output channel is specifically: ； ； ； wherein, represents the data bit-width of each address in BRAM, , represents the parallelism of the input and output channel settings of the convolution operation, represents the bit-width of quantization, ; represents the data depth of BRAM, , is the input and output channel number of the current layer network, and the size of the convolution kernel is ; finally, the 18K BRAM resource number consumed by the current layer network can be determined by the numerical size of and .

8. The method of claim 7, wherein the method further comprises: In the step S7, the network layer module multiplexing architecture based on FPGA includes a convolution module, a normal / depth convolution module, a weight reading module, a bias reading module, an addition tree module, a ping-pong cache module, a global pooling module and a full connection module; The weight reading module is responsible for configuring the weight parameters to the convolution calculation module, the ping-pong cache module is responsible for caching and reading the intermediate feature data, and the addition tree module is responsible for adding the multi-channel convolution results of the normal convolution and the point convolution.

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