Anti-fuse circuit and anti-fuse cell burn-in status verification method

Abstract

This disclosure provides an antifuse circuit, including: an antifuse unit; a programming circuit connected to the antifuse unit, the programming circuit being used to program the antifuse unit according to a programming control signal and a programming signal; a reading unit being used to read data signals from the antifuse unit; and a verification control unit being used to control the reading unit to electrically connect to the antifuse unit according to a verification enable signal and the programming signal of the antifuse unit when verifying the programming status of the antifuse unit. The antifuse circuit, by controlling the reading unit to electrically connect to the antifuse unit according to the verification enable signal and the programming signal of the antifuse unit when verifying the programming status of the antifuse unit, achieves real-time verification of the programming status.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to an antifuse circuit and a method for verifying the programming status of antifuse units. Background Technology

[0002] In the semiconductor industry, fuses are widely used in integrated circuits due to their versatility. For example, multiple circuit modules with the same function are designed as backups in an integrated circuit. When one circuit module fails, the fuse burns out the circuit module and other functional circuits in the integrated circuit, and another circuit module with the same function replaces the failed one.

[0003] With the continuous development of semiconductor technology, anti-fuse technology has attracted the attention of many inventors and manufacturers. Anti-fuse elements store information by changing from an insulating state to a conductive state. Writing information to the anti-fuse element is performed by applying high voltage, causing dielectric breakdown. Before programming, the anti-fuse memory cell exhibits capacitive characteristics, with no conductive channel formed; after programming breakdown occurs, a conductive channel is formed across the cell, allowing current to pass through. The magnitude of the conducting current is related to the programming effect.

[0004] However, existing antifuse circuits cannot achieve real-time verification of antifuse units, thus failing to meet the requirements. Summary of the Invention

[0005] The technical problem to be solved by the embodiments of this disclosure is to provide an antifuse circuit and an antifuse programming status verification method, which can verify the programming status of the antifuse unit in real time.

[0006] To address the aforementioned problems, this disclosure provides an antifuse circuit comprising: an antifuse unit; a programming circuit connected to the antifuse unit, the programming circuit being configured to program the antifuse unit according to a programming control signal and a programming signal; a reading unit being configured to read data signals from the antifuse unit; and a verification control unit being configured to, when verifying the programming status of the antifuse unit, control the reading unit to be electrically connected to the antifuse unit according to a verification enable signal and the programming signal.

[0007] In one embodiment, the verification control unit includes: a first transistor, the first terminal of which is connected to the antifuse unit, and the second terminal of which is connected to the input terminal of the read unit; a signal receiving unit, including a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the signal receiving unit receives the programming signal, the second input terminal of the signal receiving unit receives the verification enable signal, and the output terminal of the signal receiving unit is electrically connected to the control terminal of the first transistor. When verifying the programming state of the antifuse unit, if the programming signal indicates that the antifuse unit is not burned through, the signal receiving unit controls the first transistor to turn on.

[0008] In one embodiment, the first transistor is an NMOS transistor.

[0009] In one embodiment, the signal receiving unit includes: a NAND gate, the output of which serves as the output of the signal receiving unit; and a first inverter, the first input of the signal receiving unit being electrically connected to one input of the NAND gate via the first inverter, and the other input of the NAND gate being electrically connected to a second input of the signal receiving unit.

[0010] In one embodiment, the first transistor is a PMOS transistor.

[0011] In one embodiment, the signal receiving unit includes a NAND gate, the two input terminals of which are electrically connected to a first output terminal and a second input terminal, respectively, and the output terminal of the NAND gate serves as the output terminal of the signal receiving unit.

[0012] In one embodiment, the antifuse unit includes a first end and a second end, the first end of the antifuse unit is grounded, and the second end of the antifuse unit is electrically connected to the input end of the reading unit.

[0013] In one embodiment, the reading unit includes: a pre-charging unit for pre-charging the input terminal of the reading unit according to a pre-charging control signal; and a latch, the input terminal of which is electrically connected to the input terminal of the reading unit, and the output terminal of which is electrically connected to the output terminal of the reading unit.

[0014] In one embodiment, the pre-charge unit includes a second transistor, the first terminal of which is connected to a power supply voltage, the second terminal of which is connected to the input terminal of the readout unit, and the gate of which receives the pre-charge control signal.

[0015] In one embodiment, the antifuse circuit further includes a read switch unit, which is used to control the input terminal of the read unit to be electrically connected to the second terminal of the antifuse unit according to the read enable signal.

[0016] In one embodiment, the read switch unit includes a third transistor, the first terminal of which is connected to the second terminal of the antifuse unit, the second terminal of which is connected to the input terminal of the read unit, and the gate of which receives the read enable signal.

[0017] In one embodiment, the read unit further includes a second inverter disposed between the latch and the output of the read unit.

[0018] This disclosure also provides a method for verifying the programming status of an antifuse unit, using the aforementioned antifuse circuit. The method includes: inputting a programming signal; programming the antifuse unit according to the programming signal; controlling a reading unit to electrically connect to the antifuse unit according to the programming signal and a verification enable signal; the reading unit reading the antifuse unit to obtain a data signal; and verifying whether the antifuse unit is programmed correctly according to the data signal and the programming signal.

[0019] In one embodiment, the step of verifying whether the antifuse unit is correctly programmed based on the data signal and the programming signal further includes: comparing the data signal and the programming signal, and determining whether the antifuse unit is correctly programmed based on the comparison result of the data signal and the programming signal.

[0020] In one embodiment, the step of determining whether the antifuse unit is correctly programmed based on the comparison result of the data signal and the programming signal further includes: if the data signal and the programming signal are consistent, the antifuse unit is programmed correctly; if the data signal and the programming signal are inconsistent, the antifuse unit is incorrectly programmed.

[0021] In one embodiment, the step of programming the antifuse unit according to the programming signal further includes: the programming signal indicating that the antifuse unit is not burned through.

[0022] The antifuse programming status verification method provided in this embodiment can verify the programming status of the antifuse unit in real time using the programming signal and the data signal read from the antifuse unit. It does not require verification of the programming status of the antifuse unit through a test machine, and can quickly verify whether the antifuse unit has been mistakenly burned through, saving time and with high verification accuracy. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the antifuse circuit provided in the first embodiment of this disclosure;

[0024] Figure 2 This is a signal timing diagram of the antifuse circuit provided in the first embodiment of this disclosure;

[0025] Figure 3 This is a circuit diagram of the antifuse circuit provided in the second embodiment of this disclosure;

[0026] Figure 4 This is a schematic diagram of the steps of the antifuse unit programming status verification method provided in the third embodiment of this disclosure;

[0027] Figure 5 It is a truth table for signals. Detailed Implementation

[0028] The embodiments of the antifuse circuit and antifuse programming status verification method provided in this disclosure are described in detail below with reference to the accompanying drawings.

[0029] Figure 1 This is a schematic diagram of the antifuse circuit provided in the first embodiment of this disclosure. Please refer to [link / reference]. Figure 1 The antifuse circuit includes an antifuse unit 10, a programming circuit 20, a reading unit 30, and a verification control unit 40. The programming circuit 20 is connected to the antifuse unit 10 and is used to program the antifuse unit 10 according to the programming control signal BlowEn. The reading unit 30 reads the data signal from the antifuse unit 10. The verification control unit 40 is used to control the reading unit 30 to be electrically connected to the antifuse unit 10 according to the verification enable signal VerifyEn and the programming signal Data of the antifuse unit 10 when verifying the programming status of the antifuse unit 10.

[0030] In this embodiment, the antifuse unit 10 includes a first terminal 10A and a second terminal 10B. The first terminal 10A is grounded (GND), and the second terminal 10B can be electrically connected to the input terminal of the read unit 30 and the write unit 20. A high voltage is applied between the first terminal 10A and the second terminal 10B of the antifuse unit 10. This high voltage can break down the dielectric of the antifuse unit 10, causing it to change from an insulating state to a conductive state, thus storing information. After performing a write operation on the antifuse unit 10, if the antifuse unit 10 is in a conductive state, it indicates that the antifuse unit 10 has been burned through; if the antifuse unit 10 is in an insulating state, it indicates that the antifuse unit 10 has not been burned through. In this embodiment, the write signal Data is used to characterize whether the antifuse unit has been burned through.

[0031] In this embodiment, the programming circuit 20 is connected to the antifuse unit 10 and is used to program the antifuse unit 10 according to the programming control signal BlowEn and the programming signal Data. That is, the programming control signal BlowEn serves as the enable signal for the programming circuit 20. When programming the antifuse unit 10 is required, the programming control signal BlowEn enables the programming circuit 20, and the programming signal Data performs the programming operation on the antifuse unit 10.

[0032] As an example, this embodiment also provides a structure for a programming circuit 20. The programming circuit 20 includes a programming control unit 21 and a signal conversion unit 22.

[0033] The programming control unit 21 uses the programming control signal BlowEn as an enable signal to transmit the programming signal Data to the signal conversion unit 22. For example, in this embodiment, the programming control unit includes a first NMOS transistor MN1. The control terminal of the first NMOS transistor MN1 is connected to the programming control signal BlowEn. One end of the first NMOS transistor MN1 is connected to the programming signal Data, and the other end is connected to the signal conversion unit 22. When programming is required, the programming control signal BlowEn is set to 1, so that the first NMOS transistor MN1 is turned on, and the programming signal Data is transmitted to the signal conversion unit 22. In this embodiment, 1 represents a logic high level, and 0 represents a logic low level.

[0034] The signal conversion unit 22 is connected at one end to the programming voltage VPP and at the other end to the antifuse unit 10, and uses the programming signal Data as the control signal to program the antifuse unit 10. For example, in this embodiment, the signal conversion unit 22 includes a first PMOS transistor MP1 and a second PNOS transistor MP2. One end of the first PMOS transistor MP1 is connected to the programming voltage VPP and the other end is connected to the antifuse unit 10. The control terminal of the first PMOS transistor MP1 receives the programming signal Data. One end of the second PNOS transistor MP2 is connected to the programming voltage VPP and the other end is connected to the control terminal of the first PMOS transistor MP1. The control terminal of the second PNOS transistor MP2 receives a bias signal, wherein the voltage Vbias of the bias signal is less than the programming voltage VPP.

[0035] When the antifuse unit 10 needs to be programmed, the programming signal Data is set to 0, the programming control signal BlowEn is set to 1, the first NMOS transistor MN1 is turned on, and the programming signal Data controls the first PMOS transistor MP1 to turn on. The voltage difference across the antifuse unit 10 is the voltage difference between the programming voltage VPP and the ground terminal GND, thereby achieving breakdown programming of the antifuse unit 10. If the programming signal Data is set to 1, the first PMOS transistor MP1 is not turned on, and the antifuse unit 10 is not broken down.

[0036] In this embodiment, the programming circuit 20 further includes an amplification unit 23, and the programming signal Data output by the programming control unit 21 is transmitted to the signal conversion unit 22 after passing through the amplification unit 23.

[0037] In the above example, the first terminal 10A of the antifuse unit 10 is grounded to GND, and the second terminal 10B is electrically connected to the input terminal IN of the read unit 30 and the programming circuit 20. It can be understood that in other examples, the first terminal of the antifuse unit 10 is connected to the programming voltage, the second terminal is connected to the input terminal of the read unit and the programming circuit, and the programming circuit is connected to the ground terminal GND.

[0038] Please continue reading. Figure 1 The input terminal IN of the reading unit 30 is connected to the second terminal 10B of the antifuse unit 10. The reading unit 30 reads the antifuse unit 10 to obtain a data signal, and its output terminal OUT outputs a signal. The input signal EFDAT of the input terminal IN of the reading unit 30 is affected by the antifuse unit 10. The reading unit 30 reads the antifuse unit 10 to obtain a data signal and outputs the data signal as the output signal EFOUT to the output terminal OUT. In this embodiment, if the antifuse unit 10 is burned through, it conducts, and the data signal read from the antifuse unit 10 is the ground terminal GND signal, which is 0. The input signal EFDAT of the input terminal IN of the reading unit 30 is pulled low. If the antifuse unit 10 is not burned through, it does not conduct, and the data signal of the antifuse unit 10 is not the ground terminal GND signal, which is 1. The input signal EFDAT of the input terminal IN of the reading unit 30 remains 1.

[0039] As an example, this embodiment provides a circuit structure for a read unit 30. The read unit 30 includes a pre-charge unit 31 and a latch 32.

[0040] The pre-charging unit 31 is used to pre-charge the input terminal of the reading unit 30 according to the pre-charging control signal pre, that is, to charge the latch 32.

[0041] In some embodiments, the pre-charge unit 31 includes a second transistor. The first terminal of the second transistor is connected to the power supply voltage VDD, the second terminal of the second transistor is connected to the input terminal IN of the read unit 30, and the gate of the second transistor receives the pre-charge control signal pre. Specifically, please refer to... Figure 1 In this embodiment, the second transistor is a third PMOS transistor MP3. The first terminal of the third PMOS transistor MP3 is connected to the power supply voltage VDD, and the second terminal of the third PMOS transistor MP3 is connected to the input terminal IN of the read unit 30. The gate of the third PMOS transistor MP3 receives a precharge control signal pre. When the precharge control signal pre is set to 0, the third PMOS transistor MP3 is turned on, the input terminal IN of the read unit 30 is connected to the power supply voltage VDD, the precharge unit 31 charges the input terminal IN of the read unit 30, pulls up the voltage of the input terminal IN of the read unit 30, and makes the input signal EFDAT of the input terminal IN of the read unit 30 1.

[0042] The input terminal of the latch 32 is electrically connected to the input terminal IN of the read unit 30, and the output terminal is electrically connected to the output terminal OUT of the read unit 30. The latch 32 can latch the input signal EFDAT at the input terminal IN of the read unit 30. In this embodiment, the latch includes a third inverter P3 and a fourth inverter P4, which are connected end to end. The input terminal of the third inverter P3 is electrically connected to the input terminal IN of the read unit 30, and the output terminal of the third inverter P3 is electrically connected to the output terminal OUT of the read unit 30. The input terminal of the fourth inverter P4 is electrically connected to the output terminal of the third inverter P3, and the output terminal of the fourth inverter P4 is electrically connected to the input terminal of the third inverter P3, thus realizing the function of the latch.

[0043] In this embodiment, the antifuse circuit further includes a read switch unit S1, which controls the electrical connection between the read unit 30 and the antifuse unit 10 according to the read enable signal discharge. In some embodiments, the read switch unit S1 includes a third transistor, the first terminal of which is connected to the second terminal of the antifuse unit 10, the second terminal of which is connected to the input terminal IN of the read unit 30, and the gate of which receives the read enable signal discharge. Specifically, please refer to... Figure 1In this embodiment, the third transistor is the second NMOS transistor MN2. When the read enable signal discharge is set to 1, the second NMOS transistor MN2 is turned on, and the read unit 30 is electrically connected to the antifuse unit 10. The read unit 30 can then read the data signal from the antifuse unit 10. It is understood that when the programming circuit 20 programs the antifuse unit 10, the read enable signal discharge is set to 0, the read switch unit S1 is disconnected, and the read unit 30 is not connected to the antifuse unit 10.

[0044] In this embodiment, the reading unit 30 further includes a second inverter P2, which is disposed between the latch 32 and the output terminal OUT of the reading unit 30 to shape the signal output by the latch 32.

[0045] In this embodiment, when reading and writing amplification of the antifuse unit 10, the read enable signal discharge is first set to 0, the read switch unit S1 is turned off, and the pre-charge unit 31 charges the input terminal IN of the read unit 30, making the input terminal IN of the read unit 30 set to 1; the read enable signal discharge is then set to 1, the read switch unit S1 is turned on, and the input terminal IN of the read unit is connected to the second terminal 10B of the antifuse unit 10. If the antifuse unit 10 is burned through, the input terminal of the read unit 30 becomes 0, and the output terminal OUT outputs 0. If the antifuse unit 10 is not burned through, the input terminal of the read unit 30 remains 1, and the output terminal OUT outputs 1.

[0046] The verification control unit 40 is used to control the reading unit 30 to be electrically connected to the antifuse unit 10 according to the verification enable signal VerifyEn and the antifuse unit 10's writing signal Data when verifying the writing status of the antifuse unit 10.

[0047] In this embodiment, the verification control unit 40 includes a first transistor and a signal receiving unit 42. The first terminal of the first transistor is electrically connected to the antifuse unit 10, and the second terminal is electrically connected to the input terminal IN of the read unit 30. When verifying the burning status of the antifuse unit, if the burning signal indicates that the antifuse unit 10 has not been burned through, the signal receiving unit 42 controls the first transistor to turn on. In some embodiments, the first transistor is an NMOS transistor. Specifically, in this embodiment, the first transistor is a third NMOS transistor MN3. The output signal of the signal receiving unit 42 serves as the control signal for the third NMOS transistor MN3. The first terminal of the third NMOS transistor MN3 is electrically connected to the antifuse unit 10, and the second terminal of the third NMOS transistor MN3 is electrically connected to the input terminal IN of the read unit 30, for example, through the read switch unit S1 which is electrically connected to the input terminal IN of the read unit 30. When verifying the burning status of the antifuse unit, if the burning signal indicates that the antifuse unit 10 is not burned through, the signal receiving unit 42 controls the third NMOS transistor MN3 to turn on.

[0048] The signal receiving unit 42 includes a first input terminal 42A, a second input terminal 42B, and an output terminal 42C. The first input terminal 42A receives the programming signal Data, the second input terminal 42B receives the verification enable signal VerifyEn, and the output terminal 42C is electrically connected to the control terminal of the first transistor. In this embodiment, the signal receiving unit 42 includes a NAND gate 421 and a first inverter P1. The output terminal of the NAND gate 421 serves as the output terminal 42C of the signal receiving unit 42. The first input terminal 42A is electrically connected to one input terminal of the NAND gate 421 via the first inverter P1, and the other input terminal of the NAND gate 421 is electrically connected to the second input terminal 42B of the signal receiving unit 42.

[0049] The antifuse circuit provided in this embodiment allows the verification control unit to control the read unit to electrically connect with the antifuse unit after the antifuse unit 10 has been programmed, entering a verification mode, thereby enabling real-time verification of the antifuse unit 10. It is understood that when the read unit 30 performs read / write amplification operations, the first transistor remains in a conducting state to avoid affecting the connection between the antifuse unit 10 and the read unit 30.

[0050] Figure 2 This is a signal timing diagram of the antifuse circuit provided in the first embodiment of this disclosure. Please refer to it. Figure 2After the antifuse unit 10 completes the breakdown programming, it enters the verification mode. In verification mode, the programming control signal BlowEn of the programming unit is set to 0, the precharge control signal pre is set to 0, the precharge unit 31 of the read unit 30 charges the latch 32, the input signal EFDAT of the input terminal IN of the read unit 30 is set to 1, and the output signal EFOUT of the output terminal OUT of the read unit 30 outputs 1. After charging is completed, the precharge control signal pre is set to 1, the verification enable signal VerifyEn is set to 1, the read enable signal discharge is set to 1, and the read unit 30 is connected to the antifuse unit 10. If the programming signal Data is 1 (i.e., the antifuse unit 10 does not need to be programmed), and the output signal EFOUT (i.e., the data signal) of the output terminal OUT of the read unit 30 is 1 (e.g., ... Figure 2 (As shown by the dashed line), this indicates that the actual state of the antifuse unit 10 is that it has not been programmed. This actual state is consistent with the programming signal, and the antifuse unit 10 has been programmed correctly. If the programming signal Data is 1 (i.e., the antifuse unit 10 does not need to be programmed), and the output signal EFOUT of the output terminal OUT of the read unit 30 is 0 (e.g., ... Figure 2 As shown by the solid line, this indicates that the actual state of the antifuse unit 10 is being programmed, but this actual state is inconsistent with the programming signal, indicating that the antifuse unit 10 has been mistakenly programmed. Therefore, the antifuse circuit disclosed herein does not require verification of the programming state of the antifuse unit 10 using a testing machine; instead, it can verify the programming state of the antifuse unit 10 in real time, quickly verifying whether the antifuse unit 10 has been mistakenly burned through, saving time, and achieving high verification accuracy.

[0051] As an example, the second embodiment of this disclosure also provides an antifuse circuit; please refer to [link to relevant documentation]. Figure 3 This is a circuit diagram of the antifuse circuit provided in the second embodiment of this disclosure. The difference between the second embodiment and the first embodiment is that the first transistor of the verification control unit is a fourth PMOS transistor MP4, and the signal receiving unit 42 includes a NAND gate 421 but does not include the first inverter P1. The two input terminals of the NAND gate 421 are electrically connected to the first output terminal 42A and the second input terminal 42B, respectively, and the output terminal of the NAND gate 421 serves as the output terminal 42C of the signal receiving unit 42. When both the verification enable signal VerifyEn and the programming signal Data are 1, the signal receiving unit 42 outputs 0, the verification switch unit 41 is turned on, and the reading unit 30 is connected to the antifuse unit 10.

[0052] This disclosure also provides a method for verifying the programming status of an antifuse unit, wherein the verification method uses the aforementioned antifuse circuit. Figure 4This is a schematic diagram illustrating the steps of the antifuse unit programming status verification method provided in the third embodiment of this disclosure. Please refer to [link / reference]. Figure 1 and Figure 4 The method includes:

[0053] Step S401: Input a programming signal and program the antifuse unit 10 according to the programming signal Data.

[0054] Specifically, in this embodiment, the programming control signal BlowEn enables the programming unit 20 of the antifuse circuit, allowing the programming circuit to determine whether to perform a programming operation on the antifuse unit 10 based on the programming signal Data. For example, in this embodiment, the programming signal Data is input through the programming control unit 21 and serves as the control signal for the signal conversion unit 22. If the programming signal Data indicates that the antifuse unit 10 is not burned through, then the programming signal Data is 1; if the programming signal Data indicates that the antifuse unit 10 is burned through, then the programming signal Data is 0.

[0055] Step S402: Control the reading unit 30 to electrically connect with the antifuse unit 10 according to the programming signal Data and the verification enable signal VerifyEn.

[0056] In this step, the programming signal Data and the verification enable signal VerifyEn serve as input signals to the verification control unit 40. The verification control unit 40 controls the reading unit 30 to electrically connect with the antifuse unit 10 based on the verification enable signal VerifyEn and the programming signal Data of the antifuse unit 10. After the antifuse unit 10 completes the breakdown programming, the verification enable signal VerifyEn is set to 1, and the programming signal Data is set to 1. The programming signal Data indicates that the antifuse unit 10 has not been burned through, and the system enters the verification mode, which verifies whether the antifuse unit 10 has been mistakenly burned through. If the programming signal Data is set to 0, it indicates that the antifuse unit 10 has been burned through, and the verification enable signal VerifyEn is set to 1. The verification control unit 40 cannot control the reading unit 30 to connect with the antifuse unit 10. It is understandable that when the reading unit 30 performs the read amplification operation, it is necessary to set the programming signal Data and the verification enable signal VerifyEn to keep the verification switch unit 41 in the on state, so as to avoid affecting the connection between the reading unit 30 and the antifuse unit 10.

[0057] In step S403, the reading unit 30 reads the data signal from the antifuse unit 10. In this step, if the antifuse unit 10 is burned through, the data signal read when reading the antifuse unit 10 is 0, and the input signal EFDAT at the input terminal IN of the reading unit 30 also becomes 0. If the antifuse unit 10 is not burned through, the data signal read from the antifuse unit 10 is 1, and the input signal EFDAT at the input terminal IN of the reading unit 30 remains at 1. The reading unit 30 outputs an output signal EFOUT based on the input signal EFDAT. The output signal EFOUT is related to the data signal read when reading the antifuse unit 10, thereby realizing the reading of the data signal from the antifuse unit 10 by the reading unit 30. In this embodiment, the output signal EFOUT of the read unit is consistent with the data signal of the antifuse unit 10; that is, when the data signal of the antifuse unit 10 is 1, the output signal EFOUT of the read unit is also 1; when the data signal of the antifuse unit 10 is 0, the output signal EFOUT of the read unit is also 0. It is understood that in other embodiments of this disclosure, the output signal EFOUT of the read unit and the data signal of the antifuse unit 10 may also be out of phase; that is, when the data signal of the antifuse unit 10 is 1, the output signal EFOUT of the read unit is 0; when the data signal of the antifuse unit 10 is 0, the output signal EFOUT of the read unit is 1.

[0058] Step S404: Verify whether the antifuse unit 10 is programmed correctly based on the data signal and the programming signal Data.

[0059] In this step, the data signal (i.e., the output signal EFOUT of the output terminal OUT of the read unit 30) and the programming signal Data are compared. Based on the comparison result, it is determined whether the antifuse unit 10 has been programmed correctly. If the data signal and the programming signal Data are consistent, the antifuse unit 10 has been programmed correctly; if the data signal and the programming signal Data are inconsistent, the antifuse unit 10 has been programmed incorrectly.

[0060] Specifically, please refer to Figure 5This is a signal truth table. If the programming signal Data is 1 (i.e., indicating that the antifuse unit 10 has not been programmed), and the data signal (i.e., the output signal EFOUT of the output terminal OUT of the read unit 30) is 1, the true state of the antifuse unit 10 is that it has not been programmed, which is consistent with the programming signal characterization. That is, the data signal and the programming signal Data are consistent, and the antifuse unit 10 is programmed correctly. If the programming signal Data is 1 (i.e., indicating that the antifuse unit 10 has not been programmed), and the data signal (i.e., the output signal EFOUT of the output terminal OUT of the read unit 30) is 0, the true state of the antifuse unit 10 is that it has been programmed, which is inconsistent with the programming signal characterization. That is, the data signal and the programming signal Data are inconsistent, and the antifuse unit 10 is programmed incorrectly. It is understood that if the programming signal Data is 0 (i.e., indicating that the antifuse unit 10 is burned through), the verification enable signal VerifyEn is set to 1, and the verification control unit 40 cannot control the reading unit 30 to connect with the antifuse unit 10, that is, it cannot enter the verification mode.

[0061] The antifuse unit programming status verification method provided in this embodiment can verify the programming status of the antifuse unit 10 in real time using programming signals and antifuse unit data signals. It does not require verification of the programming status of the antifuse unit 10 through a testing machine, and can quickly verify whether the antifuse unit 10 has been mistakenly burned through, saving time and having a high verification accuracy.

[0062] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An antifuse circuit, characterized in that, include: Anti-fuse unit; A programming circuit is connected to the antifuse unit, and the programming circuit is used to program the antifuse unit according to the programming control signal and the programming signal. A reading unit is used to read data signals from the antifuse unit; A verification control unit is used to control the reading unit to be electrically connected to the antifuse unit according to the verification enable signal and the writing signal when verifying the writing status of the antifuse unit. The verification control unit includes: A first transistor, the first terminal of which is connected to the antifuse unit, and the second terminal of which is connected to the input terminal of the read unit; The signal receiving unit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the signal receiving unit receives the programming signal, the second input terminal of the signal receiving unit receives the verification enable signal, and the output terminal of the signal receiving unit is electrically connected to the control terminal of the first transistor. When verifying the programming status of the antifuse unit, if the programming signal indicates that the antifuse unit is not burned through, the signal receiving unit controls the first transistor to turn on.

2. The antifuse circuit according to claim 1, characterized in that, The first transistor is an NMOS transistor.

3. The antifuse circuit according to claim 2, characterized in that, The signal receiving unit includes: The NAND gate, whose output is used as the output of the signal receiving unit; The first inverter is used to electrically connect the first input terminal of the signal receiving unit to one input terminal of the NAND gate, and the other input terminal of the NAND gate is electrically connected to the second input terminal of the signal receiving unit.

4. The antifuse circuit according to claim 1, characterized in that, The first transistor is a PMOS transistor.

5. The antifuse circuit according to claim 4, characterized in that, The signal receiving unit includes: The NAND gate has its two input terminals electrically connected to the first output terminal and the second input terminal, respectively, and its output terminal serves as the output terminal of the signal receiving unit.

6. The antifuse circuit according to claim 1, characterized in that, The antifuse unit includes a first end and a second end. The first end of the antifuse unit is grounded, and the second end of the antifuse unit is electrically connected to the input end of the reading unit.

7. The antifuse circuit according to any one of claims 1 to 6, characterized in that, The reading unit includes: A pre-charging unit is used to pre-charge the input terminal of the reading unit according to a pre-charging control signal; A latch, wherein the input terminal of the latch is electrically connected to the input terminal of the read unit, and the output terminal of the latch is electrically connected to the output terminal of the read unit.

8. The antifuse circuit according to claim 7, characterized in that, The pre-charge unit includes a second transistor, the first terminal of which is connected to the power supply voltage, the second terminal of which is connected to the input terminal of the readout unit, and the gate of which receives the pre-charge control signal.

9. The antifuse circuit according to claim 7, characterized in that, The antifuse circuit also includes a read switch unit, which is used to control the input terminal of the read unit to be electrically connected to the second terminal of the antifuse unit according to the read enable signal.

10. The antifuse circuit according to claim 9, characterized in that, The read switch unit includes a third transistor, the first terminal of which is connected to the second terminal of the antifuse unit, the second terminal of which is connected to the input terminal of the read unit, and the gate of which receives the read enable signal.

11. The antifuse circuit according to claim 7, characterized in that, The reading unit further includes a second inverter, which is disposed between the latch and the output terminal of the reading unit.

12. A method for verifying the programming status of an antifuse unit, employing the antifuse circuit according to any one of claims 1 to 11, characterized in that, The method includes: Input a programming signal, and program the antifuse unit according to the programming signal; The read unit is electrically connected to the antifuse unit according to the programming signal and the verification enable signal; The reading unit reads the data signal from the antifuse unit; Verify whether the antifuse unit has been programmed correctly based on the data signal and the programming signal.

13. The method for verifying the programming status of the antifuse unit according to claim 12, characterized in that, The step of verifying whether the antifuse unit is correctly programmed based on the data signal and the programming signal further includes: The data signal and the programming signal are compared, and the antifuse unit is determined to be programmed correctly based on the comparison result.

14. The method for verifying the programming status of the antifuse unit according to claim 13, characterized in that, The step of determining whether the antifuse unit has been correctly programmed based on the comparison result of the data signal and the programming signal further includes: The data signal and the programming signal are consistent, indicating that the antifuse unit has been programmed correctly. The data signal and the programming signal are inconsistent, and the antifuse unit is mistakenly programmed.

15. The method for verifying the programming status of the antifuse unit according to claim 14, characterized in that, The step of programming the antifuse unit according to the programming signal further includes: The programming signal indicates that the antifuse unit is not burned through.

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