Semiconductor structure and semiconductor memory

Abstract

The present disclosure provides a semiconductor structure and a semiconductor memory. The semiconductor structure comprises an active layer and a first gate layer and a second gate layer juxtaposed above the active layer; the active layer comprises a first active region and a second active region extending along a first direction, and a third active region extending along a second direction and located between the first active region and the second active region; the first gate layer comprises a first gate part extending along the first direction and a second gate part extending along the second direction, the first gate part is located at a side of the first active region away from the third active region, and the second gate part spans the first active region and partially covers the third active region; the second gate layer comprises a third gate part extending along the first direction and a fourth gate part extending along the second direction, the third gate part is located at a side of the second active region away from the third active region, and the fourth gate part spans the second active region and partially covers the third active region. While reducing the size, the reliability and stability of the device can also be ensured.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and a semiconductor memory. Background Technology

[0002] As semiconductor memory fabrication processes iterate and storage demands increase, the size of memory cells continues to shrink. Simultaneously, the devices that form the core region and control memory timing also need to be further miniaturized. However, this size reduction process introduces challenges to device stability and reliability. For example, during the manufacturing process, device contamination and performance degradation may occur. Summary of the Invention

[0003] In a first aspect, embodiments of this disclosure provide a semiconductor structure, including an active layer and a first gate layer and a second gate layer disposed parallel to the active layer; wherein...

[0004] The active layer includes a first active region and a second active region extending along a first direction, and a third active region extending along a second direction. The third active region is located between the first active region and the second active region, and is connected to the first active region and the second active region respectively.

[0005] The first gate layer includes a first gate portion extending along the first direction and a second gate portion extending along the second direction, the first gate portion and the second gate portion being connected to each other, the first gate portion being located on the side of the first active region away from the third active region, and the second gate portion crossing the first active region and partially covering the third active region.

[0006] The second gate layer includes a third gate portion extending along the first direction and a fourth gate portion extending along the second direction, the third gate portion and the fourth gate portion being interconnected, the third gate portion being located on the side of the second active region away from the third active region, and the fourth gate portion spanning the second active region and partially covering the third active region.

[0007] In some embodiments, the third active region includes a first sub-active region, a second sub-active region, and a third sub-active region arranged sequentially in the second direction, wherein the size of the first sub-active region in the first direction is smaller than the size of the second sub-active region in the first direction, and the size of the third sub-active region in the first direction is smaller than the size of the second sub-active region in the first direction.

[0008] The second gate portion covers the first sub-active region, and the fourth gate portion covers the third sub-active region.

[0009] In some embodiments, the first gate layer further includes a first branch and a second branch extending along the second direction, the first branch and the second branch being located on both sides of the second gate portion, respectively spanning the first active region, and respectively connected to the first gate portion;

[0010] The second gate layer further includes a third branch and a fourth branch extending along the second direction. The third branch and the fourth branch are located on both sides of the fourth gate portion, respectively spanning the second active region, and are respectively connected to the third gate portion.

[0011] In some embodiments, the second gate portion further partially covers the second sub-active region, and the fourth gate portion further partially covers the second sub-active region.

[0012] In some embodiments, the active layer is an axisymmetric shape, and the axis of symmetry of the active layer includes at least one of a first axis of symmetry parallel to a first direction and a second axis of symmetry parallel to a second direction.

[0013] In some embodiments, the first gate layer and the second gate layer are symmetrically distributed on both sides of the first axis of symmetry.

[0014] In some embodiments, the first gate layer is symmetrical about the second axis of symmetry, and the second gate layer is symmetrical about the second axis of symmetry.

[0015] In some embodiments, the first active region includes a first drain region and a second drain region located on both sides of the second gate portion, the second active region includes a third drain region and a fourth drain region located on both sides of the fourth gate portion, and the portion of the third active region located between the second gate portion and the fourth gate portion serves as a source region.

[0016] In some embodiments, the semiconductor structure includes a first transistor corresponding to the first drain region, a second transistor corresponding to the second drain region, a third transistor corresponding to the third drain region, and a fourth transistor corresponding to the fourth drain region; wherein...

[0017] The first transistor, the second transistor, the third transistor, and the fourth transistor share the source region;

[0018] The first transistor and the second transistor share the first gate layer;

[0019] The third transistor and the fourth transistor share the second gate layer.

[0020] In some embodiments, the semiconductor structure further includes a first gate dielectric layer and a second gate dielectric layer;

[0021] in,

[0022] The first gate dielectric layer is located between the first gate layer and the active layer;

[0023] The second gate dielectric layer is located between the second gate layer and the active layer.

[0024] In some embodiments, the materials of the first gate dielectric layer and the second gate dielectric layer include high dielectric constant (High K) materials, and the materials of the first gate layer and the second gate layer include metals.

[0025] In some embodiments, the semiconductor structure further includes a first contact located on the first drain region, a second contact located on the second drain region, a third contact located on the third drain region, a fourth contact located on the fourth drain region, a fifth contact located on the source region, a sixth contact located on the first gate portion, and a seventh contact located on the third gate portion.

[0026] In some embodiments, the distance between the first contact and the second contact and the first gate layer in the first direction is a first distance, and the distance between the third contact and the fourth contact and the second gate layer in the first direction is a second distance, wherein the first distance is smaller than the second distance.

[0027] In some embodiments, the first direction is perpendicular to the second direction.

[0028] In a second aspect, embodiments of this disclosure provide a semiconductor memory, including the semiconductor structure described in any one of the first aspects.

[0029] This disclosure provides a semiconductor structure and a semiconductor memory. The semiconductor structure includes an active layer and a first gate layer and a second gate layer disposed on the active layer. The active layer includes a first active region and a second active region extending along a first direction, and a third active region extending along a second direction. The third active region is located between the first and second active regions and is connected to both the first and second active regions. The first gate layer includes a first gate portion extending along the first direction and a second gate portion extending along the second direction, which are connected to each other. The first gate portion is located on the side of the first active region away from the third active region, and the second gate portion crosses the first active region and partially covers the third active region. The second gate layer includes a third gate portion extending along the first direction and a fourth gate portion extending along the second direction, which are connected to each other. The third gate portion is located on the side of the second active region away from the third active region, and the fourth gate portion crosses the second active region and partially covers the third active region. In this way, by designing the structure of the first gate layer and the second gate layer, the second gate portion is moved away from both sides of the first active region, and the second gate portion is moved away from both sides of the second active region. This avoids the pollution problem caused by gate diffusion due to damage to the protective sidewalls of the first gate layer and the second gate layer when contact vias are formed on both sides of the first active region and the second active region. At the same time, it can also adjust the size of the semiconductor structure and ensure the reliability and stability of the device while reducing the size of the semiconductor structure. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of a semiconductor structure;

[0031] Figure 2 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0032] Figure 3 A schematic diagram of another semiconductor structure provided in an embodiment of this disclosure;

[0033] Figure 4 This is a schematic diagram of an active layer structure provided in an embodiment of the present disclosure;

[0034] Figure 5 A schematic diagram of yet another semiconductor structure provided in this disclosure embodiment;

[0035] Figure 6 A schematic diagram of yet another semiconductor structure provided in this disclosure embodiment;

[0036] Figure 7 This is a schematic diagram of another active layer structure provided in an embodiment of the present disclosure;

[0037] Figure 8A schematic diagram of yet another semiconductor structure provided in this disclosure embodiment;

[0038] Figure 9 A schematic diagram of yet another semiconductor structure provided in this disclosure embodiment;

[0039] Figure 10 This is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of this disclosure. Detailed Implementation

[0040] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the relevant disclosure and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure.

[0042] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0043] It should be noted that the terms "first", "second", "third", etc., used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first", "second", "third", etc., can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0044] As memory cells in semiconductor memory arrays are further miniaturized, the devices that make up the core region and control memory timing also need to be further reduced in size. This miniaturization process introduces stability and reliability issues. Such process iteration leading to device size reduction is unacceptable from both the perspective of current technology and device stability.

[0045] In the patterning design of the core region of Dynamic Random Access Memory (DRAM), the further miniaturization of the size of the array memory cells presents further challenges to the device performance of existing structures.

[0046] In layout design, the distance from the gate to the contact via is further reduced, especially for the process of forming a gate structure with a high-k dielectric layer and a metal gate (MG) (HKMG). During the etching of the contact via, the barrier sidewalls (spacers) protecting the sidewalls of the gate structure may be partially or completely etched, exposing the gate material. As a result, on the one hand, the gate metal material may contaminate the equipment environment; on the other hand, the gate metal material may fall onto the active area (AA) and contaminate the silicon substrate. Furthermore, after the contact via is filled with metal, due to the etching of the barrier sidewalls of the gate structure and the easy diffusion of the gate metal material, the gate metal material will diffuse into the contact via, contaminating the structure of the contact via.

[0047] Figure 1 This is a schematic diagram of a semiconductor structure used to form transistors, specifically four transistors. Figure 1 As shown, the semiconductor structure can be divided into an active layer and a gate layer located on top of the active layer; wherein, the active layer is divided into a first active region 201, a second active region 202 and a third active region 203, and the gate layer is divided into a first gate layer 21 and a second gate layer 22.

[0048] exist Figure 1 In the semiconductor structure shown, C1 and C2 represent contact vias located on both sides of the first active region 201 (since the contacts are formed within the contact vias, C1 and C2 can also represent contacts formed on both sides of the first active region 201), and C3 and C4 represent contact vias located on both sides of the second active region 202 (since the contacts are formed within the contact vias, C3 and C4 can also represent contacts formed on both sides of the second active region 202); Figure 1 In this structure, both the first gate layer 21 and the second gate layer 22 are C-shaped. With this gate structure, the first gate layer 21 is close to the contact vias C1 and C2, and the second gate layer 22 is also close to the contact vias C3 and C4. Therefore, when forming the contact vias, this close proximity may cause partial or complete etching of the barrier sidewalls protecting the gate sidewalls, thus exposing the gate material. This is particularly problematic for the HKMG process, easily leading to the aforementioned issues caused by the exposure of the gate structure material.

[0049] Based on this, embodiments of the present disclosure provide a semiconductor structure, which includes an active layer and a first gate layer and a second gate layer arranged in parallel on the active layer; wherein, the active layer includes a first active region and a second active region extending along a first direction, and a third active region extending along a second direction, the third active region being located between the first active region and the second active region, and being connected to the first active region and the second active region respectively; the first gate layer includes a first gate portion extending along the first direction and a second gate portion extending along the second direction, the first gate portion and the second gate portion being connected to each other, the first gate portion being located on the side of the first active region away from the third active region, and the second gate portion crossing the first active region and partially covering the third active region; the second gate layer includes a third gate portion extending along the first direction and a fourth gate portion extending along the second direction, the third gate portion and the fourth gate portion being connected to each other, the third gate portion being located on the side of the second active region away from the third active region, and the fourth gate portion crossing the second active region and partially covering the third active region. In this way, by designing the structure of the first gate layer and the second gate layer, the second gate portion is moved away from both sides of the first active region, and the fourth gate portion is moved away from both sides of the second active region. This avoids the pollution problem caused by gate material diffusion due to damage to the protective sidewalls of the first gate layer and the second gate layer when contact vias are formed on both sides of the first active region and the second active region. At the same time, it can also adjust the size of the semiconductor structure and ensure the reliability and stability of the device while reducing the size of the semiconductor structure.

[0050] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0051] In one embodiment of this disclosure, see [link to embodiment]. Figure 2 This illustrates a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 2 As shown, the semiconductor structure may include an active layer and a first gate layer 11 and a second gate layer 12 arranged in parallel on the active layer; wherein,

[0052] The active layer includes a first active region 101 and a second active region 102 extending along a first direction, and a third active region 103 extending along a second direction. The third active region 103 is located between the first active region 101 and the second active region 102, and is connected to the first active region 101 and the second active region 102 respectively.

[0053] The first gate layer 11 includes a first gate portion 111 extending along a first direction and a second gate portion 112 extending along a second direction. The first gate portion 111 and the second gate portion 112 are connected to each other. The first gate portion 111 is located on the side of the first active region 101 away from the third active region 103. The second gate portion 112 spans the first active region 101 and partially covers the third active region 103.

[0054] The second gate layer 12 includes a third gate portion 121 extending along a first direction and a fourth gate portion 122 extending along a second direction. The third gate portion 121 and the fourth gate portion 122 are connected to each other. The third gate portion 121 is located on the side of the second active region 102 away from the third active region 103. The fourth gate portion 122 spans the second active region 102 and partially covers the third active region 103.

[0055] It should be noted that this semiconductor structure can be divided into at least an active layer and a gate layer, with the gate layer located above the active layer. Furthermore, this semiconductor structure can be used to form transistors. The active layer is primarily used to form the source and drain electrodes of the transistor, and also to form the transistor channel; the gate layer is primarily used to form the transistor gate.

[0056] like Figure 2 As shown, the active layer can be divided into a first active region 101 extending along a first direction, a second active region 102 extending along a first direction, and a third active region 103 extending along a second direction. The third active region 103 is located between the first active region 101 and the second active region 102. One side of the third active region 103 is connected to the first active region 101, and the other side is connected to the second active region 102.

[0057] In this configuration, the first direction and the second direction intersect, and in some embodiments, the first direction is perpendicular to the second direction. Thus, when fabricating this semiconductor structure, two mutually perpendicular directions are more conducive to process implementation. Furthermore, the perpendicularity of the first and second directions results in a neat and concise semiconductor structure, which is beneficial for device design and saves device area.

[0058] like Figure 2 As shown, the gate layer can be divided into a first gate layer 11 and a second gate layer 12, and both the first gate layer 11 and the second gate layer 12 can include two parts.

[0059] The first gate layer 11 includes a first gate portion 111 and a second gate portion 112. For ease of distinction, in Figure 2 The connection between the first gate portion 111 and the second gate portion 112 is shown by a dashed line. The first gate portion 111 extends along a first direction and is located on the side of the first active region 101 away from the third active region 103; that is, the first gate portion 111 is not formed above the active layer. Specifically, the first gate portion 111 may be formed above a shallow trench isolation (STI) structure (not shown) used to isolate the active layer. The second gate portion 112 is mainly formed above the active layer, with one side connected to the first gate portion 111, and extends along a second direction across the first active region 101 to the third active region 103, partially covering the third active region 103. Figure 2 As shown, the connection between the second gate portion 112 and the first gate portion 111 is the middle part of the first gate portion 111 and the side of the second gate portion 112 away from the third active region 103.

[0060] The second gate layer 12 includes a third gate portion 121 and a fourth gate portion 122. For ease of distinction, in Figure 2 The connection between the third gate portion 121 and the fourth gate portion 122 is shown by a dashed line. The third gate portion 121 extends along the first direction and is located on the side of the second active region 102 away from the third active region 103; that is, the third gate portion 121 is not formed above the active layer. Specifically, the third gate portion 121 may be formed above the STI (not shown in the figure). The fourth gate portion 122 is mainly formed above the active layer. One side of the fourth gate portion 122 is connected to the third gate portion 121 and extends along the second direction across the second active region 102 to the third active region, partially covering the third active region 103. Figure 2 As shown, the connection between the fourth gate portion 122 and the third gate portion 121 is the middle portion of the third gate portion 121 and the side portion of the fourth gate portion 122 away from the third active region 103.

[0061] like Figure 2 As shown, both the first gate layer 11 and the second gate layer 12 can be in the form of a "T" shape. For the first gate layer 11, the first gate portion 111 forms the head of the "T" shape, and the second gate portion 112 forms the foot of the "T" shape; for the second gate layer 12, the third gate portion 121 forms the head of the "T" shape, and the fourth gate portion 122 forms the foot of the "T" shape.

[0062] Based on the structure of the first gate layer 11 and the second gate layer 12, since the second gate portion 112 is far from both sides of the first active region 101 and the fourth gate portion 122 is also far from both sides of the second active region 102, when etching is performed on both sides of the first active region 101 and the second active region 102 along the first direction to form contact vias (contact vias are used to fill conductive material to form contacts), the barrier sidewalls used to protect the gate sidewalls will not be etched, thus the gate material will not be exposed. This avoids the problem of contamination of the equipment or silicon substrate caused by gate material exposure, and also prevents contamination of the contact vias due to gate material diffusion. Especially for the HKMG process, it can better avoid problems such as contamination caused by gate material exposure.

[0063] and Figure 1 In comparison, Figure 2In the gate layer structure shown, the second gate portion 112 is far from both sides of the first active region 101, and the fourth gate portion 122 is also far from both sides of the second active region 102. Therefore, when forming contact vias, the blocking sidewalls will not be damaged, and the gate will not be exposed. This can effectively avoid problems such as contamination caused by the gate being too close to the contact via, and enable the semiconductor structure to achieve better reliability and stability.

[0064] See Figure 3 This illustrates a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure. For the first gate layer 11 and the second gate layer 12, as... Figure 3 As shown, in some embodiments, the first gate layer 11 further includes a first branch 113 and a second branch 114 extending along a second direction. The first branch 113 and the second branch 114 are located on both sides of the second gate portion 112, respectively spanning the first active region 101, and respectively connected to the first gate portion 111.

[0065] The second gate layer 12 also includes a third branch 123 and a fourth branch 124 extending along the second direction. The third branch 123 and the fourth branch 124 are located on both sides of the fourth gate portion 122, respectively spanning the second active region 102, and respectively connected to the third gate portion 121.

[0066] It should be noted that, in Figure 2 Based on the semiconductor structure shown, such as Figure 3 As shown, the first gate layer 11 may further include a first branch 113 and a second branch 114. The first branch 113 and the second branch 114 are respectively located on both sides of the second gate portion 112. Both the first branch 113 and the second branch 114 span the first active region 101 and are connected to the first gate portion 111. Moreover, the connection points with the first gate portion 111 do not extend beyond the two side boundaries of the first gate portion 111. The first branch 113 and the second branch 114 may have the same size as the second gate portion 112 or may have a different size; no specific limitation is made here.

[0067] The second gate layer 12 may further include a third branch 123 and a fourth branch 124, which are located on opposite sides of the fourth gate portion 122. Both the third branch 123 and the fourth branch 124 span the second active region 102 and are connected to the third gate portion 121, with their connections not extending beyond the lateral boundaries of the third gate portion 121. The third branch 123 and the fourth branch 124 may have the same or different dimensions as the fourth gate portion 122; no specific limitation is made here.

[0068] like Figure 3 As shown, both the first gate layer 11 and the second gate layer 12 have a three-finger structure. Alternatively, the first gate layer 11 and the second gate layer 12 may also have other numbers of multi-finger structures.

[0069] Thus, for Figure 3 In terms of the provided semiconductor structure, since the distance between the first branch 113 and one side of the first active region 101, the distance between the second branch 114 and the other side of the first active region 101 are all relatively large, the distance between the third branch 123 and one side of the second active region 102, and the distance between the fourth branch 124 and the other side of the second active region 102 are all relatively large, it is also possible to avoid problems such as contamination caused by gate material exposure, so that the semiconductor structure can achieve better reliability and stability.

[0070] For the active layer, in one possible implementation, see [link to relevant documentation]. Figure 4 This illustrates a schematic diagram of an active layer structure provided in an embodiment of this disclosure. For example, Figure 4 The active layer shown is Figure 3 The active layer in the semiconductor structure shown. For example... Figure 4 As shown, the third active region 103 may include a first sub-active region 1031, a second sub-active region 1032 and a third sub-active region 1033 arranged sequentially in the second direction. The size of the first sub-active region 1031 in the first direction is smaller than the size of the second sub-active region 1032 in the first direction, and the size of the third sub-active region 1033 in the first direction is smaller than the size of the second sub-active region 1032 in the first direction.

[0071] The second gate portion 112 covers the first sub-active region 1031, and the fourth gate portion 122 covers the third sub-active region 1033.

[0072] It should be noted that the third active region 103 may be composed of a first sub-active region 1031, a second sub-active region 1032, and a third sub-active region 1033. The second sub-active region 1032 is located between the first sub-active region 1031 and the third sub-active region 1033, with its two sides connected to the first sub-active region 1031 and the third sub-active region 1033, respectively. One side of the first sub-active region 1031 is connected to the first active region 101, and the other side is connected to the second sub-active region 1032. One side of the third sub-active region 1033 is connected to the second active region 102, and the other side is connected to the second sub-active region 1032. The second gate portion 112 covers the first sub-active region 1031, and the fourth gate portion 122 covers the third sub-active region 1033.

[0073] Furthermore, combined Figure 2 and Figure 4As shown, the first active region 101 includes a first drain region 1011 and a second drain region 1012 located on both sides of the second gate portion 112, the second active region 102 includes a third drain region 1021 and a fourth drain region 1022 located on both sides of the fourth gate portion 122, and the portion of the third active region 103 located between the second gate portion 112 and the fourth gate portion 122 serves as the source region.

[0074] It should be noted that in the first active region 101, the two sides along the first direction are respectively the first drain region 1011 and the second drain region 1012, and the part between the first drain region 1011 and the second drain region 1012 is referred to as the first channel region 1013; in the second active region 102, the two sides are the third drain region 1021 and the fourth drain region 1022, and the part between the third drain region 1021 and the fourth drain region 1022 is referred to as the second channel region 1023.

[0075] In the third active region 103, the first sub-active region 1031 is covered by the second gate portion 112, and the third sub-active region 1033 is covered by the fourth gate portion 122. The portion between the second gate portion 112 and the fourth gate portion 122 is the second sub-active region 1032. In this case, the second sub-active region 1032 is the source region.

[0076] For example, see Figure 5 This illustrates a schematic diagram of yet another semiconductor structure provided in this disclosure embodiment. To show the locations of the covered first sub-active region 1031 and third sub-active region 1033, in... Figure 5 In the diagram, the outlines of the first sub-active region 1031 and the third sub-active region 1033 are shown with dashed lines. Figure 5 The second gate portion 112 only covers the first sub-active region 1031 in the third active region 103, and the fourth gate portion only covers the third sub-active region 1033 in the third active region 103, that is, the second sub-active region 1032 serves as the source region.

[0077] In this case, the first channel region 1013 and the first sub-active region 1031 together form the channel of the active layer on one side of the second direction, and the second channel region 1023 and the third sub-active region 1033 together form the channel of the active layer on the other side of the second direction.

[0078] Furthermore, in some embodiments, the second gate portion 112 may also partially cover the second sub-active region 1032, and the fourth gate portion 122 may also partially cover the second sub-active region 1032.

[0079] It should be noted that the second gate portion 112 may cover not only the first sub-active region 1031, but also partially cover the second sub-active region 1032, and the fourth gate portion 122 may cover not only the third sub-active region 1033, but also partially cover the second sub-active region 1032.

[0080] For example, see Figure 6 This illustrates a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure. To show the location of the covered portion in the third active region 103, in... Figure 6 In the diagram, the covered portions of the first sub-active region 1031, the third sub-active region 1033, and the second sub-active region 1032 are outlined with dashed lines. In this case, the source region is the second sub-active region 1032 between the second gate portion 112 and the fourth gate portion 122, rather than the entire second sub-active region 1032.

[0081] In this case, the first channel region 1013, the first sub-active region 1031, and the portion of the second sub-active region 1032 covered by the second gate portion 112 together form a channel of the active layer on one side of the second direction, and the second channel region 1032, the third sub-active region 1033, and the portion of the second sub-active region 1032 covered by the fourth gate portion 122 together form a channel of the active layer on the other side of the second direction.

[0082] like Figure 4 As shown, the size H1 of the first sub-active region 1031 in the first direction is smaller than the size H2 of the second sub-active region 1032 in the first direction, and the size H3 of the third sub-active region 1033 in the first direction is smaller than the size H2 of the second sub-active region 1032 in the first direction.

[0083] In contrast, in another possible implementation, for the active layer, see [link to relevant documentation]. Figure 7 This illustrates a schematic diagram of an active layer structure provided in an embodiment of this disclosure. For example... Figure 7 As shown, the active layer is divided into a first active region 201, a second active region 202, and a third active region 203; wherein, the first active region 201 includes a first drain region 2011 and a second drain region 2022 on both sides, and a first channel region 2013 in the middle; the second active region 202 includes a third drain region 2013 and a fourth drain region 2014 on both sides, and a second channel region 2023 in the middle.

[0084] and Figure 7 Compared to the active layer shown, Figure 4 The active layer shown has a relatively narrow first sub-active region 1031 and a second sub-active region 1032, which can increase the channel length, for example, taking the first drain region as an example. Figure 4The channel length between the first drain region 1011 and the source region in the middle is greater than Figure 7 The channel length between the first drain region 2011 and the source region is reduced so that when current flows between the first drain region 1011 and the source region, the channel length through which the current flows is longer, thereby effectively suppressing the short channel effect (SCE) caused by size reduction.

[0085] SCE (Short-Circuit Voltage Coefficient) is a common phenomenon in Complementary Metal Oxide Semiconductor (CMOS) devices when the channel length is reduced. It causes threshold voltage drift, source-drain punch-through, and a lower drain induction barrier (DIBL), which can lead to CMOS device failure in severe cases. Therefore, in this embodiment, increasing the channel length suppresses SCE, thus ensuring the effective channel length of the device while reducing the overall device size, achieving better device stability.

[0086] It should also be noted that in the semiconductor structure provided in the embodiments of this disclosure, optimization may be performed only on the structure of the gate layer, or only on the structure of the active layer, or simultaneously on both the gate layer and the active layer; no specific limitation is made in this regard. For example, for Figure 2 In this regard, the active layer can be as follows: Figure 4 The structure shown can also be as follows: Figure 7 The structure shown.

[0087] Furthermore, the semiconductor structure provided in this embodiment is used to form transistors, specifically four transistors. That is, the semiconductor structure includes a first transistor corresponding to the first drain region 1011, a second transistor corresponding to the second drain region 1012, a third transistor corresponding to the third drain region 1021, and a fourth transistor corresponding to the fourth drain region 1022; wherein,

[0088] The first transistor, the second transistor, the third transistor, and the fourth transistor share a source region;

[0089] The first transistor and the second transistor share the first gate layer 11;

[0090] The third and fourth transistors share the second gate layer 12.

[0091] It should be noted that the drain region is used to form the drain of the transistor. The active layer includes four drain regions, which correspond to the formation of four transistors. Each drain region forms the drain of the corresponding transistor, that is, each of the four transistors includes a separate drain.

[0092] The source region is used to form the source of a transistor. That is, four transistors share the same source region, which forms the source of the first transistor, the source of the second transistor, the source of the third transistor, and the source of the fourth transistor.

[0093] The gate layer is used to form the gate of the transistor, wherein the first gate layer 101 is shared by the first transistor and the second transistor, that is, the first gate layer 101 forms both the gate of the first transistor and the gate of the second transistor; the second gate layer 102 is shared by the third transistor and the fourth transistor, that is, the second gate layer 102 forms both the gate of the third transistor and the gate of the fourth transistor.

[0094] Understandably, in Figure 3 In the semiconductor structure shown, the first transistor, the second transistor, the third transistor, and the fourth transistor are all dual-gate transistors.

[0095] In this way, by sharing the source region and gate region among transistors, it is possible to fabricate a larger number of transistors in the same area, which is beneficial for reducing the size of semiconductor structures and saving area.

[0096] In addition, the channel between the first drain region 1011 and the source region serves as the channel of the first transistor, the channel between the second drain region 1012 and the source region serves as the channel of the second transistor, the channel between the third drain region 1021 and the source region serves as the channel of the third transistor, and the channel between the fourth drain region 1022 and the source region serves as the channel of the fourth transistor.

[0097] Furthermore, such as Figure 4 As shown, the active layer is an axisymmetric figure, and the axis of symmetry of the active layer includes at least one of a first axis of symmetry AA' parallel to the first direction and a second axis of symmetry BB' parallel to the second direction.

[0098] It should be noted that the schematic diagrams provided in the embodiments of this disclosure are all top view schematic diagrams. In the top view, the active layer is an axisymmetric figure. Its axis of symmetry can be a first axis of symmetry AA' parallel to the first direction, or a second axis of symmetry BB' parallel to the second direction. Alternatively, the active layer can be symmetrically distributed in both the first and second directions, with the first axis of symmetry AA' and the second axis of symmetry BB' being its axes of symmetry.

[0099] It should also be noted that, such as Figure 7 The active layer shown is also an axisymmetric figure, which may include at least one of a first axis of symmetry AA' parallel to the first direction and a second axis of symmetry BB' parallel to the second direction.

[0100] In this way, whether Figure 4 or Figure 7 The active layer shown is axially symmetric, which makes the semiconductor structure neatly arranged and helps to save device area.

[0101] See Figure 8 It shows a schematic diagram of another semiconductor structure provided in the embodiments of this disclosure. Figure 8 and Figure 2 The structure is the same, except that it adds identifiers for the first axis of symmetry AA' and the second axis of symmetry BB'. For example... Figure 8 As shown, the first gate layer 11 and the second gate layer 12 are symmetrically distributed on both sides of the first axis of symmetry AA'. The first gate layer 11 is symmetrical about the second axis of symmetry BB', and the second gate layer 12 is symmetrical about the second axis of symmetry BB'.

[0102] It should be noted that in this embodiment, the gate layer is also an axisymmetric pattern. Specifically, for the gate layer as a whole, as... Figure 8 As shown, the axis of symmetry can be a first axis of symmetry AA' and / or a second axis of symmetry BB'. When the first axis of symmetry AA' is the axis of symmetry, the first gate layer 11 and the second gate layer 12 can be symmetrically distributed on both sides of the first axis of symmetry AA'. When the second axis of symmetry BB' is the axis of symmetry, both the first gate layer 11 and the second gate layer 12 are symmetrical about the second axis of symmetry BB'.

[0103] By setting the gate layer as an axisymmetric image, the overall semiconductor structure can be arranged neatly, which is beneficial for process implementation and saves area.

[0104] Furthermore, the semiconductor structure also includes a first gate dielectric layer and a second gate dielectric layer; wherein,

[0105] The first gate dielectric layer is located between the first gate layer 11 and the active layer;

[0106] The second gate dielectric layer is located between the second gate layer 12 and the active layer.

[0107] It should be noted that the semiconductor structure provided in this embodiment may further include a gate dielectric layer, which is divided into a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is located between the first gate layer 11 and the active layer, and the second gate dielectric layer is located between the second gate layer 12 and the active layer. Since the gate dielectric layer is covered beneath the gate layer, and the accompanying drawing is a top view, the gate dielectric layer is not shown in the drawing.

[0108] Similar to the sharing relationship of the gate layer, the first transistor and the second transistor share the first gate dielectric layer, and the third transistor and the fourth transistor share the second gate dielectric layer.

[0109] Furthermore, in the embodiments of this disclosure, the first transistor, the second transistor, the third transistor, and the fourth transistor can all be N-channel metal-oxide-semiconductor (NMOS) or P-channel metal-oxide-semiconductor (PMOS), and different types of transistors can be implemented by performing different types of doping in the active layer.

[0110] In some embodiments, the materials of the first gate dielectric layer and the second gate dielectric layer include high dielectric constant (High K) materials, and the materials of the first gate layer and the second gate layer include metals.

[0111] It should be noted that the gate in this semiconductor structure can be fabricated using the HKMG process. In this case, the first gate dielectric layer and the second gate dielectric layer are made of High K material, while the first gate layer and the second gate layer are made of metal material. Thus, the HKMG process can effectively improve the performance of the transistor, giving the semiconductor structure the advantages of lower power consumption and less leakage.

[0112] See Figure 9 It illustrates a schematic diagram of another semiconductor structure provided in an embodiment of this disclosure, such as... Figure 9 As shown, the semiconductor structure also includes a first contact C1 located on the first drain region 1011, a second contact C2 located on the second drain region 1012, a third contact C3 located on the third drain region 1021, a fourth contact C4 located on the fourth drain region 1022, a fifth contact C5 located on the source region, a sixth contact C6 located on the first gate portion 111, and a seventh contact C7 located on the third gate portion 121.

[0113] It should be noted that the contacts can be fabricated by depositing conductive material in the contact vias. The contacts are used for electrical connections to traces or components in a semiconductor structure, or for electrical connections to other external devices. For example, the first contact C1, the second contact C2, the third contact C3, the fourth contact C4, and the fifth contact C5 can be connected to a power supply or a ground terminal, etc.; the sixth contact C6 and the seventh contact C7 can be connected to a control power supply, or to an input signal, etc.

[0114] Compared to Figure 1 ,exist Figure 9In this configuration, the second gate portion 112 is far from the first contact C1 and the second contact C2, and the fourth gate portion 122 is far from the third contact C3 and the fourth contact C4. This effectively avoids the loss of the blocking sidewall of the gate sidewall when forming the contact via, thereby avoiding the exposure of the gate material and the various problems caused therefrom.

[0115] like Figure 9 As shown, the distance between the first contact C1 and the second contact C2 and the first gate layer 11 in the first direction is the first distance S1, and the distance between the third contact C3 and the fourth contact C4 and the second gate layer 12 in the first direction is the second distance S2. The first distance S1 is smaller than the second distance S2.

[0116] It should be noted that, as Figure 9 As shown, the distance between the first contact C1 and the first gate layer 11 in the first direction is represented by the distance between the first contact C1 and the second gate portion 112, which is the first distance S1; the distance between the second contact C2 and the first gate layer 11 in the first direction is represented by the distance between the second contact C2 and the second gate portion 112, which is also the first distance S1; that is, the distance between the first contact C1 and the second contact C2 and the first gate layer 11 in the first direction is the first distance S1, and the first contact C1 and the second contact C2 are also symmetrical about the second axis of symmetry BB'.

[0117] The distance between the third contact C3 and the second gate layer 12 in the first direction is expressed as the distance between the third contact C3 and the fourth gate portion 122, which is the second distance S2; the distance between the fourth contact C4 and the second gate layer 12 in the first direction is expressed as the distance between the fourth contact C4 and the fourth gate portion 122, which is also the second distance S2; that is, the distance between the third contact C3 and the fourth contact C4 and the second gate layer 12 in the first direction is the second distance S2, and the third contact C3 and the fourth contact C4 are also symmetrical about the second axis of symmetry BB'.

[0118] It should also be noted that, to facilitate upper-layer wiring, the first contact C1 and the third contact C3 on one side of the active layer in the first direction, and the third contact C3 and the fourth contact C4 on the other side of the active layer in the first direction, are not necessarily symmetrically distributed, but rather staggered by a certain distance. That is, the first spacing S1 can be smaller than the second spacing S2, or the first spacing S1 can be larger than the second spacing S2. This ensures that when wiring is connected through each contact or when electrical connections are made with internal or external components, space is used efficiently, and the stability of the circuit is guaranteed.

[0119] In short, the embodiments disclosed herein can be applied to the DRAM field, relating to DRAM Very Large Scale Integration (VLSI) design, and CMOS structure design. They address device surface efficiency (SCE) and reliability issues caused by size miniaturization by optimizing the structural design of the CMOS core region. Figure 4 As shown, by adjusting the dimensions of the connection between the common source and drain regions during the active region structure design, the device size can be adjusted. The area of ​​the active layer between the gate and drain regions can also be adjusted to create... Figure 2 and Figure 3 The two designs shown enable the device to maintain an effective channel length while further shrinking, and to ensure that the contact vias are far from the gate layer, thereby achieving better device reliability and stability. Additionally, [the following text appears to be incomplete and requires further context: "will..."] Figure 2 and Figure 1 In contrast, the embodiments of this disclosure can also increase the area of ​​the gate layer away from the contact via, which can solve the problems of contamination caused by the partial or complete etching of the gate sidewalls due to etching; at the same time, by increasing the area of ​​the active layer covered by the gate, the channel length can be increased even when the semiconductor structure size shrinks, so as to ensure the device reliability and stability of the semiconductor structure.

[0120] This disclosure provides a semiconductor structure including an active layer and a first gate layer and a second gate layer disposed on the active layer; wherein, the active layer includes a first active region and a second active region extending along a first direction, and a third active region extending along a second direction, the third active region being located between the first active region and the second active region, and being connected to the first active region and the second active region respectively; the first gate layer includes a first gate portion extending along the first direction and a second gate portion extending along the second direction, the first gate portion and the second gate portion being connected to each other, the first gate portion being located on the side of the first active region away from the third active region, and the second gate portion crossing the first active region and partially covering the third active region; the second gate layer includes a third gate portion extending along the first direction and a fourth gate portion extending along the second direction, the third gate portion and the fourth gate portion being connected to each other, the third gate portion being located on the side of the second active region away from the third active region, and the fourth gate portion crossing the second active region and partially covering the third active region. In this way, by designing the structure of the first gate layer and the second gate layer, the second gate portion is moved away from both sides of the first active region, and the second gate portion is moved away from both sides of the second active region. This avoids the pollution problem caused by gate diffusion due to damage to the protective sidewalls of the first gate layer and the second gate layer when contact vias are formed on both sides of the first active region and the second active region. At the same time, it can also adjust the size of the semiconductor structure and ensure the reliability and stability of the device while reducing the size of the semiconductor structure.

[0121] In another embodiment of this disclosure, see Figure 10 This illustrates a schematic diagram of the structural composition of a semiconductor memory 100 provided in an embodiment of this disclosure. For example... Figure 10 As shown, the semiconductor memory 100 includes the semiconductor structure 10 described in any of the foregoing embodiments.

[0122] It should be noted that the semiconductor memory 100 can be DRAM, or other types of memory, such as Static Random-Access Memory (SRAM), Synchronous Dynamic Random-Access Memory (SDRAM), etc.

[0123] As for the semiconductor memory 100, since it includes the semiconductor structure 10 described in the foregoing embodiments, the semiconductor memory 100 can be reduced in size, has better storage performance, and improves the yield of the semiconductor memory.

[0124] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure.

[0125] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0126] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0127] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0128] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0129] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0130] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, It includes an active layer and a first gate layer and a second gate layer arranged in parallel on the active layer; wherein, The active layer includes a first active region and a second active region extending along a first direction, and a third active region extending along a second direction. The third active region is located between the first active region and the second active region, and is connected to the first active region and the second active region respectively. The first gate layer includes a first gate portion extending along the first direction and a second gate portion extending along the second direction, the first gate portion and the second gate portion being connected to each other, the first gate portion being located on the side of the first active region away from the third active region, and the second gate portion crossing the first active region and partially covering the third active region. The second gate layer includes a third gate portion extending along the first direction and a fourth gate portion extending along the second direction, the third gate portion and the fourth gate portion being interconnected, the third gate portion being located on the side of the second active region away from the third active region, and the fourth gate portion spanning the second active region and partially covering the third active region.

2. The semiconductor structure according to claim 1, characterized in that, The third active region includes a first sub-active region, a second sub-active region, and a third sub-active region arranged sequentially in the second direction. The size of the first sub-active region in the first direction is smaller than the size of the second sub-active region in the first direction, and the size of the third sub-active region in the first direction is smaller than the size of the second sub-active region in the first direction. The second gate portion covers the first sub-active region, and the fourth gate portion covers the third sub-active region.

3. The semiconductor structure according to claim 2, characterized in that, The first gate layer further includes a first branch and a second branch extending along the second direction. The first branch and the second branch are located on both sides of the second gate portion, respectively spanning the first active region, and respectively connected to the first gate portion. The second gate layer further includes a third branch and a fourth branch extending along the second direction. The third branch and the fourth branch are located on both sides of the fourth gate portion, respectively spanning the second active region, and are respectively connected to the third gate portion.

4. The semiconductor structure according to claim 2 or 3, characterized in that, The second gate portion also partially covers the second sub-active region, and the fourth gate portion also partially covers the second sub-active region.

5. The semiconductor structure according to any one of claims 1-3, characterized in that, The active layer is an axisymmetric shape, and the axis of symmetry of the active layer includes at least one of a first axis of symmetry parallel to a first direction and a second axis of symmetry parallel to a second direction.

6. The semiconductor structure according to claim 5, characterized in that, The first gate layer and the second gate layer are symmetrically distributed on both sides of the first axis of symmetry.

7. The semiconductor structure according to claim 5, characterized in that, The first gate layer is symmetrical about the second axis of symmetry, and the second gate layer is symmetrical about the second axis of symmetry.

8. The semiconductor structure according to any one of claims 1-3, characterized in that, The first active region includes a first drain region and a second drain region located on both sides of the second gate portion. The second active region includes a third drain region and a fourth drain region located on both sides of the fourth gate portion. The portion of the third active region located between the second gate portion and the fourth gate portion serves as the source region.

9. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure includes a first transistor corresponding to the first drain region, a second transistor corresponding to the second drain region, a third transistor corresponding to the third drain region, and a fourth transistor corresponding to the fourth drain region; wherein... The first transistor, the second transistor, the third transistor, and the fourth transistor share the source region; The first transistor and the second transistor share the first gate layer; The third transistor and the fourth transistor share the second gate layer.

10. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure further includes a first gate dielectric layer and a second gate dielectric layer; wherein... The first gate dielectric layer is located between the first gate layer and the active layer; The second gate dielectric layer is located between the second gate layer and the active layer.

11. The semiconductor structure according to claim 10, characterized in that, The materials of the first gate dielectric layer and the second gate dielectric layer include high dielectric constant (High K) materials, and the materials of the first gate layer and the second gate layer include metals.

12. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure further includes a first contact located on the first drain region, a second contact located on the second drain region, a third contact located on the third drain region, a fourth contact located on the fourth drain region, a fifth contact located on the source region, a sixth contact located on the first gate portion, and a seventh contact located on the third gate portion.

13. The semiconductor structure according to claim 12, characterized in that, The first contact and the second contact are spaced apart from the first gate layer in the first direction by a first spacing, and the third contact and the fourth contact are spaced apart from the second gate layer in the first direction by a second spacing, wherein the first spacing is smaller than the second spacing.

14. The semiconductor structure according to any one of claims 1-3, characterized in that, The first direction is perpendicular to the second direction.

15. A semiconductor memory, characterized in that, Including the semiconductor structure according to any one of claims 1-14.

Images