Preparation method of semiconductor structure and semiconductor structure
By employing a specific etching process during DRAM manufacturing to form material layers with varying thicknesses and node contact holes, the air gap problem in the contact and conductive structures is solved, thereby improving conductivity and the overall structural reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- RUILI INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2024-11-19
- Publication Date
- 2026-05-19
AI Technical Summary
During DRAM manufacturing, as chip size shrinks, air gaps appear in the contact or conductive structures, leading to a decrease in conductivity.
A first material layer with gradually varying thickness is formed using a first etching process, and a fourth opening is formed below the third opening using a second etching process to form a node contact hole and prevent air gaps from forming.
It improves the conductivity of the conductive and contact structures, prevents the formation of air gaps, ensures the formation of the bonding structure, and enhances the overall performance of the semiconductor structure.
Smart Images
Figure CN122069706A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductors, and in particular to a method for preparing a semiconductor structure and the semiconductor structure thereof. Background Technology
[0002] In the manufacturing process of DRAM (Dynamic Random Access Memory), as chip size continues to shrink, the challenges of the process become increasingly significant, resulting in air gaps in the contact or conductive structures, which may lead to a deterioration in the performance of the conductive or contact structures. Summary of the Invention
[0003] This disclosure provides a method for preparing a semiconductor structure and the semiconductor structure thereof, which at least helps to solve the problem that air gaps in contact or conductive structures may lead to a deterioration in the performance of the conductive or contact structures.
[0004] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for fabricating a semiconductor structure, including:
[0005] Provide a base;
[0006] Bit line structures are formed on the substrate. The bit line structures extend along a first direction and are spaced apart along a second direction. The first direction is perpendicular to the second direction. There is a first opening between adjacent bit line structures.
[0007] A first initial material layer is formed, which covers the sidewalls and top of the bitline structure and the bottom of the first opening;
[0008] A first etching process is used to remove part of the first initial material layer to form a first material layer. The thickness of the first material layer gradually increases from the top of the bit line structure to the first position at a first rate, and gradually increases from the first position to the bottom of the first material layer at a second rate; the first rate is greater than the second rate.
[0009] A second material layer is formed, which covers the first material layer;
[0010] A first initial dielectric layer is formed, which fills the remaining first opening; a portion of the first initial dielectric layer is removed to form a second opening, and the remaining first initial dielectric layer serves as the first dielectric layer. The first dielectric layer and the second opening are located between adjacent bit line structures and are spaced apart along a first direction.
[0011] A second dielectric layer is formed, and the second dielectric layer fills the second opening;
[0012] The first dielectric layer is removed to form a third opening, the third opening being located between adjacent bit line structures, and the third opening being spaced apart from the second dielectric layer along a first direction;
[0013] The second etching process is used to etch using the third opening as a mask to remove the first and second material layers above the first position, and to form a fourth opening below the third opening. The third and fourth openings together constitute the node contact hole.
[0014] In some embodiments, the method further includes: forming a contact structure, an adhesive structure, and a conductive structure in a node contact hole, wherein the contact structure, adhesive structure, and conductive structure are arranged sequentially from bottom to top, and the contact structure at least fills the fourth opening.
[0015] In some embodiments, the second etching process is used to etch using the third opening as a mask, and further includes removing a portion of the second dielectric layer to form a rounded corner at the top of the second dielectric layer.
[0016] In some embodiments, the bit line structure includes a bit line conductive layer and a bit line cover layer, with the bit line cover layer located above the bit line conductive layer; a first location is near the top of the bit line cover layer.
[0017] In some embodiments, the height of the first position is h, the height of the bit line overlay is H, and 1 / 7H≤h≤2 / 5H.
[0018] In some embodiments, the etching gas in the first etching process is a mixture of fluoride, oxygen and argon; the first etching process is divided into two stages, with the etching power of the first stage being 400-800 watts and the etching frequency being 10-15 MHz, and the etching power of the second stage being 50-100 watts and the etching frequency being 1-3 MHz.
[0019] In some embodiments, removing the first material layer and the second material layer above the first position and forming a fourth opening below the third opening specifically includes: a first etching process and a second etching process; the first etching process removes the first material layer and the second material layer above the first position; the second etching process forms the fourth opening.
[0020] In some embodiments, the first etching process uses methyl fluoride and oxygen as etching gases, with an etching power of 550-650 watts and an etching frequency of 10-15 MHz.
[0021] In some embodiments, the second etching process uses hexafluorobutadiene, oxygen and argon as etching gases. The second etching process first uses an etching power of 550-650 watts and an etching frequency of 10-15 MHz; then it uses an etching power of 80-120 watts and an etching frequency of 1-3 MHz.
[0022] Another aspect of this disclosure provides a semiconductor structure, including: a substrate;
[0023] Bit line structures are formed on a substrate, the bit line structures extend along a first direction and are spaced along a second direction, the first direction being perpendicular to the second direction;
[0024] There is a third opening and a second dielectric layer between adjacent bit line structures, and the third opening and the second dielectric layer are spaced apart along a first direction;
[0025] The fourth opening is formed below the third opening, and the third and fourth openings together constitute the node contact hole;
[0026] A first material layer covers the sidewall of the bitline structure, and the first material layer extends from a first position of the bitline structure to the bottom of the bitline structure.
[0027] The second material layer covers the first material layer;
[0028] The bitline structure is not covered by the first material layer and the second material layer from the top to the first position.
[0029] In some embodiments, the system further includes a contact structure, an adhesive structure, and a conductive structure, wherein the contact structure, adhesive structure, and conductive structure are arranged sequentially from bottom to top within the node contact hole, and the contact structure at least fills the fourth opening.
[0030] In some embodiments, the top of the second dielectric layer has rounded corners.
[0031] In some embodiments, the bit line structure includes a bit line conductive layer and a bit line cover layer, with the bit line cover layer located above the bit line conductive layer; a first location is near the top of the bit line cover layer.
[0032] In some embodiments, the height of the first position is h, the height of the bit line overlay is H, and 1 / 7H≤h≤2 / 5H.
[0033] In some embodiments, the fourth opening is an inverted trapezoid.
[0034] The technical solution provided by the embodiments of this disclosure has at least the following advantages: by using a first etching process to remove part of the first initial material layer to form a first material layer, the thickness of the first material layer gradually increases from the top of the bit line structure to the first position at a first rate, and gradually increases from the first position to the bottom of the first material layer at a second rate; the first rate is greater than the second rate; by using a second etching process to remove the first material layer and the second material layer above the first position, and forming a fourth opening below the third opening, the third opening and the fourth opening together constitute a node contact hole; this makes the top opening of the node contact hole larger, which can prevent the generation of air gaps when subsequently filling to form a contact structure, bonding structure and conductive structure, and improve the conductivity of the conductive structure and the contact structure. Attached Figure Description
[0035] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0036] Figure 1 This is a schematic diagram of a semiconductor structure in one implementation method;
[0037] Figure 2 This is a schematic diagram of a semiconductor structure formation method in one embodiment of the present disclosure;
[0038] Figure 3 This is a top view of the semiconductor structure in an embodiment of this disclosure;
[0039] Figure 4A-18B This is a process flow diagram of the semiconductor structure formation method in the embodiments of this disclosure, wherein... Figure 4A , 5A 6A, 7A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A to Figure 18A It is along Figure 3 Sectional view along the B-B' direction; Figure 4B , 5B 6B, 7B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B to Figure 18B It is along Figure 3 Sectional view along the D-D' direction; Figure 8 for Figure 7A Enlarged view of the circled area; Figure 12C for Figure 12A A top-down view; Figure 13C for Figure 13A A top-down view; Figure 14C for Figure 14A A top-down view. Detailed Implementation
[0040] As is known from the background technology, in the manufacturing process of DRAM (Dynamic Random Access Memory), as chip size continues to shrink, the challenges in the process become increasingly significant, resulting in air gaps in the contact structure or conductive structure, which may lead to a deterioration in the performance of the conductive structure or contact structure.
[0041] This disclosure provides a method for fabricating a semiconductor structure. A first etching process is used to remove a portion of a first initial material layer to form a first material layer. The thickness of the first material layer gradually increases at a first rate from the top of the bitline structure to a first position, and at a second rate from the first position to the bottom of the first material layer; the first rate is greater than the second rate. A second material layer is formed, covering the first material layer. A second etching process is used to remove the first and second material layers above the first position, and a fourth opening is formed below a third opening. The third and fourth openings together constitute a node contact hole. This enlarges the top opening of the node contact hole, preventing air gaps during subsequent filling to form contact, bonding, and conductive structures, thereby improving the conductivity of the conductive and contact structures.
[0042] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.
[0043] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.
[0044] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.
[0045] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0046] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.
[0047] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.
[0048] Figure 1 This is a schematic diagram of a semiconductor structure in one implementation method; Figure 2 This is a schematic diagram of a semiconductor structure formation method in one embodiment of the present disclosure; Figure 3 This is a top view of the semiconductor structure in an embodiment of this disclosure; Figure 4A-18B This is a process flow diagram of the semiconductor structure formation method in the embodiments of this disclosure, wherein... Figure 4A , 5A 6A, 7A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A to Figure 18A It is along Figure 3 Sectional view along the B-B' direction; Figure 4B , 5B 6B, 7B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B to Figure 18B It is along Figure 3 Sectional view along the D-D' direction;
[0049] Figure 8 for Figure 7A Enlarged view of the circled area; Figure 12C for Figure 12A A top-down view; Figure 13C for Figure 13A A top-down view; Figure 14C for Figure 14A A top-down view.
[0050] refer to Figure 1 This is a schematic diagram of a semiconductor structure in one embodiment, including: a substrate 1, bit line structures 2 on the substrate 1, adjacent bit line structures 2 being filled by connecting structures 3, the connecting structures 3 including, from bottom to top, a contact structure 31, an adhesive structure 32, and a conductive structure 33, the adhesive structure 32 being located between the contact structure 31 and the conductive structure 33, and the conductive structure 33 also covering the top of the bit line structures 2. Air gaps 4 exist in the contact structures 31, and some air gaps 4 exist in both the contact structures 31 and the conductive structures 33. When air gaps 4 exist in the contact structures 31, they not only affect the conductivity of the contact structures 31, but also affect the formation of the adhesive structure 32, preventing the formation of the adhesive structure 32 that should have been formed between the contact structures 31 and the conductive structures 33, resulting in the disappearance of the adhesive structure 32, affecting the conductivity of both the contact structures 31 and the conductive structures 33, and also affecting the overall performance of the semiconductor structure. Figure 1The dashed circle indicates the location where the bonding structure 32 should have been generated but was not. The bonding structure 32 is generated by the reaction of the reacting gas with the contact structure 31. The reason why the bonding structure 32 disappears is mainly because the presence of the air gap 4 makes the surface of the contact structure 31 uneven, making the reaction difficult to proceed, and ultimately leading to the disappearance of the bonding structure 32.
[0051] To address the above problems, this disclosure provides a method for fabricating a semiconductor structure and the semiconductor structure itself. Please refer to [reference needed] for details. Figure 2-Figure 18B , Figure 2 This is a schematic diagram of a semiconductor structure formation method in one embodiment of the present disclosure; Figure 3 This is a top view of the semiconductor structure in an embodiment of this disclosure.
[0052] refer to Figure 1 , Figure 1 A method for fabricating a semiconductor structure specifically includes: step S10 providing a substrate; step S20 forming bit line structures on the substrate, the bit line structures extending along a first direction and spaced apart along a second direction, the first direction being perpendicular to the second direction, and adjacent bit line structures having a first opening; step S30 forming a first initial material layer, the first initial material layer covering the sidewalls and top of the bit line structures and covering the bottom of the first opening; step S40 removing a portion of the first initial material layer using a first etching process to form a first material layer, the thickness of the first material layer gradually increasing from the top of the bit line structure to a first position at a first rate, and gradually increasing from the first position to the bottom of the first material layer at a second rate; the first rate being greater than the second rate; and step S50 forming a second material layer, the second material layer covering the first material layer. Step S60: A first initial dielectric layer is formed, which fills the remaining first opening; a portion of the first initial dielectric layer is removed to form a second opening, and the remaining first initial dielectric layer serves as the first dielectric layer. The first dielectric layer and the second opening are located between adjacent bit line structures and are spaced apart along the first direction. Step S70: A second dielectric layer is formed, which fills the second opening. Step S80: The first dielectric layer is removed to form a third opening, which is located between adjacent bit line structures and is spaced apart from the second dielectric layer along the first direction. Step S90: A second etching process is used with the third opening as a mask to etch, thereby removing the first material layer and the second material layer above the first position, and forming a fourth opening below the third opening. The third opening and the fourth opening together constitute a node contact hole.
[0053] Figure 3 This is a top view of the semiconductor structure in an embodiment of this disclosure, with reference to... Figure 3For ease of subsequent description, a top view of a semiconductor structure is provided here, including an active region 102, which extends along a certain inclined direction. Multiple active regions 102 are spaced apart along the extension direction and perpendicular to the extension direction. The blank area between adjacent active regions 102 is an isolation structure (not shown in the figure). A word line structure 104 passes through multiple active regions 102 and extends along a second direction Y. Adjacent word line structures 104 are spaced apart along a first direction X. A bit line structure 20 extends along the first direction X. Multiple bit line structures 20 are spaced apart along the second direction Y.
[0054] Figure 4A-18B This is a process flow diagram of the semiconductor structure formation method in the embodiments of this disclosure, wherein... Figure 4A , 5A 6A, 7A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A to Figure 18A It is along Figure 3 Sectional view along the B-B' direction; Figure 4B , 5B 6B, 7B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B to Figure 18B It is along Figure 3 Sectional view along the D-D' direction; Figure 12C for Figure 12A A top-down view; Figure 13C for Figure 13A A top-down view; Figure 14C for Figure 14A A top-down view.
[0055] This application provides a method for fabricating a semiconductor structure, comprising: providing a substrate 10; forming bit line structures 20 on the substrate 10, the bit line structures 20 extending along a first direction X and spaced apart along a second direction Y, the first direction X being perpendicular to the second direction Y, and a first opening 301 between adjacent bit line structures 20; forming a first initial material layer 401', the first initial material layer 401' covering the sidewalls and top of the bit line structures 20 and covering the bottom of the first opening 301; removing a portion of the first initial material layer 401' using a first etching process to form a first material layer 401, the thickness of the first material layer 401 gradually increasing at a first rate from the top of the bit line structure 20 to a first position P1, and gradually increasing at a second rate from the first position P1 to the bottom of the first material layer 401; the first rate being greater than the second rate; forming a second material layer 402, the second material layer 402 covering the first material layer 401; forming a first initial dielectric layer 501', the second initial material layer 402 covering the first material layer 401; and forming a first initial dielectric layer 501'. An initial dielectric layer 501' fills the remaining first opening 301; a portion of the first initial dielectric layer 501' is removed to form a second opening 302, and the remaining first initial dielectric layer 501' serves as the first dielectric layer 501. The first dielectric layer 501 and the second opening 302 are located between adjacent bit line structures 20 and are spaced apart along the first direction X; a second dielectric layer 502 is formed, and the second dielectric layer 502 fills the second opening 302; the first dielectric layer 501 is removed to form a third opening 303, and the third opening 303 is located between adjacent bit line structures 20, and the third opening 303 and the second dielectric layer 502 are spaced apart along the first direction X; a second etching process is used with the third opening 303 as a mask to etch, so as to remove the first material layer 401 and the second material layer 402 above the first position P1, and a fourth opening 304 is formed below the third opening 303. The third opening 303 and the fourth opening 304 together constitute the node contact hole 30.
[0056] Please refer to the details. Figure 4A and 4B A method for forming a semiconductor structure includes: providing a substrate 10; the substrate 10 includes isolation structures 101, and an active region 102 is provided between adjacent isolation structures 101, such as... Figure 4B The substrate also includes word line structures 104 extending along a second direction Y, with adjacent word line structures 104 spaced apart along a first direction X. Bit line structures 20 are formed on the substrate 10, extending along the first direction X and spaced apart along the second direction Y. The bit line structures 20 have a certain height in a third direction Z. The first direction X is perpendicular to the second direction Y, and a first opening 301 exists between adjacent bit line structures 20. In some embodiments, the bit line structure 20 includes a bit line conductive layer 201 and a bit line cover layer 202, with the bit line cover layer 202 located above the bit line conductive layer 201.
[0057] Please refer to the following: Figure 6Aand 6B A first initial material layer 401' is formed, which covers the sidewalls and top of the bit line structure 20 and the bottom of the first opening 301.
[0058] In some embodiments, please refer to Figure 5A and 5B Before forming the first initial material layer 401', the process further includes forming a first protective layer M1, which covers the sidewalls and top of the bitline structure 20 and the bottom of the first opening 301. The first initial material layer 401' covers the protective layer M1.
[0059] Please refer to the following: Figure 7A and 7B A first etching process is used to remove a portion of the first initial material layer 401' to form a first material layer 401. The thickness of the first material layer 401 gradually increases at a first rate from the top of the bit line structure 20 to the first position P1, and at a second rate from the first position P1 to the bottom of the first material layer 401; the first rate is greater than the second rate. Specifically, as shown... Figure 8 , Figure 8 for Figure 7A The enlarged view of the circled portion shows that the first material layer 401 covers the top and sidewalls of the bitline structure 20. The thickness of the first material layer 401 on the sidewalls of the bitline structure 20 gradually increases from the top of the bitline structure 20 to the first position P1, with an increase rate of 1 / 7H ≤ h ≤ 2 / 5H. The thickness of the first material layer 401 also gradually increases from the first position P1 to the bottom of the first material layer 401, with an increase rate of 2 / 2. The first rate is greater than the second rate. It should be noted that the thickness here refers to the distance along the Y direction. The bitline structure 20 includes a bitline conductive layer 201 and a bitline cover layer 202. The bitline cover layer 202 is located above the bitline conductive layer 201. The first position P1 is close to the top of the bitline cover layer 202. In a specific embodiment, the height of the first position P1 is h, and the height of the bitline cover layer 202 is H, where 1 / 7H ≤ h ≤ 2 / 5H. The height h mentioned here refers to the distance from the top of the bitline cover layer 202 to the first position P1.
[0060] In one specific embodiment, a first etching process is used to remove a portion of the first initial material layer 401' to form the first material layer 401. The etching gas in the first etching process is a mixture of fluoride, oxygen, and argon; wherein the fluoride can be carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), or mixtures thereof. The first etching process consists of two stages: the etching power of the first stage is 400-800 watts, and the etching frequency is 10-15 MHz; the etching power of the second stage is 50-100 watts, and the etching frequency is 1-3 MHz. The etching power and etching frequency of the first stage are both greater than those of the second stage.
[0061] During the etching process, etching power and etching frequency are two key parameters. Etching power primarily affects the energy and density of particles in the plasma. Higher power means more energy is input into the plasma, which increases the average energy of particles (ions, electrons, free radicals, etc.) in the plasma, thereby increasing their reaction rate with the wafer surface material. Etching frequency mainly affects the generation and distribution of plasma, as well as the movement of particles in the plasma. Etching frequencies are further divided into low-frequency and high-frequency. Low-frequency etching can provide higher ion energy, which helps to enhance the etching capability of the plasma in the vertical direction. For etching the sidewalls of trenches with high aspect ratios, low-frequency etching can provide better anisotropic control, i.e., enhance the etching of the upper film layer. High-frequency plasma etching can produce a more uniform plasma distribution, which is crucial for maintaining the anisotropy and uniformity of the etching. In this application, the first stage employs a relatively high etching power and etching frequency to remove the first initial material layer 401' relatively uniformly from top to bottom. However, due to the large depth-to-width ratio of the first opening 301, the energy and density of the plasma at the bottom of the first opening 301 will inevitably be lower than at the top, resulting in relatively more removal at the top and relatively less removal at the bottom of the first initial material layer 401'. In the next stage, a relatively lower etching power and etching frequency are used, resulting in higher ion energy in the plasma near the top of the first opening 301, strengthening the anisotropic etching capability, and further reducing the removal of the plasma near the top of the first opening 301. The first initial material layers 401' on both sides are further removed to create a platform with a rapid thickness change on both sides of the top of the first opening 301. This means that the thickness change of the first material layers 401 above and below the first position P1 is significantly different. The rate of thickness change from the top of the bitline structure 20 to the first position P1 is the first rate, and the rate of thickness change from the first position P1 to the bottom of the first material layer 401 is the second rate. The first rate is greater than the second rate, resulting in a larger top opening between adjacent first material layers 401, providing more space for subsequent filling material and preventing air gaps. In one specific embodiment, the first rate is 3-6 times the second rate.
[0062] Please continue reading. Figure 9A and 9B A second material layer 402 is formed, which covers the first material layer 401. In a specific embodiment, the first protective layer M1, the first material layer 401, and the second material layer 402 together constitute the protective layer of the bit line structure 20. The material of the first protective layer M1 can be silicon nitride (SiN) or silicon oxynitride (SiON), the material of the first material layer 401 can be silicon oxide (SiO2), and the material of the second material layer 402 can be silicon nitride (SiN) or silicon oxynitride (SiON).
[0063] Please continue reading. Figures 10A to 12CA first initial dielectric layer 501' is formed, and the first initial dielectric layer 501' fills the remaining first opening 301; a portion of the first initial dielectric layer 501' is removed to form a second opening 302, and the remaining first initial dielectric layer 501' serves as the first dielectric layer 501. The first dielectric layer 501 and the second opening 302 are located between adjacent bit line structures 20 and are spaced apart along the first direction X.
[0064] Please refer to 10A and 10B for details. First, a first initial dielectric layer 501' is formed. The first initial dielectric layer 501' fills the remaining first opening 301, as shown below. Figure 10A As shown, the first initial dielectric layer 501' also covers the top of the second material layer 402. Then, as... Figure 11A and 11B As shown, chemical mechanical polishing is used to remove part of the first initial dielectric layer 501' to expose the top of the second material layer 402. Then, as... Figure 12A and 12C As shown, a portion of the first initial dielectric layer 501' is then removed to form the second opening 302. The remaining first initial dielectric layer 501' serves as the first dielectric layer 501. The first dielectric layer 501 and the second opening 302 are located between adjacent bit line structures 20 and are spaced apart along the first direction X. It should be noted that Figure 12C yes Figure 12A A top-down view diagram, for clearer illustration. Figure 12C Only the bit line structure 20 is shown, and the second material layer 402 covering the bit line structure 20 is not shown.
[0065] Please continue reading. Figures 13A to 13C A second dielectric layer 502 is formed, which fills the second opening 302; along the BB' direction Figure 13A and Figure 12A There is no difference, but in the DD' direction, the second dielectric layer 502 fills the second opening 302, such as... Figure 13C As shown in the top view, the bit line structure 20 extends along the first direction X, and the first dielectric layer 501 and the second dielectric layer 502 are located between the two bit line structures 20, with the first dielectric layer 501 and the second dielectric layer 502 spaced apart from each other. Figure 13C As shown, it presents a checkerboard pattern, with multiple first dielectric layers 501 spaced apart from the bit line structure 20 along the Y direction, and multiple second dielectric layers 502 also spaced apart from the bit line structure 20.
[0066] Please continue reading. Figures 14A to 14C The first dielectric layer 501 is removed to form a third opening 303. The third opening 303 is located between adjacent bit line structures 20, and the third opening 303 and the second dielectric layer 502 are spaced apart along the first direction X.
[0067] Please continue reading. Figures 15A to 17B The second etching process uses the third opening 303 as a mask to etch away the first material layer 401 and the second material layer 402 above the first position P1, forming a fourth opening 304 below the third opening 303. The third opening 303 and the fourth opening 304 together constitute the node contact hole 30. The removal of the first material layer 401 and the second material layer 402 above the first position P1 and the formation of the fourth opening 304 below the third opening 303 specifically includes: a first etching process and a second etching process; the first etching process removes the first material layer 401 and the second material layer 402 above the first position P1; the second etching process forms the fourth opening 304.
[0068] Please refer to the details. Figure 15A and 15B First, the first material layer 401 above the first position P1 is removed. During the removal of the first material layer 401 above the first position P1, part of the second dielectric layer 502 is also removed, so that the top of the second dielectric layer 502 forms a rounded corner. The rounded corner of the top of the second dielectric layer 502 makes the top opening between adjacent second dielectric layers 502 larger, making subsequent filling easier and further preventing the formation of air gaps.
[0069] Please refer to the following: Figure 16A and 16B The second material layer 402 above the first position P1 is then removed, ensuring that both the first material layer 401 and the second material layer 402 above the first position P1 are completely removed. At this point, the top opening between adjacent bit line structures 20 is further enlarged, further ensuring subsequent filling and preventing the formation of air gaps. As described above, the first material layer 401 and the second material layer 402 above the first position P1 are removed primarily through the first etching process. The first etching process uses methyl fluoride and oxygen as etching gases, with an etching power of 550-650 watts and an etching frequency of 10-15 MHz.
[0070] Please refer to the following: Figure 17A and 17BUsing the third opening 303 as a mask, the substrate 10 is etched further to form the fourth opening 304. The fourth opening 304 extends into the substrate 10 and is located below the third opening 303. The third opening 303 and the fourth opening 304 together constitute the node contact hole 30. As described above, the fourth opening 304 is mainly formed through a second etching process. The second etching process uses hexafluorobutadiene, oxygen, and argon as etching gases. The second etching process first uses an etching power of 550-650 watts and an etching frequency of 10-15 MHz; then it uses an etching power of 80-120 watts and an etching frequency of 1-3 MHz. The formation of the fourth opening 304 increases the contact area between the subsequently formed contact structure and the active region 102, improving the performance of the semiconductor structure.
[0071] Please continue reading. Figure 18A and 18B A contact structure 601, an adhesive structure 602, and a conductive structure 603 are formed in the node contact hole 30, arranged sequentially from bottom to top. The contact structure 601 at least fills the fourth opening 304. The contact structure 601 is used to electrically connect with the active region 102, and the conductive structure 603 is used to electrically connect with the subsequently formed capacitor structure. Since the adhesion between the contact structure 601 and the conductive structure 603 is poor, the adhesive structure 602 is used to improve the adhesion performance between the contact structure 601 and the conductive structure 603. In a specific embodiment, the contact structure 601 can be polycrystalline silicon, the adhesive structure 602 can be cobalt silicide or nickel silicide, and the conductive structure 603 can be titanium nitride or tungsten, or a stack of titanium nitride and tungsten. No air gaps are generated in the contact structure 601, bonding structure 602 and conductive structure 603 prepared by this application. That is, this application can prevent the bonding structure 602 from failing to form due to the presence of air gaps, thereby improving the conductivity of the contact structure 31 and conductive structure 33 and improving the overall performance of the semiconductor structure.
[0072] This application employs a first etching process to remove a portion of the first initial material layer to form a first material layer. The thickness of the first material layer gradually increases from the top of the bitline structure to the first position at a first rate, and gradually increases from the first position to the bottom at a second rate, with the first rate being greater than the second rate. A second material layer is then formed, covering the first material layer. A second etching process is then used to remove the first and second material layers above the first position, and a fourth opening is formed below the third opening. The third and fourth openings together constitute a node contact hole. This enlarges the top opening of the node contact hole, preventing the formation of air gaps during subsequent filling to form contact, bonding, and conductive structures, thereby improving the conductivity of the conductive and contact structures.
[0073] Another embodiment of this disclosure also provides a semiconductor structure; please refer to [reference needed] for details. Figures 17A to 18B A semiconductor structure includes: a substrate 10; bit line structures 20 formed on the substrate 10, the bit line structures 20 extending along a first direction X and spaced apart along a second direction Y, the first direction being perpendicular to the second direction Y; a third opening 303 and a second dielectric layer 502 between adjacent bit line structures 20, the third opening 303 and the second dielectric layer 502 being spaced apart along the first direction X; a fourth opening 304 formed below the third opening 303, the third opening 303 and the fourth opening 304 together forming a node contact hole 30, the fourth opening 304 being an inverted trapezoid; a first material layer 401 covering the sidewalls of the bit line structures 20, the first material layer 401 extending from a first position P1 of the bit line structures 20 to the bottom of the bit line structures 20; a second material layer 402 covering the first material layer 401; the bit line structures 20 from the top to the first position P1 are not covered by the first material layer 401 and the second material layer 402. Contact structure 601, adhesive structure 602, and conductive structure 603 are sequentially arranged from bottom to top within the node contact hole 30, with contact structure 601 at least filling the fourth opening 304. The top of the second dielectric layer 502 has rounded corners. The bit line structure 20 includes a bit line conductive layer 201 and a bit line cover layer 202, with the bit line cover layer 202 located above the bit line conductive layer 201. A first position P1 is close to the top of the bit line cover layer 202, and the height of the first position is h, where h refers to the distance from the top of the bit line cover layer 202 to the first position P1. The height of the bit line cover layer is H, where H refers to the distance from the first position P1 to the bottom of the bit line cover layer 202, where 1 / 7H ≤ h ≤ 2 / 5H.
[0074] In the semiconductor structure of this application, since the bit line structure 20 is not covered by the first material layer 401 and the second material layer 402 from the top to the first position P1, and the top of the second dielectric layer 502 is rounded, the top opening between adjacent bit line structures 20 is relatively large. This prevents the formation of air gaps during the filling and formation of the contact structure 601. Without air gaps, the bonding structure 602 is easier to form, preventing the bonding structure 602 from disappearing. The function of the bonding structure 602 is to improve the adhesion performance between the contact structure 601 and the conductive structure 603. The easier formation of the bonding structure 602 ensures the adhesion performance between the contact structure 601 and the conductive structure 603. Furthermore, the conductive structure 603 is formed on the bonding structure 602, and there are no air gaps in the conductive structure 603, which improves the conductivity of both the conductive structure 603 and the contact structure 601, further improving the performance of the entire semiconductor device.
[0075] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; A bit line structure is formed on the substrate. The bit line structure extends along a first direction and is spaced apart along a second direction. The first direction is perpendicular to the second direction. A first opening is provided between adjacent bit line structures. A first initial material layer is formed, which covers the sidewalls and top of the bitline structure and the bottom of the first opening; A first etching process is used to remove part of the first initial material layer to form a first material layer. The thickness of the first material layer gradually increases from the top of the bit line structure to a first position at a first rate, and gradually increases from the first position to the bottom of the first material layer at a second rate; the first rate is greater than the second rate. A second material layer is formed, which covers the first material layer; A first initial dielectric layer is formed, which fills the remaining first opening; a portion of the first initial dielectric layer is removed to form a second opening, and the remaining first initial dielectric layer serves as the first dielectric layer. The first dielectric layer and the second opening are located between adjacent bit line structures and are spaced apart along the first direction. A second dielectric layer is formed, which fills the second opening; The first dielectric layer is removed to form a third opening, the third opening being located between adjacent bit line structures and spaced apart from the second dielectric layer along the first direction; A second etching process is used to etch the third opening as a mask to remove the first material layer and the second material layer above the first position, and to form a fourth opening below the third opening. The third opening and the fourth opening together constitute a node contact hole.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Also includes: A contact structure, an adhesive structure, and a conductive structure are formed in the node contact hole, wherein the contact structure, the adhesive structure, and the conductive structure are arranged sequentially from bottom to top, and the contact structure at least fills the fourth opening.
3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The second etching process, using the third opening as a mask, further includes removing a portion of the second dielectric layer to form a rounded corner at the top of the second dielectric layer.
4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The bit line structure includes a bit line conductive layer and a bit line cover layer, with the bit line cover layer located above the bit line conductive layer; the first position is close to the top of the bit line cover layer.
5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The height of the first position is h, and the height of the bit line overlay layer is H.
6. The method for preparing a semiconductor structure according to any one of claims 1-5, characterized in that, The etching gas in the first etching process is a mixture of fluoride, oxygen and argon. The first etching process is divided into two stages: the etching power of the first stage is 400-800 watts and the etching frequency is 10-15 MHz; the etching power of the second stage is 50-100 watts and the etching frequency is 1-3 MHz.
7. The method for preparing a semiconductor structure according to any one of claims 1-5, characterized in that, Removing the first material layer and the second material layer above the first position and forming the fourth opening below the third opening specifically includes: a first etching process and a second etching process; the first etching process removes the first material layer and the second material layer above the first position; the second etching process forms the fourth opening.
8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The first etching process uses methyl fluoride and oxygen as etching gases, with an etching power of 550-650 watts and an etching frequency of 10-15 MHz.
9. The method for preparing a semiconductor structure according to claim 7, characterized in that, The second etching process uses hexafluorobutadiene, oxygen and argon as etching gases. The second etching process first uses an etching power of 550-650 watts and an etching frequency of 10-15 MHz; then it uses an etching power of 80-120 watts and an etching frequency of 1-3 MHz.
10. A semiconductor structure, characterized in that, include: Base; Bit line structures are formed on the substrate, the bit line structures extending along a first direction and spaced along a second direction, the first direction being perpendicular to the second direction; A third opening and a second dielectric layer are provided between adjacent bit line structures, and the third opening and the second dielectric layer are spaced apart along the first direction; A fourth opening is formed below the third opening, and the third and fourth openings together constitute a node contact hole; A first material layer covers the sidewall of the bit line structure, and the first material layer extends from a first position of the bit line structure to the bottom of the bit line structure. A second material layer covers the first material layer; The bitline structure is not covered by the first material layer and the second material layer from the top to the first position.
11. The semiconductor structure according to claim 10, characterized in that, Also includes: The contact structure, the adhesive structure, and the conductive structure are arranged sequentially from bottom to top within the node contact hole, and the contact structure at least fills the fourth opening.
12. The semiconductor structure according to claim 10, characterized in that, The top of the second dielectric layer has rounded corners.
13. The semiconductor structure according to claim 10, characterized in that, The bit line structure includes a bit line conductive layer and a bit line cover layer, with the bit line cover layer located above the bit line conductive layer; the first position is close to the top of the bit line cover layer.
14. The semiconductor structure according to claim 13, characterized in that, The height of the first position is h, the height of the bit line overlay layer is H, and 1 / 7H≤h≤2 / 5H.
15. The semiconductor structure according to claim 10, characterized in that, The fourth opening is an inverted trapezoid.