Operational amplifier circuit

Abstract

Embodiments of the present disclosure provide an operational amplifier circuit, which includes a current source circuit, first and second input circuits, first and second voltage control circuits, a current mirror circuit, and an output circuit. The current source circuit distributes a constant current to the first and second input circuits and the second voltage control circuit. The first input circuit generates and provides a first current signal to the first voltage control circuit. The first voltage control circuit passes the first current signal to the current mirror circuit and controls a voltage of a third node according to a voltage of a second node. The current mirror circuit generates and distributes a mirror signal of the first current signal to the second voltage control circuit and the output circuit. The second voltage control circuit controls the voltage of the second node according to a voltage of a fourth node such that the voltages of the third and fourth nodes are equal. The second input circuit generates and provides a second current signal to the output circuit. The output circuit generates an output signal according to the distributed mirror signal and the second current signal.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to operational amplifier circuits. Background Technology

[0002] Cascode amplifiers are widely used in integrated circuits. A cascode amplifier circuit can include two structures: a common-source structure and a common-gate structure. The common-source structure consists of two transistors connected at their sources, while the common-gate structure consists of two transistors connected at their gates. Cascading common-source and common-gate structures together constitute the cascode amplifier circuit. Cascode amplifier circuits feature high bandwidth, high gain, and high output impedance, and can be used to improve the performance of integrated circuits. Summary of the Invention

[0003] The embodiments described herein provide an operational amplifier circuit.

[0004] According to a first aspect of this disclosure, an operational amplifier circuit is provided. The operational amplifier circuit includes: a current source circuit, a first input circuit, a second input circuit, a first voltage control circuit, a second voltage control circuit, a current mirror circuit, and an output circuit. The current source circuit is configured to distribute a constant current to the first input circuit, the second voltage control circuit, and the second input circuit. The first input circuit is configured to generate a first current signal based on a first input signal from a first input terminal and provide the first current signal to the first voltage control circuit via a first node. The first voltage control circuit is coupled to the second voltage control circuit via a second node and is configured to transmit the first current signal to the current mirror circuit via a third node and control the voltage of the third node based on the voltage of the second node. The current mirror circuit is configured to generate a mirror signal of the first current signal and distribute the mirror signal to the second voltage control circuit and the output circuit via a fourth node. The second voltage control circuit is configured to control the voltage of the second node based on the voltage of the fourth node such that the voltage of the third node is equal to the voltage of the fourth node. The second input circuit is configured to generate a second current signal based on a second input signal from a second input terminal and provide the second current signal to the output circuit. The output circuit is configured to generate an output signal based on the assigned mirror signal and the second current signal, and output the output signal from the signal output terminal.

[0005] In some embodiments of this disclosure, the ratio of the constant current distributed by the current source circuit to the first input circuit, the second voltage control circuit, and the second input circuit is (N+a):a:N. Where a is less than or equal to N.

[0006] In some embodiments of this disclosure, a equals 1 and N is greater than 1.

[0007] In some embodiments of this disclosure, the first voltage control circuit includes a first transistor. The control electrode of the first transistor is coupled to a second node. The first electrode of the first transistor is coupled to a third node. The second electrode of the first transistor is coupled to a first node.

[0008] In some embodiments of this disclosure, the current mirror circuit includes a second transistor and a third transistor. The control electrode of the second transistor is coupled to the control electrode of the third transistor and a first node. The first electrode of the second transistor is coupled to the first electrode of the third transistor and a first voltage terminal. The second electrode of the second transistor is coupled to a third node. The second electrode of the third transistor is coupled to a fourth node.

[0009] In some embodiments of this disclosure, the second voltage control circuit includes a fourth transistor and a fifth transistor. The control electrode of the fourth transistor is coupled to the second node and the second terminal of the fourth transistor. The first terminal of the fourth transistor is coupled to the fourth node. The control electrode of the fifth transistor is coupled to the second input terminal. The first terminal of the fifth transistor is coupled to the output terminal of the current source circuit. The second terminal of the fifth transistor is coupled to the second terminal of the fourth transistor.

[0010] In some embodiments of this disclosure, the second voltage control circuit further includes a sixth transistor and a seventh transistor. The control electrode of the sixth transistor is coupled to the control electrode of the fourth transistor and the second electrode of the sixth transistor. The first electrode of the sixth transistor is coupled to the fourth node. The control electrode of the seventh transistor is coupled to the second input terminal. The first electrode of the seventh transistor is coupled to the output terminal of the current source circuit. The second electrode of the seventh transistor is coupled to the second electrode of the sixth transistor.

[0011] In some embodiments of this disclosure, the output circuit includes an eighth transistor. The control electrode of the eighth transistor is coupled to a bias voltage terminal. The first electrode of the eighth transistor is coupled to a fourth node. The second electrode of the eighth transistor is coupled to a signal output terminal.

[0012] According to a second aspect of this disclosure, an operational amplifier circuit is provided. The operational amplifier circuit includes: a first to a fifth transistor, an eighth to a tenth transistor, and a current source circuit. The control electrode of the first transistor is coupled to the control electrode and the second electrode of the fourth transistor. The first electrode of the first transistor is coupled to the second electrode of the second transistor. The second electrode of the first transistor is coupled to the control electrode of the second transistor, the control electrode of the third transistor, and the second electrode of the ninth transistor. The first electrode of the second transistor is coupled to the first electrode of the third transistor and a first voltage terminal. The second electrode of the third transistor is coupled to the first electrode of the fourth transistor and the first electrode of the eighth transistor. The second electrode of the fourth transistor is coupled to the second electrode of the fifth transistor. The control electrode of the fifth transistor is coupled to a second input terminal. The first electrode of the fifth transistor is coupled to the output terminal of the current source circuit. The control electrode of the eighth transistor is coupled to a bias voltage terminal. The second electrode of the eighth transistor is coupled to a signal output terminal. The control electrode of the ninth transistor is coupled to a first input terminal. The first electrode of the ninth transistor is coupled to the output terminal of the current source circuit. The control electrode of the tenth transistor is coupled to a second input terminal. The first electrode of the tenth transistor is coupled to the output terminal of the current source circuit. The second electrode of the tenth transistor is coupled to the signal output terminal. The current source circuit is configured to distribute a constant current to the ninth, fifth, and tenth transistors.

[0013] In some embodiments of this disclosure, the aspect ratio of the ninth transistor: the aspect ratio of the fifth transistor: the aspect ratio of the tenth transistor is equal to (N+a):a:N. And the aspect ratio of the first transistor: the aspect ratio of the fourth transistor: the aspect ratio of the eighth transistor is equal to (N+a):a:N. Where a is less than or equal to N.

[0014] In some embodiments of this disclosure, a equals 1 and N is greater than 1.

[0015] In some embodiments of this disclosure, the operational amplifier circuit further includes a sixth transistor and a seventh transistor. The control electrode of the sixth transistor is coupled to the second electrode of both the fourth and sixth transistors. The first electrode of the sixth transistor is coupled to the first electrode of the fourth transistor. The control electrode of the seventh transistor is coupled to a second input terminal. The first electrode of the seventh transistor is coupled to the output terminal of a current source circuit. The second electrode of the seventh transistor is coupled to the second electrode of the sixth transistor. The current source circuit is further configured to distribute a constant current to the seventh transistor. The aspect ratio of the ninth transistor: aspect ratio of the fifth transistor: aspect ratio of the seventh transistor: aspect ratio of the tenth transistor is equal to (N+a):a:b:(Nb). Furthermore, the aspect ratio of the first transistor: aspect ratio of the fourth transistor: aspect ratio of the sixth transistor: aspect ratio of the eighth transistor is equal to (N+a):a:b:(Nb). Where a is less than or equal to N, and b is less than N.

[0016] In some embodiments of this disclosure, a equals 1, b equals 1, and N is greater than 2. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0018] Figure 1 This is an exemplary circuit diagram of an operational amplifier circuit;

[0019] Figure 2 This is a schematic block diagram of an operational amplifier circuit according to an embodiment of the present disclosure;

[0020] Figure 3 This is an exemplary circuit diagram of an operational amplifier circuit according to embodiments of the present disclosure; and

[0021] Figure 4 This is another exemplary circuit diagram of an operational amplifier circuit according to an embodiment of the present disclosure.

[0022] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0025] In all embodiments of this disclosure, since the source and drain (emitter and collector) of the transistor are symmetrical, and the conduction current directions between the source and drain (emitter and collector) of N-type and P-type transistors are opposite, the controlled middle terminal of the transistor is referred to as the control terminal, and the remaining two terminals of the transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily MOS (Metal Oxide Semiconductor) transistors. Furthermore, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0026] Figure 1 An exemplary circuit diagram of an operational amplifier circuit 100 is shown. The operational amplifier circuit 100 may include eleventh transistor M11 through sixteenth transistor M16, and a current source I. L Among them, transistors eleven through fourteen (M14) are PMOS transistors, while transistors fifteen (M15) and sixteenth (M16) are NMOS transistors. The aspect ratio of transistor fifteen (M15) is equal to that of transistor sixteen (M16). The aspect ratio of transistor twelfth (M12) is equal to that of transistor fourteenth (M14). The aspect ratio of transistor eleventh (M11) is equal to that of transistor thirteenth (M13).

[0027] Transistors M11 through M14 form a common-source, common-gate amplifier, also known as a cascode amplifier. Transistors M11 and M13 form the common-source structure of the cascode amplifier, while transistors M12 and M14 form the common-gate structure.

[0028] The gate of the fifteenth transistor M15 is coupled to the first signal input terminal INP, and the gate of the sixteenth transistor M16 is coupled to the second signal input terminal INN. The fifteenth transistor M15 generates a first current signal I based on the first input signal input from the first signal input terminal INP. 11 First current signal I 11 It is supplied to the twelfth transistor M12 and the eleventh transistor M11. The first current signal I is generated by the load current mirror circuit composed of the eleventh transistor M11 and the thirteenth transistor M13. 11 The mirror current signal I 11 The generated mirror current signal I 11 The signal is supplied to the fourteenth transistor M14. The sixteenth transistor M16 generates the second current signal I based on the second input signal input from the second signal input terminal INN. 12The drains of the fourteenth transistor M14 and the sixteenth transistor M16 are jointly coupled to the signal output terminal Vo of the operational amplifier circuit 100. A voltage signal is output from the signal output terminal Vo. The amplitude of this voltage signal is determined by the mirror current signal I. 11 ' and second current signal I 12 To determine.

[0029] During static operation, the first current signal I 11 and mirror current signal I 11 The values ​​of ' are equal, V GS_M12 =V GS_M14 ,|V DS_M11 |=VDD+V GS_M12 -Vbp,|V DS_M13 |=VDD+V GS_M14 -Vbp,|V DS_M11 |=|V DS_M13 | where VDD represents the power supply voltage, Vbp represents the voltage at the bias voltage terminal bp, and V GS_M12 V represents the gate-source voltage of the twelfth transistor M12. GS_M14 V represents the gate-source voltage of the fourteenth transistor M14. DS_M11 V represents the drain-source voltage of the eleventh transistor M11. DS_M13 This represents the drain-source voltage of the thirteenth transistor, M13.

[0030] During static operation, there is no AC signal input at the first signal input terminal INP and the second signal input terminal INN, and the current source I... L Current is distributed according to the width-to-length ratio of the fifteenth transistor M15 and the sixteenth transistor M16. The gates of the twelfth transistor M12 and the fourteenth transistor M14 are coupled to the bias voltage terminal bp, and the gate voltages of the twelfth transistor M12 and the fourteenth transistor M14 remain constant. If the voltage output at the signal output terminal Vo increases to Vo > Vbp - V GS_M12 Then |V DS_M13 | is approximately equal to VDD-Vo, while |V DS_M11 | Remains unchanged, therefore |V DS_M11 | and | V DS_M13 The pressure difference between |V increases,|V DS_M11 | and | V DS_M13 They cannot remain nearly equal, thus making the first current signal I... 11 and mirror current signal I 11 The values ​​of ' are no longer equal, causing a large system offset, which increases the equivalent input offset of the op-amp and reduces the accuracy of the output voltage.

[0031] Embodiments of this disclosure present an operational amplifier circuit. Figure 2A schematic block diagram of an operational amplifier circuit 200 according to an embodiment of the present disclosure is shown. Figure 2 As shown, the operational amplifier circuit 200 may include: a current source circuit 210, a first input circuit 220, a second input circuit 230, a first voltage control circuit 240, a second voltage control circuit 250, a current mirror circuit 260, and an output circuit 270.

[0032] The current source circuit 210 can be coupled to the first input circuit 220, the second input circuit 230, the second voltage control circuit 250, and the second voltage terminal V2. The current source circuit 210 can be configured to distribute a constant current to the first input circuit 220, the second voltage control circuit 240, and the second input circuit 230. The ratio of the constant current distributed by the current source circuit 210 to the first input circuit 220, the second voltage control circuit 250, and the second input circuit 230 is (N+a):a:N, where a is less than or equal to N. In one example, a equals 1, and N is greater than 1.

[0033] The first input circuit 220 can be coupled to the current source circuit 210, the first voltage control circuit 240, and the first input terminal INP. The first input circuit 220 can be configured to generate a first current signal I1 based on a first input signal from the first input terminal INP, and provide the first current signal I1 to the first voltage control circuit 240 via the first node N1.

[0034] The first voltage control circuit 240 can be coupled to the first input circuit 220, the second voltage control circuit 250, and the current mirror circuit 260. The first voltage control circuit 240 can be configured to transmit the first current signal I1 to the current mirror circuit 260 via the third node N3, and control the voltage of the third node N3 according to the voltage of the second node N2.

[0035] The current mirror circuit 260 is coupled to a first input circuit 220, a first voltage control circuit 240, a second voltage control circuit 250, an output circuit 270, and a first voltage terminal V1. The current mirror circuit 260 is configured to generate a mirror signal I1' of a first current signal I1, and distribute the mirror signal I1' to the second voltage control circuit 250 and the output circuit 270 via a fourth node N4. Here, the mirror signal I1' is a current signal. The mirror signal I1' can be divided into a third current signal I3 and a fourth current signal I4. The third current signal I3 is provided to the second voltage control circuit 250, and the fourth current signal I4 is provided to the output circuit 270. In some embodiments of this disclosure, the ratio of the third current signal I3 to the fourth current signal I4 is a:N.

[0036] The second voltage control circuit 250 can be coupled to the current source circuit 210, the first voltage control circuit 240, the current mirror circuit 260, and the second input terminal INN. The second voltage control circuit 250 can be configured to control the voltage of the second node N2 based on the voltage of the fourth node N4, so that the voltage of the third node N3 is equal to the voltage of the fourth node N4.

[0037] The second input circuit 230 can be coupled to the current source circuit 210, the output circuit 270, the second input terminal INN, and the signal output terminal Vo. The second input circuit 230 can be configured to generate a second current signal I2 based on the second input signal from the second input terminal INN, and provide the second current signal I2 to the output circuit 270.

[0038] The output circuit 270 can be coupled to the second input circuit 230, the current mirror circuit 260, the signal output terminal Vo, and the bias voltage terminal bp. The output circuit 270 can be configured to generate an output signal based on the assigned mirror signal (i.e., the fourth current signal) I4 and the second current signal I2, and output the output signal from the signal output terminal Vo.

[0039] exist Figure 2 In the example, a high voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded.

[0040] The second voltage control circuit 250 controls the voltage of the second node N2 based on the voltage of the fourth node N4. The first voltage control circuit 240 controls the voltage of the third node N3 based on the voltage of the second node N2. Thus, under the control of the second voltage control circuit 250 and the first voltage control circuit 240, the voltage of the third node N3 is equal to the voltage of the fourth node N4. For example, when the voltage of the fourth node N4 increases, the voltage of the second node N2 will also increase, leading to an increase in the voltage of the third node N3, so the voltage of the third node N3 is equal to the voltage of the fourth node N4. This ensures that the quiescent currents of the first current signal I1 and the mirror signal I1' are equal, thereby avoiding the problem of equivalent input offset of the operational amplifier and improving the amplifier's swing and accuracy.

[0041] Furthermore, as described above, the mirror signal I1' is split into a third current signal I3 and a fourth current signal I4. By controlling the ratio of the third current signal I3 to the fourth current signal I4 to be a:N (where N is much larger than a, for example, a equals 1 and N is greater than 100), the fourth current signal I4 can be made much larger than the third current signal I3. Thus, during static operation, the amplitude of the output signal output from the signal output terminal Vo of the operational amplifier circuit 200 is not affected by the shunting of the mirror signal I1', and therefore the amplifier gain remains unaffected.

[0042] Figure 3An exemplary circuit diagram of an operational amplifier circuit 200 according to an embodiment of the present disclosure is shown. Figure 3 As shown, the first voltage control circuit 240 may include: a first transistor M1. The control electrode of the first transistor M1 is coupled to a second node N2. The first electrode of the first transistor M1 is coupled to a third node N3. The second electrode of the first transistor M1 is coupled to a first node N1.

[0043] The current mirror circuit 260 may include a second transistor M2 and a third transistor M3. The control electrode of the second transistor M2 is coupled to the control electrode of the third transistor M3 and a first node N1. The first electrode of the second transistor M2 is coupled to the first electrode of the third transistor M3 and a first voltage terminal V1. The second electrode of the second transistor M2 is coupled to a third node N3. The second electrode of the third transistor M3 is coupled to a fourth node N4.

[0044] The second voltage control circuit 350 may include a fourth transistor M4 and a fifth transistor M5. The control electrode of the fourth transistor M4 is coupled to the second node N2 and the second terminal of the fourth transistor M4. The first terminal of the fourth transistor M4 is coupled to the fourth node N4. The control electrode of the fifth transistor M5 is coupled to the second input terminal INN. The first terminal of the fifth transistor M5 is coupled to the output terminal of the current source circuit 210. The second terminal of the fifth transistor M5 is coupled to the second terminal of the fourth transistor M4.

[0045] The output circuit 270 may include: an eighth transistor M8. The control electrode of the eighth transistor M8 is coupled to the bias voltage terminal bp. The first electrode of the eighth transistor M8 is coupled to the fourth node N4. The second electrode of the eighth transistor M8 is coupled to the signal output terminal Vo.

[0046] The first input circuit 220 may include a ninth transistor M9. The control electrode of the ninth transistor M9 is coupled to the first input terminal INP. The first electrode of the ninth transistor M9 is coupled to the output terminal of the current source circuit 210. The second electrode of the ninth transistor M9 is coupled to the first node N1.

[0047] The second input circuit 230 may include: a tenth transistor M10. The control electrode of the tenth transistor M10 is coupled to the second input terminal INN. The first electrode of the tenth transistor M10 is coupled to the output terminal of the current source circuit 210. The second electrode of the tenth transistor M10 is coupled to the signal output terminal Vo.

[0048] The current source circuit 210 can be coupled to the second voltage terminal V2, the first terminal of the fifth transistor M5, the first terminal of the ninth transistor M9, and the first terminal of the tenth transistor M10. The current source circuit is configured to distribute a constant current to the fifth transistor M5, the ninth transistor M9, and the tenth transistor M10.

[0049] exist Figure 3In this example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. Transistors M1 through M4 and the eighth transistor M8 are PMOS transistors. Transistors M5, M9, and M10 are NMOS transistors. The substrates of transistors M1 through M4 and the eighth transistor M8 are coupled to the first voltage terminal V1. The substrates of transistors M5, M9, and M10 are coupled to the second voltage terminal V2. The threshold voltage V of transistor M1... th_M1 With the threshold voltage V of the fourth transistor M4 th_M4 Equal. Those skilled in the art will understand that, based on the above inventive concept, [the following applies]. Figure 3 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 3 The examples shown have different settings.

[0050] The following is combined Figure 3 The following example illustrates the operation of the operational amplifier circuit 200 according to an embodiment of the present disclosure.

[0051] The current source circuit 210 generates a constant current and provides a constant current to the fifth transistor M5, the ninth transistor M9, and the tenth transistor M10. In some embodiments of this disclosure, the width-to-length ratio of the ninth transistor M9:the width-to-length ratio of the fifth transistor M5:the width-to-length ratio of the tenth transistor M10 is equal to (N+a):a:N. Thus, the ratio of the current allocated to the ninth transistor M9, the fifth transistor M5, and the tenth transistor M10 is equal to the ratio of the width-to-length ratios of the ninth transistor M9, the fifth transistor M5, and the tenth transistor M10. Therefore, in static operation, the first current signal I1:the third current signal I3:the fourth current signal I4 is equal to (N+a):a:N. Figure 3 In the example, the aspect ratios of the ninth transistor M9, the fifth transistor M5, and the tenth transistor M10 are the same. The aspect ratio of the first transistor M1:the aspect ratio of the fourth transistor M4:the aspect ratio of the eighth transistor M8 is equal to (N+a):a:N. Where a is less than or equal to N. In one example, a equals 1, and N is greater than 1.

[0052] According to Kirchhoff's voltage law, we can obtain |V GS_M1 |+|V DS_M2 |=|V GS_M4 |+|V DS_M3 |, where V GS_M1 V represents the gate-source voltage of the first transistor M1. DS_M2 V represents the drain-source voltage of the second transistor M2. GS_M4 V represents the gate-source voltage of the fourth transistor M4.DS_M3 This represents the drain-source voltage of the third transistor M3. Since the first transistor M1 and the fourth transistor M4 are both operating in the saturation region, the gate-source voltages of the first transistor M1 and the fourth transistor M4 can be calculated according to the following formula (1).

[0053]

[0054] As described above, the ratio between the first current signal I1 and the third current signal I3 is equal to the ratio of the width-to-length ratio of the ninth transistor M9 to the width-to-length ratio of the fifth transistor M5 (N+a):a, and the ratio of the width-to-length ratio of the first transistor M1 to the width-to-length ratio of the fourth transistor M4 is also (N+a):a, and the threshold voltage V of the first transistor M1... th_M1 and the threshold voltage V of the fourth transistor th_M4 They are equal. Substituting the above relationship into equation (1), we get |V GS_M1 |=|V GS_M4 Because the control electrode of the fourth transistor M4 is coupled to its second electrode, when the voltage at the fourth node N4 increases, the voltage at the second node N2 will also increase, thus causing the voltage at the third node N3 to increase. This is because the control electrode of the first transistor M1 is coupled to the control electrode of the fourth transistor M4, and |V GS_M1 |=|V GS_M4 Therefore, the voltage at the first terminal of the first transistor M1 is equal to the voltage at the first terminal of the fourth transistor M4, that is, the voltage at the third node N3 and the voltage at the fourth node N4. In this way, the quiescent currents of the first current signal I1 and the mirror signal I1' are equal, thereby avoiding the problem of equivalent input offset of the op-amp.

[0055] Furthermore, the control electrode of the eighth transistor M8 is coupled to the bias voltage terminal bp. The bias voltage terminal bp provides a constant bias voltage. As mentioned above, the width-to-length ratio of the eighth transistor M8 to the fourth transistor M4 is N:a. By setting the ratio of a to N (where N is much larger than a, for example: a equals 1, N is greater than 100), the current I3 flowing through the fourth transistor M4 can be made negligible compared to the current I4 flowing through the eighth transistor M8. Thus, during static operation, the amplitude of the output signal output from the signal output terminal Vo of the operational amplifier circuit 200 is not affected by the shunting of the mirror signal I1', and therefore the amplifier gain is unaffected.

[0056] Figure 4 Another exemplary circuit diagram of an operational amplifier circuit 200 according to an embodiment of the present disclosure is shown. Figure 4 The operational amplifier circuit 200 shown is... Figure 3The operational amplifier circuit 200 shown differs in its second voltage control circuit. The second voltage control circuit 450 of the operational amplifier circuit 200 may further include a sixth transistor M6 and a seventh transistor M7. The sixth transistor M6 is a PMOS transistor, and the seventh transistor M7 is an NMOS transistor. The substrate of the sixth transistor M6 is coupled to a first voltage terminal V1. The substrate of the seventh transistor M7 is coupled to a second voltage terminal V2. The control electrode of the sixth transistor M6 is coupled to the second electrode of the fourth transistor M4 and the second electrode of the sixth transistor M6. The first electrode of the sixth transistor M6 is coupled to the first electrode of the fourth transistor M4. The control electrode of the seventh transistor M7 is coupled to the second input terminal INN. The first electrode of the seventh transistor M7 is coupled to the output terminal of the current source circuit 210. The second electrode of the seventh transistor M7 is coupled to the second electrode of the sixth transistor M6. The threshold voltage V of the first transistor M1... th_M1 With the threshold voltage V of the fourth transistor th_M4 and the threshold voltage V of the sixth transistor M6 th_M6 equal.

[0057] The current source circuit 210 is configured to distribute a constant current to the fifth transistor M5, the seventh transistor M7, the ninth transistor M9, and the tenth transistor M10. The mirror signal I1' can be split into a current signal I. 3_1 Current signal I 3_2 And the fourth current signal I4. In Figure 3 Based on the example, Figure 4 The example is equivalent to splitting the third current signal I3 into current signals I... 3_1 and current signal I 3_2 Current signal I 3_1 The current signal I is supplied to the fourth transistor M4. 3_2 The fourth current signal I4 is provided to the sixth transistor M6, and the fifth current signal I4 is provided to the eighth transistor M8. Those skilled in the art will understand that, based on the above inventive concept... Figure 4 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 4 The examples shown have different settings.

[0058] The following is combined with Figure 4 The following example illustrates the operation of the operational amplifier circuit 200 according to an embodiment of the present disclosure.

[0059] The current source circuit 210 generates a constant current and provides a constant current to the fifth transistor M5, the seventh transistor M7, the ninth transistor M9, and the tenth transistor M10. In some embodiments of this disclosure, the width-to-length ratio of the ninth transistor M9: the width-to-length ratio of the fifth transistor M5: the width-to-length ratio of the seventh transistor M7: the width-to-length ratio of the tenth transistor M10 is equal to (N+a):a:b:(Nb). Thus, the ratio of the current allocated to the ninth transistor M9, the fifth transistor M5, the seventh transistor M7, and the tenth transistor M10 is equal to the ratio of the width-to-length ratios of the ninth transistor M9, the fifth transistor M5, the seventh transistor M7, and the tenth transistor M10. Therefore, in static operation, the first current signal I1: current signal I3_1: current signal I3_2: fourth current signal I4 is equal to (N+a):a:b:(Nb). Figure 4 In the example, the aspect ratios of the ninth transistor M9, the fifth transistor M5, the seventh transistor M7, and the tenth transistor M10 are the same. The aspect ratios of the first transistor M1, the fourth transistor M4, the sixth transistor M6, and the eighth transistor M8 are equal to (N+a):a:b:(Nb). Where a is less than or equal to N, and b is less than N. In one example, a = 1, b = 1, and N is greater than 1.

[0060] According to Kirchhoff's voltage law, we can obtain |V GS_M1 |+|V DS_M2 |=|V GS_M4 |+|V DS_M3 |=|V GS_M6 |+|V DS_M3 |. Among them, V GS_M6 This represents the gate-source voltage of the sixth transistor M6. Since the first transistor M1, the fourth transistor M4, and the sixth transistor M6 are all operating in the saturation region, the gate-source voltages of the first transistor M1, the fourth transistor M4, and the sixth transistor M6 can be calculated according to equation (1).

[0061] As described above, the ratios of the first current signal I1, current signal I3_1, and current signal I3_2 are equal to the ratios of the width-to-length ratios of the ninth transistor M9, the fifth transistor M5, and the seventh transistor M7 (N+a):a:b. The ratios of the width-to-length ratios of the first transistor M1, the fourth transistor M4, and the sixth transistor M6 are also (N+a):a:b. Furthermore, the threshold voltage V of the first transistor M1... th_M1 The threshold voltage V of the fourth transistor th_M4 and the threshold voltage V of the sixth transistor M6 th_M6 They are equal. Substituting the above relationship into equation (1), we get |V GS_M1 |=|V GS_M4|=|V GS_M6 Since the control electrode of the fourth transistor M4 is coupled to the second electrode of the fourth transistor M4, or the control electrode of the sixth transistor M6 is coupled to the second electrode of the sixth transistor M6, when the voltage of the fourth node N4 increases, the voltage of the second node N2 will also increase, thus causing the voltage of the third node N3 to increase. This is because the control electrode of the first transistor M1 is coupled to both the control electrodes of the fourth transistor M4 and the sixth transistor M6, and |V GS_M1 |=|V GS_M4 |=|V GS_M6 Therefore, the voltage at the first terminal of the first transistor M1 is equal to the voltage at the first terminal of the fourth transistor M4 (or the first terminal of the sixth transistor M6), that is, the voltage at the third node N3 and the voltage at the fourth node N4. This makes the quiescent currents of the first current signal I1 and the mirror signal I1' equal, thus avoiding the problem of equivalent input offset in the op-amp.

[0062] pass Figure 3 and Figure 4 As the example shows, more shunt circuits can be set in the second voltage control circuit to divide the third current signal I3 into more parts. Regardless of how many parts I3 is divided into, the circuit can be equivalent to... Figure 3 The example shown falls within the scope of this disclosure.

[0063] In summary, the operational amplifier circuit according to the embodiments of this disclosure maintains equal voltages across the common-source structure by setting the bias voltage in the common-gate structure to an adaptive bias voltage. This ensures that the current in the load current mirror remains equal even when the output voltage is close to the supply voltage, thus avoiding the equivalent input offset problem of the op-amp and improving the amplifier's swing and accuracy. Furthermore, the operational amplifier circuit according to the embodiments of this disclosure also maintains the amplifier's gain unaffected.

[0064] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0065] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0066] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0067] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. An operational amplifier circuit, comprising: The circuit includes a current source circuit, a first input circuit, a second input circuit, a first voltage control circuit, a second voltage control circuit, a current mirror circuit, and an output circuit. The current source circuit is configured to distribute a constant current to the first input circuit, the second voltage control circuit, and the second input circuit. The first input circuit is configured to generate a first current signal based on a first input signal from a first input terminal, and provide the first current signal to the first voltage control circuit via a first node; The first voltage control circuit is coupled to the second voltage control circuit via the second node and is configured to: transmit the first current signal to the current mirror circuit via the third node, and control the voltage of the third node according to the voltage of the second node; The current mirror circuit is configured to generate a mirror signal of the first current signal and distribute the mirror signal to the second voltage control circuit and the output circuit via the fourth node. The second voltage control circuit is configured to control the voltage of the second node according to the voltage of the fourth node so that the voltage of the third node is equal to the voltage of the fourth node; The second input circuit is configured to generate a second current signal based on a second input signal from a second input terminal, and to provide the second current signal to the output circuit; The output circuit is configured to generate an output signal based on the assigned mirror signal and the second current signal, and to output the output signal from the signal output terminal.

2. The operational amplifier circuit according to claim 1, wherein, The ratio of the constant current allocated by the current source circuit to the first input circuit, the second voltage control circuit, and the second input circuit is (N+a):a:N, where a is less than or equal to N.

3. The operational amplifier circuit according to claim 1, wherein, The first voltage control circuit includes: a first transistor, In this configuration, the control electrode of the first transistor is coupled to the second node, the first electrode of the first transistor is coupled to the third node, and the second electrode of the first transistor is coupled to the first node.

4. The operational amplifier circuit according to claim 1, wherein, The current mirror circuit includes a second transistor and a third transistor. Wherein, the control electrode of the second transistor is coupled to the control electrode of the third transistor and the first node, the first electrode of the second transistor is coupled to the first electrode of the third transistor and the first voltage terminal, and the second electrode of the second transistor is coupled to the third node; The second terminal of the third transistor is coupled to the fourth node.

5. The operational amplifier circuit according to claim 1, wherein, The second voltage control circuit includes a fourth transistor and a fifth transistor. The control electrode of the fourth transistor is coupled to the second node and the second electrode of the fourth transistor, and the first electrode of the fourth transistor is coupled to the fourth node; The control electrode of the fifth transistor is coupled to the second input terminal, the first electrode of the fifth transistor is coupled to the output terminal of the current source circuit, and the second electrode of the fifth transistor is coupled to the second electrode of the fourth transistor.

6. The operational amplifier circuit according to claim 5, wherein, The second voltage control circuit further includes: a sixth transistor and a seventh transistor. The control electrode of the sixth transistor is coupled to the control electrode of the fourth transistor and the second electrode of the sixth transistor, and the first electrode of the sixth transistor is coupled to the fourth node; The control electrode of the seventh transistor is coupled to the second input terminal, the first electrode of the seventh transistor is coupled to the output terminal of the current source circuit, and the second electrode of the seventh transistor is coupled to the second electrode of the sixth transistor.

7. The operational amplifier circuit according to claim 1, wherein, The output circuit includes: an eighth transistor, The control electrode of the eighth transistor is coupled to the bias voltage terminal, the first electrode of the eighth transistor is coupled to the fourth node, and the second electrode of the eighth transistor is coupled to the signal output terminal.

8. An operational amplifier circuit, comprising: The first to fifth transistors, the eighth to tenth transistors, and the current source circuit. Wherein, the control electrode of the first transistor is coupled to the control electrode and the second electrode of the fourth transistor, the first electrode of the first transistor is coupled to the second electrode of the second transistor, and the second electrode of the first transistor is coupled to the control electrode of the second transistor, the control electrode of the third transistor, and the second electrode of the ninth transistor; The first terminal of the second transistor is coupled to the first terminal of the third transistor and the first voltage terminal; The second terminal of the third transistor is coupled to the first terminal of the fourth transistor and the first terminal of the eighth transistor; The second terminal of the fourth transistor is coupled to the second terminal of the fifth transistor; The control electrode of the fifth transistor is coupled to the second input terminal, and the first electrode of the fifth transistor is coupled to the output terminal of the current source circuit. The control electrode of the eighth transistor is coupled to the bias voltage terminal, and the second electrode of the eighth transistor is coupled to the signal output terminal; The control electrode of the ninth transistor is coupled to the first input terminal, and the first electrode of the ninth transistor is coupled to the output terminal of the current source circuit. The control electrode of the tenth transistor is coupled to the second input terminal, the first electrode of the tenth transistor is coupled to the output terminal of the current source circuit, and the second electrode of the tenth transistor is coupled to the signal output terminal. The current source circuit is configured to distribute a constant current to the ninth transistor, the fifth transistor, and the tenth transistor.

9. The operational amplifier circuit according to claim 8, wherein, The width-to-length ratio of the ninth transistor: the width-to-length ratio of the fifth transistor: the width-to-length ratio of the tenth transistor is equal to (N+a):a:N, and the width-to-length ratio of the first transistor: the width-to-length ratio of the fourth transistor: the width-to-length ratio of the eighth transistor is equal to (N+a):a:N, where a is less than or equal to N.

10. The operational amplifier circuit according to claim 8, further comprising: The sixth and seventh transistors, The control electrode of the sixth transistor is coupled to the second electrode of the fourth transistor and the second electrode of the sixth transistor, and the first electrode of the sixth transistor is coupled to the first electrode of the fourth transistor. The control electrode of the seventh transistor is coupled to the second input terminal, the first electrode of the seventh transistor is coupled to the output terminal of the current source circuit, and the second electrode of the seventh transistor is coupled to the second electrode of the sixth transistor. The current source circuit is also configured to distribute a constant current to the seventh transistor; Wherein, the width-to-length ratio of the ninth transistor: the width-to-length ratio of the fifth transistor: the width-to-length ratio of the seventh transistor: the width-to-length ratio of the tenth transistor is equal to (N+a):a:b:(Nb), and the width-to-length ratio of the first transistor: the width-to-length ratio of the fourth transistor: the width-to-length ratio of the sixth transistor: the width-to-length ratio of the eighth transistor is equal to (N+a):a:b:(Nb), where a is less than or equal to N, and b is less than N.

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