Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a substrate; a dielectric layer on the substrate, an opening penetrating through the dielectric layer is formed in the dielectric layer, the opening comprises a first opening and a second opening, the first opening and the second opening are located at different positions of the dielectric layer in a direction parallel to a top surface of the substrate; a growth layer on a sidewall of the second opening; a line width compensation layer on a sidewall of the growth layer and a sidewall of the first opening, the line width compensation layer on the sidewall of the first opening is different in thickness from the line width compensation layer on the sidewall of the growth layer in a direction perpendicular to the sidewall of the opening; and a conductive layer in the opening. The embodiments of the present application are beneficial to improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] The reduction of feature size in integrated circuits has become a driving force behind the booming semiconductor industry. Increasingly smaller feature sizes enable high density and high integration of functional units on semiconductor chip substrates. For example, by reducing transistor size, more memory or logic devices can be included on a chip, resulting in products with greater capacity. However, with the technological demands for larger capacity products, the need to optimize the performance of each device becomes increasingly significant.

[0003] In semiconductor manufacturing processes, after semiconductor devices are formed on a substrate, multiple metal layers are used to connect the semiconductor devices together to form a circuit. The metal layers include interconnects, contacts (CTs), and via interconnect structures. CTs are used to connect semiconductor devices, and interconnects and via interconnect structures are used to connect the contacts on different semiconductor devices to form a circuit.

[0004] Currently, the performance of semiconductor devices needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to improving the performance of semiconductor devices.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate; a dielectric layer located on the substrate, wherein an opening penetrating the dielectric layer is formed within the dielectric layer, the opening including a first opening and a second opening, which are located at different positions in the dielectric layer along a direction parallel to the top surface of the substrate; a growth layer located on the sidewall of the second opening; a linewidth compensation layer located on the sidewall of the growth layer and the sidewall of the first opening, along a direction perpendicular to the sidewall of the opening, wherein the linewidth compensation layer on the sidewall of the first opening has a different thickness than the linewidth compensation layer on the sidewall of the growth layer; and a conductive layer located within the opening.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, forming a dielectric layer on the substrate, forming an opening penetrating the dielectric layer within the dielectric layer, the opening including a first opening and a second opening, the first opening and the second opening being located at different positions in the dielectric layer along a direction parallel to the top surface of the substrate; forming a growth layer on the sidewall of the second opening; forming a linewidth compensation layer on the sidewall of the growth layer and the sidewall of the first opening, the linewidth compensation layer on the sidewall of the first opening having a different thickness than the linewidth compensation layer on the sidewall of the growth layer along a direction perpendicular to the sidewall of the opening; and forming a conductive layer within the opening after forming the linewidth compensation layer.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] The semiconductor structure provided in this embodiment of the invention has an opening penetrating the dielectric layer, including a first opening and a second opening. Since a growth layer is formed on the sidewall of the second opening, while the first opening exposes the dielectric layer, the interface basis for the linewidth compensation layer formed in the first and second openings is different. Within the same process time, the formation rate of the linewidth compensation layer in the first and second openings is different, allowing the linewidth compensation layer located on the sidewall of the first opening to have a different thickness than the linewidth compensation layer located on the sidewall of the growth layer. This facilitates the formation of a linewidth compensation layer of the required thickness as needed, enabling control of the linewidth of the conductive layer through the linewidth compensation layer (e.g., when the linewidths of the first and second openings are the same, the conductive layers formed in the first and second openings can have different linewidths; or, when the linewidths of the first and second openings are different, the conductive layers formed in the first and second openings can have the same linewidth). Consequently, the performance of the semiconductor device is improved.

[0010] In the semiconductor structure formation method provided by the embodiments of the present invention, a dielectric layer is formed on a substrate, and an opening penetrating the dielectric layer is formed within the dielectric layer. The opening includes a first opening and a second opening. A growth layer is formed on the sidewall of the second opening, and a linewidth compensation layer is formed on the sidewall of the growth layer and the sidewall of the first opening. Along the direction perpendicular to the sidewall of the opening, the interface basis when the linewidth compensation layer is formed in the first opening and the second opening is different. In the same process time, the formation rate of the linewidth compensation layer in the first opening and the second opening is different. Therefore, the thickness of the linewidth compensation layer located on the sidewall of the first opening is different from that of the linewidth compensation layer located on the sidewall of the growth layer. This facilitates the formation of a linewidth compensation layer of the required thickness according to the needs, so as to control the linewidth of the conductive layer through the linewidth compensation layer (for example, when the linewidths of the first opening and the second opening are the same, the conductive layers formed in the first opening and the second opening can have different linewidths, or when the linewidths of the first opening and the second opening are different, the conductive layers formed in the first opening and the second opening can have the same linewidth). Accordingly, the performance of the semiconductor device is improved. Attached Figure Description

[0011] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figure 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0013] Figures 5 to 8 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0014] Figure 9 This is a schematic diagram illustrating the formation of a growth layer in one embodiment of the semiconductor structure formation method of the present invention;

[0015] Figure 10 This is a schematic diagram of the formation of a linewidth compensation layer in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0016] As the background technology shows, the performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using a semiconductor structure formation method as an example. Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0017] refer to Figure 1A substrate 100 is provided, on which a gate structure 104 is formed. Source and drain doped regions 105 are formed in the substrate 100 on both sides of the gate structure 104. A dielectric layer 101 is formed on the substrate 100 on the side of the gate structure 104 and covers the top and sidewalls of the gate structure 104. An opening 102 is formed in the dielectric layer 101, which exposes the source and drain doped regions 105.

[0018] refer to Figure 2 An isolation layer 110 is formed on the sidewall of the opening 102.

[0019] refer to Figure 3 After the isolation layer 110 is formed, a conductive layer 118 is formed inside the opening 102.

[0020] The thickness of the isolation layer 110 formed on the sidewall of the opening 102 is fixed, thereby the linewidth of the conductive layer 118 formed in the opening 102 is fixed. It is impossible to form a conductive layer 118 with the required linewidth according to the requirements, which correspondingly reduces the performance of the semiconductor device.

[0021] To address the technical problem, embodiments of the present invention provide a semiconductor structure in which an opening penetrating the dielectric layer is formed within the dielectric layer. The opening includes a first opening and a second opening. Since a growth layer is formed on the sidewall of the second opening, while the first opening exposes the dielectric layer, the interface basis for the linewidth compensation layer formed in the first and second openings is different. Within the same process time, the formation rate of the linewidth compensation layer in the first and second openings differs, allowing the linewidth compensation layer located on the sidewall of the first opening to have a different thickness than the linewidth compensation layer located on the sidewall of the growth layer. This facilitates the formation of a linewidth compensation layer of the required thickness as needed, enabling control of the linewidth of the conductive layer through the linewidth compensation layer (e.g., when the linewidths of the first and second openings are the same, the conductive layers formed in the first and second openings can have different linewidths; or, when the linewidths of the first and second openings are different, the conductive layers formed in the first and second openings can have the same linewidth). Consequently, the performance of the semiconductor device is improved.

[0022] To address the technical problem, this invention also provides a method for forming a semiconductor structure. A dielectric layer is formed on a substrate, and an opening penetrating the dielectric layer is formed within the dielectric layer. The opening includes a first opening and a second opening. A growth layer is formed on the sidewall of the second opening. A linewidth compensation layer is formed on the sidewall of the growth layer and the sidewall of the first opening. Along a direction perpendicular to the sidewall of the opening, the interface basis of the linewidth compensation layer formed in the first and second openings is different. Within the same process time, the formation rate of the linewidth compensation layer in the first and second openings is different. Therefore, the thickness of the linewidth compensation layer located on the sidewall of the first opening is different from that located on the sidewall of the growth layer. This facilitates the formation of a linewidth compensation layer of the required thickness according to demand, so that the linewidth of the conductive layer can be controlled through the linewidth compensation layer (for example, when the linewidths of the first and second openings are the same, the conductive layers formed in the first and second openings can have different linewidths; or, when the linewidths of the first and second openings are different, the conductive layers formed in the first and second openings can have the same linewidth). Correspondingly, this improves the performance of the semiconductor device.

[0023] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figure 4 The diagram shows a schematic representation of an embodiment of the semiconductor structure of the present invention.

[0024] like Figure 4 As shown, in this embodiment, the semiconductor structure includes: a substrate 600; a dielectric layer 601 located on the substrate 600, wherein an opening (not shown) is formed in the dielectric layer 601 penetrating the dielectric layer 601, the opening including a first opening (not shown) and a second opening (not shown); a growth layer 613 located on the sidewall of the second opening; a linewidth compensation layer 614 located on the sidewall of the growth layer 613 and the sidewall of the first opening, wherein the linewidth compensation layer 614 located on the sidewall of the first opening has a different thickness than the linewidth compensation layer 614 located on the sidewall of the growth layer 613 along a direction perpendicular to the sidewall of the opening; and a conductive layer 618 located in the opening.

[0025] In this embodiment, the substrate 600 is used to provide a process platform for forming a semiconductor structure.

[0026] In this embodiment, when the semiconductor structure is a planar transistor, the substrate 600 is a substrate. Alternatively, when the semiconductor structure is a FinFET, the substrate 600 may also include a substrate and fins located on the substrate. Alternatively, when the semiconductor structure is a gate-all-around transistor (GAA), the substrate 600 may also include a substrate, fins located on the substrate, and a channel structure located above and spaced from the fins, the channel structure including one or more longitudinally spaced channel layers.

[0027] In this embodiment, the substrate is a silicon substrate. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, or other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0028] In this embodiment, the dielectric layer 601 is used to provide space for forming the opening and also to achieve electrical isolation between the conductive layers 618.

[0029] The dielectric layer 601 is made of an insulating material. In this embodiment, the dielectric layer 601 is made of silicon oxide. In other embodiments, the dielectric layer may also be made of other dielectric materials such as silicon nitride or silicon oxynitride.

[0030] In this embodiment, the opening is used to provide space for the formation of the conductive layer 618.

[0031] In this embodiment, the opening includes a first opening and a second opening, which are located at different positions in the dielectric layer along a direction parallel to the top surface of the substrate.

[0032] As an example, the first opening and the second opening have the same line width. In other embodiments, the line widths of the first opening and the second opening may also be different.

[0033] In this embodiment, the semiconductor structure includes a gate structure 604 located on the substrate 600.

[0034] The gate structure 604 is used to control the opening and closing of the channel.

[0035] In this embodiment, the gate structure 604 includes a gate dielectric layer (not shown) located on the surface of the substrate 600, and a gate layer (not shown) located on the gate dielectric layer.

[0036] In this embodiment, the gate structure 604 is a metal gate structure.

[0037] In this embodiment, the gate dielectric layer is used to isolate the gate electrode layer and the channel. The material of the gate dielectric layer includes one or more of hafnium oxide, zirconium oxide, silicon hafnium oxide, silicon oxynitride hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, aluminum oxide, silicon oxide, and lanthanum oxide.

[0038] In this embodiment, the gate layer is used to subsequently achieve electrical connections with other interconnect structures. The material of the gate layer includes one or more of titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.

[0039] As an example, the gate layer may include a work function layer and an electrode layer located on the work function layer, wherein the work function layer is used to regulate the threshold voltage of the transistor. In other embodiments, the gate layer may also consist only of a work function layer.

[0040] In other embodiments, the gate structure may also be a polysilicon gate structure, therefore the material of the gate dielectric layer is silicon oxide and the material of the gate layer is polysilicon.

[0041] In this embodiment, a gate capping layer 606 is formed on the gate structure 604.

[0042] In this embodiment, the gate cap layer 606 is used to protect the top of the gate structure 604 during the formation of the opening, so as to achieve self-aligned etching.

[0043] In this embodiment, the gate cap layer 606 is made of one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the gate cap layer 606 is made of silicon nitride.

[0044] In this embodiment, a gate sidewall 607 is also formed on the sidewall of the gate structure 604.

[0045] In this embodiment, the gate sidewall 607 is used to protect the sidewall of the gate structure 604. The gate sidewall 607 can be a single-layer structure or a multilayer structure, and the material of the gate sidewall 607 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, boron carbonitride, and low dielectric constant (LowK). Here, low dielectric constant means that the dielectric constant k is less than 3.9.

[0046] In this embodiment, the semiconductor structure also includes source and drain doped regions 605 located within the substrate 600 on both sides of the gate structure 604.

[0047] In this embodiment, the source / drain doped region 605 serves as the source or drain of the transistor structure. The source / drain doped region 605 is used to provide stress to the channel, which is beneficial to increasing the migration rate of carriers in the channel.

[0048] Accordingly, in this embodiment, the dielectric layer 601 is located on the substrate 600 on the side of the gate structure 604 and covers the top and sidewalls of the gate structure 604, thereby facilitating the isolation of adjacent gate structures 604. Moreover, in this embodiment, the opening exposes the source / drain doped regions 605, thereby realizing the electrical connection between the conductive layer 618 and the source / drain doped regions 605.

[0049] In this embodiment, the semiconductor structure further includes an enhancement layer 610 located on the sidewall of the opening.

[0050] In this embodiment, during the formation of the enhancement layer 610, the enhancement layer 610 is also located at the bottom of the opening. The enhancement layer 610 located at the bottom of the opening is used to enhance the electrical properties of the source / drain doped region 605. During the formation of the conductive layer 618, since the enhancement layer 610 has enhanced the electrical properties of the source / drain doped region 605 and it is necessary to expose the source / drain doped region 605, the enhancement layer 610 at the bottom of the opening is removed.

[0051] In this embodiment, the reinforcing layer 610 is made of silicon oxide. In other embodiments, the protective layer may be made of one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride.

[0052] In this embodiment, the growth layer 613 is used to change the interface basis when forming the linewidth compensation layer 614, thereby controlling the width of the linewidth compensation layer 614 in the direction perpendicular to the opening sidewall.

[0053] In this embodiment, the growth layer 613 is an ion-doped layer, and the ion-doped layer is formed by transforming a portion of the width of the dielectric layer 601 on the second opening sidewall. Specifically, the dielectric layer 601 on the second opening sidewall is transformed into an ion-doped layer by ion doping, which helps to reduce the complexity and cost of forming the growth layer 613. Moreover, it is easy to select the type and concentration of dopant ions according to requirements.

[0054] In this embodiment, the doping ions of the growth layer 613 include phosphorus ions or boron ions.

[0055] refer to Figure 9 The diagram illustrates the principle of forming a growth layer in one embodiment of the semiconductor structure formation method of the present invention. When the material of the dielectric layer 601 is silicon oxide, phosphorus ions or boron ions are beneficial to breaking the hydroxyl bonds in silicon oxide and forming more free hydroxyl bonds (-OH). The hydroxyl bonds combine with the reaction precursor (e.g., diiodosilane) of the formed linewidth compensation layer 614. Therefore, more free hydroxyl bonds are beneficial to accelerating the combination of the reaction precursor and the hydroxyl bonds, thereby increasing the growth rate of the linewidth compensation layer 614 and increasing the thickness of the linewidth compensation layer 614 under the condition of a certain process time.

[0056] In this embodiment, the concentration of dopant ions should not be too low or too high. If the concentration of dopant ions is too low, the effect of changing the interface basis when forming the linewidth compensation layer 614 will be poor, resulting in a poor effect of making the thickness of the linewidth compensation layer 614 located on the first opening sidewall different from that on the growth layer 613 sidewall, thereby reducing the effectiveness of controlling the size of the conductive layer 618 by changing the thickness of the linewidth compensation layer 614. If the concentration of dopant ions is too high, the probability of dopant ions entering the gate structure 604 will increase, which will easily have an adverse effect on the gate structure 604. Therefore, in this embodiment, the concentration of dopant ions is 3E. 14 atom / cm 2 Up to 7E 14 atom / cm 2 .

[0057] In this embodiment, the width of the growth layer 613 along the direction perpendicular to the opening sidewall should not be too small or too large. If the width of the growth layer 613 is too small, it will easily lead to poor effect in changing the interface base when forming the linewidth compensation layer 614. This will result in poor effect in making the linewidth compensation layer 614 on the first opening sidewall different from the linewidth compensation layer 614 on the sidewall of the growth layer 613, thereby reducing the effectiveness of controlling the size of the conductive layer 618 by changing the thickness of the linewidth compensation layer 614. If the width of the growth layer 613 is too large, it will reduce the range of linewidth control of the conductive layer 618 by changing the thickness of the linewidth compensation layer 614, and it will easily lead to difficulty in achieving the preset value of the linewidth of the conductive layer 618. Therefore, in this embodiment, the width of the growth layer 613 is 2nm to 5nm.

[0058] In this embodiment, the linewidth compensation layer 614 is used to control the linewidth of the conductive layer 618.

[0059] In this embodiment, the interface basis when the linewidth compensation layer 614 is formed in the first opening and the second opening is different. Within the same process time, the formation rate of the linewidth compensation layer in the first opening and the second opening is different, which makes the thickness of the linewidth compensation layer 614 located on the sidewall of the first opening different from that of the linewidth compensation layer 614 located on the sidewall of the growth layer 613. This is beneficial to form the linewidth compensation layer 614 of the required thickness according to the needs, so as to control the size of the conductive layer through the linewidth compensation layer 614 (for example, when the linewidth size of the first opening and the second opening is the same, the conductive layer 618 formed in the first opening and the second opening can have different linewidths, or when the linewidth size of the first opening and the second opening is different, the conductive layer formed in the first opening and the second opening can have the same linewidth). Accordingly, the performance of the semiconductor device is improved.

[0060] In this embodiment, the material of the linewidth compensation layer 614 is silicon nitride; in other embodiments, the material of the linewidth compensation layer is silicon oxide.

[0061] In this embodiment, a number of free hydroxyl bonds are formed on the surface of the growth layer 613. Therefore, the linewidth compensation layer 614 is formed at a faster rate on the surface of the growth layer 613, resulting in the thickness of the linewidth compensation layer 614 located on the first opening sidewall being less than the thickness of the linewidth compensation layer 614 located on the sidewall of the growth layer 613.

[0062] Specifically, refer to Figure 10 This diagram illustrates the principle of forming a linewidth compensation layer in one embodiment of the semiconductor structure formation method of the present invention, taking silicon nitride as an example as the material of the linewidth compensation layer 614. During the formation of the growth layer 613, when the doping ions are phosphorus ions or boron ions, the phosphorus ions or boron ions break the hydroxyl bonds in silicon oxide, thereby forming more free hydroxyl bonds. When the material of the linewidth compensation layer 614 is silicon nitride, the hydroxyl bonds react with diiodosilane (SiH2I2), a reactant for forming silicon nitride, thereby increasing the thickness of the linewidth compensation layer 614.

[0063] It should be noted that, in other embodiments, depending on the material of the growth layer, the thickness of the linewidth compensation layer located on the first opening sidewall may be greater than the thickness of the linewidth compensation layer located on the growth layer sidewall. For example, the doping ions in the growth layer include oxygen ions.

[0064] In this embodiment, the conductive layer 618 is used to achieve electrical connection with an external circuit.

[0065] In this embodiment, the conductive layer 618 is electrically connected to the source / drain doped region 604, which facilitates the electrical connection between the source / drain doped region 605 and the external circuit.

[0066] In this embodiment, the first opening and the second opening have the same linewidth. Then, through the growth layer 613 and the linewidth compensation layer 614, the conductive layers located in the first opening and the second opening can have different linewidths.

[0067] In other embodiments, if the linewidths of the first opening and the second opening are different, the conductive layers located in the first opening and the second opening can also have the same linewidth through the growth layer and the linewidth compensation layer. For example, when the linewidth of the second opening is greater than that of the second opening, the doping ions of the growth layer located on the sidewall of the first opening include oxygen ions; or, the doping ions of the growth layer located on the sidewall of the second opening include phosphorus ions or boron ions.

[0068] In this embodiment, the conductive layer 618 is made of tungsten. In other embodiments, the conductive layer is made of other conductive materials such as cobalt or ruthenium.

[0069] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 5 to 8 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0070] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0071] refer to Figure 5 A substrate 800 is provided, on which a dielectric layer 801 is formed, and an opening penetrating the dielectric layer 801 is formed in the dielectric layer 801, the opening including a first opening 802 and a second opening 803.

[0072] The substrate 800 is used to provide a process platform for forming semiconductor structures.

[0073] When the semiconductor structure is a planar transistor, the substrate 800 is a substrate. Alternatively, when the semiconductor structure is a FinFET, the substrate 800 may also include a substrate and fins located on the substrate. Alternatively, when the semiconductor structure is a gate-all-around transistor (GAA), the substrate 800 may also include a substrate, fins located on the substrate, and a channel structure located above and spaced from the fins, the channel structure including one or more longitudinally spaced channel layers.

[0074] In this embodiment, the substrate is a silicon substrate. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, or other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0075] In this embodiment, the dielectric layer 801 is used to provide space for forming the opening and also to achieve electrical isolation between it and the subsequently formed conductive layer.

[0076] The dielectric layer 801 is made of an insulating material. In this embodiment, the dielectric layer 801 is made of silicon oxide. In other embodiments, the dielectric layer may also be made of other dielectric materials such as silicon nitride or silicon oxynitride.

[0077] In this embodiment, the opening is used to provide space for the subsequent formation of the conductive layer.

[0078] In this embodiment, the opening includes a first opening 802 and a second opening 803. The first opening 802 and the second opening 803 have the same size. Along a direction parallel to the top surface of the substrate, the first opening 802 and the second opening 803 are located at different positions in the dielectric layer.

[0079] As an example, the first opening 802 and the second opening 803 have the same line width. In other embodiments, the line widths of the first opening and the second opening may be different.

[0080] In this embodiment, a photolithographic pattern layer (not shown) is formed on the dielectric layer 801, and a mask opening (not shown) is formed in the photolithographic pattern layer. Using the photolithographic pattern layer as a mask, the dielectric layer 801 is etched along the mask opening to form the opening.

[0081] In this embodiment, after the opening is formed, the photolithographic pattern layer is removed.

[0082] In this embodiment, the dielectric layer 801 is specifically etched using a dry etching process (e.g., anisotropic dry etching). Dry etching facilitates control over the initiation and termination of the process, and improves the morphological quality and dimensional accuracy of the openings. In other embodiments, the etching process for the dielectric layer also includes a wet etching process.

[0083] In this embodiment, in the step of providing the substrate 800, a gate structure 804 is formed on the substrate 800, and active and drain doped regions 805 are formed in the substrate 800 on both sides of the gate structure 804. A dielectric layer 801 is formed on the substrate 800 on the side of the gate structure 804 and covers the top and sidewalls of the gate structure 804, with an opening to expose the active and drain doped regions 805.

[0084] In this embodiment, the gate structure 804 is used to control the opening and closing of the channel.

[0085] In this embodiment, the gate structure 804 includes a gate dielectric layer (not shown) located on the surface of the substrate 800, and a gate layer (not shown) located on the gate dielectric layer.

[0086] In this embodiment, the gate structure 804 is a metal gate structure.

[0087] In this embodiment, the gate dielectric layer is used to isolate the gate electrode layer and the channel. The material of the gate dielectric layer includes one or more of hafnium oxide, zirconium oxide, silicon hafnium oxide, silicon oxynitride hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, aluminum oxide, silicon oxide, and lanthanum oxide.

[0088] In this embodiment, the gate layer is used to subsequently achieve electrical connections with other interconnect structures. The material of the gate layer includes one or more of titanium nitride, tantalum nitride, tantalum, titanium, titanium aluminide, tungsten, aluminum, titanium silicon nitride, and titanium aluminum carbide.

[0089] As an example, the gate layer may include a work function layer and an electrode layer located on the work function layer, wherein the work function layer is used to regulate the threshold voltage of the transistor. In other embodiments, the gate layer may also consist only of a work function layer.

[0090] In other embodiments, the gate structure may also be a polysilicon gate structure, therefore the material of the gate dielectric layer is silicon oxide and the material of the gate layer is polysilicon.

[0091] In this embodiment, a gate capping layer 806 is formed on the gate structure 804.

[0092] In this embodiment, the gate cap layer 806 is used to protect the top of the gate structure 604 during the formation of the opening, so as to achieve self-aligned etching.

[0093] In this embodiment, the gate cap layer 806 is made of one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the gate cap layer 806 is made of silicon nitride.

[0094] In this embodiment, a gate sidewall 807 is also formed on the sidewall of the gate structure 804.

[0095] In this embodiment, the gate sidewall 807 is used to protect the sidewall of the gate structure 804. The gate sidewall 807 can be a single-layer structure or a multilayer structure, and the material of the gate sidewall 807 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, boron carbonitride, and low dielectric constant (LowK). Here, low dielectric constant means that the dielectric constant k is less than 3.9.

[0096] In this embodiment, the source / drain doped region 805 serves as the source or drain of the transistor structure. The source / drain doped region 805 is used to provide stress to the channel, which is beneficial to increasing the migration rate of carriers in the channel.

[0097] Accordingly, in this embodiment, the dielectric layer 801 is formed on the substrate 800 on the side of the gate structure 804 and covers the top and sidewalls of the gate structure 804, thereby facilitating the isolation of adjacent gate structures 804. Moreover, in this embodiment, in the subsequent step of forming a conductive layer in the opening, the conductive layer is electrically connected to the source and drain doped regions.

[0098] In this embodiment, the opening exposes the source / drain doped region 805, which facilitates the electrical connection between the conductive layer subsequently formed in the opening and the source / drain doped region 805.

[0099] In other embodiments, the opening may also expose other structures that need to be connected to external circuits, thereby facilitating the electrical connection between these other structures and the external circuits.

[0100] Continue to refer to Figure 5 After the opening is formed, a reinforcing layer 810 is formed on the bottom and sidewalls of the opening.

[0101] In this embodiment, the enhancement layer 810 is used to enhance the electrical properties of the source / drain doped regions 805.

[0102] In this embodiment, a reinforcing layer 810 is formed at the bottom, sidewalls and surface of the dielectric layer 801 of the opening, the reinforcing layer 810 located on the surface of the dielectric layer 801 is removed, and the remaining reinforcing layer 810 is retained.

[0103] In this embodiment, the reinforcing layer 810 is formed by atomic layer deposition (ALD). The ALD process provides good step coverage, which is beneficial for forming a high-quality compensation sidewall with high thickness uniformity. In other embodiments, the protective layer is formed using chemical vapor deposition (CVD) or furnace tube deposition (FCD).

[0104] In this embodiment, the reinforcing layer 810 is made of silicon oxide. In other embodiments, the protective layer may also be made of silicon nitride.

[0105] refer to Figure 6 A growth layer 813 is formed on the sidewall of the second opening 803.

[0106] In this embodiment, the growth layer 813 is used to change the interface basis when the linewidth compensation layer is subsequently formed, thereby controlling the width of the linewidth compensation layer in the direction perpendicular to the sidewall of the second opening 803.

[0107] In this embodiment, the step of forming a growth layer 813 on the sidewall of the second opening 803 includes: performing ion implantation on the dielectric layer 801 exposed on the sidewall of the second opening 803, so that a portion of the width of the dielectric layer 801 on the sidewall of the second opening 803 is transformed into a growth layer 813, thereby reducing the complexity and cost of forming the growth layer 813. Moreover, it is easy to select the type and concentration of dopant ions according to requirements.

[0108] In this embodiment, the process parameters for ion implantation include: implanted ions include phosphorus ions or boron ions.

[0109] refer to Figure 9 When the material of the dielectric layer 801 is silicon oxide, phosphorus ions or boron ions are beneficial to breaking the hydroxyl bonds in silicon oxide and forming more free hydroxyl bonds (-OH). The hydroxyl bonds combine with the reaction precursors (e.g., diiodosilane) of the formed linewidth compensation layer. Therefore, more free hydroxyl bonds are beneficial to accelerate the combination of the reaction precursors and hydroxyl bonds, thereby increasing the growth rate of the linewidth compensation layer and thus increasing the thickness of the subsequently formed linewidth compensation layer under the condition of a certain process time.

[0110] In other embodiments, the process parameters for ion implantation include: implanted ions include oxygen ions; oxygen ions are not conducive to the formation of free hydroxyl bonds in silicon oxide, thereby reducing the thickness of the subsequently formed linewidth compensation layer, and thus making the thickness of the linewidth compensation layer located on the first opening sidewall greater than the thickness of the linewidth compensation layer located on the growth layer sidewall.

[0111] In this embodiment, the angle between the ion implantation direction and the normal direction of the substrate 800 surface during ion implantation should not be too small or too large. If the angle is too small, the implanted ions are likely to concentrate at the bottom of the opening, making it difficult to form on the sidewall of the opening; if the angle is too large, the implanted ions are likely to concentrate at the upper part of the sidewall of the opening, making it impossible to form evenly on the sidewall of the opening. Therefore, in this embodiment, the angle is 5° to 10°.

[0112] In this embodiment, the process parameters for ion implantation include: the implanted ion energy. The implanted ion energy should not be too low or too high. If the ion energy is too low, it will easily lead to poor effect in changing the interface basis when forming the linewidth compensation layer later. This will result in poor effect in making the linewidth compensation layer located on the first opening sidewall different from the linewidth compensation layer located on the growth layer sidewall, thereby reducing the effectiveness of controlling the size of the subsequently formed conductive layer by changing the thickness of the linewidth compensation layer. If the ion energy is too high, it will increase the probability of implanted ions penetrating into the gate structure 804, thereby easily damaging the gate structure 804. Therefore, in this embodiment, the ion energy is 1 keV to 2 keV.

[0113] Accordingly, the implanted ion dose should not be too small or too large. If the implanted ion dose is too small, it will easily lead to poor effect on changing the interface basis when forming the linewidth compensation layer later, resulting in a poor effect of different thicknesses between the linewidth compensation layer located on the first opening sidewall and the linewidth compensation layer located on the growth layer sidewall. If the implanted ion dose is too large, it will increase the probability of implanted ions penetrating into the gate structure 804, which will easily have an adverse effect on the gate structure 804. Therefore, in this embodiment, the implanted ion dose is 3E. 14 atom / cm 2 Up to 7E 14 atom / cm 2 .

[0114] refer to Figure 7 A linewidth compensation layer 814 is formed on the sidewall of the growth layer 813 and the sidewall of the first opening 802. The linewidth compensation layer 814 on the sidewall of the first opening 802 has a different thickness than the linewidth compensation layer 814 on the sidewall of the growth layer 813 along a direction perpendicular to the sidewall of the opening.

[0115] In this embodiment, the linewidth compensation layer 814 is used to control the size of the subsequently formed conductive layer.

[0116] The linewidth compensation layer 814 located on the sidewall of the first opening 802 has a different thickness than the linewidth compensation layer 814 located on the sidewall of the growth layer 813. This allows for the formation of a linewidth compensation layer 814 of the required thickness as needed, so that the size of the conductive layer can be controlled through the linewidth compensation layer 814 (for example, when the linewidth dimensions of the first opening 802 and the second opening 803 are the same, the conductive layers formed in the first opening 802 and the second opening 803 can have different linewidths, or when the linewidth dimensions of the first opening 802 and the second opening 803 are different, the conductive layers formed in the first opening 802 and the second opening 803 can have the same linewidth). Accordingly, the performance of the semiconductor device is improved.

[0117] In this embodiment, the process for forming the linewidth compensation layer 814 is plasma-enhanced atomic layer deposition (PEALD). PALD has a high step coverage, which is beneficial for forming a high-quality linewidth compensation layer 814 with high thickness uniformity.

[0118] In this embodiment, the process parameters for forming the linewidth compensation layer 814 include power. The power should not be too low or too high. If the power is too low, it will be difficult to form the linewidth compensation layer 814 with the required width. If the power is too high, it will easily have an adverse effect on the gate structure 804. Therefore, in this embodiment, the power is 500W to 8000W.

[0119] In this embodiment, the process parameters for forming the linewidth compensation layer 814 also include the process temperature. The process temperature should not be too low or too high. If the process temperature is too low, it will easily lead to poor effect in increasing the thickness of the linewidth compensation layer 814; if the process temperature is too high, it will easily damage the gate structure 804. Therefore, in this embodiment, the process temperature is 300°C to 500°C.

[0120] In this embodiment, the material of the linewidth compensation layer 814 is silicon nitride; in other embodiments, the material of the linewidth compensation layer is silicon oxide.

[0121] refer to Figure 10 When the ion implantation process is carried out, if the implanted ions are phosphorus ions or boron ions, the phosphorus ions or boron ions break the hydroxyl bonds in silicon oxide, thereby forming more free hydroxyl bonds. When the material of the linewidth compensation layer 814 is silicon nitride, the hydroxyl bonds react with diiodosilane, a reactant that forms silicon nitride, thereby increasing the thickness of the linewidth compensation layer 814.

[0122] In this embodiment, in the step of forming a linewidth compensation layer 814 on the sidewall of the growth layer 813 and the sidewall of the first opening 802, the thickness of the linewidth compensation layer 814 on the sidewall of the first opening 802 is less than the thickness of the linewidth compensation layer 814 on the sidewall of the growth layer 813.

[0123] In other embodiments, where the linewidths of the first opening and the second opening are different, the conductive layers located in the first and second openings can also have the same linewidth through the growth layer and the linewidth compensation layer. For example, when the linewidth of the second opening is greater than that of the first opening, the doping ions of the growth layer located on the sidewall of the first opening include oxygen ions; or, the doping ions of the growth layer located on the sidewall of the second opening include phosphorus ions or boron ions.

[0124] It should be noted that, in the step of forming the linewidth compensation layer 814, the linewidth compensation layer 814 is also formed on the top of the dielectric layer 801 and the bottom of the opening.

[0125] refer to Figure 8 After forming the linewidth compensation layer 814, a conductive layer 818 is formed inside the opening.

[0126] In this embodiment, the conductive layer 818 is used to achieve electrical connection with an external circuit.

[0127] In this embodiment, during the step of forming a conductive layer 818 inside the opening, the conductive layer 818 is electrically connected to the source / drain doped region 805, which facilitates the electrical connection between the source / drain doped region 805 and the external circuit.

[0128] Specifically, a conductive material layer (not shown) is formed inside the opening, the conductive material layer on the dielectric layer 801 is removed, and the remaining conductive material layer inside the opening is used as the conductive layer 818.

[0129] In this embodiment, the conductive layer 818 is made of tungsten. In other embodiments, the conductive layer is made of other conductive materials such as cobalt or ruthenium.

[0130] In this embodiment, a conductive material layer is formed inside the opening using a chemical vapor deposition process. In other embodiments, depending on the material of the conductive material layer, other suitable deposition processes may be selected.

[0131] In this embodiment, before forming the conductive layer 818, the method for forming the semiconductor structure further includes: removing the linewidth compensation layer 814 and the enhancement layer 810 located at the bottom of the opening, as well as the linewidth compensation layer 814 located at the top of the dielectric layer 801.

[0132] In this embodiment, since the enhancement layer 810 has enhanced the electrical properties of the source / drain doped region 805 and it is necessary to expose the source / drain doped region 805, the enhancement layer 810 at the bottom of the opening is removed.

[0133] In this embodiment, the linewidth compensation layer 814 and the reinforcement layer 810 located at the bottom of the opening, as well as the linewidth compensation layer 814 located at the top of the dielectric layer 801, are removed, which helps to expose the source / drain doped region 805, and further facilitates the electrical connection between the source / drain doped region 805 and the conductive layer 818.

[0134] In this embodiment, an anisotropic dry etching process is used to remove the linewidth compensation layer 814 and the reinforcement layer 810 at the bottom of the opening, as well as the linewidth compensation layer 814 at the top of the dielectric layer 801. The lateral etching rate of the anisotropic dry etching process is lower than the longitudinal etching rate, which is beneficial for selectively removing the linewidth compensation layer 814 and the reinforcement layer 810 at the bottom of the opening, as well as the linewidth compensation layer 814 at the top of the dielectric layer 801, while retaining the linewidth compensation layer 814 and the reinforcement layer 810 on the sidewall of the opening.

[0135] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A dielectric layer is located on the substrate, and an opening is formed in the dielectric layer that penetrates the dielectric layer. The opening includes a first opening and a second opening, which are located in a direction parallel to the top surface of the substrate. The first opening and the second opening are located at different positions in the dielectric layer. The growth layer is located on the sidewall of the second opening; A linewidth compensation layer is located on the sidewall of the growth layer and the sidewall of the first opening. The linewidth compensation layer on the sidewall of the first opening has a different thickness than the linewidth compensation layer on the sidewall of the growth layer in a direction perpendicular to the sidewall of the opening. A conductive layer is located in the opening.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a gate structure located on the substrate; source / drain doped regions located within the substrate on both sides of the gate structure; a dielectric layer located on the substrate on the side of the gate structure and covering the top and sidewalls of the gate structure, and the opening exposing the source / drain doped regions; The conductive layer is electrically connected to the source / drain doped regions.

3. The semiconductor structure as described in claim 1, characterized in that, The growth layer is an ion-doped layer, and the ion-doped layer is formed by transforming a portion of the dielectric layer of the second opening sidewall.

4. The semiconductor structure as described in claim 3, characterized in that, The doping ions in the growth layer include phosphorus ions or boron ions; The thickness of the linewidth compensation layer located on the sidewall of the first opening is less than the thickness of the linewidth compensation layer located on the sidewall of the growth layer; or, The doping ions in the growth layer include oxygen ions; The thickness of the linewidth compensation layer located on the sidewall of the first opening is greater than the thickness of the linewidth compensation layer located on the sidewall of the growth layer.

5. The semiconductor structure as described in claim 3 or 4, characterized in that, The concentration of doped ions in the growth layer is 3E. 14 atom / cm 2 Up to 7E 14 atom / cm 2 .

6. The semiconductor structure as described in claim 1, characterized in that, The width of the growth layer is 2 nm to 5 nm along a direction perpendicular to the sidewall of the opening.

7. The semiconductor structure as described in claim 1, characterized in that, The material of the linewidth compensation layer includes silicon nitride or silicon oxide.

8. The semiconductor structure as described in claim 1, characterized in that, The first opening and the second opening have the same line width; the conductive layers located in the first opening and the second opening have different line widths. Alternatively, the line widths of the first opening and the second opening are different; The conductive layers located in the first opening and the second opening have the same linewidth.

9. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, on which a dielectric layer is formed, and an opening penetrating the dielectric layer is formed within the dielectric layer. The opening includes a first opening and a second opening, which are located at different positions in the dielectric layer along a direction parallel to the top surface of the substrate. A growth layer is formed on the sidewall of the second opening; A linewidth compensation layer is formed on the sidewall of the growth layer and the sidewall of the first opening. The linewidth compensation layer on the sidewall of the first opening has a different thickness than the linewidth compensation layer on the sidewall of the growth layer in a direction perpendicular to the sidewall of the opening. After the linewidth compensation layer is formed, a conductive layer is formed inside the opening.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of providing a substrate, a gate structure is formed on the substrate, source and drain doped regions are formed in the substrate on both sides of the gate structure, a dielectric layer is formed on the substrate on the side of the gate structure and covers the top and sidewalls of the gate structure, and the opening exposes the source and drain doped regions. In the step of forming a conductive layer within the opening, the conductive layer is electrically connected to the source / drain doped region.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, The step of forming a growth layer on the sidewall of the second opening includes: performing ion implantation on the dielectric layer exposed on the sidewall of the second opening, so that a portion of the width of the dielectric layer on the sidewall of the second opening is converted into a growth layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The process parameters for the ion implantation treatment include: implanted ions include phosphorus ions or boron ions; In the step of forming a linewidth compensation layer on the sidewall of the growth layer and the sidewall of the first opening, the thickness of the linewidth compensation layer on the sidewall of the first opening is less than the thickness of the linewidth compensation layer on the sidewall of the growth layer. or, The process parameters for the ion implantation treatment include: implanted ions include oxygen ions; In the step of forming linewidth compensation layers on the sidewalls of the growth layer and the first opening, the thickness of the linewidth compensation layer on the sidewall of the first opening is greater than the thickness of the linewidth compensation layer on the sidewall of the growth layer.

13. The method for forming a semiconductor structure as described in claim 11, characterized in that, The angle between the ion implantation direction of the ion implantation process and the normal direction of the top surface of the substrate is 5° to 10°.

14. The method for forming a semiconductor structure as described in claim 11, characterized in that, The process parameters for the ion implantation treatment include: the implanted ion energy is 1 keV to 2 keV, and the implanted ion dose is 3E. 14 atom / cm 2 Up to 7E 14 atom / cm 2 .

15. The method for forming a semiconductor structure as described in claim 9, characterized in that, The process for forming the linewidth compensation layer includes: plasma-enhanced atomic layer deposition.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The process parameters of the plasma-enhanced atomic layer deposition process include: power of 500W to 8000W and process temperature of 300℃ to 500℃.

17. The method for forming a semiconductor structure as described in claim 9, characterized in that, The material of the linewidth compensation layer includes silicon nitride or silicon oxide.

18. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming the linewidth compensation layer, the linewidth compensation layer is also formed on top of the dielectric layer and at the bottom of the opening; Before forming the conductive layer, the method for forming the semiconductor structure further includes: removing the linewidth compensation layer located at the bottom of the opening and the linewidth compensation layer located at the top of the dielectric layer.

Images