Method of forming a semiconductor structure
By filling the gate transistor with a sacrificial layer to occupy a specific space, the problem of damage to the second device region caused by the etching process is solved, and the performance of the semiconductor structure is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2022-05-23
- Publication Date
- 2026-07-03
AI Technical Summary
In existing technologies, when forming fully enclosed gate transistors, the etching process can easily damage the shielding layer and work function layer of the second device region, affecting the performance of the semiconductor structure.
A sacrificial layer covering the work function layer is filled in the spatial position between the channel layer and the substrate. By occupying the spatial position of the adjacent channel layer, the probability of the formation of the shielding layer is reduced. The shielding layer is removed by a single etching process, which reduces the damage to the second device region.
This reduces the risk of excessive consumption of the shielding layer and exposure of the work function layer in the second device region, thereby improving the performance of the semiconductor structure.
Smart Images
Figure CN117153787B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology
[0002] With the rapid development of semiconductor manufacturing technology, semiconductor transistors are evolving towards higher device density and higher integration, and semiconductor process nodes are continuously shrinking in accordance with Moore's Law. Transistors, as the most basic semiconductor material, are currently widely used. Therefore, as the device density and integration of semiconductor transistors increase, the channel length of transistors must be continuously shortened to adapt to the shrinking process nodes.
[0003] To better adapt to the requirement of proportionally shrinking transistor dimensions, semiconductor manufacturing processes have gradually transitioned from planar transistors to more efficient three-dimensional transistors, such as FinFETs and Gate-all-around (GAA) transistors. GAA transistors include vertical and horizontal types. In a GAA transistor, the gate surrounds the channel region from all sides. Compared to planar transistors, GAA transistors offer stronger control over the channel and better suppress short-channel effects.
[0004] As device size continues to shrink, improving the performance of fully enclosed gate structure devices becomes increasingly difficult and challenging. Summary of the Invention
[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to further improve the performance of the semiconductor structure.
[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including adjacent first device regions and second device regions, wherein a channel structure layer is suspended on the top of the first device regions and the second device regions along the normal direction of the substrate surface, the channel structure layer including one or more channel layers spaced apart in the longitudinal direction; forming a gate dielectric layer and a work function layer surrounding the gate dielectric layer at a portion of the top, a portion of the sidewalls, and a portion of the bottom of the channel layers; filling a sacrificial layer covering the work function layer in the first device region at spatial positions opposite to adjacent channel layers and at spatial positions opposite to the substrate; forming a shielding layer covering the top and sidewalls of the work function layer and the sidewalls of the sacrificial layer on the substrate exposed by the channel structure layer; removing the shielding layer, the sacrificial layer, and the work function layer of the first device region; and removing the shielding layer, the sacrificial layer, and the work function layer of the first device region after removing the shielding layer, the sacrificial layer, and the work function layer of the first device region.
[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0008] This invention provides a method for forming a semiconductor structure. A sacrificial layer covering the work function layer is filled in the spatial positions opposite adjacent channel layers and the spatial positions opposite the channel layer and the substrate. That is, by occupying the spatial positions opposite the channel layer and the substrate, and the spatial positions opposite adjacent channel layers, the probability of forming a masking layer in the first device region and the second device region is reduced. Correspondingly, in the subsequent step of removing the masking layer in the first device region, the masking layer in the first device region can be completely removed in a single etching process, reducing the probability of excessive consumption of the masking layer in the second device region. This reduces the risk of the work function layer in the second device region being exposed, and consequently reduces the probability of damage to the work function layer in the second device region during the subsequent removal of the work function layer in the first device region, thereby improving the performance of the semiconductor structure. Attached Figure Description
[0009] Figures 1 to 6 This is a schematic diagram of a semiconductor structure.
[0010] Figures 7 to 17 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation
[0011] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a particular semiconductor structure needs further improvement.
[0012] Figures 1 to 6 This is a schematic diagram of a semiconductor structure.
[0013] refer to Figure 1 A substrate 10 is provided, which includes an adjacent first device region 10A and a second device region 10B. A channel structure layer 16 is suspended on the top of the substrate 10 along the normal direction of the surface of the substrate 10. The channel structure layer 16 includes one or more channel layers 15 spaced apart in the longitudinal direction. A gate dielectric layer 18 is formed on a portion of the top, a portion of the sidewalls and a portion of the bottom of the channel layer 15, and a work function layer 19 surrounds and covers the gate dielectric layer 18.
[0014] refer to Figure 2 A shielding layer 20 covering the work function layer 19 is formed on the exposed substrate 10 of the channel structure layer 16.
[0015] refer to Figure 3In the first device region 10A, the shielding layer 20 on the sidewall of the channel structure layer 16 is removed.
[0016] refer to Figure 4 After removing the shielding layer 20 from the sidewall of the channel structure layer 16, the shielding layer 20 is removed in the first device region 10A in the spatial position directly opposite the adjacent channel layer 15 and in the spatial position directly opposite the channel layer 15 and the substrate 10.
[0017] refer to Figure 5 Remove the work function layer 19 of the first device region 10A.
[0018] refer to Figure 6 After removing the work function layer 19 of the first device region 10A, the shielding layer 20 of the second device region 10B is removed.
[0019] Studies have shown that after removing the shielding layer 20 from the sidewall of the channel structure layer 16, the etching process used in the first device region 10A to remove the shielding layer 20 located in the space opposite to the adjacent channel layer 15 and in the space opposite to the substrate 10 is prone to excessive consumption of the shielding layer 20 in the second device region 10B. Consequently, this increases the risk of the work function layer 19 in the second device region 10B being exposed. In the subsequent step of removing the work function layer 19 in the first device region 10A, this increases the probability of the work function layer 19 in the second device region 10B being damaged, thereby affecting the performance of the semiconductor structure.
[0020] To address the technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including adjacent first device regions and second device regions, a channel structure layer suspended on top of the first device regions and second device regions along the normal direction of the substrate surface, the channel structure layer including one or more channel layers spaced apart in the longitudinal direction; forming a gate dielectric layer and a work function layer surrounding the gate dielectric layer at a portion of the top, a portion of the sidewalls and a portion of the bottom of the channel layers; filling sacrificial layers covering the work function layers in the first device region at spatial positions opposite to adjacent channel layers and at spatial positions opposite to the substrate; forming a shielding layer covering the top and sidewalls of the work function layer and the sidewalls of the sacrificial layer on the substrate exposed by the channel structure layer; removing the shielding layer, the sacrificial layer and the work function layer of the first device region; and removing the shielding layer, the sacrificial layer and the work function layer of the first device region after removing the shielding layer, the sacrificial layer and the work function layer of the first device region.
[0021] This invention provides a method for forming a semiconductor structure. A sacrificial layer covering the work function layer is filled in the spatial positions opposite adjacent channel layers and the spatial positions opposite the channel layer and the substrate. That is, by occupying the spatial positions opposite the channel layer and the substrate, and the spatial positions opposite adjacent channel layers, the probability of forming a masking layer in the first device region and the second device region is reduced. Correspondingly, in the subsequent step of removing the masking layer in the first device region, the masking layer in the first device region can be completely removed in a single etching process, reducing the probability of excessive consumption of the masking layer in the second device region. This reduces the risk of the work function layer in the second device region being exposed, and consequently reduces the probability of damage to the work function layer in the second device region during the subsequent removal of the work function layer in the first device region, thereby improving the performance of the semiconductor structure.
[0022] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0023] Figures 7 to 17 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.
[0024] refer to Figure 7 A substrate (not shown) is provided, the substrate includes an adjacent first device region 100A and a second device region 100B, and a channel structure layer 106 is suspended on the top of the substrate of the first device region 100A and the second device region 100B along the normal direction of the substrate surface. The channel structure layer 106 includes one or more channel layers 105 arranged longitudinally at intervals.
[0025] The substrate is used to provide a process platform for subsequent process manufacturing.
[0026] In this embodiment, the substrate has a three-dimensional structure, including a substrate 100 and fins 101 disposed on the substrate 100 in the first device region 100A and the second device region 100B. In other embodiments, the substrate may also be a planar substrate 100. In this embodiment, the substrate 100 is a silicon substrate 100. In other embodiments, the substrate 100 may also be a silicon-germanium composite.
[0027] In this embodiment, the fin 101 is made of the same material as the substrate 100, and the material of the fin 101 is silicon.
[0028] In this embodiment, the first device region 100A is used to form a first-type transistor, and the second device region 100B is used to form a second-type transistor. The first-type transistor and the second-type transistor have different channel conductivity types. Specifically, the first-type transistor is an NMOS transistor, and the second-type transistor is a PMOS transistor; in other embodiments, the first-type transistor is a PMOS transistor, and the second-type transistor is an NMOS transistor.
[0029] The channel layer 105 is used as a conductive channel for the first device region 100A and the second device region 100B.
[0030] In this embodiment, both the first type transistor and the second type transistor are fully enclosed gate transistors. Therefore, the channel layer 105 and the substrate are spaced apart in the longitudinal direction.
[0031] In this embodiment, the channel layer 105 is made of one or more of silicon, silicon germanide, germanium, and group III-V semiconductor materials. The material of the channel layer 105 in the first device region 100A is determined according to the performance of a first-type transistor, and the material of the channel layer 105 in the second device region 100B is determined according to the performance of a second-type transistor. As an example, the material of the channel layer 105 in both the first device region 100A and the second device region 100B is silicon.
[0032] In this embodiment, there are three channel layers 105. In other embodiments, the number of channel layers 105 may be other numbers.
[0033] In this embodiment, the method for forming the semiconductor structure further includes: before forming the channel structure layer 106, forming an isolation layer 102 on the substrate 100 exposed by the fin 101, wherein the isolation layer 102 covers the sidewall of the fin 101.
[0034] The isolation layer 102 is used to isolate adjacent first device region 100A and second device region 100B. Therefore, the material of the isolation layer 102 is a dielectric material, which may include silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 102 is silicon oxide.
[0035] In this embodiment, during the step of providing the substrate, an interlayer dielectric layer (not shown) covering the channel structure layer 106 is also formed on the substrate. A gate opening 107 spanning the channel structure layer 106 is formed in the interlayer dielectric layer, and the gate opening 107 exposes part of the top and part of the sidewalls of the channel structure layer 106.
[0036] The interlayer dielectric layer is used to isolate adjacent devices. The material of the interlayer dielectric layer is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer is silicon oxide.
[0037] In this embodiment, the gate opening 107 provides a process window for subsequent process fabrication.
[0038] refer to Figure 8 A gate dielectric layer 108 and a work function layer 109 surrounding and covering the gate dielectric layer 108 are formed on a portion of the top, a portion of the sidewalls and a portion of the bottom of the channel layer 105.
[0039] The gate dielectric layer 108 is used to reduce the probability of leakage current in semiconductor devices, thereby improving the reliability of semiconductor devices.
[0040] In this embodiment, in the step of forming the gate dielectric layer 108, the gate dielectric layer 108 is formed on a portion of the top, a portion of the sidewalls, and a portion of the bottom of the channel layer 105 exposed by the gate opening 107.
[0041] In this embodiment, the material of the gate dielectric layer 108 includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.
[0042] Specifically, the gate dielectric layer 108 includes a gate oxide layer that conformally covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the channel layer 105, and a high-k gate dielectric layer 108 that conformally covers the gate oxide layer. The high-k gate dielectric layer 108 is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide.
[0043] In this embodiment, the process for forming the gate dielectric layer 108 includes atomic layer deposition.
[0044] The work function layer 109 is used to adjust the threshold voltage of the type II transistor.
[0045] In this embodiment, the material of the work function layer 109 includes one or more of TiN, TaN, TiAl, TiSiN, and TiAlC. The specific material of the work function layer 109 is determined based on the performance of the type-2 transistor.
[0046] In this embodiment, the process for forming the power function layer 109 includes atomic layer deposition.
[0047] refer to Figure 9 In the first device region 100A, a sacrificial layer 112 covering the work function layer 109 is filled in the spatial positions directly opposite the adjacent channel layer 105 and the spatial positions directly opposite the channel layer 105 and the substrate.
[0048] It should be noted that the sacrificial layer 112, which covers the work function layer 109, is filled in the spatial positions directly opposite each other of the adjacent channel layer 105 and the spatial positions directly opposite each other of the channel layer 105 and the substrate. That is, by occupying the spatial positions directly opposite each other of the channel layer 105 and the substrate, and the spatial positions directly opposite each other of the adjacent channel layer 105, the subsequent step of forming a shielding layer in the first device region 100A and the second device region 100B reduces the amount of shielding material formed in the spatial positions directly opposite each other of the channel layer 105 and the substrate, and the spatial positions directly opposite each other of the adjacent channel layer 105. The probability of the shielding layer being consumed is reduced. Consequently, in the subsequent step of removing the shielding layer of the first device region 100A, the shielding layer of the first device region 100A can be completely removed in a single etching process. This reduces the probability that the shielding layer in the second device region 100B will be excessively consumed, thereby reducing the risk of the work function layer 109 in the second device region 100B being exposed. In the subsequent step of removing the work function layer 109 of the first device region 100A, the probability of the work function layer 109 of the second device region 100B being damaged is also reduced, thereby improving the performance of the semiconductor structure.
[0049] In this embodiment, the step of filling the sacrificial layer 112 covering the work function layer 109 in the spatial positions directly opposite each other of the adjacent channel layers 105 and the spatial positions directly opposite each other of the channel layer 105 and the substrate includes: forming the sacrificial layer 112 on the exposed top surface of the substrate of the channel structure layer 106, the top, sidewall and bottom of the channel layer 105, and the sacrificial layer 112 surrounding the work function layer 109.
[0050] It should be noted that the thickness of the sacrificial layer 112 located on the sidewall of the channel layer 105 should not be too large or too small. If the thickness of the sacrificial layer 112 located on the sidewall of the channel layer 105 is too large, the process difficulty of removing the sacrificial layer 112 in the subsequent process increases, reducing the process efficiency of the semiconductor manufacturing process. If the thickness of the sacrificial layer 112 located on the sidewall of the channel layer 105 is too small, it is easy for the sacrificial layer 112 to fail to fill the space positions directly opposite the adjacent channel layer 105 and the space positions directly opposite the substrate in the subsequent process of forming the shielding layer. Accordingly, in the subsequent process of forming the shielding layer, the probability of forming the shielding layer in the space positions directly opposite the adjacent channel layer 105 and the space positions directly opposite the substrate increases. In the subsequent process of removing the shielding layer, the probability of the shielding layer in the second device region 100B being consumed excessively increases, that is, the risk of the work function layer 109 in the second device region 100B being exposed increases, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the sacrificial layer 112 located on the sidewall of the channel layer 105 is 10 nanometers to 20 nanometers.
[0051] In this embodiment, the process of forming the sacrificial layer 112 on the exposed top surface of the substrate of the channel structure layer 106, the top, sidewalls and bottom of the channel layer 105 includes an atomic layer deposition process.
[0052] The atomic layer deposition process involves multiple atomic layer deposition cycles, which helps to improve the thickness uniformity of the sacrificial layer 112 and enables the sacrificial layer 112 to cover the exposed top surface of the substrate of the channel structure layer 106, the top, sidewalls, and bottom of the channel layer 105. In other embodiments, the sacrificial layer 112 can also be formed using a chemical vapor deposition (CVD) process.
[0053] It should be noted that, in this embodiment, during the step of forming the sacrificial layer 112, the sacrificial layer 112 is also formed in the second device region 100B.
[0054] Specifically, by forming a sacrificial layer 112 in the second device region 100B, the probability of forming a masking layer in the subsequent step of forming a masking layer is reduced in the spatial position where the adjacent channel layer 105 of the second device region 100B is directly opposite each other, and in the spatial position where the channel layer 105 is directly opposite the substrate. Accordingly, in the subsequent step of removing the masking layer of the second device region 100B, the masking layer can be removed by a single etching process, reducing process steps and lowering process costs.
[0055] In this embodiment, the material of the sacrificial layer 112 includes one or more of silicon oxide, aluminum oxide, and amorphous silicon.
[0056] Specifically, silicon oxide, aluminum oxide, and amorphous silicon have a large etching selectivity ratio with the materials used in the channel structure layer 106, which is beneficial for removing the sacrificial layer using subsequent etching processes, while reducing the probability of damaging the channel structure layer 106.
[0057] refer to Figure 10 A shielding layer 115 is formed on the exposed substrate of the channel structure layer 106, covering the top and sidewalls of the work function layer 109 and the sidewalls of the sacrificial layer 112.
[0058] Specifically, by forming a shielding layer 115 on the exposed substrate of the channel structure layer 106, covering the top and sidewalls of the work function layer 109 and the sidewalls of the sacrificial layer 112, the second device region 100B is protected during the subsequent removal of the sacrificial layer 112 of the first device region 100A. At the same time, during the subsequent removal of the work function layer 109 of the first device region 100A, the shielding layer 115 located in the second device region 100B acts as an etching mask.
[0059] In this embodiment, the process of forming a shielding layer 115 covering the top and sidewalls of the work function layer 109 and the sidewalls of the sacrificial layer 112 on the exposed substrate of the channel structure layer 106 includes a spin coating process.
[0060] In this embodiment, the material of the shielding layer 115 includes one or more of BARC (bottom anti-reflective coating) and SARC (sacrificial anti-reflective coating).
[0061] Specifically, the BARC and SARC materials have a large etching selectivity ratio with the work function layer 109. In the subsequent step of removing the work function layer 109 of the first device region 100A, the shielding layer 115 of the second device region 100B can serve as an etching mask. At the same time, since both BARC and SARC materials are organic materials, the process difficulty of removing the shielding layer 115 is reduced in the subsequent step of removing the shielding layer 115, thereby improving the performance of the semiconductor structure.
[0062] refer to Figures 11 to 14 Remove the shielding layer 115, the sacrificial layer 112 and the work function layer 109 from the first device region 100A.
[0063] Specifically, removing the shielding layer 115, sacrificial layer 112, and work function layer 109 of the first device region 100A is beneficial for the subsequent formation of the gate electrode layer spanning the channel layer 105.
[0064] Reference Figures 11 to 14 The steps for removing the shielding layer 115, the sacrificial layer 112 and the work function layer 109 of the first device region 100A are described in detail.
[0065] refer to Figures 11 to 12 Remove the shielding layer 115 from the first device region 100A.
[0066] Specifically, the shielding layer 115 of the first device region 100A is removed to expose the sacrificial layer 112 of the first device region 100A, providing a process basis for the subsequent removal of the sacrificial layer 112 and the work function layer 109.
[0067] In this embodiment, the step of removing the shielding layer 115 of the first device region 100A includes: as follows Figure 11 As shown, a mask layer 118 is formed on top of the shielding layer 115 of the second device region 100B, and the mask layer 118 exposes the first device region 100A; as Figure 12 As shown, using mask layer 118 as a mask, the masking layer 115 of the first device region 100A is removed.
[0068] In this embodiment, the material of the mask layer 118 is photoresist.
[0069] In this embodiment, the process of removing the shielding layer 115 of the first device region 100A includes a dry etching process.
[0070] Dry etching processes include anisotropic dry etching processes. Anisotropic dry etching processes have the characteristics of anisotropic etching, so their vertical etching rate is much greater than their horizontal etching rate. While achieving fairly accurate pattern transfer, this helps to ensure the sidewall morphology quality of the shielding layer 115 of the second device region 100B, and helps to ensure that the shielding layer 115 of the second device region 100B can completely cover the work function layer 109.
[0071] refer to Figures 13 to 14 Using the remaining masking layer 115 of the second device region 100B as a mask, the sacrificial layer 112 and the work function layer 109 of the first device region 100A are removed.
[0072] In this embodiment, the steps of removing the sacrificial layer 112 and the work function layer 109 of the first device region 100A include: as follows Figure 13 As shown, the sacrificial layer 112 of the first device region 100A is removed; as Figure 14 As shown, after removing the sacrificial layer 112 of the first device region 100A, the work function layer 109 of the first device region 100A is removed.
[0073] Specifically, by first removing the sacrificial layer 112, the work function layer 109 of the first device region 100A is exposed, which facilitates the subsequent removal of the exposed work function layer 109 by etching.
[0074] In this embodiment, the process for removing the sacrificial layer 112 of the first device region 100A includes a wet etching process or an isotropic dry etching process.
[0075] Specifically, the wet etching process is characterized by its simple operation and high process efficiency, and can completely remove the sacrificial layer 112 in the first device region 100A, reducing the probability of residual sacrificial layer 112 in the first device region 100A.
[0076] In this embodiment, the process for removing the work function layer 109 of the first device region 100A includes a wet etching process or an isotropic dry etching process.
[0077] Specifically, the wet etching process is characterized by its simple operation and high process efficiency, and can completely remove the work function layer 109 of the first device region 100A, reducing the probability of residual work function layer 109 in the first device region 100A.
[0078] It should be noted that after removing the masking layer 115, the sacrificial layer 112 and the work function layer 109 of the first device region 100A, the process also includes removing the mask layer 118.
[0079] Specifically, the process for removing the mask layer 118 includes one or both of wet etching and ashing processes.
[0080] refer to Figure 15 After removing the shielding layer 115, sacrificial layer 112 and work function layer 109 of the first device region 100A, the shielding layer 115 of the second device region 100B is removed.
[0081] Specifically, by removing the shielding layer 115 of the second device region 100B, the sacrificial layer 112 of the second device region 100B is exposed, which facilitates the subsequent removal of the sacrificial layer 112 through the gate opening 107.
[0082] In this embodiment, the process of removing the shielding layer 115 of the second device region 100B includes an ashing process.
[0083] Specifically, the ashing process has the advantages of low process cost and simple operation. By using the ashing process to remove the shielding layer 115 of the second device region 100B, it is beneficial to completely remove the shielding layer 115 of the second device region 100B, thereby reducing the probability of the shielding layer 115 remaining in the second device region 100B and thus improving the performance of the semiconductor structure.
[0084] It should be noted that in this embodiment, after removing the shielding layer 115 of the second device region 100B, the sacrificial layer 112 of the second device region 100B is removed.
[0085] refer to Figure 16 After removing the shielding layer 115, sacrificial layer 112 and work function layer 109 of the first device region 100A, the method further includes removing the sacrificial layer 112 of the second device region 100B.
[0086] Specifically, removing the sacrificial layer 112 of the second device region 100B facilitates the subsequent formation of a gate electrode layer surrounding the work function layer 109 in the second device region 100B.
[0087] In this embodiment, the process for removing the sacrificial layer 112 of the second device region 100B includes a wet etching process.
[0088] Specifically, the wet etching process is characterized by its simple operation and high process efficiency. It can completely remove the sacrificial layer 112 of the second device region 100B, reducing the probability of residual sacrificial layer 112 in the second device region 100B, thereby improving the performance of the semiconductor structure.
[0089] refer to Figure 17After removing the shielding layer 115 of the second device region 100B, the method for forming the semiconductor structure further includes: forming a gate electrode layer 130 across the channel layer 105 on the top of the substrate of the first device region 100A and the second device region 100B, wherein the gate electrode layer 130 in the first device region 100A surrounds and covers the gate dielectric layer 108, and the gate electrode layer 130 in the second device region 100B surrounds and covers the work function layer 109.
[0090] The gate electrode layer 130 is used for subsequent electrical connection with external structures.
[0091] The gate electrode layer 130 is made of one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. In this embodiment, the gate electrode layer 130 is made of W.
[0092] In this embodiment, the process of forming a gate electrode layer 130 across the channel layer 105 on top of the substrate of the first device region 100A and the second device region 100B includes a chemical vapor deposition process.
[0093] It should be noted that, taking the aforementioned work function layer 109 as the first work function layer 109, before forming the gate electrode layer 130, it may also include: forming a second work function layer (not shown) surrounding the gate dielectric layer 108 in the first device region 100A, the second work function layer being used to adjust the threshold voltage of the first type transistor.
[0094] As an example, the first type of transistor is an NMOS transistor, the second work function layer is an N-type work function layer, and the material of the second work function layer includes one or more of TiAl, Mo, MoN, AlN and TiAlC.
[0095] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including an adjacent first device region and a second device region, and a channel structure layer is suspended on the top of the first device region and the second device region along the normal direction of the substrate surface, the channel structure layer including one or more channel layers spaced apart in the longitudinal direction; A gate dielectric layer is formed at a portion of the top, a portion of the sidewalls, and a portion of the bottom of the channel layer, and a work function layer surrounds and covers the gate dielectric layer; In the first device region, a sacrificial layer covering the work function layer is filled in the spatial positions directly opposite each other of the adjacent channel layers and in the spatial positions directly opposite each other of the channel layers and the substrate. A shielding layer is formed on the substrate exposed by the channel structure layer, covering the top and sidewalls of the work function layer and the sidewalls of the sacrificial layer; Remove the shielding layer, sacrificial layer, and work function layer from the first device region; After removing the shielding layer, sacrificial layer and power function layer of the first device region, the shielding layer of the second device region is removed.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of filling the sacrificial layer covering the work function layer in the spatial locations opposite each other of the adjacent channel layers and in the spatial locations opposite each other of the channel layer and the substrate includes: forming the sacrificial layer on the exposed top surface of the substrate of the channel structure layer, the top, sidewall and bottom of the channel layer, the sacrificial layer surrounding and covering the work function layer.
3. The method for forming a semiconductor structure as described in claim 2, characterized in that, In the step of filling the sacrificial layer, the thickness of the sacrificial layer located on the sidewall of the channel layer is 10 nanometers to 20 nanometers.
4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The process of forming a sacrificial layer on the exposed top surface of the substrate, the top of the channel structure layer, the sidewalls and the bottom of the channel layer includes atomic layer deposition.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of removing the masking layer, sacrificial layer and work function layer of the first device region includes: removing the masking layer of the first device region; and using the remaining masking layer of the second device region as a mask to remove the sacrificial layer and work function layer of the first device region.
6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The step of removing the masking layer of the first device region includes: forming a mask layer on top of the masking layer of the second device region, the mask layer exposing the first device region; and removing the masking layer of the first device region using the mask layer as a mask.
7. The method for forming a semiconductor structure as described in claim 1 or 5, characterized in that, The process for removing the masking layer from the first device region includes a dry etching process.
8. The method for forming a semiconductor structure as described in claim 5, characterized in that, The steps of removing the sacrificial layer and the work function layer of the first device region include: removing the sacrificial layer of the first device region; and after removing the sacrificial layer of the first device region, removing the work function layer of the first device region.
9. The method for forming a semiconductor structure as described in claim 1 or 8, characterized in that, The process for removing the sacrificial layer in the first device region includes a wet etching process or an isotropic dry etching process; The process for removing the work function layer of the first device region includes a wet etching process or an isotropic dry etching process.
10. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the sacrificial layer, the sacrificial layer is also formed in the second device region; After removing the shielding layer, sacrificial layer and power function layer of the first device region, the method further includes: removing the sacrificial layer of the second device region.
11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The process for removing the sacrificial layer from the second device region includes a wet etching process.
12. The method for forming a semiconductor structure as described in claim 10, characterized in that, After removing the masking layer of the second device region; remove the sacrificial layer of the second device region.
13. The method for forming a semiconductor structure as described in claim 1 or 12, characterized in that, The process for removing the shielding layer from the second device region includes an ashing process.
14. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the sacrificial layer, the material of the sacrificial layer includes one or more of silicon oxide, aluminum oxide, and amorphous silicon.
15. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the shielding layer, the material of the shielding layer includes one or both of BARC and SARC.
16. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the gate dielectric layer and the work function layer, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3; The material of the work function layer includes one or more of TiN, TaN, TiAl, TiSiN, and TiAlC.
17. The method for forming a semiconductor structure as described in claim 1, characterized in that, After removing the shielding layer of the second device region, the method of forming the semiconductor structure further includes: forming a gate electrode layer across the channel layer on top of the substrate of the first device region and the second device region, wherein the gate electrode layer in the first device region surrounds and covers the gate dielectric layer, and the gate electrode layer in the second device region surrounds and covers the work function layer.
18. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing a substrate, an interlayer dielectric layer covering the channel structure layer is further formed on the substrate, and a gate opening is formed in the interlayer dielectric layer that spans the channel structure layer, the gate opening exposing a portion of the top and a portion of the sidewalls of the channel structure layer; In the step of forming the gate dielectric layer, the gate dielectric layer is formed on a portion of the top, a portion of the sidewalls, and a portion of the bottom of the channel layer exposed at the gate opening.