Modular radio frequency receive front end with fast power up capability

Abstract

The application provides a modular radio frequency receiving front end with fast power-on capability. The modular radio frequency receiving front end comprises a filtering limiting front end, a switch filtering amplification circuit, a power division circuit, a large dynamic SDLVA circuit and an SDLVA power supply circuit, and is connected with each functional module through an SMP joint to realize modular design, detects the performance of each circuit through multi-stage self-checking, increases the isolation degree between the SDLVA chip and the rear-stage operational amplifier circuit through an operational amplifier, and provides the power supply voltage of the ns level rising edge for the SDLVA detection module, so as to reduce the complexity of the radio frequency signal interconnection and the power supply control wiring of the multi-channel receiving front end, and has the characteristics of modular design, high sensitivity, high reliability, strong universality and the like.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency front-end technology, specifically relating to a modular radio frequency receiving front-end with fast power-on capability. Background Technology

[0002] The radio frequency (RF) receiver front-end is a crucial component of electronic warfare systems and a key factor restricting the design and production of electronic reconnaissance equipment. The RF front-end deployed in electronic reconnaissance equipment is complex in structure and diverse in function, and its performance directly affects various key technical indicators of the equipment. Traditional RF front-ends consist of multiple microwave components, employing a brick-like design where all components are integrated into a single housing, forming a unified whole. This approach is characterized by its multifunctionality and high integration. However, the corresponding functional units are fixed from the initial design stage, hindering generalization and modular design, and increasing the difficulty of BIT (Built-in Test) testing of each stage of the RF front-end circuitry.

[0003] Logarithmic video amplifiers (MVA) are key components for high-speed, accurate microwave pulse measurement. They are commonly used in radar and electronic warfare systems for direction finding and power detection. For example, in radar warning receivers (RWRs) and electronic support measures receivers (ESMs), the angle of arrival (AH) of the received signal can be determined by comparing the amplitude of the received pulse signal. To reduce direction finding errors and simultaneously detect weak and strong signals, a wide dynamic range, high channel consistency, and good linearity between the output voltage and input microwave power are required. MVA generally falls into two categories: Logarithmic Video Amplification (DLVA) and Path-Side Logarithmic Detection Amplification (SDLVA). Currently, most MVA systems use imported state detectors (MBD3057) and imported logarithmic amplifier chips (L-17D), which limits the localization of electronic reconnaissance equipment. Furthermore, SDLVA chips often suffer from issues such as failure to start at low temperatures and backfeeding of video signals from subsequent operational amplifiers, leading to malfunctions and limiting their application scope. Summary of the Invention

[0004] To overcome the shortcomings of existing technologies, this invention provides a modular RF receiver front-end with rapid power-up capability. It includes a filtering and limiting front-end, a switching filter amplifier circuit, a power divider circuit, a large dynamic range SDLVA circuit, and an SDLVA power supply circuit. Modular design is achieved by connecting each functional module through SMP connectors. Multi-stage self-testing is used to monitor the performance of each circuit stage. Operational amplifiers are used to increase the isolation between the SDLVA chip and subsequent operational amplifier circuits. Furthermore, a power supply voltage with a rising edge at the nanosecond level is provided for the SDLVA detection module. This reduces the complexity of RF signal interconnection and power supply control wiring in multi-channel receiver front-ends, and features modular design, high sensitivity, high reliability, and strong versatility.

[0005] A modular radio frequency receiver front-end with fast power-up capability is characterized by comprising: a filter limiting front-end, a switching filter amplifier circuit, a power divider circuit, a large dynamic range SDLVA circuit, and an SDLVA power supply circuit;

[0006] The filtering and limiting front-end includes an RF BMA connector, a filter, a limiter, a first switch, a first low-noise amplifier, an SMP connector, a 5-pin J30J connector, and a power divider. The RF BMA connector is connected to the receiving antenna, receiving radar signals which are transmitted to the filter. The filter filters out out-of-band signals in the useful frequency band before transmitting the signals to the limiter. The limiter performs limiting processing and outputs a low-power signal that the first low-noise amplifier can handle. The first switch includes a single-pole single-throw switch and a single-pole double-throw switch. The single-pole single-throw switch increases the isolation between the single-pole double-throw switch and the limiter. One port of the single-pole double-throw switch serves as a self-test input connected to the SMP connector, and its output is connected to the first low-noise amplifier. The first low-noise amplifier amplifies the received radar signal and outputs it to the switching filter amplifier circuit. The 5-pin J30J connector transmits external input power and control signals to the filtering and limiting front-end. The power divider divides the external self-test sweep signal into several paths and outputs them through the SMP connector to the self-test input of the single-pole double-throw switch, realizing the self-test and calibration functions of the RF receiving front-end.

[0007] The switching filter amplifier circuit includes a second switch, a bandpass filter, and a second low-noise amplifier. The working input terminal of the second switch receives the radio frequency signal output from the filtering and limiting front end, and the self-test input terminal is connected to an external self-test sweep signal to introduce a second-stage self-test. The output terminal of the second switch is connected to the bandpass filter, which filters out out-of-band harmonics and noise. The signal is then amplified by the second low-noise amplifier and output to the power divider circuit one through an SMP connector.

[0008] The power divider circuit divides the RF signal output from the switching filter amplifier circuit into two paths: one path is transmitted to the RF output interface to output the RF signal; the other path is transmitted to the large dynamic range SDLVA circuit.

[0009] The large dynamic range SDLVA circuit includes a power divider circuit II, an SDLVA detector circuit, and an operational amplifier-combiner circuit. The SDLVA detector circuit includes a limiting amplifier, an SDLVA detector module I, an operational amplifier I, an SDLVA detector module II, and an operational amplifier II. The power divider circuit II splits the RF signal output from the power divider circuit I into two paths. One path is output to the limiting amplifier, which amplifies the low-power portion of the signal to the detection dynamic range of the SDLVA detector module I and outputs it to the SDLVA detector module I. The SDLVA detector module I performs detection and video logarithmic amplification processing, outputting the low-power portion corresponding to video signal I. Simultaneously, the limiting amplifier's limiting function limits the input signal to the theoretically designed intermediate splicing power of -30dBm, thereby limiting the maximum level of the video signal I output from the SDLVA detector module I. The operational amplifier I is configured as an emitter follower to isolate the SDLVA detector module I from the operational amplifier-combiner circuit. The power divider circuit II... The other output signal is transmitted to SDLVA detector module 2 via SMP converter. The high-power portion of the input signal is attenuated to the detection dynamic range of SDLVA detector module 2 by an attenuator. After detection and video logarithmic amplification, SDLVA detector module 2 outputs video signal 2 corresponding to the high-power portion. Operational amplifier 2 is set as an emitter follower to isolate SDLVA detector module 2 from the operational amplifier synthesis circuit. Video signal 1 and video signal 2 enter the operational amplifier synthesis circuit after passing through operational amplifier 1 and operational amplifier 2 respectively. The operational amplifier synthesis circuit includes a temperature compensation circuit, an inverting circuit, an adder circuit, and an amplification circuit. The temperature compensation circuit compensates for the noise baseline drift of the two video signals respectively. The inverting circuit changes the two video signals from negative detection signals to positive signals. The adder circuit adds the two positive video signals and their corresponding temperature compensation signals to synthesize them. The amplification circuit amplifies the synthesized video signal and outputs it, obtaining the logarithmic slope of the amplified signal.

[0010] The SDLVA power supply circuit described herein provides a power-on voltage with a rise time of less than 100ns to the large dynamic SDLVA circuit by cascading a comparator, a dual inverter, and a PMOS transistor voltage switch control circuit.

[0011] Specifically, the RF BMA connector of the filtering and limiting front end is directly connected to the receiving antenna, the 5-pin J30J connector is a floating 5-pin blind-fit connector, the SMP connector is a blind-fit connector, the RF BMA connector, J30J connector and SMP connector are precisely positioned by positioning pins, supported by the mounting base, and installed on the same cross section.

[0012] Specifically, the bottom and sides of the filter at the filtering and limiting front end are bonded together with conductive adhesive.

[0013] Specifically, the SDLVA detection circuit of the large dynamic SDLVA circuit is composed of SDLVA detection module one and SDLVA detection module two spliced ​​together, and both SDLVA detection modules use SDLVA chips from Anqiwei Company.

[0014] Specifically, the two SDLVA detector modules of the large dynamic SDLVA circuit adopt an LTCC integrated design, integrating the surrounding bias and matching circuits on a ceramic plate, and sintering the LTCC on a Kovar pad. The input and output terminals are designed with a total of 4 SMP connectors, two of which are used for signal transmission and the other two are used to power the SDLVA detector modules.

[0015] Specifically, the operational amplifiers one and two of the large dynamic range SDLVA circuit have a voltage amplification factor of 1, are common-collector amplifier circuits, and isolate the front and back end circuits.

[0016] Specifically, the SDLVA power supply circuit includes a comparator U1, a dual inverter U2, resistors R1, R2, R3, C1, R4, R5, R6, and a PMOS transistor voltage switch control circuit. The input of the SDLVA power supply circuit is connected to a +5V power supply. The negative input of the comparator U1 is divided by resistors R1 and R2 in series, and the positive input is delayed by an RC circuit composed of resistor R3 and capacitor C1. When the voltage at the positive terminal rises to the voltage at the negative terminal, the comparator U1 outputs a high level. The high level is input to the dual inverter U2 after passing through resistor R4. The dual inverter U2 outputs a low level, which is then fed into the gate of the PMOS transistor voltage switch control circuit U3 after passing through resistor R5. The gate-source voltage VGS is less than the PMOS transistor threshold voltage, so the drain and source of the PMOS transistor are turned on for a time in the nanosecond range, providing the SDLVA chip with a power supply voltage with a rise time in the nanosecond range.

[0017] The beneficial effects of this invention are:

[0018] (1) By connecting the filtering and limiting front end directly to the antenna back end through the BMA connector, the connection loss before the filtering and amplification link can be reduced, the noise figure can be reduced, and out-of-band spurious and noise can be filtered out through the bandpass filter. By bonding the bottom and sides of the bandpass filter with conductive adhesive, good grounding can be achieved and grounding continuity can be improved, in-band fluctuations can be reduced, and system sensitivity can be improved.

[0019] (2) The use of blind-fit connectors such as BMA, SMP and J30J reduces the complexity of the equipment and makes the reliability of the RF front end higher. At the same time, since multi-level self-testing can be performed, the performance of each receiving channel can be detected by injecting a sweep frequency self-test signal through the self-test channel, and the self-test function can be optimized, which can further improve the system reliability. In addition, by connecting an operational amplifier in series between the SDLVA detector module and the subsequent operational amplifier circuit and setting it as an emitter follower, the isolation between the two circuits can be increased, which can further improve the circuit reliability.

[0020] (3) Due to the modular design, it is easy to replace, debug and use in a universal way; due to the use of domestic SDLVA chip to replace imported chip, the large dynamic detection circuit is 100% domestically produced;

[0021] (4) By using a cascaded comparator, dual inverter and PMOS tube voltage switch control circuit, the power-on rise time of the whole equipment can be increased from the ms level to the ns level, which meets the power supply requirements of SDLVA and solves the problem of SDLVA chip not starting at low temperature. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of a modular radio frequency receiver front-end with fast power-on capability according to the present invention;

[0023] Figure 2 This is a schematic diagram of the filtering and limiting front-end structure of the present invention;

[0024] Figure 3 This is a schematic diagram of the installation of the filter limiting front end of the present invention;

[0025] Figure 4 This is a schematic diagram of the switching filter amplifier circuit structure of the present invention;

[0026] Figure 5 This is a schematic diagram of the large dynamic range SDLVA circuit structure of the present invention;

[0027] Figure 6 This is a schematic diagram of the SDLVA detector module design of the present invention;

[0028] Figure 7 This is a schematic diagram of the SDLVA power supply circuit structure of the present invention. Detailed Implementation

[0029] The present invention will be further described below with reference to the accompanying drawings and embodiments. The present invention includes, but is not limited to, the following embodiments.

[0030] like Figure 1As shown, the present invention provides a modular radio frequency receiving front end with fast power-on capability, including: a filtering and limiting front end, a switching filtering and amplification circuit, a power divider circuit, a large dynamic range SDLVA circuit, and an SDLVA power supply circuit.

[0031] like Figure 2 As shown, the filtering and limiting front-end includes an RF BMA connector, a filter, a limiter, a first switch, a first low-noise amplifier, an SMP connector, a 5-pin J30J connector, and a power divider. The RF BMA connector is connected to the receiving antenna, receiving radar signals which are transmitted to the filter. The filter filters out out-of-band signals in the useful frequency band before transmitting the signals to the limiter. The limiter performs limiting processing and outputs a low-power signal that the first low-noise amplifier can handle. The first switch includes a single-pole single-throw switch and a single-pole double-throw switch. The single-pole single-throw switch increases the isolation between the single-pole double-throw switch and the limiter. One port of the single-pole double-throw switch serves as a self-test input connected to the SMP connector, and its output is connected to the first low-noise amplifier. The first low-noise amplifier amplifies the received radar signal and outputs it to the switching filter amplifier circuit. The 5-pin J30J connector transmits external input power and control signals to the filtering and limiting front-end. The power divider divides the external self-test sweep signal into several paths and outputs them through the SMP connector to the self-test input of the single-pole double-throw switch, realizing the self-test and calibration functions of the RF receiving front-end.

[0032] like Figure 3 As shown, the BMA connector at the filter limiting front end is directly plugged into the receiving antenna, eliminating the need for a connecting cable and reducing the link noise figure. The 5-pin J30J connector uses a floating 5-pin blind-mating connector, and the SMP connector also uses a blind-mating connector. The RF BMA connector, J30J blind-mating connector, and SMP blind-mating connector are precisely positioned using locating pins, supported by a mounting base, and installed on the same cross-section. The bottom and sides of the filter at the filter limiting front end are bonded with conductive adhesive to achieve good grounding.

[0033] like Figure 4 As shown, the switching filter amplifier circuit includes a second switch, a bandpass filter, and a second low-noise amplifier. The working input terminal of the second switch receives the RF signal output from the filter limiting front end, and the self-test input terminal is connected to an external self-test sweep signal to introduce the second-stage self-test. The output terminal of the second switch is connected to the bandpass filter, which filters out out-of-band harmonics and noise. The signal is then amplified by the second low-noise amplifier and output to the power divider circuit one through the SMP connector.

[0034] The power divider circuit divides the RF signal output from the switching filter amplifier circuit into two paths. One path is transmitted to the RF output interface to output the RF signal, and the other path is transmitted to the large dynamic range SDLVA circuit.

[0035] like Figure 5As shown, the large dynamic range SDLVA circuit includes a power divider circuit 2, an SDLVA detector circuit, and an operational amplifier-combiner circuit. The SDLVA detector circuit includes a limiting amplifier, an SDLVA detector module 1, an operational amplifier 1, an SDLVA detector module 2, and an operational amplifier 2. The power divider circuit 2 splits the RF signal output from the power divider circuit 1 into two paths. One path is output to the limiting amplifier, which amplifies the low-power portion of the signal to the detection dynamic range of the SDLVA detector module 1 and outputs it to the SDLVA detector module 1. The SDLVA detector module 1 performs detection and video logarithmic amplification, outputting the low-power portion corresponding to video signal 1. Simultaneously, the limiting amplifier's limiting function limits the input signal to the theoretically designed intermediate splicing power of -30dBm, thus limiting the maximum level of the video signal 1 output by the SDLVA detector module 1. The operational amplifier 1 is configured as an emitter follower to isolate the SDLVA detector module 1 from the operational amplifier-combiner circuit. The power divider circuit 2... The other output signal is transmitted to SDLVA detector module two via an SMP converter. An attenuator attenuates the high-power portion of the input signal to the detection dynamic range of SDLVA detector module two. After detection and logarithmic amplification of the video signal, SDLVA detector module two outputs the high-power portion corresponding to video signal two. Operational amplifier two is configured as an emitter follower to isolate SDLVA detector module two from the operational amplifier synthesis circuit. Video signal one and video signal two are then fed into the operational amplifier synthesis circuit after passing through operational amplifier one and operational amplifier two, respectively. The operational amplifier synthesis circuit includes a temperature compensation circuit, an inverting circuit, an adder circuit, and an amplification circuit. The temperature compensation circuit compensates for the noise baseline drift of the two video signals. The inverting circuit converts the two video signals from negative detection signals to positive signals. The adder circuit adds the two positive video signals and their corresponding temperature compensation signals to synthesize them. The amplification circuit amplifies the synthesized video signal and outputs it, obtaining the logarithmic slope of the amplified signal.

[0036] The SDLVA detector circuit of the large dynamic SDLVA circuit can also be composed of SDLVA detector module one and SDLVA detector module two spliced ​​together. The large dynamic function is realized through dynamic splicing. In the SDLVA detector module, the SDLVA chip is the chip of Anqiwei Company (replacing the imported chip).

[0037] like Figure 6 As shown, the SDLVA detector module of the large dynamic SDLVA circuit adopts an LTCC integrated design, integrating the surrounding bias and matching circuits on a ceramic plate. The LTCC is sintered on the Kovar pad. The input and output terminals are designed with a total of 4 SMP connectors. Two SMP connectors (K1 and K2) are used for signal transmission and the other two SMP connectors (K3 and K4) are used for power supply to the SDLVA detector module.

[0038] The operational amplifiers 1 and 2 of the large dynamic range SDLVA circuit have a voltage amplification factor of 1. They are common-collector amplifier circuits with high input impedance and low output impedance. They can transmit the input signal to the back-end circuit accurately, isolate the influence between the front and rear stages, effectively isolate the interference between the front and rear stage circuits, and at the same time enhance the signal driving capability.

[0039] The SDLVA power supply circuit provides a power-on voltage with a rise time of less than 100ns for the large dynamic SDLVA circuit through a cascaded comparator, dual inverters and PMOS transistor voltage switch control circuit, meeting the power supply requirements of SDLVA and solving the problem of SDLVA chip not starting at low temperature.

[0040] Specifically, such as Figure 7 As shown, the SDLVA power supply circuit includes a comparator U1, a dual inverter U2, resistors R1, R2, R3, C1, R4, R5, R6, and a PMOS transistor voltage switch control circuit. The input of the SDLVA power supply circuit is connected to a +5V power supply. The negative input of the comparator U1 is divided by resistors R1 and R2 in series, and the positive input is delayed by an RC circuit composed of resistor R3 and capacitor C1. When the voltage at the positive terminal rises to the voltage at the negative terminal, the comparator U1 outputs a high level (+5V). The high level is input to the dual inverter U2 after passing through resistor R4. The dual inverter U2 outputs a low level (0V), which enters the gate of the PMOS transistor voltage switch control circuit U3 after passing through resistor R5. The gate-source voltage VGS is less than the PMOS transistor threshold voltage, so the drain and source of the PMOS transistor are turned on. The conduction time is on the order of nanoseconds, providing the SDLVA chip with a power supply voltage with a rising edge on the order of nanoseconds.

Claims

1. A modular radio frequency receiver front end with fast power-on capability, characterized in that... include: Filtering and limiting front end, switching filter amplifier circuit, power divider circuit 1, large dynamic range SDLVA circuit and SDLVA power supply circuit; The filtering and limiting front-end includes an RF BMA connector, a filter, a limiter, a first switch, a first low-noise amplifier, an SMP connector, a 5-pin J30J connector, and a power divider. The RF BMA connector is connected to the receiving antenna, receiving radar signals which are transmitted to the filter. The filter filters out out-of-band signals in the useful frequency band before transmitting the signals to the limiter. The limiter performs limiting processing and outputs a low-power signal that the first low-noise amplifier can handle. The first switch includes a single-pole single-throw switch and a single-pole double-throw switch. The single-pole single-throw switch increases the isolation between the single-pole double-throw switch and the limiter. One port of the single-pole double-throw switch serves as a self-test input connected to the SMP connector, and its output is connected to the first low-noise amplifier. The first low-noise amplifier amplifies the received radar signal and outputs it to the switching filter amplifier circuit. The 5-pin J30J connector transmits external input power and control signals to the filtering and limiting front-end. The power divider divides the external self-test sweep signal into several paths and outputs them through the SMP connector to the self-test input of the single-pole double-throw switch, realizing the self-test and calibration functions of the RF receiving front-end. The switching filter amplifier circuit includes a second switch, a bandpass filter, and a second low-noise amplifier. The working input terminal of the second switch receives the radio frequency signal output from the filtering and limiting front end, and the self-test input terminal is connected to an external self-test sweep signal to introduce a second-stage self-test. The output terminal of the second switch is connected to the bandpass filter, which filters out out-of-band harmonics and noise. The signal is then amplified by the second low-noise amplifier and output to the power divider circuit one through an SMP connector. The power divider circuit divides the RF signal output from the switching filter amplifier circuit into two paths: one path is transmitted to the RF output interface to output the RF signal; the other path is transmitted to the large dynamic range SDLVA circuit. The large dynamic range SDLVA circuit includes a power divider circuit II, an SDLVA detector circuit, and an operational amplifier-combiner circuit. The SDLVA detector circuit includes a limiting amplifier, an SDLVA detector module I, an operational amplifier I, an SDLVA detector module II, and an operational amplifier II. The power divider circuit II splits the RF signal output from the power divider circuit I into two paths. One path is output to the limiting amplifier, which amplifies the low-power portion of the signal to the detection dynamic range of the SDLVA detector module I and outputs it to the SDLVA detector module I. The SDLVA detector module I performs detection and video logarithmic amplification processing, outputting the low-power portion corresponding to video signal I. Simultaneously, the limiting amplifier's limiting function limits the input signal to the theoretically designed intermediate splicing power of -30dBm, thereby limiting the maximum level of the video signal I output from the SDLVA detector module I. The operational amplifier I is configured as an emitter follower to isolate the SDLVA detector module I from the operational amplifier-combiner circuit. The power divider circuit II... The other output signal is transmitted to SDLVA detector module 2 via SMP converter. The high-power portion of the input signal is attenuated to the detection dynamic range of SDLVA detector module 2 by an attenuator. After detection and video logarithmic amplification, SDLVA detector module 2 outputs video signal 2 corresponding to the high-power portion. Operational amplifier 2 is set as an emitter follower to isolate SDLVA detector module 2 from the operational amplifier synthesis circuit. Video signal 1 and video signal 2 enter the operational amplifier synthesis circuit after passing through operational amplifier 1 and operational amplifier 2 respectively. The operational amplifier synthesis circuit includes a temperature compensation circuit, an inverting circuit, an adder circuit, and an amplification circuit. The temperature compensation circuit compensates for the noise baseline drift of the two video signals respectively. The inverting circuit changes the two video signals from negative detection signals to positive signals. The adder circuit adds the two positive video signals and their corresponding temperature compensation signals to synthesize them. The amplification circuit amplifies the synthesized video signal and outputs it, obtaining the logarithmic slope of the amplified signal. The SDLVA power supply circuit described herein provides a power-on voltage with a rise time of less than 100ns to the large dynamic SDLVA circuit by cascading a comparator, a dual inverter, and a PMOS transistor voltage switch control circuit.

2. The modular radio frequency receiver front-end with fast power-on capability as described in claim 1, characterized in that: The RF BMA connector of the filtering and limiting front end is directly connected to the receiving antenna. The 5-pin J30J connector is a floating 5-pin blind-mating connector, and the SMP connector is a blind-mating connector. The RF BMA connector, J30J connector and SMP connector are precisely positioned by positioning pins, supported by the mounting base, and installed on the same cross section.

3. The modular radio frequency receiver front-end with fast power-on capability as described in claim 1, characterized in that: The bottom and sides of the filter at the filtering and limiting front end are bonded together with conductive adhesive.

4. The modular radio frequency receiver front-end with fast power-on capability as described in claim 1, characterized in that: The SDLVA detection circuit of the large dynamic SDLVA circuit is composed of SDLVA detection module one and SDLVA detection module two spliced ​​together. Both SDLVA detection modules use SDLVA chips from Anqiwei Company.

5. A modular radio frequency receiver front-end with fast power-on capability as described in claim 1 or 4, characterized in that: The two SDLVA detector modules of the large dynamic SDLVA circuit adopt an LTCC integrated design, integrating the surrounding bias and matching circuits on a ceramic plate. The LTCC is sintered on a Kovar pad. The input and output terminals are designed with a total of 4 SMP connectors. Two SMP connectors are used for signal transmission, and the other two SMP connectors are used to power the SDLVA detector modules.

6. The modular radio frequency receiver front end with fast power-on capability as described in claim 1, characterized in that: The operational amplifiers 1 and 2 of the large dynamic range SDLVA circuit have a voltage amplification factor of 1 and are common-collector amplifier circuits that isolate the front and back end circuits.

7. A modular radio frequency receiver front-end with fast power-on capability as described in claim 1, characterized in that: The SDLVA power supply circuit includes a comparator U1, a dual inverter U2, resistors R1, R2, R3, C1, R4, R5, R6, and a PMOS transistor voltage switch control circuit. The input of the SDLVA power supply circuit is connected to a +5V power supply. The negative input of the comparator U1 is divided by resistors R1 and R2 in series, while the positive input is delayed by an RC circuit composed of resistor R3 and capacitor C1. When the voltage at the positive terminal rises to the voltage at the negative terminal, the comparator U1 outputs a high level. The high level is then input to the dual inverter U2 via resistor R4. The dual inverter U2 outputs a low level, which is then input to the gate of the PMOS transistor voltage switch control circuit U3 via resistor R5. Since the gate-source voltage VGS is less than the PMOS transistor threshold voltage, the drain and source of the PMOS transistor are turned on for a time in the nanosecond range, providing the SDLVA chip with a power supply voltage that has a rise time in the nanosecond range.

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