An adaptive true time delay alignment device for analog quantization
By adopting an analog quantized adaptive real delay alignment device based on a multi-comparator module and a logic decision CNC module in the communication system, the problems of high complexity and high cost of delay alignment in the prior art are solved, and efficient and low-cost signal delay alignment is achieved.
Patent Information
- Application Number
- CN202311111827.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-30
- Publication Date
- 2025-06-17
- Estimated Expiration
- 2043-08-30
AI Technical Summary
The prior art has problems such as algorithm dependence, system vulnerability, high complexity and high cost when eliminating signal time delays, especially in real-time applications or high-speed data processing systems, which are difficult to achieve efficient delay alignment.
An analog quantization adaptive real delay alignment device based on the multi-comparator module and the logic judgment CNC module is adopted. The delay alignment of signals is achieved through the signal input module, the delay module, the peak detection module, the amplitude normalization module, the multiple comparator module, the delay quantization module, the filtering module and the logic judgment CNC module.
It realizes delay alignment with simple structure, low complexity and strong adaptability, and is suitable for a variety of signals and distorted signals, improving system performance and accuracy, and reducing cost and power consumption.
Smart Images
Figure CN117155745B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of communication technologies, and particularly relates to an adaptive true time delay alignment device for analog quantization. Background Art
[0002] In communication and radar systems, signals need to be processed such as filtering and power amplification, but there is always a time delay in the output signal after processing. The time delay of the signal will cause a phase shift in the time domain of the signal. In an actual circuit, such as when a power amplifier performs digital pre-distortion (DPD) processing, the phase difference of the signal will affect the performance and accuracy of DPD. If the time delays between two signals are inconsistent, the collected input and output data will not correspond, and the modeling and pre-distortion processes of DPD will deviate and cannot achieve an excellent linearization effect, resulting in distortion and non-linearity still existing in the PA output signal. Therefore, in the process of digital pre-distortion or other processing that requires relevant analysis of input and output signals, the time delay of the signal must be considered. One solution is to eliminate the signal delay through appropriate synchronization and calibration techniques to ensure that the collected data corresponds correctly, thereby reducing errors and improving system performance.
[0003] Currently, most of the techniques for eliminating signal time delay are achieved through the method of "digital time delay alignment". For different signals, corresponding algorithms or techniques are selected to adjust the moment of the signal, estimate, adjust or compensate for the time offset of the signal, so that the input and output signals are aligned in time. For example, in a radar system, "digital alignment" is achieved by down-converting, digitizing, and algorithmically aligning the received radar echo signal. After the radar echo signal is down-converted and digitized, the algorithm alignment step ensures the alignment of the input and output signals in time, so that accurate processing and analysis of the radar echo signal can be achieved, improving the performance and accuracy of the radar system. However, "digital time delay alignment" currently has the disadvantages of algorithm dependence and system vulnerability, which means that the alignment performance and stability are affected by the algorithm selection and implementation; and because down-conversion digitization requires the use of analog-to-digital converters (DACs), etc., "digital time delay alignment" is not advantageous in terms of complexity and cost. In order to obtain better alignment effects, especially for real-time applications or high-speed data processing systems, high complexity and computational overhead may require more resources and processing capabilities, increasing the cost, complexity, and power consumption of the system.
[0004] At present, the academic community has carried out a series of studies on analog delay alignment. The main implementation methods include delay lines, clock delays, signal processor delays, etc. These analog delays also have the disadvantages of large area and difficulty in integration, high power consumption, lack of adaptive delay alignment, and inability to perform delay alignment on distorted signals. Therefore, the current research focus is on how to design an analog delay alignment that meets accuracy, adjustability, stability, and consistency to meet a large adjustable delay range, and achieve automatic alignment with advantages such as low cost and simple structure. Summary of the Invention
[0005] In view of the problems existing in the digital delay alignment and traditional analog delay alignment proposed in the background technology, the present invention provides an analog quantization-based adaptive true delay alignment device based on a multi-channel comparator module and a logic decision numerical control module. The present invention takes the detection module, multi-channel comparator module, and logic decision numerical control module as the core, statistically analyzes and judges the comparison signals through digital gate circuits, and feeds them back to the delay module after false signal determination to achieve delay alignment, laying a foundation for subsequent circuit signal processing. Compared with digital delay alignment, the present invention has a simple structure, low complexity, and adaptive ability, and can be applied to the delay alignment of various signals and distorted signals, including but not limited to the circuit delay alignment of radio frequency power amplifiers, antenna arrays, and radar signals.
[0006] To achieve the above object, the technical solution of the present invention is as follows:
[0007] An analog quantization-based adaptive true delay alignment device, characterized in that the device includes a signal input module, a delay module, a first peak detection module, a second peak detection module, a first amplitude normalization module, a second amplitude normalization module, a multi-channel comparator module, a delay quantization module, a filtering module, a logic decision numerical control module, and a power amplifier module.
[0008] The signal input module is used to split the input radio frequency signal into two equal-amplitude and in-phase radio frequency signals; among them, the first radio frequency signal is sequentially delayed by the delay module, peak-detected by the first peak detection module, and normalized by the first amplitude normalization module to obtain an amplitude-normalized first signal that has undergone delay processing and contains its envelope information, and finally output to the comparator module; the second radio frequency signal is sequentially amplified by the power amplifier module, peak-detected by the second peak detection module, and normalized by the second amplitude normalization module to obtain an amplitude-normalized second signal that has undergone amplification processing and contains its envelope information, and finally output to the comparator module.
[0009] The multiplex comparator module is composed of N comparator modules with the same structure but different comparison threshold voltages in parallel; each comparator module respectively compares and quantifies the first signal and the second signal, and outputs the first square wave signal and the second square wave signal to the time delay quantization module.
[0010] The time delay quantization module is composed of N exclusive-OR gates and an N-input OR gate; among them, each exclusive-OR gate respectively performs an exclusive-OR operation on the first square wave signal and the second square wave signal under the same reference voltage and outputs to the N-input OR gate for combined statistics, and finally the N-input OR gate outputs a square wave sequence signal to the filtering module.
[0011] The filtering module is used to filter the noise of the square wave sequence signal, and obtain the mean value of the square wave sequence signal as the correlation of the time delay difference between the first signal and the second signal and output it to the logic decision numerical control module.
[0012] The logic decision numerical control module includes a register, a time delay decision comparator, an inverter, and a numerical control module; among them, the register is used to store the voltage value of the mean value of the square wave sequence signal output by the filtering module and output it to the time delay decision comparator as a reference voltage value; the time delay decision comparator is used to receive the mean value of the square wave sequence signal at the next moment output by the filtering module and compare it with the reference voltage value to obtain the comparison result of the time delay difference between the two moments; the inverter reverses the comparison result output by the time delay decision comparator and outputs it to the numerical control module; the numerical control module outputs a time delay control signal according to the reversed comparison result to control the time delay size selection of the delay module, so as to complete the time delay alignment.
[0013] Further, the numerical control module adopts a feedback control method. After each time delay, it judges whether the time delay alignment situation between the first signal and the second signal is optimized through the comparison result after the next inversion; if the reversed comparison result is 1, continue to increase the time delay, if the reversed comparison result is 0, record the current time delay control signal as the optimal control signal, and enter the false signal determination.
[0014] Further, the numerical control module is also set with a judgment condition to prevent false signals: after recording the optimal control signal, continue to increase the time delay and judge the subsequent reversed comparison results; if 0 appears continuously for multiple times, judge that the optimal control signal is true, if 1 appears, judge that the optimal control signal is false, and take this 1 as the standard to find the next optimal control signal again.
[0015] Further, the filtering module adopts a passive low-pass filter.
[0016] Further, the value of N is 3 or 4 or 5.
[0017] In summary, due to the adoption of the above technical solutions, the beneficial effects of the present invention are as follows:
[0018] 1. The present invention obtains the envelope information of two signals through two peak detection modules, and performs multi-bit quantization on the two signals respectively through the multi-channel comparison voltages of the multi-channel comparator module; realizes the conversion of radio frequency signals into digital signals, which is convenient for subsequent time delay determination and control; and has a simple structure, sensitive response, and small signal distortion.
[0019] 2. The two amplitude normalization modules proposed by the present invention are used to perform amplitude normalization processing on the two signals, so that the amplitude of one signal passing through the radio frequency power amplifier corresponds to that of the other signal, avoiding the influence of the gain of the radio frequency power amplifier on the subsequent signal comparison and quantization, and improving the comparison and quantization accuracy of the subsequent comparison circuit.
[0020] 3. The time delay quantization module proposed by the present invention processes the output of the multi-channel comparator module by using digital gate circuits; first performs an exclusive OR operation on the outputs of the two comparators under the same comparison threshold voltage, and then uses an OR gate to combine and statistically analyze the differences between the two signals under different reference voltages, and outputs a square wave sequence signal, which can reflect the time delay information of the two signals, avoiding the decrease in comparison accuracy caused by the radio frequency power amplifier, having low complexity and good accuracy.
[0021] 4. The logic decision numerical control module proposed by the present invention determines whether the time delay amount needs to be increased by comparing the magnitudes of the filtered levels, and then controls the time amount compensated by the delay module through the numerical control module to form a feedback circuit, finally realizing adaptive balance, with simple operation and excellent effects.
[0022] 5. The judgment condition for preventing false signals proposed by the present invention, that is, after recording the optimal control signal, continue to increase the time delay and judge the subsequent comparison results. If 0 appears continuously for multiple times, confirm the optimal control signal. If 1 appears, take this 1 as the standard and re-look for the next 0 to record as the optimal control signal. It can eliminate the error time delay compensation caused by false signals and improve the accuracy of analog time delay alignment.
[0023] 6. An analog quantization adaptive true time delay alignment device proposed by the present invention can align the time delay between a distorted signal after being amplified by a radio frequency power amplifier and another signal. It is manifested that after being controlled by the time delay module, when the time delay quantization voltage is the minimum value, time delay alignment is achieved. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 It is the overall block diagram of the analog time delay alignment device of the present invention.
[0025] Figure 2This is the normal working time-domain waveform and quantization timing diagram of the normalization detection comparator in Embodiment 1 of the present invention.
[0026] Figure 3 This is the normal working timing diagram of the exclusive OR gate in the delay quantization module in Embodiment 1 of the present invention.
[0027] Figure 4 This is the normal working timing diagram of the OR gate and the filtering module in the delay quantization module in Embodiment 1 of the present invention.
[0028] Figure 5 This is the logic block diagram of the logic decision numerical control module in Embodiment 1 of the present invention.
[0029] Figure 6 This is the example diagram of two input signals in Embodiment 2 of the present invention.
[0030] Figure 7 This is the schematic diagram of the output result of the initial two input signals in Embodiment 2 of the present invention after detection, amplitude normalization, and passing through comparator 1.
[0031] Figure 8 This is the output result of the exclusive OR gate in the initial delay quantization module in Embodiment 2 of the present invention.
[0032] Figure 9 This is the initial delay quantization result and the filter result in Embodiment 2 of the present invention.
[0033] Figure 10 This is the example diagram of two input signals after delay alignment in Embodiment 2 of the present invention.
[0034] Figure 11 This is the schematic diagram of the output result of the two input signals after delay alignment in Embodiment 2 of the present invention after detection, amplitude normalization, and passing through comparator 1.
[0035] Figure 12 This is the normal working timing diagram of the exclusive OR gate in the delay quantization module after signal delay alignment in Embodiment 2 of the present invention.
[0036] Figure 13 This is the delay quantization result and the filter result after delay alignment in Embodiment 2 of the present invention. Detailed implementation manners
[0037] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the implementation manners and the accompanying drawings.
[0038] An adaptive true time delay alignment device for analog quantization, characterized in that the device includes a signal input module, a delay module, a first peak detection module, a second peak detection module, a first amplitude normalization module, a second amplitude normalization module, a multi-channel comparator module, a time delay quantization module, a filtering module, a logic decision numerical control module, and a power amplifier module.
[0039] The signal input module is used to split the input radio frequency signal into two radio frequency signals with equal amplitude and the same direction; among them, the first radio frequency signal passes through the input delay module for time delay, the first peak detection module for peak detection, and the first amplitude normalization module for normalization processing in sequence, to obtain the amplitude-normalized first signal after time delay processing and including its envelope information, and finally output it to the comparator module; the second radio frequency signal passes through the power amplifier module for amplification, the second peak detection module for peak detection, and the second amplitude normalization module for normalization processing in sequence, to obtain the amplitude-normalized second signal after amplification processing and including its envelope information, and finally output it to the comparator module.
[0040] The multi-channel comparator module is composed of 3 comparator modules with the same structure but different comparison threshold voltages in parallel; each comparator module respectively compares and quantizes the first signal and the second signal, and outputs the first square wave signal and the second square wave signal to the time delay quantization module.
[0041] The time delay quantization module is composed of 3 exclusive-OR gates and a 3-input OR gate; among them, each exclusive-OR gate respectively performs an exclusive-OR operation on the first square wave signal and the second square wave signal under the same reference voltage and outputs them to the 3-input OR gate for combined statistics, and finally the 3-input OR gate outputs a square wave sequence signal to the filtering module.
[0042] The filtering module is used to filter the noise of the square wave sequence signal, and obtain the mean value of the square wave sequence signal as the correlation of the time delay difference between the first signal and the second signal and output it to the logic decision numerical control module.
[0043] The logic decision numerical control module includes a register, a time delay decision comparator, an inverter, and a numerical control module; among them, the register is used to store the voltage value of the mean value of the square wave sequence signal output by the filtering module, and output it to the time delay decision comparator as a reference voltage value; the time delay decision comparator is used to receive the mean value of the square wave sequence signal at the next moment output by the filtering module, and compare it with the reference voltage value to obtain the comparison result of the time delay difference between the two moments; the inverter reverses the comparison result output by the time delay decision comparator and outputs it to the numerical control module; the numerical control module outputs a time delay control signal according to the reversed comparison result to control the selection of the time delay size of the delay module, so as to complete the time delay alignment.
[0044] The initial state delay module is not working. There is no delay for the two input signals. The second input signal is input into the second peak detector module after passing through the RF power amplifier, and at this time, a time delay will be generated after the signal passes through the RF power amplifier; the first signal is input into the first peak detector module after passing through the delay module; then the peak detection of the above two signals is performed to obtain the envelope information, and then the amplitude normalization is achieved through the amplitude normalization module; the delay module is controlled by comparing the differences in the amplitude information of the two normalized signals.
[0045] In the multi-channel comparator module, the comparison method is as follows: the two signals first perform digital quantization on the detected signals through the comparator, the output with a higher comparison level is 0, and the output with a lower comparison level is 1. At the same time, the quantization results of the two channels are passed through an exclusive-OR gate. If the quantization results are the same, the output is 0, and if the quantization results are different, the output is 1. And to improve the accuracy of the time delay, the multi-channel comparator module performs multi-bit quantization at different comparison threshold voltages, and the output of the multi-channel comparator module passes through the output of the exclusive-OR gate and then through an OR gate and then outputs. The multi-bit quantization results are statistically analyzed and converted into a square wave sequence signal of 0 / 1. The more 1s there are, the greater the quantization difference between the two signals, and adjustment is required.
[0046] Then the filter module obtains the voltage value of the mean of the square wave sequence signal and stores it in the register as the reference voltage of the time delay decision comparator; according to the description of the above square wave sequence signal, the more 1s there are, the greater the time delay between the two signals. Therefore, the mean of the square wave sequence signal with a greater time delay difference will also be greater. By optimizing the time delay of the two signals through the delay module, the mean will become smaller and smaller, and vice versa, the mean will become larger.
[0047] In the time delay decision comparator, the mean of the next moment square wave sequence signal output by the receiving filter module is received and compared with the reference voltage value (the initial reference voltage value in the register is 1); if it is smaller than the previous time, it means that the time delay situation of the two signals has been optimized, and the output of the time delay decision comparator is 0; to be more logical, an inverter is used to change 0 to 1 as the control logic of the subsequent numerical control circuit, but at this time, it is not certain whether it is the optimal situation. The numerical control module controls the delay module to increase the time delay once and records it as 1 in the numerical control module, and so on until the delay quantization size is larger than the previous time, indicating that the time delay deteriorates at this time and is recorded as 0. The previous current time delay control signal of this 0 signal is the optimal control signal. But to prevent false signals, the time delay control signal needs to be continuously increased. If the subsequent two time delays are both deteriorating, it means that the signal before the control signal where the previous 0 signal is located is the optimal control signal. If 1 appears later, it means that the delay of the signal continues to increase, but the time delay does not deteriorate, indicating that the previous 0 is a false signal. At this time, the numerical control module continues to add time delay to find the next 0 signal.
[0048] Principle for preventing false signal judgment: Initially, the first output of the inverter is 1. The first bit of the digital control module first obtains 1 from the delay judgment comparator, causing the delay module to perform a one-unit delay. The second bit starts continuously obtaining values from the delay judgment comparator until the result is 0, i.e., the possible optimal delay alignment situation appears. After that, the digital control module will continue to output 1 to increase the delay. The subsequent output of the delay judgment comparator is ORed with 0. If two consecutive 0s appear, it indicates that the previously appeared 0 meets the requirements and is the optimal delay alignment without false values. Then the digital control module will read the number of this 0 and subtract 1 (the position of the 0 has deteriorated once) to control the delay amount of the delay module; if the result of the OR operation is 1, it means that the previous 0 is a false value. Starting from this 1, the digital control module continues to output 1 to increase the delay to find the next 0 signal. An RF signal is analog-input to the analog delay alignment circuit. In this embodiment, the overall implementation block diagram of the analog delay alignment device is as Figure 1 shown.
[0049] The signal is input to the signal input module, which is composed of a power divider and divides the input signal into two signals with equal amplitude and the same direction; Signal 1 is input to the delay module with a delay of 0, and the output is Signal 1'. Signal 2 is input to the RF power amplifier module, and the output is Signal 2'. Two peak detection modules respectively perform peak detection on Signal 1' and Signal 2 to obtain their envelope signals, denoted as V1 and V2. Assuming the input is 0 dBm, the RF power amplifier is 20 dB, and the impedance is 50 Ω, then the output power is 20 dBm, and the amplitude will increase by 10 times. Therefore, it is necessary to first normalize the amplitudes of the two signals.
[0050] The structural flowchart of the two signals with normalized amplitudes input to the multiplex comparator module is as Figure 2 shown. The two input signals are quantized by three groups of comparison modules at different comparison threshold voltages to provide input for the subsequent delay quantization module.
[0051] The delay quantization module includes an exclusive-OR gate that performs an exclusive-OR operation on the signals obtained by comparing the two signals through a comparator with the same comparison threshold voltage, and an OR gate that performs an OR operation after multiple exclusive-OR operations. After V1' and V2' are compared through a comparator with the same comparison threshold voltage, they first perform an exclusive-OR operation to analyze the differences between the quantized voltages, such as Figure 3As shown. For example, if the quantization results of V1' and V2' are both 1 or both 0, it indicates that the two signals are the same under the quantization with the same comparison threshold voltage. Therefore, the output of the exclusive-OR gate is 0. On the contrary, if the quantization results of V1' and V2' are one 0 and the other 1, it means that the two signals are different under the same comparison threshold voltage and there is a time delay. Therefore, the output of the exclusive-OR gate is 1, representing that there is a time delay between the two signals at this moment. Finally, the outputs of the three exclusive-OR gates are OR-operated to obtain VQ, and the overall time delay information is obtained. As Figure 4 shown. The high level in the VQ square wave sequence represents the existence of a time delay between the two signals. The longer the duration of the high level, the worse the time delay situation, and vice versa, thus achieving the purpose of quantifying the time delay situation between the two signals.
[0052] Filter module. The optimal choice is a second-order passive RC filter, which is used to filter out the noise and interference from the previous stage and calculate the mean value of the output voltage of the time delay quantization module as the input for the subsequent logic judgment module. The mean value calculation is as Figure 4 shown in Valign in. The magnitude of Valign is related to the output of the time delay quantization, that is, the longer the duration of the high level of the time delay quantization square wave sequence signal VQ, the larger the value of Valign, and the shorter the duration of the high level of VQ, the smaller the value of Valign. Therefore, combining the relationship between the output VQ of the above time delay quantization module and the time delay situation, it can be obtained that the larger the value of Valign, the worse the time delay situation between the two signals, and the smaller the value of Valign, the better the time delay situation between the two signals. This is the basis and standard for the subsequent logic decision module to make a decision. When the number of 0s in the quantization results of the two signals is the least, the value of Valign is also the minimum at this time, and the time delay situation between the two signals is the best. This determination logic also applies to distorted signals. If the amplitude is distorted after the signal is amplified by the radio frequency power amplifier, although it cannot be guaranteed that the waveforms are completely aligned after amplitude normalization and time delay alignment, after the above time delay quantization and time delay compensation, the value of Valign can also be guaranteed to be the minimum, that is, the optimal time delay alignment. Therefore, the device can also achieve time delay alignment for distorted signals.
[0053] The specific logic judgment flow chart of the logic decision module is as Figure 5As shown. The numerical control module has 12-bit control by default. After removing 2 bits required for false signal judgment and 1 bit required for triggering false signal judgment, up to 9-bit time delay control can be achieved. Before the numerical control module finds the optimal time delay control signal, the numerical control module will keep increasing the time delay until the optimal time delay control signal is obtained after false signal judgment. Then, the optimal time delay control signal is used to numerically control the delay module and continuously corrected to achieve dynamic balance. The switches of the numerical control module are represented by Y1Y2…Y12, where 1 represents turning on the switch to increase the delay, and 0 represents turning off the switch without delay. Ai is the i-th output of the inverter when the numerical control module is finding the optimal time delay, and Aj is the j-th output of the inverter during false signal judgment. The specific implementation logic is as follows: In the initial state, no time delay processing is performed, and Y1Y2…Y12 are all 0. After two input signals are received, the inverter starts to output Ai, and the numerical control module also starts to continuously increase the time delay and sequentially turn on Y1Y2…Y12 until a certain Ai output is 0, indicating that the optimal time delay value may appear. At this time, the output of the numerical control module is Y1…Yi-1Yi…Y12 = 1…10…0. Then, it enters the false signal judgment module, and the output of Yi remains 1 to increase the time delay. At this time, the output of the inverter is Aj. When Aj is 0 for two consecutive times, it means that increasing the time delay twice in a row will cause the time delay to deteriorate. Therefore, Y1…Yi-1Yi…Y12 = 1…10…0 is the optimal time delay control signal, that is, turning on i-1 mosfet switches to increase the time delay. If Aj is 1 and j is less than or equal to 2, it means that increasing the time delay of the control signal will result in a better time delay situation, that is, the previous Yi being 0 is a false signal and is not used as the control basis for the numerical control module. After that, starting from the i + j bit, continue to increase the time delay to find the number of bits where the next 0 appears, so as to distinguish false signals; this false signal judgment method has a simple logic and can greatly improve the accuracy of the numerical control module. Finally, the output of the numerical control module is Y1…Yi-1Yi…Y12 = 1…10…0, that is, i-1 mosfets are turned on and 13 - i mosfets are not turned on. Then, the system can loop according to the situation, continuously adjust the output of the numerical control module, and thus achieve dynamic control of the time delay of the two signals.
[0054] The delay module is controlled by the numerical control module to switch the MOS transistors. Initially, Y1…Yi-1Yi…Y12 are all 0, corresponding to the switch states of 12 MOS transistors being all off. Then, starting from Y1, the MOS transistors are turned on in sequence. The numerical control module will judge how many MOS transistors need to be turned on to achieve time delay alignment according to the inputs Ai / Aj of the comparator. The technical solution is verified on the Matlab R2022b simulation platform, and the two original input signals are shown in Figure 6 . The quantization results of the two input signals before time delay alignment by Comparator 1 are as shown in Figure 7 , and there are obvious differences in the quantization results; the exclusive OR output results of the outputs of the three comparators are as shown in Figure 8 , and finally the time delay quantization results are as shown in Figure 9As shown, after passing through the filter module, VQ is obtained. VQ is a relatively large DC voltage, indicating that there is a relatively large time delay between the two input signals before alignment. The comparison of the two signals aligned by using the analog time delay alignment circuit of the present invention is shown in Figure 10 , and the quantization result of the two input signals after time delay alignment by comparator 1 is as shown in Figure 11 ; the exclusive OR output result of the outputs of the three comparators is as shown in Figure 12 ; finally, the time delay quantization result is as shown in Figure 13 . The DC level of VQ decreases, and the time delay quantization square wave sequence is almost all 0. The time delay between the two input signals decreases after passing through the analog time delay alignment circuit, achieving time delay alignment.
[0055] As described above, the above are only specific embodiments of the present invention. Any feature disclosed in this specification, unless specifically stated, can be replaced by other equivalent or similar-purpose alternative features; all features disclosed, or all steps in any method or process, except for mutually exclusive features and / or steps, can be combined in any way.
Claims
1. An adaptive true delay alignment device for analog quantization, characterized in that, The device includes a signal input module, a delay module, a first peak detection module, a second peak detection module, a first amplitude normalization module, a second amplitude normalization module, a multi-channel comparator module, a time delay quantization module, a filtering module, a logic decision numerical control module, and a power amplifier module; The signal input module is used to split the input radio frequency signal into two radio frequency signals with equal amplitude and the same direction; among them, the first radio frequency signal is successively delayed by the delay module, peak detected by the first peak detection module, and normalized by the first amplitude normalization module to obtain the amplitude-normalized first signal with delay processing and including its envelope information, and finally output to the comparator module; the second radio frequency signal is successively amplified by the power amplifier module, peak detected by the second peak detection module, and normalized by the second amplitude normalization module to obtain the amplitude-normalized second signal with amplification processing and including its envelope information, and finally output to the comparator module; The multi-channel comparator module is composed of N comparator modules with the same structure but different comparison threshold voltages in parallel; each comparator module respectively compares and quantifies the first signal and the second signal, and outputs the first square wave signal and the second square wave signal to the time delay quantization module; The time delay quantization module is composed of N exclusive-OR gates and an N-input OR gate; among them, each exclusive-OR gate respectively performs an exclusive-OR operation on the first square wave signal and the second square wave signal under the same reference voltage and outputs to the N-input OR gate for combined statistics, and finally the N-input OR gate outputs a square wave sequence signal to the filtering module; The filtering module is used to filter the noise of the square wave sequence signal and obtain the mean value of the square wave sequence signal as the correlation of the time delay difference between the first signal and the second signal and output to the logic decision numerical control module; The logic decision numerical control module includes a register, a time delay decision comparator, an inverter, and a numerical control module; among them, the register is used to store the voltage value of the mean value of the square wave sequence signal output by the filtering module and output it to the time delay decision comparator as a reference voltage value; the time delay decision comparator is used to receive the mean value of the square wave sequence signal at the next moment output by the filtering module and compare it with the reference voltage value to obtain the comparison result of the time delay difference between the two moments; the inverter reverses the comparison result output by the time delay decision comparator and outputs it to the numerical control module; the numerical control module outputs a time delay control signal according to the reversed comparison result to control the time delay size selection of the delay module, so as to complete the time delay alignment.
2. The adaptive true delay alignment device for analog quantization according to claim 1, characterized in that, The numerical control module adopts a feedback control method. After each time delay, it judges whether the time delay alignment situation between the first signal and the second signal is optimized through the comparison result after the next inversion; if the reversed comparison result is 1, continue to increase the time delay, if the reversed comparison result is 0, record the current time delay control signal as the optimal control signal, and enter the false signal determination.
3. The adaptive true delay alignment device for analog quantization according to claim 2, characterized in that, The numerical control module is further provided with a judgment condition for preventing false signals: after recording the optimal control signal, continue to increase the time delay and judge the subsequent reverse comparison result; if multiple 0s appear continuously, it is judged that the optimal control signal is true, if 1 appears, it is judged that the optimal control signal is false, and based on this 1, search for the next optimal control signal again.
4. The adaptive true delay alignment device for analog quantization according to claim 3, characterized in that, The filtering module adopts a passive low-pass filter.
5. The adaptive true delay alignment device for analog quantization according to claim 3, characterized in that, The value of N is 3 or 4 or 5.