Array substrate, manufacturing method thereof and display device

Abstract

An array substrate includes a substrate, a first gate line, a plurality of data lines, a plurality of first pixel electrodes, a plurality of first transistors and a plurality of first capacitor lines disposed on the substrate. A data line crosses and is insulated from a first gate line. A first pixel electrode is located on a first side of the first gate line. A gate electrode, a first electrode and a second electrode of a first transistor are coupled to the first gate line, the data line and the first pixel electrode in sequence. A first capacitor line has an intersection with a first pixel electrode on the substrate; the first capacitor line includes a first conductive segment, the first conductive segment is close to the first gate line, the first conductive segment is provided with a first break, the first break is located on a side of a charging coupling point away from the data line and deviates from a middle portion of the first conductive segment; a portion of the first conductive segment on a side of the first break away from the middle portion and the second electrode of the first transistor have intersections on the substrate.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to an array substrate, a manufacturing method thereof and a display device. BACKGROUND

[0002] In the manufacturing process of an array substrate of a display device (such as a liquid crystal display), the scanning lines (also referred to as gate lines) are often broken. At this time, a repair method of connecting a repair line on both sides of the broken scanning line is usually adopted. However, this repair method is prone to bright spots. SUMMARY

[0003] In one aspect, an array substrate is provided, which includes a substrate and a first gate line, a plurality of data lines, a plurality of first pixel electrodes, a plurality of first transistors and a plurality of first capacitor lines disposed on the substrate.

[0004] The first gate line has a first side and a second side opposite in the width direction of the first gate line. A data line crosses and is insulated from the first gate line. A first pixel electrode is located on the first side of the first gate line. A gate electrode, a first electrode and a second electrode of a first transistor are coupled to the first gate line, the data line and the first pixel electrode in sequence.

[0005] A first capacitor line has an intersection with a first pixel electrode on the substrate; the first capacitor line includes a first conductive segment; the extension direction of the first conductive segment is substantially parallel to the extension direction of the first gate line, and the first conductive segment is close to the first gate line; a first break is provided on the first conductive segment, the first break is located on a side of a charging coupling point away from the data line, and deviates from the middle part of the first conductive segment; the charging coupling point is the coupling position of the first pixel electrode and the second electrode of the first transistor, the middle part of the first conductive segment is the part on the first conductive segment which is in the middle and has a length of 1 / 3 of the total length; the part on the first conductive segment on the side away from the middle part of the first break and the second electrode of the first transistor have an intersection on the substrate.

[0006] In some embodiments, the first break is located on the side of the middle part of the first conductive segment close to the charging coupling point, or the first break is located on the side of the middle part of the first conductive segment away from the charging coupling point.

[0007] In some embodiments, the part on the first conductive segment on the side away from the middle part of the first break, the second electrode of the first transistor and the first pixel electrode have an intersection on the substrate.

[0008] In some embodiments, a groove with an opening facing or away from the first gate line is provided on the first conductive segment, and the groove and the first break are disposed on both sides of the middle part.

[0009] In some embodiments, the part of the first conductive segment on the side of the recess away from the middle and the second electrode of the first transistor have overlapping orthogonal projections on the substrate.

[0010] In some embodiments, the ratio of the width of the remaining part of the first conductive segment to the width of the first conductive segment at the recess is 1 / 3-1 / 2; and / or, the width of the opening of the recess is 7.5-8.5 μm.

[0011] In some embodiments, the length of the part of the first conductive segment on the side of the first breakaway away from the middle is greater than or equal to 15 μm.

[0012] In some embodiments, the first gate line has a first gate line breakaway. The array substrate further includes a first bridge, two ends of the first bridge being connected to the two sides of the first gate line breakaway, the first bridge crossing a first repair capacitor line, the first repair capacitor line being one of the plurality of first capacitor lines. The first repair capacitor line has a first repair breakaway and a second repair breakaway disposed on the two sides of the first bridge, the first repair breakaway being on the first conductive segment; wherein one of the first repair breakaway and the second repair breakaway is the first breakaway, or the first repair breakaway and the second repair breakaway are on the two sides of the first breakaway. The part of the first conductive segment on the side of the first repair breakaway away from the first bridge is coupled to the second electrode of a first repair transistor, the first repair transistor being one of the plurality of first transistors and corresponding to the first repair capacitor line.

[0013] In some embodiments, the first repair capacitor line includes a recess on the first conductive segment. One of the first repair breakaway and the second repair breakaway is at the position of the recess of the first repair capacitor line.

[0014] In some embodiments, the first repair breakaway is between the first bridge and a charging coupling point. At the charging coupling point, the second electrode of the first repair transistor, the pixel electrode and the first repair capacitor line are coupled.

[0015] In some embodiments, the first gate line has a second gate line break. The array substrate further includes a second bridge, two ends of the second bridge being connected to the first gate line on two sides of the second gate line break, the second bridge intersecting with the second repair capacitor line and the third repair capacitor line, the second repair capacitor line and the third repair capacitor line being one of the plurality of first capacitor lines. The second repair capacitor line has a third repair break and a fourth repair break disposed on two sides of the second bridge, the third repair break being located on the first conductive segment; a portion of the first conductive segment located on a side of the third repair break away from the middle portion is coupled to a second electrode of a second repair transistor, the second repair transistor being one of the plurality of first transistors and corresponding to the second repair capacitor line. The third repair capacitor line has a fifth repair break and a sixth repair break disposed on two sides of the second bridge, the fifth repair break being located on the first conductive segment; a portion of the first conductive segment of the third repair capacitor line located on a side of the fifth repair break away from the middle portion is coupled to a second electrode of a third repair transistor, the third repair transistor being one of the plurality of first transistors and corresponding to the third repair capacitor line.

[0016] In some embodiments, the third repair break is a first break of the second repair capacitor line, or the fifth repair break is a first break of the third repair capacitor line.

[0017] In some embodiments, the array substrate further includes a plurality of second pixel electrodes, a plurality of second transistors, and a plurality of second capacitor lines disposed on the substrate. A second pixel electrode is located on the second side of the first gate line. A gate electrode, a first electrode, and a second electrode of a second transistor are sequentially coupled to the first gate line, a data line, and a second pixel electrode. A second capacitor line has an intersection with a second pixel electrode on the substrate.

[0018] In some embodiments, the array substrate further includes a second gate line and a plurality of third transistors disposed on the substrate. A gate electrode of a third transistor is coupled to the second gate line, a first electrode of the third transistor is coupled to a second electrode of the second transistor, and a second electrode of the third transistor has an intersection with the second capacitor line on the substrate.

[0019] In another aspect, a display device is provided, the display device including the display panel described above.

[0020] In yet another aspect, a method for manufacturing an array substrate is provided, the method including:

[0021] forming a first gate line, a plurality of data lines, a plurality of first transistors, and a plurality of first capacitor lines on a substrate; the first gate line having a first side and a second side opposite in a width direction of the first gate line; a data line intersecting and insulating with the first gate line; a gate electrode and a first electrode of a first transistor being sequentially coupled to the first gate line and the data line.

[0022] forming a plurality of first pixel electrodes on the substrate; a first pixel electrode is located on a first side of the first gate line and coupled with a second electrode of the first transistor.

[0023] The first capacitor line includes a first conductive segment, an extension direction of the first conductive segment is substantially parallel to an extension direction of the first gate line, the first conductive segment is close to the first gate line, the first conductive segment is provided with a first break, the first break is located on a side of the charging coupling point away from the data line and deviates from a middle part of the first conductive segment, the charging coupling point is a coupling position of the first pixel electrode and the second electrode of the first transistor, the middle part of the first conductive segment is a part on the first conductive segment which is located in the middle and has a length of 1 / 3 of a total length; a part of the first conductive segment located on a side of the first break away from the middle part and the second electrode of the first transistor have overlapping projections on the substrate.

[0024] In some embodiments, the first gate line has a first gate line break. The method for manufacturing the array substrate further includes:

[0025] A first bridge is arranged on the substrate, two ends of the first bridge are respectively connected on two sides of the first gate line break of the first gate line, the first bridge crosses the first repair capacitor line, and the first repair capacitor line is one of the plurality of first capacitor lines.

[0026] The first repair capacitor line is subjected to at least one cutting treatment to obtain a first repair break and a second repair break which are respectively arranged on two sides of the first bridge, and the first repair break is located on the first conductive segment; one of the first repair break and the second repair break is the first break, or the first repair break and the second repair break are located on two sides of the first break.

[0027] A part of the first conductive segment located on a side of the first repair break away from the middle part is coupled with a second electrode of the first repair transistor, the first repair transistor is one of the plurality of first transistors and corresponds to the first repair capacitor line.

[0028] In some embodiments, the first gate line has a second gate line break; the method for manufacturing the array substrate further includes:

[0029] A second bridge is arranged on the substrate, two ends of the second bridge are respectively connected on two sides of the second gate line break of the first gate line, the second bridge crosses the second repair capacitor line and the third repair capacitor line, and the second repair capacitor line and the third repair capacitor line are respectively one of the plurality of first capacitor lines.

[0030] The second repair capacitor line is subjected to cutting treatment to obtain a third repair break and a fourth repair break which are respectively arranged on two sides of the second bridge, and the third repair break is located on the first conductive segment.

[0031] The part of the first conductive segment of the second repair capacitor line located on the side of the third repair break far from the middle is coupled with the second electrode of the second repair transistor, and the second repair transistor is one of the plurality of first transistors and corresponds to the second repair capacitor line.

[0032] The third repair capacitor line is cut to obtain a sixth repair break; the first break on the third repair capacitor line is a fifth repair break, and the fifth repair break and the sixth repair break are arranged on the two sides of the second bridge.

[0033] The part of the first conductive segment of the third repair capacitor line located on the side of the fifth repair break far from the middle is coupled with the second electrode of the third repair transistor, and the third repair transistor is one of the plurality of first transistors and corresponds to the third repair capacitor line. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly introduced as follows. Obviously, the drawings in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual time sequence, etc. of the product involved in the embodiments of the present disclosure.

[0035] Figure 1 is a sectional view of a display panel according to some embodiments;

[0036] Figure 2 is a partial top view of an array substrate according to some embodiments;

[0037] Figure 3 is a sectional view of Figure 2 is an enlarged view of M1 of

[0038] Figure 4 is an enlarged view of M2 of Figure 3

[0039] is a sectional view along A1A2 of Figure 5 Figure 4

[0040] Figure 6 is a schematic diagram of the position and structure of the first capacitor line in Figure 5

[0041] Figure 7 is a schematic diagram of the position and structure of the first capacitor line according to some other embodiments;

[0042] ​​​Figure 8 a top view of an array substrate after wire breakage repair according to some embodiments;

[0043] Figure 9 a cross-sectional view of the array substrate shown in Figure 8 a close-up view of M3;

[0044] Figure 10 a close-up view of M3 according to some embodiments; Figure 8 a close-up view of M3 according to some embodiments;

[0045] Figure 11 a cross-sectional view of the array substrate shown in Figure 10 a cross-sectional view of the array substrate shown in

[0046] Figure 12 a close-up view of M3 according to some embodiments; Figure 8 a close-up view of M3 according to some embodiments;

[0047] Figure 13 a cross-sectional view of the array substrate shown in Figure 12 a cross-sectional view of the array substrate shown in

[0048] Figure 14 a close-up view of M3 according to some embodiments; Figure 8 a close-up view of M3 according to some embodiments;

[0049] Figure 15 a cross-sectional view of the array substrate shown in Figure 14 a cross-sectional view of the array substrate shown in

[0050] Figure 16A a close-up view of M2 according to some embodiments; Figure 3 a close-up view of M2 according to some embodiments;

[0051] Figure 16B a close-up view of M5; Figure 16A a close-up view of M5;

[0052] Figure 17 a close-up view of M3 according to some embodiments; Figure 8 a close-up view of M3 according to some embodiments;

[0053] Figure 18 a cross-sectional view of the array substrate shown in Figure 17 a cross-sectional view of the array substrate shown in

[0054] Figure 19 a close-up view of M3 according to some embodiments; Figure 8 a close-up view of M3 according to some embodiments;

[0055] Figure 20 a close-up view of M3 according to some embodiments; Figure 8 a close-up view of M3 according to some embodiments;

[0056] Figure 21 Another possible enlarged view of M3 according to some embodiments Figure 8 Another possible enlarged view of M3 according to some embodiments

[0057] Figure 22 Another possible enlarged view of M3 according to some embodiments Figure 8 Another possible enlarged view of M3 according to some embodiments

[0058] Figure 23A Another possible enlarged view of M3 according to some embodiments Figure 8 Another possible enlarged view of M3 according to some embodiments

[0059] Figure 23B Another possible enlarged view of M3 according to some embodiments Figure 8 Another possible enlarged view of M3 according to some embodiments

[0060] Figure 24 Another possible enlarged view of M3 according to some embodiments Figure 8 Another possible enlarged view of M3 according to some embodiments

[0061] Figure 25 Another possible enlarged view of M3 according to some embodiments Figure 8 Another possible enlarged view of M3 according to some embodiments

[0062] Figure 26 Another possible enlarged view of M1 according to some embodiments Figure 2 Another possible enlarged view of M1 according to some embodiments

[0063] Figure 27 Equivalent circuit diagram of Figure 3 Equivalent circuit diagram of

[0064] Figure 28A Top view of an array substrate after wire breakage repair according to some embodiments

[0065] Figure 28B Enlarged view of M6 according to some embodiments Figure 28A Enlarged view of M6 according to some embodiments

[0066] Figure 29 Another possible enlarged view of M6 according to some embodiments Figure 28A Another possible enlarged view of M6 according to some embodiments

[0067] Figure 30 Partial structure diagram of an array panel according to some embodiments

[0068] Figure 31 Flow chart of a method of manufacturing an array substrate according to some embodiments

[0069] Figure 32 Process diagram of array substrate manufacturing according to some embodiments

[0070] Figure 33 Process diagram of array substrate manufacturing according to some embodiments DETAILED DESCRIPTION

[0071] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0072] Unless otherwise required by context, the term "comprise" and its other forms such as "comprises" and "comprising" are to be construed as open, inclusive, meaning that "comprising" means "including, but not limited to." In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to mean that a particular feature, structure, material or characteristic included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0073] Hereinafter, the terms "first", "second" are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0074] In describing some embodiments, "coupled" and "connected" and their derivatives can be used. For example, the term "connected" can be used to describe some embodiments to indicate that two or more components have direct physical or electrical contact with each other. For another example, the term "coupled" can be used to describe some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" can also mean that two or more components have no direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0075] “A, B, and C at least one of” has the same meaning as “at least one of A, B, or C,” and includes the following combinations: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0076] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0077] As used herein, the term “if’ is optionally interpreted as meaning “when” or “upon” or “in response to a determination” or “in response to a detection of,” depending on the context. Similarly, the phrase “if determined” or “if detected [a stated condition or event]” is optionally interpreted as meaning “upon a determination” or “in response to a determination” or “upon a detection of [a stated condition or event]” or “in response to a detection of [a stated condition or event],” depending on the context.

[0078] Use of “adapted to” or “configured to” herein means open and inclusive language that does not exclude devices that are adapted to or configured to perform additional tasks or steps.

[0079] Additionally, use of “based on” means open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values can in practice be based on additional conditions or values beyond those stated.

[0080] As used herein, “about,” “approximately,” or “circa” includes the recited value and average values within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0081] As used herein, “parallel,” “perpendicular,” “equal” includes the recited condition and conditions that approximate the recited condition, the approximation being within an acceptable range of deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallel and near parallel, where near parallel can have an acceptable range of deviation of, e.g., within 5°; “perpendicular” includes absolute perpendicular and near perpendicular, where near perpendicular can also have an acceptable range of deviation of, e.g., within 5°. “Equal” includes absolute equality and near equality, where near equality can have an acceptable range of deviation of, e.g., a difference between the two that is less than or equal to 5% of either.

[0082] It will be appreciated that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present. That is, it can be in contact with the other layer or substrate, or there can be intervening layers present.

[0083] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the layers of components of the devices are shown in the drawings. Therefore, it will be appreciated that variations in the shapes of the layers and regions are to be expected. Thus, the shapes shown are exemplary in nature and are not intended to limit the scope of the exemplary embodiments. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0084] Some embodiments of the present disclosure provide a display device. The display device is a display panel or a product including the display panel. The display panel is a flat panel that can display an image. For example, the display panel can be referred to as a screen, and specifically can be a liquid crystal display panel, an OLED display panel, etc.

[0085] The product including the display panel is a product having an image (including a still image or a dynamic image, where the dynamic image can be a video) display function. For example, the product can be any one of a display, a television, a billboard, a digital photo frame, a laser printer having a display function, a telephone, a mobile phone, a picture screen, a personal digital assistant (PDA), a digital camera, a camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information inquiry device (such as a business inquiry device of an electronic government, a bank, a hospital, a power company, etc.), a monitor, etc.

[0086] The size of the display area of the display panel can be greater than or equal to 65 inches, such as 75 inches, 85 inches, 86 inches, or 90 inches, etc. In an example, the product can include, in addition to the display panel, a mainboard coupled with the display panel. The mainboard is configured to provide image data. The display panel is configured to display a corresponding image in response to the image data.

[0087] Figure 1 A cross-sectional view of the display panel.

[0088] In some embodiments, the display panel is a liquid crystal display panel having a plurality of sub-pixel regions. See Figure 1The display panel includes an array substrate 10, an opposing substrate 20, and a liquid crystal layer 30 disposed between the array substrate 10 and the opposing substrate 20. In some examples, the array substrate 10 includes a pixel electrode and a common electrode located in each sub-pixel region. The pixel electrode and the common electrode are configured to drive a portion of the liquid crystal layer 30 in that sub-pixel region, thereby controlling the light transmittance of that sub-pixel region and thus realizing image display. The opposing substrate 20 may include color filters of various colors, such as red, green, and blue filters. In other examples, the array substrate 10 includes a pixel electrode located in a sub-pixel region, and the opposing substrate 20 includes a common electrode directly opposite the pixel electrode. Similarly, the pixel electrode and the common electrode can control the light transmittance of that sub-pixel region.

[0089] Figure 2 This is a partial top view of the array substrate. Figure 3 for Figure 2 The image shown is an enlarged view of the array substrate at point M1; Figure 4 for Figure 3 The array substrate shown is in Figure 3 A magnified view of point M2. Figure 5 for Figure 4 A sectional view along the A1A2 direction.

[0090] See Figure 2 The array substrate 10 includes a substrate and a first gate line 100, multiple data lines 200, multiple first pixel electrodes 300, multiple first transistors T1, and multiple first capacitor lines 500 disposed on the substrate. The number of first gate lines 100 can be multiple.

[0091] The substrate can be a rigid substrate or a flexible substrate. The rigid substrate includes, for example, at least one of a glass substrate, a PMMA (polymethyl methacrylate) substrate, a quartz substrate, and a metal substrate. The flexible substrate includes, for example, at least one of a PET (polyethylene terephthalate) substrate, a PEN (polyethylene naphthalate dimethyl methacrylate) substrate, and a PI (polyimide) substrate.

[0092] See Figure 3 and Figure 4The first gate line 100 can transmit a gate signal (also referred to as a scan signal), such as a gate-on voltage and a gate-off voltage. For the convenience of description, the extending direction of the first gate line 100 is defined as a first direction X. The width direction of the first gate line 100 is perpendicular to the extending direction of the first gate line 100, and is defined as a second direction Y. The first gate line 100 has a first side and a second side opposite in the width direction of the first gate line 100; for example, the side indicated by the arrow of the second direction Y.

[0093] The material of the first gate line 100 can include at least one of copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and the like, and can also be an alloy composed of some of these metals.

[0094] The data line 200 can transmit a data signal (for example, a data voltage). A data line 200 (for example, each data line 200) crosses and is insulated from the first gate line 100. The extending direction of the data line 200 is arranged at a certain angle with the extending direction of the first gate line 100. For example, the two are perpendicular or substantially perpendicular. Exemplarily, the extending direction of the data line 200 is perpendicular to the extending direction of the first gate line 100. For the convenience of description, the extending direction of the data line 200 is defined as the second direction Y. The material of the data line can refer to the material of the first gate line 100, which is not described here.

[0095] Referring to Figure 4 and Figure 5 , the data line 200 and the first gate line 100 are located in different pattern layers. The first gate line 100 is located in a first pattern layer L1, the data line 200 is located in a second pattern layer L2, and there is an insulating layer (hereinafter referred to as a first insulating layer) L4 between the first pattern layer L1 and the second pattern layer L2, so that the data line 200 is insulated from the first gate line 100. For example, the second pattern layer L2 is located on the side of the first pattern layer L1 away from the substrate BS, that is, above the first gate line 100. For the convenience of description, the vertical direction of the substrate BS is defined as a third direction Z.

[0096] A "pattern layer" can be a layer structure containing a specific pattern formed by using the same film forming process to form at least one film layer, and then using the same mask plate to perform a patterning process on the at least one film layer. According to different specific patterns, the same patterning process can include coating, exposure, development or etching process, and the specific patterns in the formed layer structure can be continuous or discontinuous, and these specific patterns can also be at different heights or have different thicknesses. Multiple patterns belonging to the same pattern layer can be said to be the same layer and the same material.

[0097] Continuing to refer to Figure 3 and Figure 4 The first pixel electrode 300 is configured to generate an electric field in cooperation with the common electrode, and the liquid crystal molecules in the liquid crystal layer corresponding to the first pixel electrode 300 can rotate under the drive of the electric field. The material of the first pixel electrode 300 can include a transparent conductive material such as ITO (indium tin oxide), IZO (indium zinc oxide), etc. The first pixel electrode 300 (for example, each first pixel electrode 300) is located on the first side of the first gate line 100. Specifically, for example, the first pixel electrode 300 is located within one sub-pixel region. For example, the first pixel electrode 300 is located on the first side of the first gate line 100 while being located on the right side of the data line 200.

[0098] Referring to Figure 5 The first pixel electrode 300 can be located on the side of the data line 200 away from the substrate BS, meaning on the side of the second pattern layer L2 away from the substrate BS, i.e., above the second pattern layer L2.

[0099] Continuing to refer to Figure 4 The first transistor T1 can be a thin film transistor (TFT) or a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET, also referred to as MOS tube). For the convenience of description, the following description is taken as an example of the first transistor T1 being a TFT.

[0100] The first transistor T1 can include a gate T13, a first pole T11, and a second pole T12. The first pole T11 of the first transistor T1 can be a drain d, and the second pole T12 can be a source s. Alternatively, the first pole T11 of the first transistor T1 can be a source s, and the second pole T12 can be a drain d. The first transistor T1 can further include a first active layer (not shown in the figure for the sake of clear display of the connection relationship between the transistors), which is coupled (for example, in contact) with the first pole T11 and the second pole T12, respectively.

[0101] The gate T13, the first pole T11, and the second pole T12 of the first transistor T1 (for example, each first transistor T1) are sequentially coupled with the first gate line 100, the data line 200, and the first pixel electrode 300. The gate T13 of the first transistor T1 is coupled with the first gate line 100 to receive a gate signal of the first gate line 100. Exemplarily, the gate T13 of the first transistor T1 can be a part of the first gate line 100; for example, the gate T13 of the first transistor T1 and the first gate line 100 can be an integral pattern of the same layer and the same material, prepared in the same process.

[0102] The first electrode T11 of the first transistor T1 is coupled with the data line 200 to receive a data signal of the data line 200. The first electrode T11 of the first transistor T1 and the data line 200 can be an integral pattern.

[0103] Referring to Figure 4 and Figure 5 The second electrode T12 of the first transistor T1 is coupled with the first pixel electrode 300. The first pixel electrode 300 and the second electrode T12 of the first transistor T1 are located in different layers, for example, the first pixel electrode 300 is located in the third pattern layer L3, the second electrode T12 of the first transistor T1 is located in the second pattern layer L2, the third pattern layer L3 is located above (i.e. away from the substrate BS) the second pattern layer L2, and the third pattern layer L3 and the second pattern layer L2 have an insulating layer (which can be referred to as a second insulating layer L5 herein) therebetween.

[0104] Exemplarily, a via is provided on the second insulating layer L5, and when the first pixel electrode 300 is made, the transparent conductive film is lapped on the second electrode T12 of the first transistor T1 through the via, and then the first pixel electrode 300 is made by etching or other processes. In this way, the second electrode T12 of the first transistor T1 is coupled with the first pixel electrode 300. For ease of description, the coupling position of the first pixel electrode 300 and the second electrode T12 of the first transistor T1 can also be referred to as a charging coupling point 310.

[0105] The gate T13 of the first transistor T1 receives a gate signal of the first gate line 100, and the first transistor T1 is configured to be turned on in response to the gate signal received by the gate T13 being a valid voltage (i.e. gate turn-on voltage), at which time the first active layer of the first transistor T1 is turned on, thereby transmitting the data signal on the data line 200 to the first pixel electrode 300.

[0106] Referring to Figure 4 and Figure 5The first capacitor line 500 and the first gate line 100 may belong to (i.e., be contained in) the same pattern layer, such as the first pattern layer L1. Exemplarily, the first capacitor line 500 and the first pixel electrode 300 may correspond one-to-one. The orthographic projection of the first capacitor line 500 on the substrate BS overlaps with the orthographic projection of the first pixel electrode 300 on the substrate BS. That is, at least a portion of the first capacitor line 500 and a portion of the first pixel electrode 300 are disposed opposite each other in the third direction Z, and the opposite portions form a storage capacitor (CS). The storage capacitor can maintain the voltage on the first pixel electrode 300 used to drive the liquid crystal layer. Exemplarily, the first capacitor line 500 may be an annular pattern or a near-annular pattern (which may be an annular pattern with a break) corresponding to the first pixel electrode. The voltage applied to the first capacitor line 500 can be set according to actual needs. For example, the first capacitor line 500 may be applied with a fixed voltage; or it may be applied with the same voltage as the common electrode, in which case the first capacitor line 500 may be coupled to the common electrode.

[0107] Figure 6 for Figure 5 A schematic diagram showing the location and structure of the first capacitor line.

[0108] See Figure 6 The first capacitor line 500 includes a first conductive segment 510, the extension direction of which is approximately parallel to the extension direction of the first gate line 100, i.e., approximately parallel to the first direction X. The first conductive segment 510 is close to the first gate line 100. When the first capacitor line 500 includes multiple conductive segments, the first conductive segment 510 is closer to the first gate line 100 than the other conductive segments; that is, there are no other conductive segments between the first conductive segment 510 and the first gate line 100.

[0109] The first conductive segment 510 is provided with a first break 514. The first break 514 completely cuts the first conductive segment 510 into two segments. The first break 514 is located on the side of the charging coupling point 310 away from the data line 200 and is offset from the middle part 513 of the first conductive segment 510.

[0110] For example, when the data line 200 is located to the left of the charging coupling point 310, the first break 514 is located to the right of the charging coupling point 310.

[0111] The first conductive segment 510 as a whole comprises a first sub-section 511, a middle section 513 and a second sub-section 512 distributed in sequence along the extension direction of the first conductive segment 510. The middle section 513 of the first conductive segment 510 is a section of the first conductive segment 510 that is located in the middle and has a length of 1 / 3 of the total length. The first sub-section 511 and the second sub-section 512 each have a length that is approximately equal to half of the length of the first conductive segment 510 excluding the middle section 513, i.e., each occupies 1 / 3 of the total length of the first conductive segment 510, and one of them is close to the data line 200 and the other is away from the data line 200. For example, the first sub-section 511 is close to the data line 200 and the second sub-section 512 is away from the data line 200. The first break 514 is offset from the middle section 513 of the first conductive segment 510, meaning that the first break 514 is not located in the middle section 513 of the first conductive segment 510 but in the first sub-section 511 or the second sub-section 512.

[0112] In an example, continuing to refer to Figure 6 , the first break 514 is located on one side of the middle section 513 of the first conductive segment 510 close to the charging coupling point 310, i.e., the first break 514 is arranged in the first sub-section 511. Moreover, the first break 514 is located on the right side of the charging coupling point 310. Specifically, along the first direction X, the first break 514 can be located between the middle section 513 of the first conductive segment 510 and the charging coupling point 310.

[0113] The part of the first conductive segment 510 located on the side of the first break 514 away from the middle section 513 and the second electrode T12 of the first transistor T1 have overlapping projections on the substrate BS.

[0114] Based on Figure 6 the case shown, the part of the first conductive segment 510 located on the side of the first break 514 away from the middle section 513 means the part of the first sub-section 511 away from the middle section 513 delimited by the first break 514, i.e., the left part of the two parts into which the first sub-section 511 is divided by the first break 514.

[0115] Exemplarily, the overlapping area of the left part of the first sub-section 511 and the second electrode T12 of the first transistor T1, both of which have projections on the substrate BS, is referred to as a first overlapping area. The first overlapping area can be configured to couple the first conductive segment 510 and the second electrode T12 of the first transistor T1 together by welding or the like during the repair of the broken line (i.e., the broken first gate line).

[0116] For example, the first overlapping region overlaps (i.e., at least partially overlaps) with the orthographic projection of the charging coupling point 310 on the substrate BS, such as partially or completely overlapping. Therefore, there is an area on the array substrate where the orthographic projections of the first pixel electrode 300, the second electrode T12 of the first transistor T1, and the left side of the first portion 511 overlap on the substrate BS. In other words, the portion of the first conductive segment 510 located on the side of the first break 514 away from the middle portion 513, the second electrode T12 of the first transistor T1, and the first pixel electrode 300 all overlap in their orthographic projections on the substrate BS.

[0117] Based on this, after the broken wire is repaired, along the thickness direction of the substrate BS, the coupling position between the first conductive segment 510 and the second electrode T12 of the first transistor T1 can be aligned with or misaligned with the charging coupling point 310. In the case of misalignment, the coupling position between the first conductive segment 510 and the second electrode T12 of the first transistor T1 can be located on the side of the charging coupling point 310 away from the first break 514 (i.e.,...). Figure 6 (to the left of the charging coupling contact 310), which helps to maintain the characteristic that the first conductive segment 510 is disconnected at the first break 514. At this time, a portion of the first overlapping region can be located on the side of the charging coupling contact 310 away from the first break 514 (i.e., Figure 6 (The left side of the charging coupling contact 310 in the middle).

[0118] For example, the first overlapping region and the orthographic projection of the charging coupling point 310 onto the substrate BS may not overlap. Based on this, at least a portion (i.e., all or part) of the first overlapping region may be located on the side of the charging coupling point 310 away from the first break 514 (i.e., Figure 7 (on the left side of the middle section) to facilitate wire break repair while maintaining the characteristic that the first conductive segment 510 is disconnected at the first break 514.

[0119] Figure 7 This is a schematic diagram showing the location and structure of the first capacitor line in another example.

[0120] See Figure 6 In another example, the first break 514 is located in the second portion 512. Typically, the charging coupling point 310 is located near the data line 200, while the second portion 512 is relatively far from the data line 200. Therefore, the second portion 512 is generally located on the side away from the data line 200 (e.g., the right side of the charging coupling point 310). Thus, the first break 514 is also located on the right side of the charging coupling point 310, that is, the first break 514 is located on the side of the middle 513 of the first conductive segment 510 away from the charging coupling point 310.

[0121] and Figure 7Similar to the array substrate shown, the portion of the first conductive segment 510 located on the side of the first break 514 away from the middle 513 and the second pole T12 of the first transistor T1 have overlapping orthogonal projections on the substrate BS.

[0122] based on Figure 6 In the case shown, the portion of the first conductive segment 510 located on the side of the first break 514 away from the middle portion 513 means the portion of the second portion 512 that is away from the middle portion 513 with the first break 514 as the boundary, that is, the right-hand portion of the two portions into which the second portion 512 is divided by the first break 514.

[0123] For example, the overlapping region of the right side portion of the second segment 512 and the second electrode T12 of the first transistor T1, as projected onto the substrate BS, is called the second overlapping region. The second overlapping region can be configured to couple the first conductive segment 510 to the second electrode T12 of the first transistor T1 together by means of welding or similar methods during the repair of the broken wire (i.e., the broken first gate wire). In this case, the second electrode T12 of the first transistor T1 can extend from the charging coupling point 310 along the first direction X to the right side of the first break 514 to form the second overlapping region.

[0124] In some embodiments, the structure of multiple sub-pixel regions (e.g., all sub-pixel regions) on the array substrate can refer to the above description. Figure 7 or Figure 8 At this point, the multiple first grid lines 100 (e.g., each first grid line 100) are not broken and require no repair.

[0125] In other embodiments, due to complex manufacturing processes and the influence of environmental foreign objects or electrostatic discharge, at least one (or more) broken first gate lines (referred to as broken lines) may exist on the array substrate. That is, at least one first gate line may have a gate line break, causing these first gate lines to disconnect at the gate line breakage location. In this case, multiple sub-pixels in a row driven by the first gate line will fail to display correctly. Bridging can be used to repair this situation. The repaired array substrate will be described in detail below.

[0126] Figure 9 This is a top view of an array substrate after wire breakage repair. Figure 8 for Figure 8 of Figure 9 A magnified view of the area at position M3. (For...) Figure 8 The structure shown is clearly visible. Only a small portion of the second electrode T12 of the first transistor T1 is retained, while the rest shown in DD is omitted.

[0127] In one possible implementation, see Figure 8The array substrate 10 is provided with a bridge 600 at the position of the gate line break 110 of the first gate line 100 Figure 9 The charging coupling point and other structures for repairing the array substrate are omitted in the figure, and the repair break is described below. The bridge 600 is a conductive wire, which can include tungsten (W), silver (Ag), or the like. In order to weaken the adverse effects of the factors causing the gate line break 110 of the first gate line 100 on the bridge 600, the bridge 600 does not directly cover the first gate line 100 in the extension direction (i.e., the first direction X) of the first gate line 100. The two ends of the bridge 600 are connected on both sides of the gate line break 110 and bypass the area of the gate line break 110, so that the first gate line 100 is restored to be conductive.

[0128] Therefore, the bridge 600 can include a plurality of bridge segments. For example, referring to Figure 9 The bridge 600 includes a first bridge segment 610, a second bridge segment 620, and a third bridge segment 630 connected in sequence. The first bridge segment 610 is close to the data line 200, and the third bridge segment 630 is away from the data line 200. The first bridge segment 610 and the third bridge segment 630 are respectively arranged on both sides of the gate line break 110. The first bridge segment 610 and the third bridge segment 630 are respectively connected to the first gate line 100 at one end and connected to the second bridge segment 620 at the other end. For example, the first bridge segment 610 and the third bridge segment 630 are perpendicular to the first gate line 100, so as to bypass the gate line break 110. The extension directions of the first bridge segment 610 and the third bridge segment 630 are different from the extension direction of the first capacitor line 500, so as to cross each other.

[0129] Due to different lengths and distribution positions of the gate line break 110, the bridge 600 can be arranged at different positions, and the bridge 600 can pass through one sub-pixel region or more than two sub-pixel regions.

[0130] For example, Figure 5 In the case shown in FIG. 6, the length of the gate line break 110 is relatively short, and the gate line break 110 is located near the middle portion 513 of the first capacitor line 500. Therefore, the bridge 600 can only pass through one sub-pixel region, i.e., cross one first capacitor line 500. For ease of description, the bridge 600 is named as a first bridge 600A, and the corresponding gate line break 110 is named as a first gate line break 111.

[0131] In this implementation, the broken first gate line 100 is repaired. If the bridge 600 is not connected to the first capacitor line 500 (for example, the bridge 600 and the first capacitor line 500 can be insulated from each other by an insulating layer), the bridge 600 has little effect on the sub-pixel region where the bridge 600 is located. However, since the bridge 600 and the first capacitor line 500 have overlapping orthographic projections on the substrate BS, the bridge 600 and the first capacitor line 500 can be connected in series (for example, no insulating layer can be arranged between the bridge 600 and the first capacitor line 500, as shown in FIG. 7).Figure 10 The bridge 600 can be set to the same potential as the first gate line 100 after the first pattern layer L1 is formed and before the first insulating layer L4 is formed, which will affect the display of each sub-pixel area corresponding to the first gate line 100 (i.e., each first pixel electrode 300 coupled to the first gate line 100). To solve this problem, the present disclosure provides the following examples.

[0132] Example One

[0133] Figure 8 Another possible enlarged view of M3. Figure 11 A cross-sectional view along B1B2. Figure 10 A cross-sectional view along B1B2. Figure 10 Referring to

[0134] On the array substrate 10, the first gate line 100 has a first gate line break 111, and the array substrate 10 further includes a first bridge 600A. The two ends of the first bridge 600A are respectively connected to the two sides of the first gate line break 111 on the first gate line 100. The first bridge 600A crosses the first repair capacitor line 500A. The first repair capacitor line 500A is one of a plurality of first capacitor lines 500; for example, the plurality of first capacitor lines 500 are the first capacitor lines 500 in all sub-pixel areas corresponding to the first gate line 100. Among them, all sub-pixel areas corresponding to the first gate line 100 are the sub-pixel areas where all first pixel electrodes 300 are coupled to the first gate line 100 through a plurality of first transistors. Specifically, among the plurality of first capacitor lines 500, the first capacitor line 500 closest to the first gate line break 111 is the first repair capacitor line 500A. Figure 10 Because the first bridge 600A crosses the first repair capacitor line 500A (specifically, it can cross the first conductive segment 510 of the first repair capacitor line 500A), the first gate line 100 and the first repair capacitor line 500A can be conductive and short-circuit. Therefore, the first repair capacitor line 500A has a first repair break 551 and a second repair break 552 disposed on the two sides of the first bridge 600A; in this way, the part of the first repair capacitor line 500A that crosses the first bridge 600A (hereinafter referred to as the first part D1, which can be conductive with the first bridge 600A) is cut off from the other part (hereinafter referred to as the second part D2), so that the other part (hereinafter referred to as the second part D2) is not conductive with the first bridge 600A.

[0135] Exemplarily,

[0136] In the above-mentioned examples, the first repair break 551 is located on the first conductive segment 510, and one of the first repair break 551 and the second repair break 552 is the first break 514 Figure 6 Or Figure 7 Figure 8 ​In the embodiment, the first breakage 514 is formed on the first capacitor line 500 itself; that is, the first breakage 514 is formed at the same time when the first capacitor line 500 is etched). Which one of the first repair breakage 551 and the second repair breakage 552 is the first breakage 514 can be determined by the position and shape of the first breakage on the first capacitor line 500 in the sub-pixel area corresponding to the first gate line which does not need to be repaired; and can also be determined by the position and shape of the first breakage on the first capacitor line 500 in the sub-pixel area (for example Figure 10 In the sub-pixel area M4, the first breakage on the first capacitor line 500 can be determined by the position and shape of the first breakage on the first capacitor line 500 in the sub-pixel area corresponding to the first gate line which does not need to be repaired.

[0137] Taking the first breakage 514 located in the first section 511 as an example, in the case that the distance between the first gate line breakage 111 and the first breakage 514 is sufficient to set the first bridge body section 610 of the first bridge 600A, the first breakage 514 can be used as a repair breakage (for example, the first repair breakage 551).

[0138] Continuing to refer to Figure 10 Taking the first breakage 514 located in the first section 511 as an example, in the case that the distance between the first gate line breakage 111 and the first breakage 514 is sufficient to set the first bridge body section 610 of the first bridge 600A, the first breakage 514 can be used as a repair breakage (for example, the first repair breakage 551).

[0139] Taking the first breakage 514 located in the first section 511 as an example, in the case that the distance between the first gate line breakage 111 and the first breakage 514 is sufficient to set the first bridge body section 610 of the first bridge 600A, the first breakage 514 can be used as a repair breakage (for example, the first repair breakage 551).

[0140] The first part D1 of the first repair capacitor line 500A and the first bridge 600A form a capacitor A1 with the first pixel electrode 300. The second part D2 of the first repair capacitor line 500A and the first pixel electrode 300 form another capacitor A2. In the case of charging two capacitors, the phenomenon of bright spots (that is, bright spots appear in the sub-pixel area) occurs. In order to achieve the purpose of darkening, the two plates of the capacitor that cause bright spots need to be coupled so that the voltage between the plates is equal, so that the capacitor is disabled, and thus the bright spots disappear.

[0141] In some embodiments, the length of the first portion D1 can be less than the length of the second portion D2. In this way, the capacitor A2 has a greater effect on the bright spot of the sub-pixel region than the capacitor A1. Therefore, the darkening operation can be performed on the second portion D2. Therefore, in the embodiments of the present disclosure, the second portion D2 of the first repair capacitor line 500A of a sub-pixel region is coupled with the first pixel electrode 300, i.e., they have the same potential, thereby realizing the darkening of the sub-pixel region.

[0142] In addition, in the present example, since both the first repair break 551 and the second repair break 552 are located on the first conductive segment 510, this helps to make the first portion D1 of the first repair capacitor line 500A as short as possible and the second portion D2 as long as possible, thereby being able to reduce the capacitance of the capacitor A1, while disabling the capacitor A2 with a larger capacitance through the darkening operation, thereby enhancing the darkening effect of the sub-pixel region. In order to perform the darkening processing on the sub-pixel region where the first bridge 600A is located, the connection between the first pixel electrode 300 and the data line 200 in the sub-pixel region can be disconnected, so that the data line 200 cannot provide the data signal to the first pixel electrode 300.

[0143] The first repair transistor T1A is one of the plurality of first transistors T1 and corresponds to the first repair capacitor line 500A. The first repair transistor T1A corresponding to the first repair capacitor line 500A means that the first pixel electrode 300 opposite to the first repair capacitor line 500A is coupled with the first repair transistor T1A.

[0144] The second electrode T12 of the first repair transistor T1A is provided with a transistor break AA1 at a position close to the first electrode T11 of the first repair transistor T1A at the charging coupling point 310, so as to disconnect the connection between the first pixel electrode 300 and the data line 200. In Figure 9 In order to clearly show the structure, part of the structure of the second electrode T12 of the first repair transistor T1A (the omitted part corresponds to the part shown in Figure 8 M3 of FIG. 3) is also omitted, and the remaining Figure 10 possible enlarged view of M3 of FIG. 3 all omit this part of the structure.

[0145] Referring to Figure 11 and Figure 11To realize the coupling of the second portion D2 of the first repair capacitor line 500A and the first pixel electrode 300, in the array substrate, the portion of the first conductive segment 510 on the first repair fracture 551 far away from the first bridge 600A (for example, the left portion of the first sub-portion 511 of the first conductive segment 510) is coupled with the second pole T12 of the first repair transistor T1A; for example, the two can be coupled by laser fusion; specifically, the laser fusion can be performed on the portions of the two that are opposite to each other (i.e., the portions of the two whose orthographic projections on the substrate completely overlap). For the convenience of description, the coupling position of the two is defined as a fusion coupling point 320. Since the charging coupling point 310 is located on the second portion D2 of the first repair capacitor line 500A; thus, the second portion D2 of the first repair capacitor line 500A is coupled with the second pole T12 of the first repair transistor T1A. Since the first pixel electrode 300 is coupled with the second pole T12 of the first repair transistor T1A at the charging coupling point 310, the first pixel electrode 300 is coupled with the second portion D2 of the first repair capacitor line 500A, so that the capacitor A2 formed by the two is disabled, thereby realizing the darkening of the sub-pixel area.

[0146] The fusion coupling point 320 can be formed in any one of the following modes:

[0147] For example, mode one: after the first gate line 100 is formed and the first gate line fracture 111 is found, and after the second pole T12 of the first repair transistor T1A is formed, before the first pixel electrode 300 is formed, laser fusion is performed downward at the selected fusion coupling point 320, so that the second pole T12 of the first repair transistor T1A and the portion of the first conductive segment 510 on the first repair fracture 551 far away from the first bridge 600A are fused together.

[0148] For another example, mode two: after the first pixel electrode 300 is formed, the first pixel electrode 300 formed has a notch, and laser fusion is performed downward at the position of the notch, so that the second pole T12 of the first repair transistor T1A and the portion of the first conductive segment 510 on the first repair fracture 551 far away from the first bridge 600A are fused together, i.e., the fusion coupling point 320 opposite to the notch is formed.

[0149] For another example, mode three: after the first pixel electrode 300 is formed, at the selected fusion coupling point 320, the first pixel electrode 300, the second pole T12 of the first repair transistor T1A, and the portion of the first conductive segment 510 on the first repair fracture 551 far away from the first bridge 600A have opposite portions (i.e., the orthographic projections of the three on the substrate overlap at the selected fusion coupling point 320); then, laser fusion is performed downward to fuse the opposite portions of the three together.

[0150] In some possible implementations, such as Figure 12 As shown, the orthographic projections of the fusion coupling point 320 and the charging coupling point 310 on the substrate overlap (e.g., at least partially overlap). For example, the orthographic projection of the fusion coupling point 320 on the substrate may lie within the orthographic projection of the charging coupling point 310 on the substrate. In this case, the area of ​​the fusion coupling point 320 is less than or equal to that of the charging coupling point 310. For example, using the above-described method three, a laser is used to fuse downwards at the charging coupling point 310, fusing the first pixel electrode 300, the second electrode T12 of the first repair transistor T1A, and the second portion D2 of the first repair capacitor line 500A together (i.e., coupling the three together) to form the fusion coupling point 320. Since the first pixel electrode 300 and the second electrode T12 of the first repair transistor T1A are already coupled together at the charging coupling point 320, this method allows the laser to achieve coupling of the three without breaking through the second insulating layer L5, thereby reducing the difficulty of fusion.

[0151] The second portion D2 of a first repair capacitor line 500A and a first repair transistor T1A can be coupled through one or more fusion coupling points 320. The diameter of a single fusion coupling point is 2.5μm to 3.5μm, for example, 2.5μm, 3μm, 3.5μm, etc. The fusion success rate of a single fusion coupling point is related to the distance between the two patterned layers to be fused; when the distance between the two patterned layers to be fused is small, the fusion success rate is high. Conversely, when the distance between the two patterned layers to be fused is large, the fusion success rate is low. The distance between the third patterned layer L3 and the second patterned layer L2 is greater than the distance between the second patterned layer L2 and the first patterned layer L1; therefore, the success rate of fusion between the third patterned layer L3 and the second patterned layer L2 is lower than the success rate of fusion between the second patterned layer L2 and the first patterned layer L1.

[0152] In the case that the success rate of the fusion of the single fusion coupling point 320 is high, the number of the fusion coupling points 320 for coupling the second part D2 of the first repair capacitor line 500A with the first repair transistor T1A can be one. For example, the array substrate is fused downward by laser at a point position in the region where the charging coupling point 310 is located. In this way, the coupling requirement can be met, and the sum of the areas of all the fusion coupling points 320 for coupling the second part D2 of the first repair capacitor line 500A with the first repair transistor T1A is small. In the process of designing and manufacturing the array substrate, the size of the first break 514 on the first conductive section 510 of the first capacitor line 500 is unchanged, and the area of the region reserved for the fusion coupling points 320 is smaller, and the size of the first conductive section 510 of the first capacitor line 500 that can be used to set the first bridge 600A is longer, thereby being able to repair the first gate line break 111 with a longer size.

[0153] In the case that the success rate of the fusion of the single fusion coupling point 320 is low, the number of the fusion coupling points 320 for coupling the second part D2 of the first repair capacitor line 500A with the first repair transistor T1A can be two or more. For example, the array substrate is fused downward by laser at multiple positions in the region where the charging coupling point 310 is located, so as to improve the overall fusion success rate.

[0154] In the present example, the first break 514 is used as a repair break (for example, the first repair break 551) as a break structure configured on the first repair capacitor line 500 itself. In this way, the number of repair breaks on the first repair capacitor line 500A set by processing, such as cutting, is reduced by one, thereby improving the repair efficiency of the array substrate. Moreover, compared with setting the first break 514 (for example, the first repair break 551) on other conductive sections, the first break 514 on the first conductive section 510 can make the length of the first part D1 in the first repair capacitor line 500A relatively shorter than the second part D2, without changing the position of another repair break (for example, the second repair break 552). In this way, the influence of the first part D1 on darkening can be reduced. In addition, without changing the position of another repair break (for example, the second repair break 552), since the first break 514 deviates from the middle of the first conductive section 510, the part (that is, the first part D1) of the first conductive section 510 for crossing the first bridge 600A can be allowed to have a longer size, and accordingly, the first bridge 600A is allowed to have a longer size (specifically, the length of the second bridge body section 630 can be longer), thereby being able to repair the first gate line break 111 with a longer size.

[0155] Example Two

[0156] Figure 8 Another possible enlarged view of M3. Figure 13 Another possible enlarged view of M3. Figure 12 Another possible enlarged view of M3. Figure 12 A cross-sectional view of the array substrate along the C1C2 direction.

[0157] Referring to Figure 13 and Figure 13 Example Two gives another implementation of the part of the first conductive segment 510 on the side of the first repair break 551 away from the first bridge 600A being coupled with the second pole T12 of the first repair transistor, and other structures on the array substrate can refer to Example One.

[0158] In this example, the first break 514 is on the first part 511 of the first repair capacitor line 500A and serves as the first repair break 551. Based on this, the fusion coupling point 320 is on the first part 511 of the first repair capacitor line 500A on the side of the first repair break 551 away from the first bridge 600A; for example, the fusion coupling point 320 is on the side of the first repair break 551 on the first part 511 close to the data line 200, i.e., on the left part of the first part 511.

[0159] Illustratively, the fusion coupling point 320 and the charging coupling point 310 do not overlap in orthographic projection on the substrate BS (i.e., they are staggered). In this way, the area of the fusion coupling point 320 is not limited by the area of the charging coupling point 310, and at this time, a proper number of fusion coupling points 320 can be selected for fusion in the area where the left part of the first part 511 and the second pole T12 of the first repair transistor T1A are directly opposite (i.e., the area occupied by the part where the orthographic projections of the two on the substrate overlap). In addition, even if there is some positional offset error in the fusion coupling point 320, it will not affect the coupling performance of the charging coupling point 310, thereby reducing the requirement for the accuracy of the fusion process, i.e., reducing the difficulty of fusion.

[0160] For example, the fusion coupling point 320 can be on the side of the first part 511 away from the first break 514 of the charging coupling point 310 (i.e., on the left part of the first part 511), which can reduce the impact of fusion on the open circuit characteristic of the first repair break 551.

[0161] In addition, in this example, the fusion coupling point 320 can be formed in any of the three ways of Example One; different from Example One, the fusion coupling point 320 is adjusted in position and is staggered with the charging coupling point 310. Among them, Figure 14The structure of forming the fusion coupling point 320 in the manner one of example one is shown. In the example, the second pole T12 of the first repair transistor T1A and the left part of the first section 511 of the first repair capacitor line 500A can be fused together to realize coupling. And the first pixel electrode 300 and the second pole T12 of the first repair transistor T1A have been coupled at the charging coupling point 310. In this way, the first pixel electrode 300 and the second part D2 of the first repair capacitor line 500A are indirectly coupled, so that the potentials of the two are equal, thereby realizing the darkening of the sub-pixel area. In addition, the other effects achieved by the present example are the same as those of example one, which will not be described here.

[0162] Example three

[0163] Figure 8 For Figure 15 Another possible enlarged view of M3. Figure 14 For Figure 14 The array substrate shown in the cross-sectional view along the F1F2 direction.

[0164] Referring to Figure 15 And Figure 15 Example three gives another implementation of the part of the first conductive segment 510 on the side away from the first bridge 600A being coupled (for example, in contact) with the second pole T12 of the first repair transistor T1A, and other structures on the array substrate can refer to example one.

[0165] In the present example, the first fracture 514 is located on the first section 511 of the first repair capacitor line 500A and serves as the second repair fracture 552. At this time, during the repair process, the first repair fracture 551 can be formed on the first conductive segment 510 by laser cutting or the like, and the first repair fracture 551 is away from the data line 300 compared with the second repair fracture 552. At this time, the first repair fracture 551 can be disposed on the middle part 513 or the second section 512 of the first conductive segment 510 according to the length of the first bridge 600A.

[0166] Based on this, the fusion coupling point 320 is located on the side of the first conductive segment 510 away from the first bridge 600A, which means that the fusion coupling point 320 is located on the right side of the first conductive segment 510, that is, on the side of the first conductive segment 510 away from the data line 200. At this time, the fusion coupling point 320 and the charging coupling point 310 are disposed on the two sides of the first bridge 600A, therefore, the setting of the fusion coupling point 320 will not affect the electrical connection performance of the charging coupling point 310. Therefore, during the formation of the fusion coupling point 320, a larger positional offset error can be allowed, thereby reducing the requirement for the accuracy of the fusion process, that is, reducing the difficulty of fusion.

[0167] In addition, in the present example, the fusion coupling point 320 can be formed in any one of the three manners of Example One; different from Example One, the fusion coupling point 320 is adjusted in position and is arranged in a staggered manner with the charging coupling point 310. Wherein, Figure 16A A structure in which the fusion coupling point 320 is formed in the manner one of Example One is shown.

[0168] In the present example, at the fusion coupling point 320, the second pole T12 of the first repair transistor T1A and the second part D2 of the first repair capacitor line 500A are fused together, realizing coupling. And the first pixel electrode 300 and the second pole T12 of the first repair transistor T1A have been coupled at the charging coupling point 310. In this way, the first pixel electrode 300 and the second part D2 of the first repair capacitor line 500A are indirectly coupled, so that their potentials are equal, thereby realizing the darkening of the sub-pixel area. In addition, the other effects that can be achieved by the present example are the same as those of Example One, and will not be described here.

[0169] Example Four

[0170] In order to facilitate the setting of the repair fracture formed by cutting off on the first conductive segment, the present example also provides another array substrate.

[0171] Figure 3 For Figure 3 In Figure 16A Another possible enlarged view of M2.

[0172] In some possible implementation manners, the array substrate provided by the present example can not have a fractured first gate line 100, at this time, the shape of the first capacitor line 500 in the plurality of sub-pixel areas in the array substrate can refer to Figure 16A .

[0173] In other possible implementation manners, the array substrate provided by the present example has at least one fractured first gate line 100, at this time, the shape of the first capacitor line 500 in some sub-pixel areas (at least one sub-pixel area, that is, a sub-pixel area other than the sub-pixel area where the fracture part of the first gate line 100 is located) in the array substrate can refer to Figure 16A . For example, Figure 8 The first capacitor line 500 shown can replace the first capacitor line 500 in the sub-pixel area M4 in Figure 16A Referring to Figure 16A , the present disclosure provides an array substrate, and the first conductive segment 510 is provided with a groove 515 with an opening facing or away from the first gate line 100. Figure 16A Taking the opening of the groove 515 facing the first gate line 100 as an example. Figure 4 In Figure 4Based on the existing design, groove 515 has been added; other features remain the same. Figure 10 The corresponding embodiments will not be described in detail. The function of the groove 515 is to facilitate the cutting of the first conductive segment 510 at the groove 515, thereby serving as a repair cut in the wire break repair process. Therefore, if the array substrate does not need to be repaired, or if the array substrate needs to be repaired but the location of the repair cut is not at the groove 515 of the first conductive segment 510, the groove 515 of the first conductive segment 510 may not need to be cut.

[0174] The groove 515 may be recessed approximately along the width direction (e.g., the second direction Y) of the first grid line 100, such that the depth direction of the groove 515 is approximately perpendicular to the extension direction of the first grid line 100 (e.g., the first direction X). The shape of the groove 515 is not specifically limited, and may be, for example, a rectangular groove, an arc-shaped groove, etc.

[0175] Repairing the broken surface (e.g., Figure 12 and Figure 14 The second repair fracture 552 in the middle, Figure 16A The first repair cut (551) can be located at the groove 515 of the first conductive segment 510. The first conductive segment 510 is narrower at the groove 515, making it easier to cut, thus improving cutting efficiency and the repair efficiency of the array substrate. Furthermore, for example, a relatively low-energy laser can be used for cutting, thereby reducing the potential impact on components near the groove 515 (e.g., the first gate line 100 or the third bridge segment 630 affecting the first bridge 600A) during the cutting process. Similarly, a narrow-beam laser can be used for cutting, again reducing the potential impact on components near the groove 515 during the cutting process. Specifically, when the opening of the groove 515 faces the first gate line 100, the distance between the first conductive segment 510 and the first gate line 100 at the groove 515 increases, further reducing the impact on the first gate line 100 when cutting the first conductive segment 510 at the groove 515.

[0176] The groove 515 and the first break 514 are respectively located on both sides of the middle portion 513. That is, the groove 515 and the first break 514 are located in the first portion 511 and the second portion 512 of the first conductive segment 510, respectively. For example, the groove 515 is located in the first portion 511, and the first break 514 is located in the second portion 512. Or, for example... Figure 16A As shown, the groove 515 is located in the second portion 512, while the first break 514 is located in the first portion 511.

[0177] See also Figure 10, specifically, in the present example, the first breakage 514 is located at the first sub-portion 511, and thus the groove 515 is located at the second sub-portion 512. After the first gate line 100 is broken, the first conductive segment 510 can be cut at the groove 515 to form a repair breakage, and the first breakage 514 serves as another repair breakage, to obtain a repaired structure similar to Figure 12 、 Figure 14 or Figure 16B shown. Since both repair breakages are located on the first conductive segment 510, the length of the first portion D1 in the first capacitor line 500 can be further reduced, and the length of the second portion D2 is relatively longer.

[0178] In some embodiments, a portion of the first conductive segment 510 located on a side of the groove 515 away from the middle portion 513 and the second electrode T12 of the first transistor T1 have overlapping projections on the substrate. In this case, when line breakage repair is needed, the first conductive segment 510 can be cut at the groove 515 to form a first repair breakage, so that a portion of the first conductive segment 510 located on a side of the first repair breakage away from the middle portion 513 is coupled to the second electrode T12 of the first repair transistor (a first transistor T1).

[0179] Figure 16A a partial enlarged view of M5 shown. Figure 16B

[0180] Referring to Figure 16A , a portion of the first conductive segment 510 located below the groove 515 is a reserved portion of the first conductive segment 510. The width W1 of the reserved portion and / or the width W2 of the opening of the groove 515 will affect the performance of the first conductive segment 510 and the performance of the array substrate 10 to some extent. For example, the ratio of the width W1 of the reserved portion of the first conductive segment 510 to the width W3 of the first conductive segment 510 at the groove 515 is 1 / 3-1 / 2. For example, the width W2 of the opening of the groove 515 is 7.5-8.5 μm. For another example, the ratio of the width W1 of the reserved portion of the first conductive segment 510 to the width W3 of the first conductive segment 510 is 1 / 3-1 / 2, and the width W2 of the opening of the groove 515 is 7.5-8.5 μm.

[0181] The width W3 of the first conductive segment 510 is the width of the first conductive segment 510 without the groove 515, which can be calculated by adding the depth W4 of the groove 515 and the width W1 of the reserved portion, or when the width of the first conductive segment 510 is substantially the same or does not change much in the first extension direction, the width of the first conductive segment 510 at a position adjacent to the groove 515 is measured.

[0182] ​The width W3 of the first conductive segment 510 can be 11.0 μm to 15.0 μm, for example, 11.2 μm, 13.4 μm, 14.6 μm, 15.0 μm, etc. In this way, the width W3 of the first conductive segment 510 is relatively wide, and the first conductive segment 510 has relatively more space to set the charging coupling point 310 and the fusion coupling point 320.

[0183] The fusion coupling point 320 is formed by laser fusion downward above the first capacitor line 500 after the first capacitor line 500 is formed. The diameter of a single fusion coupling point 320 is 2.5 μm to 3.5 μm, and the width W3 of the first conductive segment 510 is more than twice the diameter of a single fusion coupling point 320. In this way, the first conductive segment 510 has more space to set the fusion coupling point 320, and the fusion coupling point 320 is less likely to deviate out of the first conductive segment 510, which helps to improve the success rate of fusion and reduces the positioning accuracy requirement when laser fusion, thereby reducing the processing difficulty.

[0184] In the case where the ratio of the width W1 of the retained portion of the first conductive segment 510 to the width W3 of the first conductive segment 510 is 1 / 3 to 1 / 2, the width W1 of the retained portion of the first conductive segment 510 is appropriate, such as 3.7 μm to 8.5 μm, for example, 3.7 μm, 6.2 μm, 7.8 μm, and 8.5 μm. In this way, the retained portion of the first conductive segment 510 is easy to cut off and has high strength and is less likely to break, and the resistance value is also appropriate.

[0185] In the case where the width of the opening of the groove 515 is 7.5 μm to 8.5 μm, the width of the groove 515 is appropriate, which facilitates laser alignment with the groove 515 to cut off the retained portion, and the length of the retained portion is appropriate, so that the retained portion has high strength and is less likely to break.

[0186] Referring to FIG. 16, in some embodiments, the length of the portion of the first conductive segment 510 located on the side of the first fracture 514 away from the middle portion 513 is greater than or equal to 15 μm. For example, Figure 16A In some embodiments, the first fracture 514 is located on the first sub-portion 511 of the first conductive segment 510, and in this case, the left portion (see Example One or Example Two) of the first sub-portion 511 can have a fusion space for setting a fusion coupling point. In another example, the first fracture 514 can also be located on the second sub-portion 512 of the first conductive segment 510, and in this case, the portion of the second sub-portion 512 located on the right side of the first fracture 514 can have a fusion space for setting a fusion coupling point.

[0187] Specifically in the present example, the diameter of the single fusion coupling point is 2.5 μm to 3.5 μm, and the fusion space on the first conductive section 510 can allow at least two fusion coupling points to be arranged, thereby increasing the success rate of fusion between the portion of the first conductive section 510 located on the side of the first fracture 514 away from the middle portion 513 and the second electrode T12 of the first transistor T1.

[0188] It can be understood that, referring to Figure 16A In the case where the first fracture 514 is located on the second sub-portion 512, the length of the right portion of the second sub-portion 512 should be as short as possible, i.e., the first fracture 514 is located as close to the right side of the first conductive section 510 as possible, on the premise that the right portion of the second sub-portion 512 serves as a fusion space to meet the success rate requirement of fusion. In this way, the size of the first conductive section 510 of the first capacitor line 500 that can be used to arrange the first bridge 600A can be longer, thereby being able to adapt to the repair of a first gate line fracture 111 of a longer size.

[0189] Similarly, in the case where the first fracture 514 is located on the first sub-portion 511, the length of the left portion of the first sub-portion 511 should be as short as possible, i.e., the first fracture 514 is located as close to the left side of the first conductive section 510 as possible, on the premise that the left portion of the first sub-portion 511 serves as a fusion space to meet the success rate requirement of fusion. In this way, the size of the first conductive section 510 of the first capacitor line 500 that can be used to arrange the first bridge 600A can be longer, thereby being able to adapt to the repair of a first gate line fracture 111 of a longer size.

[0190] Referring to Figure 16A In other embodiments, the length of the portion of the first conductive section 510 located on the side of the recess 515 away from the middle portion 513 is greater than or equal to 15 μm.

[0191] For example, Figure 17 In the case where the first fracture 514 is located on the first sub-portion 511 of the first conductive section 510, the portion of the first conductive section 510 located on the side of the recess 515 away from the middle portion 513 is the portion of the second sub-portion 512 located on the right side of the recess 515, which can have a fusion space (see Example Three) for arranging a fusion coupling point.

[0192] For another example, the first fracture 514 can also be located on the second sub-portion 512 of the first conductive section 510, and the portion of the first conductive section 510 located on the side of the recess 515 away from the middle portion 513 is the portion of the first sub-portion 511 located on the left side of the recess 515, which can have a fusion space (see Example One or Example Two) for arranging a fusion coupling point.

[0193] The effect of this embodiment can refer to the effect that the length of the portion of the first conductive segment 510 located on the side of the first break 514 away from the middle portion 513 is greater than or equal to 15 μm.

[0194] Example Five

[0195] Figure 8 Another possible enlarged view of M3. Figure 18 An array substrate shown in Example Four along the E1E2 direction. Figure 17 An array substrate shown in Example Four along the E1E2 direction. Figure 17 An array substrate shown in Example Four along the E1E2 direction. Refer to Figure 18 and Figure 16A This example provides an array substrate having at least one broken first gate line 100, which is based on Figure 17 The structure of the sub-pixel region shown in Example Four is repaired for the broken first gate line 100.

[0196] As in the above embodiments (e.g., Example One, Example Two, or Example Three), a first bridge 600A is needed to repair the first gate line 100, and the first capacitance line 500 in the sub-pixel region where the first bridge 600A is located is referred to as a first repair capacitance line 500A. The first repair capacitance line 500A has a first repair break 551 and a second repair break 552 disposed on opposite sides of the first bridge 600A, and the first repair break 551 is located on the first conductive segment 510. One of the first repair break 551 and the second repair break 552 is the first break 514. The first repair break 551 and the second repair break 552 divide the first repair capacitance line 500A into a first portion D1 and a second portion D2, and the second portion D2 is coupled with the first pixel electrode 300 to form a fusion coupling point 320. Figure 18 and Figure 17 The fusion coupling point 320 formed with reference to the above-mentioned Example One is shown. The formation of the fusion coupling point 320 can also refer to the above-mentioned Example Two or Example Three, which will not be described here. Other structures in this sub-pixel region can also refer to the above-mentioned Example One, Example Two, or Example Three.

[0197] Unlike these examples, the first repair capacitance line 500A contains a groove 515 located on the first conductive segment 510. The position and size of the groove 515 can refer to Example Four.

[0198] Furthermore, as mentioned above, if one of the first repair break 551 and the second repair break 552 is the first break 514, then the other can be located at the location of the groove 515 of the first repair capacitor line 500A. For example, a repair break can be formed by using a laser to cut off the remaining portion at the groove 515 of the first conductive segment 510, which is easier to cut and less likely to damage other components. At this time, since both the first break 514 used as a repair break and the other repair break formed at the groove 515 are located on the first conductive segment 510, the length of the first part D1 can be shorter than the length of the second part D2, which is beneficial to the dark spot effect of the sub-pixel area.

[0199] For example, Figure 14 In this structure, the first break 514 is located in the first portion 511 and can be used as the first repair break 551; the groove 515 is located in the second portion 512, and the repair break formed by the groove 515 can be used as the second repair break 552. It should be noted that if the size of the break point at which the retained portion at the groove 515 is cut is similar to the opening width of the groove 515, then it is difficult to determine whether the second repair break 552 is located at the groove 515 by only looking at the structure within that sub-pixel area. In this case, the position of the second repair break 552 can be determined by combining the position of the groove 515 within the sub-pixel area without bridging.

[0200] In this embodiment, the effect of the array substrate is the same as in Example 1, and will not be repeated here.

[0201] In the above embodiments, see, for example, [reference needed]. Figure 17 or Figure 17 In the array substrate after wire breakage repair, both the first repair break 551 and the second repair break 552 are located on the first conductive segment 510, and one of them is the first break 514, while the other needs to be cut to form it. In some cases, see Figure 19 When the size of the first grid line break 110 is large, the size of the first bridge 600A along the first direction X is also long. For example, the third bridge body segment 630 of the first bridge 600A may need to be moved to the right side of the groove 515. At this time, the first conductive segment does not have enough space on the right side of the groove 515 to set the second repair break.

[0202] To address this issue, this disclosure also provides another array substrate, see [link to relevant documentation]. Figure 19 ,in, Figure 8 for Figure 17 Another possible enlarged view of the M3. Compared to Figure 19In the example, the specific position of the first bridge 600A is adjusted. Based on this, the first break 514 is used as the first repair break 551, and the second repair break 552 is moved from the second section 512 to the other conductive section of the first repair capacitor line 500A.

[0203] Continuing to refer to Figure 20 The first repair capacitor line 500A further includes a second conductive section 520 and a third conductive section 530. The second conductive section 520 is connected to the first conductive section 510 at the end of the first section 511, and the third conductive section 530 is connected to the first conductive section 510 at the end of the second section 512. In this case, the second repair break 552 can be located in the second conductive section 520 or the third conductive section 530 that is farther away from the first break 514.

[0204] The width of the first conductive section 510, the width of the second conductive section 520, and the width of the third conductive section 530 can be the same or different. The width of the second conductive section 520 is the length of the second conductive section 520 perpendicular to the direction of its extension. The width of the third conductive section 530 is the length of the third conductive section 530 perpendicular to the direction of its extension.

[0205] Since the second conductive section 520 and the third conductive section 530 do not need to be provided with the charging coupling point 310 and the fusion coupling point, and it can be necessary to cut off the repair break during the repair of the array substrate, the width of the second conductive section 520 and the width of the third conductive section 530 can be relatively small. In some embodiments, the width of the second conductive section 520 and the width of the third conductive section 530 can be the same and smaller than the width of the first conductive section 510. For example, the width of the second conductive section 520 and the width of the third conductive section 530 can be equal to the width of the reserved portion of the first conductive section 510, for example, 6 μm to 8 μm. In this way, the second conductive section 520 and the third conductive section 530 are easy to cut off and have high strength and are not easy to break, and the resistance value is also appropriate.

[0206] In particular, in this example, the second repair break 552 is provided on the third conductive section 530. The specific arrangement can refer to the way of providing the first repair break 551 by cutting off the first conductive section 510, which will not be described here.

[0207] In this way, the first repair break 551 and the second repair break 552 are located on the two sides of the first bridge 600A, respectively, and the first repair capacitor line 500A is also divided into two parts, the first part D1 crosses the first bridge 600A, and the second part D2 can be coupled to the first pixel electrode 300 as in Example 1 or Example 2.

[0208] The effect of the array substrate in this embodiment is the same as that in Example One, and will not be described here again.

[0209] Figure 8 For Figure 20 Another possible enlarged view of M3. See Figure 14 In some other embodiments, the first repair capacitor line 500A further includes a fourth conductive segment 540. The fourth conductive segment 540 is substantially parallel to the first conductive segment 510 and is disposed between the second conductive segment 520 and the third conductive segment 530. For example, one end of the fourth conductive segment 540 is connected to the midpoint of the second conductive segment 520, and the other end is connected to the midpoint of the third conductive segment 530. The fourth conductive segment 540 can increase the capacitance value between the first repair capacitor line 500A and the first pixel electrode 300. The width of the fourth conductive segment 540 can refer to the width of the second conductive segment 520 and the width of the third conductive segment 530, and will not be described here again.

[0210] In this way, in the sub-pixel region corresponding to the first gate line that does not need to be repaired in the array substrate, the voltage between the first capacitor line 500 and the first pixel electrode 300 can be better maintained, thereby driving the liquid crystal layer 30 to work.

[0211] Example Six

[0212] Examples One to Five all provide technical solutions in which the first break is used as a repair break. For example, see Figure 21 In the sub-pixel region of the array substrate, the first break 514 is used as the second repair break 552. This example will introduce the case where the first break 514 is not used as a repair break.

[0213] Figure 21 Another possible enlarged view of M3.

[0214] See Figure 21 For example, one of the two endpoints (e.g., the left endpoint) of the first gate line break 111 is too close to the first break 514, and there is not enough space to dispose the first bridge 600A (e.g., the first bridge body segment 610 of the first bridge 600A) between the two. For another example, the two endpoints of the first gate line break 111 can also be disposed on the two sides of the first break 514. In these cases, in order to repair the broken first gate line 100, for example, the first bridge body segment 610 of the first bridge 600A can be moved to the left side of the first break 514 or to the position of the first break 514. At this time, since the first break 514 cannot be located outside the first bridge 600A, it cannot be used as a repair break to divide the first repair capacitor line 500A into two parts (the first part D1 and the second part D2). Therefore, some other embodiments of the present application provide an array substrate 10, which continues to refer to Figure 22In the present embodiment, the first repair capacitor line 500A has the first repair break 551 and the second repair break 552 disposed on two sides of the first bridge 600A, and the first repair break 551 is located on the first conductive segment 510. Except for the specific positions of the first bridge 600A and the second repair break 552, other features can refer to Example Three.

[0215] Different from Example Three, in the present example, the first repair break 551 and the second repair break 552 are located on two sides of the first break 514.

[0216] For example, the first break 514 is located on the first sub-portion 511 of the first conductive segment 510. In this case, the first repair break 551 can be disposed on the first conductive segment 510 (e.g., the second sub-portion 512 or the middle portion 513) according to the size of the first bridge 600A along the first direction X, and the second repair break 552 can be disposed on the second conductive segment 520.

[0217] The manner of disposing the first repair break 551 can also refer to Example Three, and in addition, the first repair break 551 can be made by, for example, laser cutting at the position where the first conductive segment 510 (e.g., the second sub-portion 512) is provided with the groove 515. The second repair break 552 can be disposed on the second conductive segment 520 by cutting, for example, laser cutting.

[0218] In this way, the first repair break 551 and the second repair break 552 are respectively located on two sides of the first bridge 600A and on two sides of the first break 514. The first repair break 551 and the second repair break 552 also divide the first repair capacitor line 500A into two parts, a first part D1 crossing the first bridge 600A and a second part D2 which can refer to Example Three and be coupled to the first pixel electrode 300.

[0219] The effect of the array substrate in the present embodiment is the same as that in Example Three, and will not be described here.

[0220] The array substrate repaired by the broken line provided in the above embodiments is taken as an example where the first break is located on the first sub-portion. Some other embodiments of the present disclosure further provide an array substrate, and the first break on the array substrate is located on the second sub-portion.

[0221] Example Seven

[0222] Figure 22 Another possible enlarged view of M3.

[0223] Reference Figure 22In another embodiment of the present application, an array substrate 10 is provided. In this embodiment, the first break 514 is located at the second sub-portion 512. When the array substrate has at least one broken first gate line 100, the array substrate needs to be repaired; as in the above embodiments, the first repair capacitor line 500A needs to be provided with the first repair break 551, the second repair break 552, the first bridge 600A and the fusion coupling point 320.

[0224] In the array substrate, the first repair break 551 is located on the first conductive segment 510, and one of the first repair break 551 and the second repair break 552 is the first break 514.

[0225] Exemplarily, Figure 23A In this embodiment, the first repair break 551 can be provided between the first bridge 600A and the charging coupling point 310 by cutting off, for example, the first repair break 551 is located on the first sub-portion 511 of the first conductive segment 510. Based on this, the fusion coupling point 320 is located on the first conductive segment 510 on the side (i.e. the left side) away from the first bridge 600A of the first repair break 551, and the specific position can be referred to in Example One and Example Two. Accordingly, the first break 514 serves as the second repair break 552.

[0226] Exemplarily, the first break 514 can serve as the first repair break 551. Based on this, the fusion coupling point 320 is located on the first conductive segment 510 on the side (i.e. the right side) away from the first bridge 600A of the first repair break 551, and the specific position can be referred to in Example Three. Accordingly, the second repair break 552 can be provided between the first bridge 600A and the charging coupling point 310 by cutting off, for example, the first repair break 551 is provided on the first sub-portion 511 of the first conductive segment 510.

[0227] The effects that can be achieved by the array substrate are the same as those in Example One, which will not be described here.

[0228] Example Eight

[0229] Figure 3 For Figure 23A Another possible enlarged view of M2.

[0230] Similar to the case of Example Four, see Figure 23A This example provides an array substrate, which is provided with a groove 515 on the first conductive segment 510, the groove 515 has an opening facing or away from the first gate line, and the groove 515 and the first break 514 are located on the two sides of the middle portion 513. For example, the first break 514 is located at the second sub-portion 512, and then the groove 515 is provided at the first sub-portion 511. Except that the position of the groove 515 is different from that in Example Four, other features of the groove can be referred to the related description in Example Four.

[0231] In some possible implementation manners, the first gate line on the array substrate is not broken, and the structure of the plurality of sub-pixel regions on the array substrate can be referred to Figure 23B .

[0232] Figure 8 For another possible enlarged view of M3 in Figure 23B .

[0233] In some possible implementation manners, the first gate line on the array substrate is not broken, and the structure of the plurality of sub-pixel regions on the array substrate can be referred to Figure 23A , the array substrate has at least one broken first gate line 100, and the structure of the sub-pixel region shown in Figure 23B is repaired for the broken first gate line 100. Similar to example five, the repair of the array substrate can utilize the groove 515. One of the first repair fracture 551 and the second repair fracture 552 is located at the position of the groove 515 of the first repair capacitor line 500A; the other one can be the first fracture 514, for example.

[0234] Exemplarily, Figure 24 , the setting of the fusion coupling point 320 can refer to example one or example two, and the repair fracture formed at the groove 515 is the first repair fracture 551, and the first fracture 514 is used as the second repair fracture 552.

[0235] Exemplarily, the setting of the fusion coupling point 320 can refer to example three, and the repair fracture formed at the groove 515 is the second repair fracture 552, and the first fracture 514 is used as the first repair fracture 551.

[0236] The effect of the array substrate in this embodiment is the same as that in example one, which will not be repeated here.

[0237] Example nine

[0238] Figure 24 For another possible enlarged view of M3.

[0239] Referring to Figure 24 , similar to example six, in the case that the first fracture 514 is located in the second part 512 and the groove 515 is located in the first part 511, the repair fracture at the groove 515 can not be needed.

[0240] Based on this, the embodiment of the present disclosure provides another array substrate, referring to Figure 23B , compared with Figure 25In this example, the specific position of the first bridge 600A is adjusted. Based on this, the first break 514 is used as the first repair break 551, and the setting of the fusion coupling point 320 can refer to Example Three. And the second repair break 552 is moved from the first conductive section 510 (for example, the first sub-section 511) to other conductive sections (for example, the second conductive section 520) of the first repair capacitor line 500A.

[0241] The effect of the array substrate in this embodiment is the same as that in Example Three, and will not be repeated here.

[0242] Example Ten

[0243] Figure 8 For Figure 25 Another possible enlarged view of M3.

[0244] Referring to Figure 25 Similarly to Example Six, in the case where the first break 514 is located in the second sub-section 512 and the groove 515 is located in the first sub-section 511, there is also a case where the first break 514 cannot be used as a repair break.

[0245] Based on this, this example provides an array substrate, referring to Figure 26 In this embodiment, the first repair capacitor line 500A has a first repair break 551 and a second repair break 552 disposed on both sides of the first bridge 600A, and the first repair break 551 is located on the first conductive section 510. In addition to the specific positions of the first bridge 600A and the second repair break 552, other features can refer to Example Eight.

[0246] Different from Example Eight, in this example, the first repair break 551 and the second repair break 552 are located on both sides of the first break 514. For example, the first break 514 is located in the second sub-section 512 of the first conductive section 510. In this case, the first repair break 551 can be disposed on the first conductive section 510 (for example, the first sub-section 511 or the middle section 513) according to the size of the first bridge 600A along the first direction X, and the second repair break 552 is disposed on the third conductive section 530.

[0247] The way of setting the first repair break 551 can also refer to Example Three, in addition, the first repair break 551 can be made by, for example, laser cutting at the position where the groove 515 is provided on the first conductive section 510 (for example, the first sub-section 511). The second repair break 552 can be disposed on the third conductive section 530 by cutting, for example, laser cutting.

[0248] Thus, the first repair break 551 and the second repair break 552 are located on both sides of the first bridge 600A and on both sides of the first break 514. The first repair break 551 and the second repair break 552 also divide the first repair capacitor line 500A into two parts, a first part D1 crossing the first bridge 600A and a second part D2 which can be coupled to the first pixel electrode 300 as in Example 1 or Example 2.

[0249] The array substrate in this embodiment has the same effect as in Example 1, which will not be repeated here.

[0250] In some embodiments, a plurality of rows of sub-pixel regions are arranged one-to-one corresponding to a plurality of first gate lines, and a scan signal transmitted on each first gate line determines the charging timing of a corresponding row of sub-pixel regions.

[0251] In other embodiments, the number of rows of sub-pixel regions can be twice the number of first gate lines, and a scan signal transmitted on each first gate line determines the charging timing of two adjacent rows of sub-pixel regions.

[0252] Figure 2 For Figure 26 Another possible enlarged view of M1. Figure 3 And Figure 3 Both show a structure in which one first gate line corresponds to two rows of sub-pixel regions. Among them, Figure 26 shows a case where the first gate line 100 is not broken, Figure 26 shows a case where the first gate line 100 is broken. Among them, Figure 26 The first gate line 100 can be repaired by any of the above repair methods after being broken, that is, Figure 27 The structure of the sub-pixel region below can refer to any of the above structures of the sub-pixel region provided with the first bridge.

[0253] Figure 3 For Figure 3 Equivalent circuit diagram.

[0254] Referring to Figure 26 (or Figure 27 ) and Figure 27 , the array substrate 10 further includes a plurality of second pixel electrodes 800, a plurality of second transistors T2, and a plurality of second capacitor lines 400 arranged on the substrate.

[0255] A (for example, each) second pixel electrode 800 is located on the second side (for example, the side indicated by the arrow of the second direction Y) of the first gate line 100. Based on this, the second pixel electrode 800 can be arranged opposite to a first pixel electrode 300; for example, the two are arranged on both sides of the first gate line 100 and coupled to the same data line 100, at this time, the sub-pixel regions where the two are located can be located in the same column (that is, can be arranged along the second direction Y).

[0256] The material of the second pixel electrode 800 can refer to the material of the first pixel electrode 300, for example, both can be the same.

[0257] The gate T13, the first electrode T11 and the second electrode T12 of the second transistor T2 are sequentially coupled with the first gate line 100, the data line 200 and the second pixel electrode 800.

[0258] The functions of the gate T13, the first electrode T11 and the second electrode T12 of the second transistor T2 can refer to the functions of the gate T13, the first electrode T11 and the second electrode T12 of the second transistor T2 respectively. The gate T13 of the second transistor T2 receives the gate T13 signal of the second gate line 700, and the second transistor T2 is configured to be turned on in response to the gate T13 signal received by the gate T13 being a valid voltage, so as to transmit the voltage of the data line 200 to the second pixel electrode 800. Wherein, the second liquid crystal capacitor Cpx2 is formed between the second electrode T12 of the second transistor T2 and the common electrode, and the second storage capacitor Ccs2 is formed between the second capacitor line 400 and the second pixel electrode 800. Correspondingly, the first liquid crystal capacitor Cpx1 is formed between the second electrode T12 of the first transistor T1 and the common electrode, and the first storage capacitor Ccs1 is formed between the first capacitor line 500 and the first pixel electrode 300.

[0259] The orthographic projection of the second capacitor line 400 on the substrate BS overlaps with the orthographic projection of the second pixel electrode 800 on the substrate BS. The structure and function of the second capacitor line 400 can refer to the first capacitor line 500. The structure of the second capacitor line 400 and the structure of the first capacitor line 500 can be the same or different (for example, the first conductive segment 510 of the second capacitor line 400 and the partial width of the first conductive segment 510 of the second capacitor line 400 are different).

[0260] In the present example, the two sub-pixel regions of the same column and adjacent two rows form a group. The two sub-pixel regions in the same group are arranged opposite to each other along the second direction and controlled by the same first gate line 100. In the case of gate line breakage of the first gate line 100, the sub-pixel region on one side of the bridge 600 can be provided with the bridge 600. The bridge 600 can be arranged in the sub-pixel region on the first side of the first gate line 100, or in the sub-pixel region on the second side of the first gate line 100. In this way, the number of bridges 600 is reduced, and the repair efficiency of the array substrate 10 is improved. Moreover, the sub-pixel opposite to the side where the bridge 600 is located can not be affected by the bridge 600 and can return to the normal working state, which is basically the same as the normal sub-pixel and does not need to be darkened.

[0261] In some embodiments, referring to Figure 28AThe array substrate further includes a second gate line 700 and a plurality of third transistors T3 disposed on the substrate BS. A gate electrode T13 of a third transistor T3 is coupled to the second gate line 700. A first electrode T11 of the third transistor T3 is coupled to the second electrode T12 of the second transistor T2. A second electrode T12 of the third transistor T3 has an overlapping area with the second capacitor line 400 on the substrate BS, thereby forming a third storage capacitor Ccs3. The third storage capacitor Ccs3 can share part of the electric quantity of the second storage capacitor Ccs2, thereby reducing the voltage on the second gate line 700.

[0262] The array substrate repaired by the above-mentioned embodiments is introduced by taking the example of the bridge passing through one sub-pixel region. Some other embodiments of the present application further provide an array substrate, in which the bridge passes through two or more sub-pixel regions, i.e., the bridge intersects with two or more first capacitor lines.

[0263] For example, Figure 28A Fig. 6 is a top view of an array substrate repaired by a bridge passing through two sub-pixel regions. Figure 28B For example, the length of the gate line breakage is greater than the length of one first capacitor line. Since the two ends of the bridge are located on the two sides of the gate line breakage, the bridge needs to pass through two or more sub-pixel regions in the above-mentioned case.

[0264] For the convenience of description, the bridge is named as a second bridge, and the corresponding gate line breakage is named as a second gate line breakage.

[0265] Example XI

[0266] Figure 28A Fig. 6 is a top view of an array substrate repaired by a bridge passing through two sub-pixel regions. Figure 28A Fig. 6 is a top view of an array substrate repaired by a bridge passing through two sub-pixel regions.

[0267] Fig. 6 is a top view of an array substrate repaired by a bridge passing through two sub-pixel regions. Figure 28B Some other embodiments of the present application provide an array substrate 10. The first gate line 100 has a second gate line breakage 112. The array substrate 10 further includes a second bridge 600B, and the two ends of the second bridge 600B are connected to the two sides of the second gate line breakage 112 of the first gate line 100. The second bridge 600B intersects with a second repair capacitor line 500B and a third repair capacitor line 500C, and the second repair capacitor line 500B and the third repair capacitor line 500C are respectively one of a plurality of first capacitor lines 500.

[0268] For example, one of the first capacitor lines 500 crossing the first bridge segment 610 of the second bridge 600B is the second repair capacitor line 500B, and another of the first capacitor lines 500 crossing the third bridge segment 630 of the second bridge 600B is the third repair capacitor line 500C.

[0269] The sub-pixel region corresponding to the second repair capacitor line 500B and the third repair capacitor line 500C can also be darkened.

[0270] Referring to Figure 28B The second repair capacitor line 500B has the third repair break 553 and the fourth repair break 554 disposed on both sides of the second bridge 600B.

[0271] The second repair capacitor line 500B and the second bridge 600B have two crossing positions. One crossing position is the crossing position of the first conductive segment 510 of the second repair capacitor line 500B and the first bridge segment 610 of the second bridge 600B, which is located on the first conductive segment 510. The other crossing position is the crossing position of the third conductive segment 530 of the second repair capacitor line 500B and the second bridge segment 620 of the second bridge 600B, which is located on the third conductive segment 530. Thus, relative to the second repair capacitor line 500B, the two sides of the second bridge 600B are actually the two sides of the first bridge segment X1 composed of the first bridge segment 610 and the part of the second bridge segment 620 between the first bridge segment 610 and the corresponding third conductive segment 530.

[0272] The third repair break 553 is located on the first conductive segment 510. Specifically, since the second bridge 600B extends from the right side of the second repair capacitor line 500B to the third repair capacitor line 500C, the second part 512 of the first conductive segment 510 is at least partially located in the region of the first bridge segment X1 of the second bridge 600B, and can be coupled with the first gate line 100, so the second part 512 of the first conductive segment 510 is not suitable for setting the third repair break 553. Therefore, the third repair break 553 is located on the first conductive segment 510, which is set on the first part 511 or the middle part 513 of the first conductive segment 510 on the second repair capacitor line 500B, according to the position of the first bridge segment 610 of the second bridge 600B. The fourth repair break 554 is located on the corresponding third conductive segment 530.

[0273] Referring to Figure 10 In the second repair capacitor line 500B, when the first break 514 is located on the first part 511 and on the left side of the first bridge segment 610, the first break 514 can be used as the third repair break 553.

[0274] Then, a fourth repair break 554 is formed on the portion of the third conductive segment 530 which is located on the side of the second bridge segment 620 away from the first conductive segment 510, for example by laser cutting.

[0275] The third repair break 553 and the fourth repair break 554 also divide the second repair capacitor line 500B into two parts, the first part D1 crosses the first bridge 600B, and the second part D2 needs to be coupled with the first pixel electrode 300.

[0276] In the array substrate, the portion of the first conductive segment 510 which is located on the side of the third repair break 553 away from the middle portion 513 is coupled with the second electrode T12 of the second repair transistor T1B.

[0277] In this embodiment, the portion of the first segment 511 on the left side of the first segment 511 is coupled with the second electrode T12 of the second repair transistor T1B. The specific configuration of the fusion coupling point 320 can refer to Example 1 or Example 2.

[0278] Similarly, when performing the dark spot processing, the connection between the first pixel electrode 300 and the data line 200 in the sub-pixel area can be disconnected, so that the data line 200 cannot provide a data signal to the first pixel electrode 300.

[0279] Specifically, the second repair transistor T1B is one of the plurality of first transistors T1 and corresponds to the second repair capacitor line 500B. The second repair transistor T1B refers to the transistor in the plurality of first transistors T1 that controls the sub-pixel to which the second repair capacitor line 500B belongs. The second electrode T12 of the second repair transistor T1B is also provided with a transistor break AA1. The structure and function of the transistor break AA1 can be combined with Figure 28B and refer to Example 1.

[0280] The third repair capacitor line 500C has a fifth repair break 555 and a sixth repair break 556 disposed on two sides of the second bridge 600B. The fifth repair break 555 is located on the first conductive segment 510. Similarly, the third repair capacitor line 500C and the second bridge 600B have two crossing positions. One crossing position is the crossing position of the first conductive segment 510 of the third repair capacitor line 500C and the third bridge segment 630 of the second bridge 600B, which is located on the first conductive segment 510. The other crossing position is the crossing position of the second conductive segment 520 of the third repair capacitor line 500C and the second bridge segment 620 of the second bridge 600B, which is located on the second conductive segment 520. Thus, relative to the third repair capacitor line 500C, the two sides of the second bridge 600B are actually the two sides of a second bridge segment X2 composed of the third bridge segment 630 and the part of the second bridge segment 620 between the third bridge segment 630 and the corresponding second conductive segment 520.

[0281] Referring to Figure 28B Similarly, the fifth repair break 555 is located on the first conductive segment 510 at a position visible to the third bridge segment 630 of the second bridge 600B, and is disposed on the second sub-portion 512 or the middle portion 513 of the first conductive segment 510 of the third repair capacitor line 500C. For example, the second sub-portion 512 of the first conductive segment 510 is processed by laser cutting or the like to form the fifth repair break 555. For another example, the first conductive segment 510 of the first capacitor line 500 is provided with a groove 515. The position at the groove 515 can be cut as a repair break, and the fifth repair break 555 can be formed by cutting at the groove 515.

[0282] The sixth repair break 554 is located on the corresponding second conductive segment 520. Specifically, the sixth repair break 554 can be disposed on the part of the second conductive segment 520 located on the side of the second bridge segment 620 away from the first conductive segment 510, and can be processed by laser cutting or the like.

[0283] The fifth repair break 555 and the sixth repair break 554 also divide the third repair capacitor line 500C into two parts, a first part D1 crossing the first bridge 600B and a second part D2 needing to be coupled to the first pixel electrode 300.

[0284] In the array substrate, the part of the first conductive segment 510 of the third repair capacitor line 500C located on the side of the fifth repair break 555 away from the middle portion 513 is coupled to the second electrode T12 of the third repair transistor T1C.

[0285] Referring to Figure 13The second portion D2 of the third repair capacitor line 500C is coupled to the second electrode T12 of the third repair transistor T1C. The coupling of the second portion D2 of the third repair capacitor line 500C to the second electrode T12 of the third repair transistor T1C can refer to the coupling of the right portion of the second section 512 to the second electrode T12 of the third repair transistor T1C. The coupling of the fusion coupling point 320 can refer to the coupling of the right portion of the second section 512 to the second electrode T12 of the third repair transistor T1C.

[0286] Similarly, when the dark spot processing is performed, the connection between the first pixel electrode 300 and the data line 200 in the sub-pixel area can be disconnected, so that the data line 200 cannot provide a data signal to the first pixel electrode 300.

[0287] The third repair transistor T1C is one of the plurality of first transistors T1, and the third repair capacitor line 500C is correspondingly provided. The third repair transistor T1C means that the transistor of the plurality of first transistors T1 controls the sub-pixel to which the third repair capacitor line 500C belongs. The second electrode T12 of the third repair transistor T1C is also provided with a transistor break AA1. The structure and function of the transistor break AA1 can be combined with the structure and function of the transistor break AA1 in the first repair capacitor line 500A. Figure 29 Reference can be made to Example 1.

[0288] In the third repair capacitor line 500C, the portion of the first conductive segment 510 on the side away from the middle portion 513 is coupled to the second electrode T12 of the third repair transistor T1C. That is, the right portion of the second section 512 is coupled to the second electrode T12 of the third repair transistor T1C. In addition, in the third repair capacitor line 500C, the first pixel electrode 300 is coupled to the second electrode T12 of the third repair transistor T1C at the charging coupling point 310. In this way, the first pixel electrode 300 is coupled to the second portion D2 of the third repair capacitor line 500C. The specific coupling mode of the second portion D2 of the third repair capacitor line 500C to the first pixel electrode 300 is shown in Example 1 or Example 2.

[0289] Example 12

[0290] Figure 28A For Figure 29 Another possible enlarged view of M6.

[0291] Reference can be made to Figure 29 In the present embodiment, the first break 514 is located in the second section 512, which is different from Example 11.

[0292] Therefore, in the second repair capacitor line 500B, the first break 514 cannot be used as the third repair break 553. The third repair break 553 is located in the first section 511, and the third repair break 553 can be formed by laser cutting or the like in the first section 511. For example, the first conductive segment 510 of the first capacitor line 500 is provided with a groove 515. The position of the groove 515 can be cut off as a repair break, and the third repair break 553 can be formed by cutting off at the groove 515.

[0293] The fourth repair fracture 554 is also located on the third conductive segment 530. The fourth repair fracture 554 can be arranged in the manner as described in Example XI.

[0294] The second portion D2 of the second repair capacitor line 500B is coupled to the first pixel electrode 300 in the manner as described in Example XI.

[0295] Continuing to refer to Figure 30 Correspondingly, in the third repair capacitor line 500C, the first fracture 514 can be a fifth repair fracture 555. A sixth repair fracture 556 is located on the second conductive segment 520. The sixth repair fracture 556 can be arranged in the manner as described in Example XI.

[0296] The second portion D2 of the third repair capacitor line 500C is coupled to the first pixel electrode 300 in the manner as described in Example XI.

[0297] Examples XI and XII are both embodiments in which the second bridge 600B crosses only two capacitor lines. The following provides an embodiment in which the second bridge 600B crosses three or more first capacitor lines 500.

[0298] Example XIII

[0299] Figure 30 is a partial enlarged view of a repaired array panel. Referring to Figure 30 When the second gate line fracture 112 of the first gate line 100 is long, for example, the length of the second gate line fracture 112 is greater than the length of two first capacitor lines 500. In this way, the second bridge 600B crosses at least three first capacitor lines 500. Taking the case in which the second bridge 600B crosses three first capacitor lines 500 as an example, a description is provided. The case in which the second bridge 600B crosses more first capacitor lines 500 is similar and will not be described again.

[0300] Referring to Figure 31 The first gate line 100 has the second gate line fracture 112. The array substrate 10 includes the second bridge 600B, and the two ends of the second bridge 600B are connected to the first gate line 100 on the two sides of the second gate line fracture 112.

[0301] The second bridge 600B crosses the second repair capacitor line 500B, the third repair capacitor line 500C, and the fourth repair capacitor line 500D, and the fourth repair capacitor line 500D is located between the second repair capacitor line 500B and the third repair capacitor line 500C.

[0302] The third repair fracture 553 and the fourth repair fracture 554 of the second repair capacitor line 500B are arranged in the manner as described in Example XII.

[0303] Correspondingly, the darkening operation of the sub-pixel region corresponding to the second repair capacitor line 500B can refer to Example Twelve, such as the coupling mode of the second part D2 of the second repair capacitor line 500B.

[0304] The setting positions and setting modes of the fifth repair break 555 and the sixth repair break 556 of the third repair capacitor line 500C are similar to those of Example Twelve, which can be referred to Example Twelve.

[0305] Correspondingly, the darkening operation of the sub-pixel region corresponding to the third repair capacitor line 500C can refer to Example Twelve, such as the coupling mode of the second part D2 of the second repair capacitor line 500B.

[0306] The difference between the present example and Example Twelve is that the present example further has a fourth repair capacitor line 500D and a fourth repair transistor T1D. The fourth repair capacitor line 500D is located between the second repair capacitor line 500B and the third repair capacitor line 500C. The fourth repair transistor T1D is located between the second repair transistor T1B and the third repair transistor T1C.

[0307] A seventh repair break is arranged on the second conductive segment 520 of the fourth repair capacitor line 500D at a portion of the second bridge segment 620 away from the first conductive segment 510. An eighth repair break is arranged on the third conductive segment 530 of the fourth repair capacitor line 500D at a portion of the second bridge segment 620 away from the first conductive segment 510. The seventh repair break and the eighth repair break divide the fourth repair capacitor line 500D into a first part D1 and a second part D2. The second part D2 is not coupled with the first pixel electrode 300.

[0308] The second electrode T12 of the fourth repair transistor T1D is also provided with a transistor break AA1.

[0309] Figure 32 A flowchart of a method for manufacturing an array substrate.

[0310] Some embodiments of the present disclosure provide a method for manufacturing an array substrate, comprising:

[0311] Step S100: forming a first gate line, a plurality of data lines, a plurality of first transistors, and a plurality of first capacitor lines on a substrate; the first gate line has a first side and a second side opposite in the width direction of the first gate line; a data line crosses and is insulated from the first gate line; a gate and a first electrode of a first transistor are sequentially coupled with the first gate line and the data line;

[0312] Step S200: forming a plurality of first pixel electrodes on the substrate; a first pixel electrode is located on a first side of the first gate line and coupled with the second electrode of the first transistor;

[0313] The first capacitor line includes a first conductive segment, an extension direction of the first conductive segment is substantially parallel to an extension direction of the first gate line, the first conductive segment is close to the first gate line, the first conductive segment is provided with a first break, the first break is located on a side of the charging coupling point away from the data line and deviates from a middle part of the first conductive segment, the charging coupling point is a coupling position of the first pixel electrode and the second electrode of the first transistor, the middle part of the first conductive segment is a part of the first conductive segment located in the middle and having a length of 1 / 3 of a total length, and a part of the first conductive segment located on a side of the first break away from the middle part and the second electrode of the first transistor have projections on the substrate that overlap.

[0314] In the preparation method, the first gate line 100, the plurality of data lines 200, the plurality of first transistors T1 and the plurality of first capacitor lines 500, and the first pixel electrode 300 can be deposited by using a process such as sputtering or CVD (chemical vapor deposition) to form corresponding film layers. The film layers are subjected to steps such as coating photoresist, exposure, development and etching to obtain corresponding structures. The specific steps will not be described again.

[0315] Figure 32 A process diagram for preparing the array substrate of an embodiment. In some embodiments, referring to Figure 32 In the case where the first gate line 100 has the first gate line break 111, the array substrate needs to be repaired by arranging the bridge 600 on the first gate line 100. Correspondingly, the preparation method of the array substrate further includes:

[0316] The first bridge 600A is arranged on the substrate BS, two ends of the first bridge 600A are connected on two sides of the first gate line break 111 of the first gate line 100, the first bridge 600A crosses the first repair capacitor line 500A, and the first repair capacitor line 500A is one of the plurality of first capacitor lines 500;

[0317] The first repair capacitor line 500A is subjected to at least one cutting treatment to obtain the first repair break 551 and the second repair break 552 arranged on two sides of the first bridge 600A, and the first repair break 551 is located on the first conductive segment 510; one of the first repair break 551 and the second repair break 552 is the first break 514, or the first repair break 551 and the second repair break 552 are located on two sides of the first break 514;

[0318] The portion of the first conductive segment 510 on the first repair breakage side away from the middle portion 513 is coupled to the second electrode T12 of the first repair transistor T1A, which is one of the first transistors T1 and corresponds to the first repair capacitor line 500A.

[0319] Exemplarily, in some array substrates, the first breakage 514 on the first conductive segment 510 of the first repair capacitor line 500A can be used as the first repair breakage 551.

[0320] In this case, the first breakage 514 on the first conductive segment 510 of the first repair capacitor line 500A can be used as the first repair breakage 551. The groove 515 on the first conductive segment 510 is cut once (the black cross line represents the cut).

[0321] Then the second electrode T12 of the first repair transistor T1A can be cut at a position deviating from the charging coupling point 310 and close to the first electrode T11 of the first repair transistor T1A (the N1 position of FIG. 6), to form a transistor breakage AA1. The transistor breakage AA1 can cut the data line 200 to supply power to the second electrode T12 of the first repair transistor T1A. Figure 33

[0322] Next, the portion of the first conductive segment 510 on the first repair breakage side away from the middle portion 513 can be coupled to the second electrode T12 of the first repair transistor T1A at the position of the charging coupling point 310. In addition, in the first repair capacitor line 500A, the first pixel electrode 300 and the second electrode T12 of the first repair transistor T1A are coupled at the charging coupling point 310. In this way, the first pixel electrode 300 is coupled to the second portion D2 of the first repair capacitor line 500A, so that the potentials of the first pixel electrode 300 and the second portion D2 of the first repair capacitor line 500A are equal, and the array substrate is completed.

[0323] Exemplarily, in some array substrates, the first breakage 514 on the first conductive segment 510 of the first repair capacitor line 500A cannot be used as the first repair breakage 551.

[0324] Figure 33 A process diagram for preparing an array substrate of an embodiment. Referring to FIG. 7, the first repair capacitor line 500A is prepared. Figure 33 In this case, one-side cutting processing can be performed on the first conductive segment 510 of the first repair capacitor line 500A to obtain the first repair breakage 551. One-side cutting processing can be performed on the second conductive segment 520 of the first repair capacitor line 500A to obtain the second repair breakage 552.

[0325] ​Then, the transistor T1A can be cut off at the N2 position of the second electrode T12 of the first repair transistor T1A, away from the charging coupling point 310 and close to the first electrode T11 of the first repair transistor T1A, to form a transistor break AA1. The transistor break AA1 can cut off the data line 200 to supply power to the second electrode T12 of the first repair transistor T1A. ​

[0326] Next, the first conductive segment 510 can be coupled to the second electrode T12 of the first repair transistor T1A at the C1 position, on the side of the first repair break away from the middle portion 513. In addition, in the first repair capacitor line 500A, the first pixel electrode 300 is already coupled to the second electrode T12 of the first repair transistor T1A at the charging coupling point 310. In this way, the first pixel electrode 300 is coupled to the second portion D2 of the first repair capacitor line 500A, so that the potentials of the first pixel electrode 300 and the second portion D2 of the first repair capacitor line 500A are equal, and the array substrate is completed.

[0327] In some embodiments, when the first gate line 100 has the second gate line break 112, the array substrate needs to be repaired by arranging the bridge 600 on the first gate line 100. Accordingly, the method for manufacturing the array substrate further includes:

[0328] The second bridge 600B is arranged on the substrate BS, and the two ends of the second bridge 600B are respectively connected on the two sides of the second gate line break 112 of the first gate line 100. The second bridge 600B crosses the second repair capacitor line 500B and the third repair capacitor line 500C, and the second repair capacitor line 500B and the third repair capacitor line 500C are respectively one of the plurality of first capacitor lines 500. The second repair capacitor line 500B is cut off to obtain the third repair break 553 and the fourth repair break 554 arranged on the two sides of the second bridge 600B, and the third repair break 553 is located on the first conductive segment 510.

[0329] ​The part of the first conductive segment 510 of the second repair capacitor line 500B on the side away from the middle part 513 of the third repair break is coupled with the second pole T12 of the second repair transistor T1B, the second repair transistor T1B is one of the plurality of first transistors T1 and corresponds to the second repair capacitor line 500B; the third repair capacitor line 500C is cut off to obtain the sixth repair break 556; the first break 514 on the third repair capacitor line 500C is the fifth repair break 555, and the fifth repair break 555 and the sixth repair break 556 are arranged on the two sides of the second bridge 600B; the part of the first conductive segment 510 of the third repair capacitor line 500C on the side away from the middle part 513 of the fifth repair break is coupled with the second pole T12 of the third repair transistor T1C, the third repair transistor T1C is one of the plurality of first transistors T1 and corresponds to the third repair capacitor line 500C.

[0330] The preparation method of the array substrate with the second gate line break 112 can refer to the preparation method of the array substrate with the first gate line break 111 and be combined with the structure of the array substrate with the second gate line break 112, which will not be described herein again.

[0331] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. An array substrate, comprising: The substrate and a first gate line, multiple data lines, multiple first pixel electrodes, multiple first transistors, and multiple first capacitor lines disposed on the substrate; wherein, The first gate line has a first side and a second side that are opposite to each other in the width direction of the first gate line; A data line intersects with and is insulated from the first gate line; A first pixel electrode is located on the first side of the first gate line; The gate, first electrode, and second electrode of a first transistor are sequentially coupled to the first gate line, the data line, and the first pixel electrode. The orthographic projection of a first capacitor line on the substrate overlaps with the orthographic projection of the first pixel electrode on the substrate. The first capacitor line includes a first conductive segment, the extension direction of which is approximately parallel to the extension direction of the first gate line. The first conductive segment is close to the first gate line. A first break is provided on the first conductive segment. The first break is located on the side of the charging coupling point away from the data line and is offset from the middle of the first conductive segment. The charging coupling point is the coupling position between the first pixel electrode and the second electrode of the first transistor. The middle part of the first conductive segment is the portion located in the middle of the first conductive segment and whose length accounts for 1 / 3 of the total length. The orthographic projections of the portion of the first conductive segment located on the side of the first break away from the middle part and the second electrode of the first transistor overlap on the substrate.

2. The array substrate according to claim 1, wherein, The first break is located in the middle of the first conductive segment on the side near the charging coupling point, or the first break is located in the middle of the first conductive segment on the side away from the charging coupling point.

3. The array substrate according to claim 1 or 2, wherein, The portion of the first conductive segment located on the side away from the middle of the first break, the second electrode of the first transistor, and the first pixel electrode have overlapping orthogonal projections on the substrate.

4. The array substrate according to claim 1, wherein, The first conductive segment is provided with a groove with an opening facing or away from the first grid line, and the groove and the first break are respectively located on both sides of the middle part.

5. The array substrate according to claim 4, wherein, The portion of the first conductive segment located on the side of the groove away from the center and the second electrode of the first transistor have overlapping orthogonal projections on the substrate.

6. The array substrate according to claim 4, wherein, At the groove, the ratio of the width of the retained portion of the first conductive segment to the width of the first conductive segment is 1 / 3 to 1 / 2. And / or, the width of the opening of the groove is 7.5μm to 8.5μm.

7. The array substrate according to claim 1, wherein, The length of the portion of the first conductive segment located on the side of the first break away from the middle is greater than or equal to 15 μm.

8. The array substrate according to claim 1, wherein, The first gate line has a first gate line break; The array substrate further includes a first bridge, the two ends of which are respectively connected to both sides of the break in the first gate line on the first gate line. The first bridge intersects with a first repair capacitor line, which is one of the plurality of first capacitor lines. The first repair capacitor line has a first repair break and a second repair break located on both sides of the first bridge, and the first repair break is located on the first conductive segment; wherein, one of the first repair break and the second repair break is the first break, or the first repair break and the second repair break are located on both sides of the first break; The portion of the first conductive segment located on the side of the first repair break away from the first bridge is coupled to the second electrode of the first repair transistor, which is one of the plurality of first transistors and corresponds to the first repair capacitor line.

9. The array substrate according to claim 8, wherein, The first repair capacitor line includes a groove located on the first conductive segment; One of the first repair break and the second repair break is located at the location of the groove in the first repair capacitor line.

10. The array substrate according to claim 8, wherein, The first repair break is located between the first bridge and the charging coupling point; At the charging coupling point, the second electrode of the first repair transistor, the first pixel electrode, and the first repair capacitor line are coupled together.

11. The array substrate according to claim 1, wherein, The first gate line has a second gate line break; The array substrate further includes a second bridge, the two ends of which are respectively connected to the two sides of the second gate line break on the first gate line. The second bridge intersects with both the second repair capacitor line and the third repair capacitor line, which are one of the plurality of first capacitor lines. The second repair capacitor line has a third repair break and a fourth repair break respectively located on both sides of the second bridge. The third repair break is located on the first conductive segment. The portion of the first conductive segment located on the side away from the middle of the third repair break is coupled to the second electrode of the second repair transistor. The second repair transistor is one of the plurality of first transistors and corresponds to the second repair capacitor line. The third repair capacitor line has a fifth repair break and a sixth repair break respectively located on both sides of the second bridge. The fifth repair break is located on the first conductive segment. The portion of the first conductive segment of the third repair capacitor line located on the side away from the middle of the fifth repair break is coupled to the second electrode of the third repair transistor. The third repair transistor is one of the plurality of first transistors and corresponds to the third repair capacitor line. Wherein, the third repair break is the first break of the second repair capacitor wire, or the fifth repair break is the first break of the third repair capacitor wire.

12. The array substrate according to claim 1, further comprising: A plurality of second pixel electrodes, a plurality of second transistors, and a plurality of second capacitor lines are disposed on the substrate; A second pixel electrode is located on the second side of the first gate line; The gate, first electrode, and second electrode of a second transistor are sequentially coupled to the first gate line, the data line, and the second pixel electrode. The orthographic projection of the second capacitor line on the substrate overlaps with the orthographic projection of the second pixel electrode on the substrate.

13. The array substrate according to claim 12, further comprising: A second gate line and a plurality of third transistors are disposed on the substrate; The gate of a third transistor is coupled to the second gate line, the first terminal of the third transistor is coupled to the second terminal of the second transistor, and the orthographic projection of the second terminal of the third transistor on the substrate overlaps with the orthographic projection of the second capacitor line on the substrate.

14. A display device, comprising: The array substrate as described in any one of claims 1 to 13.

15. A method for fabricating an array substrate, comprising: A first gate line, multiple data lines, multiple first transistors, and multiple first capacitor lines are formed on a substrate; The first gate line has a first side and a second side opposite to each other in the width direction of the first gate line; a data line intersects the first gate line and is insulated from it; the gate and first electrode of a first transistor are sequentially coupled to the first gate line and the data line; A plurality of first pixel electrodes are formed on the substrate; one first pixel electrode is located on a first side of the first gate line and is coupled to the second electrode of the first transistor; In this configuration, the orthographic projection of a first capacitor line on the substrate overlaps with the orthographic projection of the first pixel electrode on the substrate. The first capacitor line includes a first conductive segment, the extension direction of which is approximately parallel to the extension direction of the first gate line. The first conductive segment is close to the first gate line, and a first break is provided on the first conductive segment. The first break is located on the side of the charging coupling point away from the data line and offset from the middle of the first conductive segment. The charging coupling point is the coupling position between the first pixel electrode and the second electrode of the first transistor. The middle part of the first conductive segment is the portion located in the middle of the first conductive segment and whose length accounts for 1 / 3 of the total length. The portion of the first conductive segment located on the side of the first break away from the middle part and the second electrode of the first transistor overlap in their orthographic projections on the substrate.

16. The method for fabricating an array substrate according to claim 15, wherein, The first gate line has a first gate line break; The preparation method further includes: A first bridge is provided on the substrate, and the two ends of the first bridge are respectively connected to the two sides of the first gate line break on the first gate line. The first bridge intersects with a first repair capacitor line, and the first repair capacitor line is one of the plurality of first capacitor lines. The first repair capacitor line is cut at least once to obtain a first repair break and a second repair break placed on both sides of the first bridge, wherein the first repair break is located on the first conductive segment; wherein, one of the first repair break and the second repair break is the first break, or the first repair break and the second repair break are located on both sides of the first break. The portion of the first conductive segment located on the side away from the middle of the first repair break is coupled to the second electrode of the first repair transistor, which is one of the plurality of first transistors and corresponds to the first repair capacitor line.

17. The method for fabricating an array substrate according to claim 15, wherein, The first gate line has a second gate line break; The preparation method further includes: A second bridge is provided on the substrate, with its two ends connected to both sides of the second gate line break on the first gate line. The second bridge intersects with both the second and third repair capacitor lines, which are one of the plurality of first capacitor lines. The second repair capacitor line is then cut to obtain a third repair break and a fourth repair break located on both sides of the second bridge. The third repair break is located on the first conductive segment. The portion of the first conductive segment of the second repair capacitor line located on the side away from the middle of the third repair break is coupled to the second electrode of the second repair transistor, which is one of the plurality of first transistors and corresponds to the second repair capacitor line; the third repair capacitor line is cut to obtain a sixth repair break; the first break on the third repair capacitor line is the fifth repair break, and the fifth and sixth repair breaks are located on both sides of the second bridge; the portion of the first conductive segment of the third repair capacitor line located on the side away from the middle of the fifth repair break is coupled to the second electrode of the third repair transistor, which is one of the plurality of first transistors and corresponds to the third repair capacitor line.

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