Methods, apparatuses, and media for improving large scale array beam steering accuracy

Abstract

The application provides a method, device and medium for improving large-scale array beam control precision. The method comprises: full-link delay distribution based on radio frequency delay chip fixed delay error, wherein the full-array delay control quantity is distributed according to the delay resolution containing the fixed error; and step-by-step dilution of the delay truncation control error is performed to sequentially determine the final delay control coefficient of the delay line of each basic delay unit. The application provides a full-link delay distribution method considering the radio frequency delay chip fixed delay error and an error control method for step-by-step dilution of the delay truncation control error, and the inherent delay error of each stage of the radio frequency delay chip and the delay line truncation error are both included in the full-link delay control of the channel, the final delay control resolution of the full array is optimized to the minimum step of the radio frequency delay line, and high-precision delay control of the large-scale array is realized.

Description

Technical Field

[0001] This invention relates to the field of phased array antenna technology, and more specifically, to a method, apparatus, and medium for improving the beam control accuracy of large-scale arrays. Background Technology

[0002] Current AESA (Active Electronically Scanned Array) radar arrays all employ TTD (True Time Delay) beam control technology. Its basic control concept is to calculate the delay length of each channel under beam scanning based on the azimuth and elevation beam scanning angles (φ, θ). Based on the delay length, a multi-bit delay chip is designed with a chosen delay resolution, and multiple chips are cascaded to achieve the delay length required to meet the maximum scanning angle. The basic principle is as follows:

[0003] Assuming the array size is M*N, the latency requirements for elevation and azimuth of the (i,j) element in the array when scanning the azimuth (φ) and elevation (θ) angles are as follows:

[0004] τ θ (i)=(i-1)*d*sin(θ) / ci=1:M

[0005]

[0006] Let L = M*N, l = (i-1)*N+j. The end-to-end delay of the (i,j) element in the M*N array is represented according to the order l = 1:L. Then the end-to-end delay requirement for the (i,j) element is:

[0007]

[0008] τ l Typically, RF TTD delay chips are used for implementation. To improve the beam scanning control resolution and accuracy of the array, the delay step of the delay chip needs to be relatively small while maintaining a high chip count (high delay resolution is required). Assuming the basic delay step of the delay line chip is x1 and the chip control bits are b, the delay chip is formed by connecting multiple basic units with a delay step of x1 in series, ultimately resulting in a maximum delay length of (2... b -1) For chips with x1, when x1 is small, the longest delay length of a single delay line chip is usually also small. Therefore, in array design, multiple delay line chips usually need to be cascaded in a single channel to meet the requirement of the longest delay line.

[0009] To achieve large-angle scanning, it is assumed that each channel has K cascaded delay line chips, and the basic delay step of the delay line chips is {x}. k The delay control coefficient for each stage is a, k = 1, ..., K. k Then the delay control coefficient for each stage in the l-th channel is a. lkThen the delay line control quantity in the l-th channel can be expressed as follows:

[0010] τ l =a l1 x1+a l2 x2+a l3 x3+…+a lK x K

[0011] The delay control values ​​for all channels of the entire array can be expressed as follows:

[0012]

[0013] The above expression provides a general delay configuration relationship for arrayed multi-channel, multi-level delay chips, where the delay control coefficients of each delay chip are based on the basic delay step {x} in the entire link. k The array is configured using the formulas k = 1, ..., K. When the array size is small and the beam is relatively wide, a slight deviation in beam hopping or beam pointing bias has little impact on the array's receive gain and transmit power. Therefore, the delay control of small-scale arrays primarily employs this configuration method based on delay chip theory and delay stepping.

[0014] In large-scale array systems, the above-mentioned delay control coefficient configuration method will cause the array beam scanning to deviate. The main reason is that the delay line chip in the project is composed of delay units with a basic delay step x1 connected in series through multiple delay units. When the basic delay step x1 has an inherent delay error e1, according to the delay control ratio, the final chip delay amount will include the actual delay amount and the inherent delay error amount in proportion.

[0015] The relationship between single-channel delay, delay error, and beam pointing angle is as follows:

[0016]

[0017] The above relationship indicates that the inherent delay error e1 will cause a change in the array beam pointing angle θ, i.e., a shift in the pointing angle. If the array size is small, x1 is usually small, and e1 is very small. Therefore, when the beamwidth is wide, the beam pointing error can be ignored. If the array size is large, in order to reduce the number of array chips, multiple stages of large-step delay chips are usually involved in the entire link. In this case, there will be two influencing factors on the channel delay error of the array: First, the large-step, large-delay RF delay chips have large delay errors, which leads to an increase in the accumulation of fixed delay errors of the delay chips in the entire link. For example, when the delay reaches more than 600ps, the delay error will be greater than 20ps. If the effect of delay error is not considered, it will cause a large shift in the array beam pointing. Second, the delay truncation control error of the large-step delay line is large, which leads to beam control accuracy problems. Existing technologies related to broadband phased array design, channel correction, and beam control methods, such as the broadband two-dimensional active time-controlled array based on two-stage time delay proposed in application number 202111500950.7, the channel correction method for an instantaneous broadband receiving phased array system with near-field correction proposed in application number 202211487649.1, and the channel correction method for an instantaneous broadband receiving phased array system with far-field correction proposed in application number 202211527024.3, cannot avoid the impact of large step delay line errors on beam control accuracy, nor can they correct the errors of large step delay lines under large delay lines. Summary of the Invention

[0018] The present invention aims to at least solve one of the technical problems in the prior art: large step size and large delay amount RF delay chips have large delay errors, which lead to the accumulation of fixed delay errors in the entire link delay chip and, if the influence of delay error is not considered, will cause a large deviation in the array beam pointing; large step size delay line delay truncation control error leads to poor beam control accuracy.

[0019] Therefore, the first aspect of the present invention provides a method for improving the beam control accuracy of large-scale arrays.

[0020] A second aspect of the present invention provides a computer device.

[0021] A third aspect of the present invention provides a computer-readable storage medium.

[0022] This invention provides a method for improving the beam control accuracy of large-scale arrays, comprising:

[0023] End-to-end delay allocation based on fixed delay error of RF delay chip, wherein the full array delay control quantity is allocated according to the delay resolution including fixed error;

[0024] The delay truncation control error is diluted step by step, and the final delay control coefficient of the delay line of each basic delay unit is determined in turn.

[0025] The method for improving the beam control accuracy of large-scale arrays according to the above-described technical solution of the present invention may further have the following additional technical features:

[0026] In the above technical solution, the end-to-end delay allocation based on the fixed delay error of the RF delay chip includes:

[0027] Obtain the actual delay step of the synchronous delay chip;

[0028] Based on the array multi-channel delay combining configuration, the delay value between relevant branches that meets the scanning angle is calculated, and the delay control quantity of each delay chip in each channel is initially allocated according to the actual delay step; the delay control coefficients of each level are determined step by step from the smallest basic delay step unit to the largest basic delay step unit.

[0029] In the above technical solution, obtaining the actual delay step of the synchronization delay chip includes:

[0030] The measured values ​​of a basic delay stepper unit within a channel under a large delay line control value are tested separately for each channel. The actual delay test values ​​are recorded at certain frequency intervals. The measured value of the large delay value is converted to the basic delay step according to the number of control bits. The actual delay step with error of the basic delay stepper unit is calculated. These converted actual delay steps are averaged to obtain the average actual delay step of the basic delay stepper unit in a single channel. Different basic delay stepper units are measured separately to form the average actual delay step of different basic delay stepper units in all channels of the entire array.

[0031] The basic delay stepping unit performs statistical processing on the average actual delay stepping value of all channel tests to obtain the statistical average actual delay stepping value corresponding to the basic delay stepping unit of the entire array.

[0032] In the above technical solution, the actual delay statistical average value y corresponding to the basic delay step unit k The calculation method is as follows:

[0033] y k =x k +e k

[0034] Where, x k For basic delay steps, e k This is due to inherent delay error.

[0035] In the above technical solution, the step-by-step determination of delay control coefficients from the smallest basic delay step unit to the largest basic delay step unit includes:

[0036] Starting with the smallest basic delay step unit, the delay control coefficients for each level are determined progressively towards the largest basic delay step unit, until the delay control coefficients for the entire delay line are finally determined, i.e., the delay allocation values ​​for each level of each channel.

[0037] In the above technical solution, the step of progressively diluting the delay truncation control error and determining the final delay control coefficient of each basic delay unit delay line includes:

[0038] Starting with the largest basic delay step unit, the delay truncation control error value is passed forward level by level. The delay allocation value of all channels is increased by the delay truncation control error value transmitted from the previous level's large delay line. Then, each channel calculates the final delay control coefficient under its current delay level according to the resolution unit of the statistical average of the actual delay step corresponding to the basic delay step unit of the entire array. The delay truncation control error value of this level is then passed to the smaller basic delay step unit delay line for dilution. In this way, the final control coefficient of the delay lines of each level of basic delay unit is determined sequentially.

[0039] In the above technical solution, the delay truncation control error value transmitted from the previous stage large delay line is the remaining value after the delay resolution control of the previous stage.

[0040] In the above technical solution, the default remaining value of the delay line of the maximum basic delay step unit is 0.

[0041] The present invention also provides a computer device, the computer device including a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the method for improving the beam control accuracy of large-scale arrays as described in any of the above technical solutions.

[0042] The present invention also provides a computer-readable storage medium storing a computer program, which is loaded and executed by a processor to implement the method for improving the beam control accuracy of large-scale arrays as described in any of the above technical solutions.

[0043] In summary, due to the adoption of the above-mentioned technical features, the beneficial effects of the present invention are:

[0044] This paper proposes a full-link delay allocation method considering the fixed delay error of RF delay chips and an error control method that progressively dilutes the delay truncation control error. The inherent delay error of each RF delay chip and the delay line truncation error are incorporated into the full-link delay control of the channel. Following the principle of decreasing delay step size, the delay truncation control error of each stage is progressively passed to the next stage chip with a smaller delay step for optimization and dilution. This ensures that the final delay control resolution of the array is equal to the resolution of the smallest delay line step, achieving precise delay control and accurate beam pointing across the entire array. This solves the problems of large beam jump and beam control accuracy caused by the fixed error of delay chips and the large delay truncation control error of large-step delay lines in large-scale arrays. The final delay control resolution of the entire array is optimized to the smallest step of the RF delay line, reducing the beam pointing error to within 0.5°, which is beneficial for achieving high-precision delay control in large-scale arrays.

[0045] Additional aspects and advantages of the invention will become apparent in the following description or may be learned by practice of the invention. Attached Figure Description

[0046] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0047] Figure 1 This is a schematic diagram of the error control model and the principle of error propagation and dilution of the delay lines at each stage in the array in a method for improving the beam control accuracy of a large-scale array according to an embodiment of the present invention;

[0048] Figure 2 These are the delay test curves for some channels without delay line correction for errors;

[0049] Figure 3 This is a delay test curve of a portion of the channel after delay correction with added error correction in a method for improving beam control accuracy of a large-scale array according to an embodiment of the present invention;

[0050] Figure 4 This is a method for improving the beam control accuracy of a large-scale array in one embodiment of the present invention, showing the beamforming pattern of the array before and after adding correction error under a -45° pointing direction. Detailed Implementation

[0051] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0052] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0053] The following reference Figures 1 to 4 This describes a method for improving the beam control accuracy of large-scale arrays according to some embodiments of the present invention.

[0054] Some embodiments of this application provide a method for improving the accuracy of beam control for large-scale arrays.

[0055] like Figures 1 to 4 As shown, the first embodiment of the present invention proposes a method for improving the beam control accuracy of large-scale arrays, assuming that the delay amounts of the basic unit of the large-scale array delay step are {x} k Let x1 be the minimum step size, x = 1, ..., K, and k be the minimum step size. K This is the maximum step size. Since all steps have the same basic delay step size x... k The delay lines are designed using the same process, and therefore have the same delay error. Here, we assume a basic delay step x. k The corresponding delay error is e k Then the delay line control quantity in the l-th channel can be expressed as follows:

[0056] τ l =a l1 (x1+e1)+a l2 (x² + e²) + a l3 (x³ + e³) + ... + a lK (x k +e k )

[0057] Considering that large stepper arrays have multiple channels sharing delay lines, the above model needs to be modified. Here, we take the L-element array being synthesized step by step and combined through 4 stages of delay as an example to modify the matrix model.

[0058] Assuming each channel of the first-level delay line is dedicated, the second-level delay line is shared by 4 channels, the third-level delay line is shared by 16 channels, and the fourth-level delay line is shared by L / 4 channels, in the model correction, the delay control quantity of the first channel participating in the synthesis of this level is used to replace the delay control quantity of other channels. Then, the delay control quantity of the entire array L-element channel delay line can be expressed as follows:

[0059]

[0060] As can be seen from the above formula, the cumulative amount of delay error increases proportionally with the beam scanning delay. Therefore, the cumulative amount of fixed delay error of the delay chip will cause the beam pointing to shift.

[0061] Let y1=x1+e1, y2=x2+e2, y3=x3+e3, y4=x4+e4.

[0062] The above equation then becomes:

[0063]

[0064] The above equation shows that precise beam control can be achieved by allocating the full array delay control quantity according to the delay resolution containing a fixed error. Wherein, the delay error e k Multiple large delay control values ​​a can be used lk The error generated under control is converted and obtained by statistical averaging of the delay errors of multiple chips.

[0065] Based on the above principles, the invention of the method for improving the beam control accuracy of large-scale arrays mainly includes: a full-link delay allocation method based on the fixed delay error of the RF delay chip (including two steps: acquiring the actual delay step of the synchronous delay chip and allocating the precise delay control coefficient), and an error control method for progressively diluting the delay truncation control error.

[0066] The end-to-end delay allocation method based on the fixed delay error of RF delay chips includes:

[0067] (1) Obtain the actual delay step of the synchronous delay chip.

[0068] Specifically, firstly, test a basic delay stepping unit {x} within each channel according to different channels. k The measured values ​​of the large delay line control values ​​(k = 1, ..., K) are recorded at certain frequency intervals. The measured values ​​of the large delay are converted to the basic delay step according to the number of control bits, and the basic delay step unit x is calculated. k The actual delay steps with error are averaged to obtain the basic delay step unit x in a single channel. k The actual average delay step size. Different basic delay step units x k The measurements were taken separately, and finally, different basic delay stepping units x were formed for all channels of the entire array. k The actual average delay step.

[0069] Secondly, according to the basic delay step unit x k The average actual delay step value of all channel tests is statistically processed to obtain the basic delay step unit x of the entire array. k The corresponding actual delay step statistical average yk , where y k =x k +e k .

[0070] (2) Precise delay control coefficient allocation

[0071] Based on the array multi-channel delay combining configuration, calculate the delay value between relevant branches that satisfies the scanning angle, and calculate the statistical average value y based on the actual delay step. k Initially allocate the delay control values ​​for each delay chip in each channel. Starting with the smallest basic delay step unit (e.g., y1), determine the delay control coefficients for each level step by step towards the largest basic delay step unit y4, until the delay control coefficients for the entire delay line are completely determined, i.e., the delay allocation values ​​for each level in each channel.

[0072] Error control methods that progressively dilute delay truncation control errors include:

[0073] Starting with the maximum basic delay step unit (e.g., y4), the delay truncation control error value is passed forward level by level. The delay allocation value for all channels is increased by the delay truncation control error value transmitted from the previous level's large delay line (this is the remaining value after the previous level's delay resolution control; the default remaining value added by the maximum basic delay step unit's delay line is 0). Afterward, each channel again follows the y... k The resolution unit calculates the final delay control coefficient for its current delay level and transmits the delay truncation control error value for this level to the delay line of the smaller basic delay step unit for dilution. The final control coefficients of the delay lines of each basic delay unit are determined sequentially using this method.

[0074] The error control model and truncation control error propagation and dilution principle of the delay lines in each stage of the array proposed in this embodiment are as follows: Figure 1 As shown, the array is divided into 4 delay lines: x1 has a basic delay step of 3ps, x2 has a basic delay step of 6ps, x3 has a basic delay step of 6ps, and x4 has a basic delay step of 12ps.

[0075] Figures 2 to 4 The diagram illustrates the delay conditions before and after channel correction and the beamforming effect of the "full-link delay allocation method considering the fixed delay error of the RF delay chip and the error control method for progressively diluting the delay truncation control error" proposed in this embodiment.

[0076] in, Figure 2This section presents the actual delay measurement values ​​of a delay chip with a basic delay step of 12ps in the RF channel of the array under delay control. The main statistical average value of the actual delay step, y4, is calculated. The control quantity is 650ps, the control coefficient is 54, the channel delay is 648ps, and the control stage error is 2ps. After statistical processing, the average actual delay measurement value is approximately 630ps. The average cumulative fixed error of the channel is approximately 20ps, and the maximum error is approximately 30ps. Therefore, the calculated statistical average value of the actual delay step, y4, is 11.7ps.

[0077] Figure 3 To control the delay based on the actual delay step statistical average value y4, and after diluting the truncation error by passing it to the x3 delay chip, the actual measured delay values ​​for each channel are as follows: The control coefficient is 55. Based on y4 of 11.7 ps, the theoretical delay is approximately 643.5 ps. Considering a truncation control error of 6.5 ps, this error is diluted by the x3 delay chip with a control coefficient of 1. Figure 3 The output is actually the result of the combined action of the delay stepper Y4 chip and the delay stepper Y3 chip. It can be seen that after correcting for the inherent error of the delay lines, the average channel delay is approximately 646 ps, with an average error of approximately 5 ps.

[0078] Figure 4 This study examines the beam pattern before and after array delay error correction, considering the fixed delay error and truncation control error of the RF delay chip, with a beam pointing at -45°. It can be seen that before array delay error correction, the delay lines did not reach the required delay length, resulting in a beam pointing deviation. After correction, the actual delay lines in the array elements are closer to the true delay than before correction, and the center value of the main lobe of the beam pattern is less different from -45°, achieving precise beam control.

[0079] A second embodiment of the present invention provides a computer device including a processor and a memory, wherein the memory stores a computer program, which is loaded and executed by the processor to implement the method for improving the accuracy of large-scale array beam control as described in the first embodiment.

[0080] A third embodiment of the present invention provides a computer-readable storage medium storing a computer program that is loaded and executed by a processor to implement the method for improving the beam control accuracy of large-scale arrays as described in the first embodiment.

[0081] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0082] Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this invention shall be included within the scope of protection of this invention.

Claims

1. A method for improving the beam control accuracy of large-scale arrays, characterized in that, include: End-to-end delay allocation based on fixed delay error of RF delay chip, wherein the full array delay control quantity is allocated according to the delay resolution including fixed error; The delay truncation control error is diluted step by step, and the final delay control coefficient of the delay line of each basic delay unit is determined in turn. The end-to-end delay allocation based on the fixed delay error of the RF delay chip includes: Obtain the actual delay step of the synchronous delay chip; Based on the array multi-channel delay combining configuration, calculate the delay value between relevant branches that satisfies the scanning angle, and initially allocate the delay control quantity of each delay chip in each channel according to the actual delay step; determine the delay control coefficient of each level step by step from the smallest basic delay step unit to the largest basic delay step unit. The process of obtaining the actual delay step of the synchronization delay chip includes: The measured values ​​of a basic delay stepper unit within each channel were tested under a large delay line control value. The actual delay test values ​​were recorded at certain frequency intervals. The actual delay test values ​​were converted to the basic delay step according to the number of control bits. The actual delay step with error of the basic delay stepper unit was calculated. These converted actual delay steps were averaged to obtain the average actual delay step of the basic delay stepper unit in a single channel. The actual delay step of different basic delay stepper units was measured separately to form the average actual delay step of different basic delay stepper units in all channels of the entire array. The basic delay stepping unit performs statistical processing on the average actual delay stepping value of all channel tests to obtain the statistical average actual delay stepping value corresponding to the basic delay stepping unit of the entire array; The stepwise determination of delay control coefficients from the minimum basic delay step unit to the maximum basic delay step unit includes: Starting with the smallest basic delay step unit, the delay control coefficients of each level are determined step by step towards the largest basic delay step unit, until the delay control coefficients of the entire delay line are completely determined, that is, the delay allocation value of each level of each channel. The process of progressively diluting the delay truncation control error and determining the final delay control coefficients of the delay lines of each basic delay unit includes: Starting with the largest basic delay step unit, the delay truncation control error value is passed forward level by level. The delay allocation value of all channels is increased by the delay truncation control error value transmitted from the previous level's large delay line. Then, each channel calculates the final delay control coefficient under its current delay level according to the resolution unit of the statistical average of the actual delay step corresponding to the basic delay step unit of the entire array. The delay truncation control error value of this level is then passed to the smaller basic delay step unit delay line for dilution. In this way, the final control coefficient of the delay lines of each level of basic delay unit is determined sequentially.

2. The method for improving beam control accuracy of large-scale arrays according to claim 1, characterized in that, The actual delay statistical average value y corresponding to the basic delay step unit k The calculation method is as follows: and k =x k + e k Where, x k For basic delay steps, e k This is due to inherent delay error.

3. The method for improving beam control accuracy of large-scale arrays according to claim 1, characterized in that, The delay truncation control error value transmitted from the previous stage large delay line is the remaining value after the delay resolution control of the previous stage.

4. The method for improving beam control accuracy of large-scale arrays according to claim 3, characterized in that, The default remaining value of the maximum basic delay step unit delay line is 0.

5. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program that is loaded and executed by the processor to implement the method for improving the accuracy of large-scale array beam control as described in any one of claims 1 to 4.

6. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which is loaded and executed by a processor to implement the method for improving the beam control accuracy of large-scale arrays as described in any one of claims 1 to 4.

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